Display panel and display device

Abstract

The present application provides a display panel and a display device. The display panel comprises a display area and a bezel area. The display panel further comprises a substrate, at least two signal wire groups arranged on the substrate, and an organic insulating layer arranged on the signal wire groups, the signal wire groups are located in the bezel area, each signal wire group comprises a plurality of signal wires arranged at intervals, and a linear insulating pattern is arranged on the organic insulating layer between adjacent signal wire groups.

Description

Display panel and display device

[0001] This application claims priority to Chinese patent application No. 202510018207.X, filed on January 6, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0003] Active matrix organic light-emitting diode (AMOLED) display panels are gradually becoming the next-generation display technology due to their high contrast, wide color gamut, and low power consumption. Compared with traditional liquid crystal displays (LCDs), AMOLED display panels are easier to make flexible, making them a key technology for wearable and foldable products. With the development of AMOLED display technology, how to reduce bezels while ensuring the reliability of the display panel is a pressing problem that screen suppliers need to solve. Invention Overview

[0004] Currently, to avoid reliability issues in display panels, the wire-on-array (WOA) area typically uses high-low voltage differential grouping to separate signal traces and prevent corrosion. However, due to the limited space in the WOA area caused by the compression of display panel bezels, the distance between high- and low-voltage differential groups is insufficient. This results in electrochemical corrosion of the signal traces between high and low voltage signals, leading to reduced display panel reliability.

[0005] Therefore, it is necessary to provide a display panel and display device to improve this deficiency.

[0006] In a first aspect, embodiments of this application provide a display panel, including:

[0007] The display panel also includes a display area and a border area disposed on one side of the display area, and further includes:

[0008] Substrate;

[0009] At least two spaced signal trace groups are disposed on the substrate and located in the border area. Each signal trace group includes multiple spaced signal traces, and the signal types transmitted by any two adjacent signal trace groups are different.

[0010] An organic insulating layer is disposed on the signal trace group;

[0011] The organic insulating layer has a linear insulating pattern disposed between adjacent signal trace groups, and the linear insulating pattern is insulatingly separated from the adjacent signal trace groups.

[0012] Secondly, embodiments of this application also provide a display device, the display device including the display panel as described above. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments disclosed. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 is a top view of the display panel provided in an embodiment of this application;

[0015] Figure 2 is an enlarged schematic diagram of point a in Figure 1;

[0016] Figure 3 is an enlarged view of point b in Figure 2;

[0017] Figure 4 is a cross-sectional view of the display panel provided in an embodiment of this application along the A-A' direction;

[0018] Figure 5 is a schematic diagram of the structure of the display device provided in an embodiment of this application. Embodiments of the present invention

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0020] In the description of this application, it should be understood that the terms "upper," "lower," etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0021] Reference numerals and / or reference letters may be repeated in different embodiments of this application. Such repetition is for the purpose of simplification and clarity and does not in itself indicate the relationship between the various implementations and / or settings discussed.

[0022] The embodiments of this application provide a display panel and display device that can solve the problem of signal line corrosion and improve the reliability of the display panel.

[0023] To achieve the above objectives, according to a first aspect of this application, a display panel is provided, comprising:

[0024] The display panel also includes a display area and a border area disposed on one side of the display area, and further includes:

[0025] Substrate;

[0026] At least two spaced signal trace groups are disposed on the substrate and located in the border area. Each signal trace group includes multiple spaced signal traces, and the signal types transmitted by any two adjacent signal trace groups are different.

[0027] An organic insulating layer is disposed on the signal trace group;

[0028] The organic insulating layer has a linear insulating pattern disposed between adjacent signal trace groups, and the linear insulating pattern is insulatingly separated from the adjacent signal trace groups.

[0029] Optionally, the signal trace group includes a first sub-signal trace group and a second sub-signal trace group. The first sub-signal trace group transmits a DC high-voltage signal, and the second sub-signal trace group transmits a DC low-voltage signal. The linear insulation pattern is provided between the first sub-signal trace group and the second sub-signal trace group.

[0030] Optionally, the first sub-signal trace group includes multiple first signal traces, and at least one of the first signal traces has a line width smaller than that of the other first signal traces.

[0031] Optionally, the first signal trace includes a light emission control signal line, the line width of which is smaller than the line width of the other first signal traces.

[0032] Optionally, the linewidth of the light emission control signal line is greater than or equal to 15 micrometers and less than or equal to 25 micrometers, and the linewidth of other first signal traces is greater than or equal to 40 micrometers and less than or equal to 80 micrometers.

[0033] Optionally, the second sub-signal trace group includes multiple second signal traces, and at least one of the second signal traces has a trace width smaller than that of the other second signal traces.

[0034] Optionally, the second sub-signal trace group includes an initial light emission signal line and an output light emission signal line, wherein the line width of at least one of the initial light emission signal line and the output light emission signal line is smaller than the line width of the other second signal traces.

[0035] Optionally, the line width of at least one of the initial light-emitting signal line and the output light-emitting signal line is greater than or equal to 15 micrometers and less than or equal to 25 micrometers, and the line width of the other second signal traces is greater than or equal to 40 micrometers and less than or equal to 80 micrometers.

[0036] Optionally, the signal trace group further includes a third sub-signal trace group, which transmits AC signals. The third sub-signal trace group is located on the side of the first sub-signal trace group away from the second sub-signal trace group, and the linear insulation pattern is provided between the first sub-signal trace group and the third sub-signal trace group.

[0037] Optionally, the third sub-signal trace group includes multiple third signal traces, and the line width of the third signal trace is greater than or equal to the line width of the signal traces in the first sub-signal trace group and the second sub-signal trace group.

[0038] Optionally, the frame area includes a first wiring area, a bending area, a second wiring area, and a terminal area, wherein the first wiring area is disposed between the display area and the bending area, and the second wiring area is disposed between the bending area and the terminal area;

[0039] The first routing area is provided with at least two signal routing groups and a linear insulation pattern located between adjacent signal routing groups; and / or, the second routing area is provided with at least two signal routing groups and a linear insulation pattern located between adjacent signal routing groups.

[0040] Optionally, the display panel further includes at least two connection line groups that correspond one-to-one with the signal line groups. The connection line groups are disposed between the bending area and the terminal area. Each connection line group includes multiple spaced connection lines. The connection line groups are disposed on different layers from the signal line groups. One end of each connection line is used to connect to an integrated circuit chip, and the other end of each connection line is connected to the corresponding signal line.

[0041] Optionally, the display panel includes:

[0042] A gate layer is disposed on the substrate;

[0043] The source and drain layers are disposed on the side of the gate layer away from the substrate;

[0044] The gate layer includes the interconnection line group, and the source / drain layer includes the signal trace group.

[0045] Optionally, the gate layer includes a first sub-gate layer and a second sub-gate layer, the first sub-gate layer is disposed on the substrate, the second sub-gate layer is disposed on the side of the first sub-gate layer away from the substrate, one of any two adjacent connection lines is disposed on the first sub-gate layer, and the other of any two adjacent connection lines is disposed on the second sub-gate layer.

[0046] Optionally, the linear insulation pattern includes grooves that extend along the extension direction of the signal trace.

[0047] Optionally, the organic insulating layer comprises:

[0048] A first planarization layer is disposed on the side of the source / drain layer away from the gate layer;

[0049] The second planarization layer is disposed on the side of the first planarization layer away from the source and drain layers;

[0050] The groove extends through the first planarization layer and the second planarization layer along the film thickness direction of the organic insulating layer.

[0051] Optionally, the display panel further includes an inorganic insulating layer, which is continuously disposed on the surface of the organic insulating layer, the sidewalls of the groove, and the bottom.

[0052] According to a second aspect of this application, a display device is provided, including a display panel as described above.

[0053] In the display panel of this application embodiment, the signal traces in the bezel area are divided into at least two signal trace groups that are spaced apart and transmit different signal types. A linear insulating pattern is formed on the organic insulating layer between adjacent signal trace groups to insulate and separate adjacent signal trace groups, thereby preventing electrochemical corrosion between adjacent signal trace groups that transmit different signal types. This reduces the risk of corrosion of the signal traces in the bezel area and improves the reliability of the display panel.

[0054] An embodiment of this application provides a display panel, which includes a display area and a frame area disposed on one side of the display area. The display panel also includes a substrate, at least two spaced signal trace groups, and an organic insulating layer. The signal trace groups are disposed on the substrate and located in the frame area. Each signal trace group includes multiple spaced signal traces. The signal types transmitted by any two adjacent signal trace groups are different. The organic insulating layer is disposed on the signal trace groups and has a linear insulating pattern disposed on the organic insulating layer. The linear insulating pattern is disposed between adjacent signal trace groups and insulatingly separates the signal trace groups.

[0055] In the embodiments of this application, by dividing the signal traces in the bezel area into at least two spaced signal trace groups that transmit different signal types, and by setting a linear insulating pattern on the organic insulating layer between adjacent signal trace groups, the adjacent signal trace groups are insulated and separated by the linear insulating pattern to prevent electrochemical corrosion between adjacent signal trace groups that transmit different signal types. This reduces the risk of corrosion of the signal traces in the bezel area and improves the reliability of the display panel.

[0056] Please refer to Figures 1 and 2. Figure 1 is a top view of the display panel provided in the embodiment of this application, and Figure 2 is an enlarged schematic diagram of point a in Figure 1. The display panel 100 includes a display area AA and a border area BA disposed on one side of the display area AA.

[0057] Please refer to Figures 3 and 4. Figure 3 is an enlarged schematic diagram of point b in Figure 2, and Figure 4 is a cross-sectional view of the display panel provided in the embodiment of this application along the A-A' direction. The display panel 100 includes a substrate 1, at least two spaced signal trace groups 2, and an organic insulating layer 3. The signal trace groups 2 are disposed on the substrate 1 and located in the bezel area BA. Each signal trace group 2 includes multiple spaced signal traces 20, and the signal types transmitted by any two adjacent signal trace groups 2 are different. The organic insulating layer 3 is disposed on the signal trace groups 2, and a linear insulating pattern 30 is disposed on the organic insulating layer 3. The linear insulating pattern 30 is disposed between adjacent signal trace groups 2 and isolates adjacent signal trace groups 2. This not only avoids signal crosstalk between signal traces transmitting different signal types, but also prevents electrochemical corrosion between adjacent signal trace groups transmitting different signal types, thereby reducing the risk of corrosion of signal traces in the bezel area and improving the reliability of the display panel.

[0058] It should be noted that the signal type can include the voltage level characteristics and directional characteristics of the signal. Each signal trace group 2 is used to transmit signals with corresponding characteristics in order to achieve accurate signal classification and efficient transmission.

[0059] In some embodiments, please refer to Figures 3 and 4. The signal trace group 2 includes a first sub-signal trace group 21 and a second sub-signal trace group 22. The first sub-signal trace group 21 and the second sub-signal trace group 22 are spaced apart. The first sub-signal trace group 21 transmits a DC high-voltage signal, and the second sub-signal trace group 22 transmits a DC low-voltage signal. A linear insulation pattern 30 is provided between the first sub-signal trace group 21 and the second sub-signal trace group 22.

[0060] In some embodiments, referring to Figures 3 and 4, the linear insulating pattern 30 includes a groove 31 extending along the extension direction of the signal trace 20. The groove 31 separates the organic insulating layer 3 above the first sub-signal trace group 21 from the organic insulating layer 3 above the second sub-signal trace group 22, preventing moisture from penetrating through the organic insulating layer 3 above the first sub-signal trace group 21 to the organic insulating layer above the second sub-signal trace group 22. This cuts off the electrochemical corrosion path between the first sub-signal trace group 21 and the second sub-signal trace group 22, thereby reducing the risk of electrochemical corrosion of the first sub-signal trace group 21 and the second sub-signal trace group 22.

[0061] In some embodiments, referring to FIG3, the first sub-signal trace group 21 includes multiple first signal traces 211 arranged side by side with intervals. The line width of at least one first signal trace 211 is smaller than the line width of the other first signal traces 211. By compressing the line width of some of the first signal traces 211, the distance between the first sub-signal trace group 21 and the second sub-signal trace group 22 is increased. This not only reduces the risk of crosstalk between the first sub-signal trace group 21 and the second sub-signal trace group 22, but also facilitates the addition of a groove 31 on the organic insulating layer 3 between the first sub-signal trace group 21 and the second sub-signal trace group 22. The groove 31 is used to isolate the organic insulating layer 3 above the first sub-signal trace group 21 from the organic insulating layer 3 above the second sub-signal trace group 22, thereby reducing the risk of electrochemical corrosion between the first sub-signal trace group 21 and the second sub-signal trace group 22.

[0062] In some embodiments, referring to FIG3, the first sub-signal trace group 21 includes a light-emitting control signal line 2111. The line width of the light-emitting control signal line 2111 is smaller than the line width of other first signal traces 211. By compressing the line width of the light-emitting control signal line 2111, the distance between the first sub-signal trace group 21 and the second sub-signal trace group 22 is increased. This not only reduces the risk of crosstalk between the first sub-signal trace group 21 and the second sub-signal trace group 22, but also facilitates the addition of a linear insulating pattern 30 on the organic insulating layer 3 between the first sub-signal trace group 21 and the second sub-signal trace group 22. The linear insulating pattern 30 is used to isolate the organic insulating layer 3 above the first sub-signal trace group 21 from the organic insulating layer 3 above the second sub-signal trace group 22, thereby reducing the risk of electrochemical corrosion between the first sub-signal trace group 21 and the second sub-signal trace group 22.

[0063] Please refer to Figure 2. The line width of the light emission control signal line 2111 is greater than or equal to 15 micrometers and less than or equal to 25 micrometers, and the line width of the other first signal traces 211 is greater than or equal to 40 micrometers and less than or equal to 85 micrometers.

[0064] In some embodiments, the first signal line 211 may include, but is not limited to, a gate high voltage signal line and an analog signal line, and the light emission control signal line 2111, the gate high voltage signal line and the analog signal line all transmit DC high voltage signals.

[0065] In some embodiments, referring to FIG3, the second sub-signal trace group 22 includes multiple second signal traces 221, which are arranged side by side at intervals. At least one second signal trace 221 has a line width smaller than the line widths of the other second signal traces 221. By compressing the line width of some of the second signal traces 221, the distance between the first sub-signal trace group 21 and the second sub-signal trace group 22 is increased. This not only reduces the risk of crosstalk between the first sub-signal trace group 21 and the second sub-signal trace group 22, but also facilitates the addition of a linear insulating pattern 30 on the organic insulating layer 3 between the first sub-signal trace group 21 and the second sub-signal trace group 22. The linear insulating pattern 30 is used to isolate the organic insulating layer 3 above the first sub-signal trace group 21 from the organic insulating layer 3 above the second sub-signal trace group 22, thereby reducing the risk of electrochemical corrosion between the first sub-signal trace group 21 and the second sub-signal trace group 22.

[0066] In some embodiments, the second sub-signal trace group 22 includes an initial light emission signal line 2211 and an output light emission signal line 2212, wherein the line width of at least one of the initial light emission signal line 2211 and the output light emission signal line 2212 is smaller than the line width of the other second signal traces 221.

[0067] Please refer to Figure 3. The line widths of the initial light emission signal line 2211 and the output light emission signal line 2212 are greater than or equal to 15 micrometers and less than or equal to 25 micrometers, and the line widths of the other second signal lines 221 are greater than or equal to 40 micrometers and less than or equal to 85 micrometers.

[0068] In some embodiments, the second signal line 221 may include, but is not limited to, the gate low voltage signal line, and the light emission initial signal line 2211, the light emission output signal line 2212 and the gate low voltage signal line may all transmit a DC low voltage signal.

[0069] In some embodiments, referring to FIG3, the signal trace group 2 further includes a third sub-signal trace group 23, which transmits AC signals. The third sub-signal trace group 23 is disposed on the side of the first sub-signal trace group 21 away from the second sub-signal trace group 22, and a linear insulation pattern 30 is disposed between the first sub-signal trace group 21 and the third sub-signal trace group 23.

[0070] Please refer to Figures 2 and 3. The groove 31 separates the organic insulating layer 3 above the first sub-signal trace group 21 from the organic insulating layer 3 above the third sub-signal trace group 23, preventing moisture from penetrating through the organic insulating layer 3 above the first sub-signal trace group 21 to the organic insulating layer above the third sub-signal trace group 23. This cuts off the electrochemical corrosion path between the first sub-signal trace group 21 and the third sub-signal trace group 23, thereby reducing the risk of electrochemical corrosion of the first sub-signal trace group 21 and the third sub-signal trace group 23.

[0071] In some embodiments, please refer to FIG3, the third sub-signal trace group 23 includes multiple third signal traces 231, the line width of the third signal traces 231 being greater than or equal to the line width of the signal traces in the first sub-signal trace group 21 and the second sub-signal trace group 22.

[0072] In some embodiments, referring to Figures 1, 2, and 3, the border area BA includes a first routing area WOA1, a bending area BA1, a second routing area WOA2, and a terminal area BA2. The first routing area WOA1 is disposed between the display area AA and the bending area BA1, and the second routing area WOA2 is disposed between the bending area BA1 and the terminal area BA2. The first routing area WOA1 is provided with at least two signal routing groups 2 and a linear insulation pattern 30 located between adjacent signal routing groups 2; and / or, the second routing area WOA2 is provided with at least two signal routing groups 2 and a linear insulation pattern 30 located between adjacent signal routing groups 2.

[0073] In some embodiments, please refer to Figures 1 to 4. The second trace area WOA2 is provided with a first sub-signal trace group 21, a second sub-signal trace group 22 and a third sub-signal trace group 23. A linear insulation pattern 30 is provided between two adjacent signal trace groups 2, which can reduce the risk of electrochemical corrosion of the signal traces in the second trace area WOA2.

[0074] In some other embodiments, the first routing area WOA1 may also be provided with at least two signal routing groups 2 and a linear insulation pattern 30 located between adjacent signal routing groups 2. The arrangement of the signal routing groups 2 and the linear insulation pattern 30 can be referred to the arrangement of the second routing area WOA2 shown in Figure 3, which will not be described in detail here.

[0075] In some embodiments, referring to FIG3, the display panel 100 further includes at least two connection line groups 4 corresponding one-to-one with the signal trace group 2. The connection line groups 4 are disposed between the bending area BA1 and the terminal area BA2. Each connection line group 4 includes multiple spaced connection lines 40. The connection line groups 4 and the signal trace group 2 are disposed on different layers. One end of the connection line 40 is used to connect to the integrated circuit chip 6, and the other end of the connection line 40 is connected to the corresponding signal trace 20. The other end of the signal trace 20 is connected to the terminal of the terminal area BA2. The terminal of the terminal area BA2 is used to bond and connect to the flexible circuit board. In the second trace area WOA2, the signal trace 20 is connected to the connection line 40 through a via, thereby realizing the line switching in the second trace area WOA2.

[0076] In some embodiments, please refer to Figures 3 and 4. The display panel 100 includes a gate layer 7 and a source-drain layer 8. The gate layer 7 is disposed on the substrate 1, and the source-drain layer 8 is disposed on the side of the gate layer 7 away from the substrate 1. The gate layer 7 includes a connection line group 4, and the source-drain layer 8 includes a signal trace group 2.

[0077] In some embodiments, please refer to Figures 3 and 4. The gate layer 7 includes a first gate layer 71 and a second gate layer 72. The first gate layer 71 is disposed on the substrate 1, and the second gate layer 72 is disposed on the side of the first gate layer 71 away from the substrate 1. One of any two adjacent connection lines is disposed on the first gate layer 71, and the other of any two adjacent connection lines is disposed on the second gate layer 72.

[0078] In some embodiments, please refer to Figures 3 and 4. The source-drain layer 8 includes a first source-drain layer 81 and a second source-drain layer (not shown in the figures). The first source-drain layer 81 is disposed on the side of the second gate layer 72 away from the first gate layer 71, and the second source-drain layer is disposed on the side of the first source-drain layer away from the second gate layer 72. The first source-drain layer 81 includes a signal trace group 2.

[0079] In some embodiments, the organic insulating layer 3 includes a first planarization layer 301 and a second planarization layer 302. The first planarization layer 301 is disposed on the side of the source-drain layer away from the gate layer, and the second planarization layer 302 is disposed on the side of the first planarization layer 301 away from the source-drain layer. The groove 31 penetrates the first planarization layer 301 and the second planarization layer 302.

[0080] In some embodiments, referring to FIG4, the display panel 100 further includes an inorganic insulating layer 5. The inorganic insulating layer 5 is continuously disposed on the surface of the organic insulating layer 3, the sidewalls of the groove 31, and the bottom. The inorganic insulating layer 5 covers the surface of the organic insulating layer 3 and the sidewalls and bottom of the groove 31. The inorganic insulating material has good water and oxygen barrier capabilities, which can further prevent water vapor from penetrating through the organic insulating layer 3 above the first sub-signal wiring group 21 to the organic insulating layer above the second sub-signal wiring group 22 or the third sub-signal wiring group 23. This can cut off the electrochemical corrosion path between the first sub-signal wiring group 21 and the second sub-signal wiring group 22 or the third sub-signal wiring group 23, thereby reducing the risk of electrochemical corrosion of the first sub-signal wiring group 21 and the second sub-signal wiring group 22 or the third sub-signal wiring group 23.

[0081] In some embodiments, please refer to FIG4, the inorganic insulating layer 5 includes a first inorganic insulating layer 51 and a second inorganic insulating layer 52 stacked together. The first inorganic insulating layer 51 and the second inorganic insulating layer 52 are both part of the touch layer and are formed by the first touch insulating layer and the second touch insulating layer extending to the border area BA.

[0082] In some embodiments, referring to FIG4, the display panel 100 further includes a cover layer 9 disposed on the surface of the inorganic insulating layer 5 away from the substrate 1.

[0083] In some embodiments, referring to FIG4, the display panel 100 further includes a buffer layer 11, a first gate insulating layer 12, a second gate insulating layer 13, a first interlayer dielectric layer 14, a second interlayer dielectric layer 15, and a passivation layer 16 stacked on the substrate 1.

[0084] Based on the display panel provided in the above embodiments of this application, embodiments of this application also provide a display device. Please refer to FIG5, which is a schematic structural diagram of the display device provided in the embodiments of this application. The display device 1000 includes a display panel 100 and a housing 200, with the display panel 100 disposed on the housing 200. The display panel 100 can be any of the display panels provided in the above embodiments. The display device provided in the embodiments of this application can achieve the same technical effects as the display panel provided in any of the above embodiments, and will not be elaborated upon here.

[0085] The beneficial effects of the embodiments of this application are as follows: The embodiments of this application provide a display panel and a display device. The display panel includes a display area and a bezel area. The display panel also includes a substrate, at least two signal trace groups disposed on the substrate, and an organic insulating layer disposed on the signal trace groups. The signal trace groups are located in the bezel area. Each signal trace group includes multiple signal traces disposed at intervals. Any two adjacent signal trace groups transmit signals of different types. By dividing the signal traces in the bezel area into at least two signal trace groups disposed at intervals and transmitting signals of different types, and by disposing a linear insulating pattern on the organic insulating layer between adjacent signal trace groups to insulate and separate adjacent signal trace groups, electrochemical corrosion can be prevented between adjacent signal trace groups transmitting different signal types. This reduces the risk of corrosion of the signal traces in the bezel area and improves the reliability of the display panel.

[0086] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0087] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0088] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0089] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, comprising a display area and a border area disposed on one side of the display area, the display panel further comprising: Substrate; At least two spaced signal trace groups are disposed on the substrate and located in the border area. Each signal trace group includes multiple spaced signal traces, and the signal types transmitted by any two adjacent signal trace groups are different. An organic insulating layer is disposed on the signal trace group; The organic insulating layer has a linear insulating pattern disposed between adjacent signal trace groups, and the linear insulating pattern is insulatingly separated from the adjacent signal trace groups.

2. The display panel as claimed in claim 1, wherein, The signal trace group includes a first sub-signal trace group and a second sub-signal trace group. The first sub-signal trace group transmits a DC high-voltage signal, and the second sub-signal trace group transmits a DC low-voltage signal. The linear insulation pattern is provided between the first sub-signal trace group and the second sub-signal trace group.

3. The display panel as described in claim 2, wherein, The first sub-signal trace group includes multiple first signal traces, and the trace width of at least one first signal trace is smaller than the trace width of the other first signal traces.

4. The display panel as claimed in claim 3, wherein, The first signal trace includes a light emission control signal line, the line width of which is smaller than the line width of the other first signal traces.

5. The display panel as claimed in claim 4, wherein, The linewidth of the light emission control signal line is greater than or equal to 15 micrometers and less than or equal to 25 micrometers, and the linewidth of the other first signal traces is greater than or equal to 40 micrometers and less than or equal to 80 micrometers.

6. The display panel as claimed in claim 2, wherein, The second sub-signal trace group includes multiple second signal traces, and at least one of the second signal traces has a trace width smaller than that of the other second signal traces.

7. The display panel as claimed in claim 6, wherein, The second sub-signal trace group includes an initial light emission signal line and an output light emission signal line. The line width of at least one of the initial light emission signal line and the output light emission signal line is smaller than the line width of the other second signal traces.

8. The display panel as claimed in claim 7, wherein, The line width of at least one of the initial light-emitting signal line and the output light-emitting signal line is greater than or equal to 15 micrometers and less than or equal to 25 micrometers, and the line width of the other second signal traces is greater than or equal to 40 micrometers and less than or equal to 80 micrometers.

9. The display panel as claimed in claim 2, wherein, The signal trace group further includes a third sub-signal trace group, which transmits AC signals. The third sub-signal trace group is located on the side of the first sub-signal trace group away from the second sub-signal trace group. The linear insulation pattern is provided between the first sub-signal trace group and the third sub-signal trace group.

10. The display panel as claimed in claim 9, wherein, The third sub-signal routing group includes multiple third signal traces, and the line width of the third signal trace is greater than or equal to the line width of the signal traces in the first sub-signal routing group and the second sub-signal routing group.

11. The display panel according to any one of claims 2 to 10, wherein, The frame area includes a first wiring area, a bending area, a second wiring area, and a terminal area. The first wiring area is disposed between the display area and the bending area, and the second wiring area is disposed between the bending area and the terminal area. The first routing area is provided with at least two signal routing groups and the linear insulation pattern located between adjacent signal routing groups; and / or, the second routing area is provided with at least two signal routing groups and the linear insulation pattern located between adjacent signal routing groups.

12. The display panel as claimed in claim 11, wherein, The display panel also includes at least two connection line groups that correspond one-to-one with the signal line groups. The connection line groups are disposed between the bending area and the terminal area. Each connection line group includes multiple spaced connection lines. The connection line groups and the signal line groups are disposed on different layers. One end of the connection line is used to connect to the integrated circuit chip, and the other end of the connection line is connected to the corresponding signal line.

13. The display panel as claimed in claim 12, wherein, The display panel includes: A gate layer is disposed on the substrate; The source and drain layers are disposed on the side of the gate layer away from the substrate; The gate layer includes the interconnection line group, and the source / drain layer includes the signal trace group.

14. The display panel as claimed in claim 13, wherein, The gate layer includes a first sub-gate layer and a second sub-gate layer. The first sub-gate layer is disposed on the substrate, and the second sub-gate layer is disposed on the side of the first sub-gate layer away from the substrate. One of any two adjacent connection lines is disposed on the first sub-gate layer, and the other of any two adjacent connection lines is disposed on the second sub-gate layer.

15. The display panel as claimed in claim 13, wherein, The linear insulation pattern includes grooves that extend along the extension direction of the signal trace.

16. The display panel as claimed in claim 15, wherein, The organic insulating layer comprises: A first planarization layer is disposed on the side of the source / drain layer away from the gate layer; The second planarization layer is disposed on the side of the first planarization layer away from the source and drain layers; The groove extends through the first planarization layer and the second planarization layer along the film thickness direction of the organic insulating layer.

17. The display panel as claimed in claim 16, wherein, The display panel also includes an inorganic insulating layer, which is continuously disposed on the surface of the organic insulating layer, the sidewalls of the groove, and the bottom.

18. A display device comprising a display panel as described in any one of claims 1 to 17.

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