Ramp compensation circuit for DC-DC converter, and DC-DC converter

Abstract

Provided in the present disclosure are a ramp compensation circuit for a DC-DC converter, and a DC-DC converter. The ramp compensation circuit comprises a first current source, a first transistor, a first switch, a first capacitor and a second capacitor; a first terminal of the first current source is coupled to an operating voltage terminal, a second terminal thereof is separately coupled to a first electrode of the first transistor, a first electrode of the first capacitor and a first terminal of the first switch via a first node, and the first current source charges the first capacitor; a clock signal is input at a control electrode of the first transistor, and a second electrode thereof is separately coupled to a second electrode of the first capacitor, a second electrode of the second capacitor and a ground terminal. The first transistor is configured such that, during a first time period of the clock signal, an upper power transistor is turned on, a lower power transistor is turned off, and the first switch is turned off; the first capacitor is first instantaneously short-circuited such that the first capacitor is instantaneously completely discharged, and then the short circuit of the first capacitor is removed, thus generating a first ramp compensation signal at the first node.

Description

Slope compensation circuit for DC-DC converter and DC-DC converter

[0001] Cross-references to related applications

[0002] This disclosure claims priority to Chinese Patent Application No. 2024120004653, filed with the Chinese Patent Office on December 31, 2024, entitled "Slope Compensation Circuit for DC-DC Converter and DC-DC Converter", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of integrated circuit technology, specifically to a slope compensation circuit for a DC-DC converter and a DC-DC converter. Background Technology

[0004] With the expanding integrated circuit market, DC-DC converters have also developed rapidly. As a switching power supply technology, DC-DC converters have advantages such as fast dynamic response and simple control, and have a wide range of applications.

[0005] A DC-DC converter with a constant on-time (COT) architecture determines whether to turn on a power transistor by detecting the difference between the feedback voltage and the reference voltage. After turning on the power transistor, it turns it off after a fixed on-time before turning on another power transistor. Therefore, a large output voltage ripple is usually required. However, as the parasitic series resistance on the output capacitor decreases, the output voltage ripple becomes smaller, which makes it impossible to guarantee the stability of the circuit.

[0006] There is currently no effective technical solution to the problem of circuit stability that cannot be guaranteed in related technologies. Summary of the Invention

[0007] The main objective of this disclosure is to provide a slope compensation circuit for a DC-DC converter and a DC-DC converter.

[0008] To achieve the above objectives, a first aspect of this disclosure provides a slope compensation circuit for a DC-DC converter. The slope compensation circuit is disposed in the DC-DC converter and includes a first current source, a first transistor, a first switch, a first capacitor, and a second capacitor.

[0009] The first end of the first current source is coupled to the working voltage terminal, and the second end of the first current source is coupled to the first terminal of the first transistor, the first terminal of the first capacitor and the first terminal of the first switch via the first node. The first current source is configured to charge the first capacitor.

[0010] The second terminal of the first switch is coupled to the first terminal of the second capacitor;

[0011] The control electrode of the first transistor receives the clock signal, and the second electrode of the first transistor is coupled to the second electrode of the first capacitor, the second electrode of the second capacitor, and the ground terminal. The first transistor is configured such that during the first time period of the clock signal, the upper power transistor in the DC-DC converter is turned on, the lower power transistor is turned off, the first switch is opened, the first capacitor is momentarily short-circuited to discharge the first capacitor momentarily, and then the short circuit to the first capacitor is disconnected, generating a first slope compensation signal at the first node.

[0012] In some embodiments of this disclosure, the slope compensation circuit further includes a second current source, a second transistor, and a third current source;

[0013] The first terminal of the second current source is coupled to the working voltage terminal and the first terminal of the first current source, respectively. The second terminal of the second current source is coupled to the control electrode and the first electrode of the second transistor, respectively. The second current source is configured to charge the second capacitor via the second transistor and the second node.

[0014] The second terminal of the second transistor is coupled to the second terminal of the first switch, the first terminal of the second capacitor, and the first terminal of the third current source via the second node.

[0015] The second terminal of the third current source is coupled to the second terminal of the second capacitor, the second terminal of the first capacitor, the second terminal of the first transistor, and the ground terminal, respectively. The third current source is configured to discharge the second capacitor.

[0016] Furthermore, during the first time interval of the clock signal, the upper power transistor is turned on, the lower power transistor is turned off, the first switch is opened, and a second ramp compensation signal is generated at the second node.

[0017] In some embodiments of this disclosure, during the first time period of the clock signal, the upper power transistor is turned on and the lower power transistor is turned off, the first switch is opened, and the charging current of the second current source to the second capacitor is controlled to be equal to the discharging current of the third current source to the second capacitor, so that the second slope compensation signal remains unchanged at the voltage value of the first slope compensation signal before the upper power transistor is turned on.

[0018] In some embodiments of this disclosure, during the first time period of the clock signal, the upper power transistor is turned on and the lower power transistor is turned off, the first switch is opened, and the charging current of the second current source to the second capacitor is controlled to be less than the discharging current of the third current source to the second capacitor, so that the second capacitor is discharged, and the second slope compensation signal decreases linearly from the voltage value of the first slope compensation signal before the upper power transistor is turned on.

[0019] In some embodiments of this disclosure, when the duty cycle of the clock signal is greater than 0.5, during the first time period of the clock signal, the upper power transistor is turned on and the lower power transistor is turned off, the first switch is opened, and the charging current of the second current source to the second capacitor is controlled to be less than the discharging current of the third current source to the second capacitor, so that the second capacitor is discharged, and the second slope compensation signal is linearly reduced from the voltage value of the first slope compensation signal before the upper power transistor is turned on to 0, and the voltage value of the second slope compensation signal is kept unchanged at 0.

[0020] In some embodiments of this disclosure, during the second time period of the clock signal, the upper power transistor is turned off and the lower power transistor is turned on, the first switch is closed, the second capacitor and the first capacitor are short-circuited, the first capacitor charges the second capacitor, and the voltage of the second capacitor is instantaneously pulled up to be the same as that of the first capacitor, wherein the capacitance value of the first capacitor is much larger than that of the second capacitor.

[0021] In some embodiments of this disclosure, the slope compensation circuit further includes a third transistor;

[0022] The control terminal of the third transistor is coupled to the control terminal and the first terminal of the second transistor, respectively. The first terminal of the third transistor is coupled to the working voltage terminal, and the second terminal of the third transistor is coupled to the voltage divider resistor.

[0023] The second and third transistors form a current mirror, which is configured to proportionally reduce the voltage value of the second slope compensation signal and generate the third slope compensation signal through a voltage divider resistor.

[0024] In some embodiments of this disclosure, the slope compensation circuit further includes a second switch, and the voltage divider resistor includes a first resistor and a second resistor.

[0025] The first terminal of the second switch is coupled to the second terminal of the first current source, and the second terminal of the second switch is coupled to the second terminal of the second current source.

[0026] The first end of the first resistor is coupled to the second terminal of the third transistor. The second end of the first resistor is coupled to the first end of the second resistor via the third node. The second end of the second resistor is coupled to the second terminal of the second capacitor, the second end of the third current source, and the ground terminal, respectively. A third slope compensation signal is generated at the third node.

[0027] The second aspect of this disclosure provides a DC-DC converter, including a slope compensation circuit for a DC-DC converter according to any one of the first aspects above, the DC-DC converter further including a ripple generation circuit, a PWM comparator, an on-time control circuit, a logic circuit, a driver, an upper power transistor, a lower power transistor, an inductor, and an output circuit.

[0028] The output terminal of the slope compensation circuit outputs a slope compensation signal, which is superimposed with the reference voltage to obtain the output signal.

[0029] The output of the ripple generation circuit is a ripple voltage. The ripple voltage and the feedback voltage are superimposed to obtain the comparison signal.

[0030] The non-inverting input of the PWM comparator receives the output signal, the inverting input receives the comparison signal, and the output output sends the control signal to the logic circuit.

[0031] The on-time control circuit is configured to set the turn-on time of the upper power transistor, the logic circuit is configured to output a PWM signal to the driver according to the turn-on time and the control signal, and the driver is configured to drive the upper power transistor and the lower power transistor according to the PWM signal.

[0032] The first end of the inductor is coupled to the first terminal of the upper power transistor and the first terminal of the lower power transistor, respectively, and the second end of the inductor is coupled to the ripple generation circuit and the output circuit, respectively.

[0033] In the slope compensation circuit for a DC-DC converter provided in this disclosure embodiment, the slope compensation circuit includes a first current source, a first transistor, a first switch, a first capacitor, and a second capacitor. The first current source is configured to charge the first capacitor. The first transistor is configured such that, during a first time period of a clock signal, the upper power transistor in the DC-DC converter is turned on, the lower power transistor is turned off, the first switch is opened, the first capacitor is momentarily short-circuited to momentarily and completely discharge the first capacitor, and then the short circuit to the first capacitor is disconnected, generating a first slope compensation signal at the first node. The first transistor in this disclosure generates the first slope compensation signal by momentarily short-circuiting and then disconnecting the first capacitor. Using the first slope compensation signal for compensation can improve the stability of the DC-DC converter circuit and solve the problem of inability to guarantee circuit stability in related technologies. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the specific embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the specific embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 shows the waveform of the compensation signal in the related technology;

[0036] Figure 2 shows the stable waveform under a large duty cycle in the related technology;

[0037] Figure 3 shows the waveform diagram of instability caused by increasing the ramp voltage under a large duty cycle in related technologies;

[0038] Figure 4 is an exemplary circuit diagram of the slope compensation circuit provided in the first embodiment of this disclosure;

[0039] Figure 5 is an exemplary circuit diagram of the slope compensation circuit provided in the second embodiment of this disclosure;

[0040] Figure 6 is an exemplary waveform diagram of the second slope compensation signal provided in an embodiment of this disclosure;

[0041] Figure 7 is an exemplary waveform diagram of the second slope compensation signal under a large duty cycle provided in an embodiment of this disclosure;

[0042] Figure 8 is an exemplary circuit diagram of a DC-DC converter provided in an embodiment of this disclosure. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0044] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0045] In all embodiments of this disclosure, since the source and drain of a metal-oxide-semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, the controlled middle terminal of the MOS transistor is referred to as the control terminal, and the remaining two terminals of the MOS transistor are referred to as the first terminal and the second terminal, respectively. The transistors used in the embodiments of this disclosure are primarily switching transistors. Furthermore, for the sake of consistency, in this context, the base of a bipolar junction transistor (BJT) is referred to as the control terminal, the emitter of the BJT as the first terminal, and the collector of the BJT as the second terminal. Additionally, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0046] A DC-DC converter with a constant on-time (COT) architecture determines whether to turn on a power transistor by detecting the difference between the feedback voltage and the reference voltage. After turning on the power transistor, it turns it off after a fixed on-time before turning on another power transistor. Therefore, a large output voltage ripple is usually required. However, as the parasitic series resistance on the output capacitor decreases, the output voltage ripple becomes smaller, which makes it impossible to guarantee the stability of the circuit.

[0047] To maintain the stability of the DC-DC converter system loop when the output voltage ripple is very small, related technologies employ additional compensation methods. Typically, a ripple voltage Vripple and a ramp voltage Vramp, both in phase with the inductor current, are introduced. Taking the BUCK circuit as an example, the compensation waveform diagram is shown in Figure 1. When the clock signal CLK goes high, it triggers the drive signal MAIN_ON of the upper power transistor, controlling the transistor to turn on. At this time, the inductor is charged, and the inductor current increases. After a fixed period, the drive signal MAIN_ON of the upper power transistor goes low, the inductor discharges, and the inductor current decreases. The ripple voltage Vripple is in the same direction as the inductor current, so it rises when the drive signal MAIN_ON of the upper power transistor is high and falls when it is low. The ramp voltage Vramp is pulled low when the drive signal MAIN_ON of the upper power transistor just goes high, and then gradually rises throughout the cycle, forming a ramp voltage.

[0048] A larger amplitude of the compensated ripple voltage (Vripple) will make the system more stable, but it will also reduce the loop bandwidth and decrease the system's dynamic response, such as its response to load changes. The compensated ramp voltage (Vramp) is generally unaffected by this; increasing the amplitude of the ramp voltage (Vramp) can achieve the same effect as increasing the ripple voltage (Vripple) without significantly affecting the loop bandwidth or sacrificing dynamic performance. However, increasing the ramp voltage (Vramp) can cause other problems. For example, increasing the amplitude of the ramp compensation signal (Vramp) while still keeping it at zero when the clock signal (CLK) arrives may lead to instability.

[0049] Because of the introduction of the ramp voltage Vramp and ripple voltage Vripple, the condition for the clock signal CLK to turn high and turn on the power transistor changes from VFB = VREF to VFB + Vripple = VREF + Vramp. The ramp voltage Vramp is quickly pulled down after the clock signal CLK goes high, ensuring that the above equation is not easily triggered again. Therefore, the clock signal CLK is less likely to erroneously go high immediately after MAIN_ON ends, thus maintaining loop stability. However, for a relatively high duty cycle, such as when the duty cycle is close to 100%, since the input voltage Vin and the output voltage Vout are very close, it takes a long time to charge the inductor Lx. At this time, the clock signal CLK is usually wider, even wider than the MAIN_ON signal. In this case, the system can automatically reduce the frequency to ensure that the inductor is charged with enough energy. An example of a stable waveform under a large duty cycle is shown in Figure 2.

[0050] However, increasing the ramp voltage Vramp amplitude while keeping it pulled down to zero when CLK arrives may lead to instability. Figure 3 shows a waveform diagram illustrating the instability caused by increasing the ramp voltage Vramp under a large duty cycle. Since the condition for CLK to rise is VFB + Vripple = VREF + Vramp, pulling down Vramp makes CLK more likely to drop. This enhances system stability at small duty cycles, but at large duty cycles, because Vin and Vout are relatively close, the charging speed is slow, and the feedback voltage VFB rises slowly. Simultaneously, Vripple rises slowly as Vramp gradually increases. This can cause the above equation to re-establish itself as Vramp gradually rises, causing CLK to rise again. This might happen just as the previous charging cycle ends, but CLK rises again, causing the power transistor to be turned on again for charging, until MAIN_ON goes low and CLK goes low again, at which point charging stops. Continuing in this way will lead to uneven output and system instability.

[0051] Meanwhile, since the slope of the ripple voltage Vripple is related to the input voltage Vin and the output voltage Vout, while the ramp voltage Vramp has a fixed slope, under certain input and output voltages, there are cases where the rising slope of Vripple is similar to that of Vramp. In this situation, after passing CLK, during the rising phase, Vramp and Vripple rise with the same slope. The equation VFB + Vripple = VREF + Vramp then becomes a comparison between the feedback voltage VFB and the reference voltage VREF, which may also lead to instability.

[0052] To address the aforementioned issues, this disclosure provides a slope compensation circuit for a DC-DC converter. An exemplary circuit diagram of the slope compensation circuit is shown in FIG4. The slope compensation circuit is disposed in the DC-DC converter and includes a first current source I1, a first transistor M1, a first switch S1, a first capacitor C1, and a second capacitor C2.

[0053] The first terminal of the first current source I1 is coupled to the working voltage terminal Vdd, and the second terminal of the first current source I1 is coupled to the first terminal of the first transistor M1, the first terminal of the first capacitor C1 and the first terminal of the first switch S1 via the first node N1. The first current source I1 is configured to charge the first capacitor C1.

[0054] The second terminal of the first switch S1 is coupled to the first terminal of the second capacitor C2;

[0055] The control electrode of the first transistor M1 receives the clock signal. The second electrode of the first transistor M1 is coupled to the second electrode of the first capacitor C1, the second electrode of the second capacitor C2, and ground. The first transistor M1 is configured such that during the first time period of the clock signal, the upper power transistor in the DC-DC converter is turned on, the lower power transistor is turned off, the first switch S1 is opened, the first capacitor C1 is momentarily short-circuited to discharge it completely, and then the short circuit is disconnected, generating a first slope compensation signal RAMP1 at the first node N1. The first time period is the period when the upper power transistor is turned on and the lower power transistor is turned off.

[0056] A first current source I1 and a first transistor M1 discharge a first capacitor C1 according to a period determined by a clock signal. The first current source I1 charges the first capacitor C1 and discharges it according to a period determined by a clock signal, generating a first slope compensation signal RAMP1.

[0057] The first transistor in this disclosure generates a first slope compensation signal by momentarily shorting and then disconnecting the first capacitor. Using the first slope compensation signal for compensation can improve the stability of the DC-DC converter circuit and solve the problem of the inability to guarantee circuit stability in related technologies.

[0058] Based on the above embodiments, in an optional implementation of this disclosure, an exemplary circuit diagram of the slope compensation circuit is shown in FIG5. The slope compensation circuit further includes a second current source I2, a second transistor M2, and a third current source I3.

[0059] The first terminal of the second current source I2 is coupled to the working voltage terminal Vdd and the first terminal of the first current source I1 respectively. The second terminal of the second current source I2 is coupled to the control terminal and the first terminal of the second transistor M2 respectively. The second current source I2 is configured to charge the second capacitor C2 via the second transistor M2 and the second node N2.

[0060] The second terminal of the second transistor M2 is coupled to the second terminal of the first switch S1, the first terminal of the second capacitor C2 and the first terminal of the third current source I3 via the second node N2.

[0061] The second terminal of the third current source I3 is coupled to the second terminal of the second capacitor C2, the second terminal of the first capacitor C1, the second terminal of the first transistor M1, and the ground terminal, respectively. The third current source I3 is configured to discharge the second capacitor C2.

[0062] The duty cycle information can be added to the third current source I3. Under a small duty cycle, the current of the third current source I3 is large and it is pulled down quickly, so that the same waveform as the first slope compensation signal RAMP can be obtained. Under a large duty cycle, the current of the third current source I3 is small and it is pulled down slowly, so that the second slope compensation signal RAMP2, which is an improvement on the first slope compensation signal RAMP, can be obtained.

[0063] In one optional embodiment of this disclosure, during the first time period of the clock signal, the upper power transistor is turned on and the lower power transistor is turned off, the first switch S1 is opened, and a second slope compensation signal RAMP2 is generated at the second node N2. Different second slope compensation signals RAMP2 can be generated under different duty cycles or other different conditions of the clock signal.

[0064] In one optional embodiment of this disclosure, during the first time period of the clock signal, the upper power transistor is turned on and the lower power transistor is turned off, the first switch S1 is opened, and the charging current of the second current source I2 to the second capacitor C2 is controlled to be equal to the discharging current of the third current source I3 to the second capacitor C2, so that the second slope compensation signal RAMP2 remains unchanged at the voltage value of the first slope compensation signal RAMP1 before the upper power transistor is turned on.

[0065] When the charging current of the second current source I2 to the second capacitor C2 and the discharging current of the third current source I3 to the second capacitor C2 are equal, the second capacitor C2 neither charges nor discharges, and the second slope compensation signal RAMP2 remains unchanged.

[0066] Figure 6 is an exemplary waveform diagram of a second slope compensation signal provided in an embodiment of this disclosure. In Figure 6, ON is the drive signal or control signal of the upper power transistor, which controls the turning on and off of the upper power transistor. As shown in path 1 of the second slope compensation signal RAMP2 in Figure 6, when the clock signal CLK turns on the upper power transistor, it is not necessary to pull the second slope compensation signal RAMP2 directly low like the first slope compensation signal RAMP1. Instead, it is kept at the original voltage value to avoid the second slope compensation signal RAMP2 being pulled down too quickly, causing the upper power transistor to turn on frequently. When the upper power transistor is off and the lower power transistor is on, the second slope compensation signal RAMP2 rises along with the first slope compensation signal RAMP1, and then the process is repeated periodically.

[0067] When the first switch S1 is turned on, the voltage of the second capacitor C2 is maintained in the previous state, which corresponds to path 1 in Figure 6. If path 2 in Figure 6 is to be achieved, the second capacitor C2 needs to be gradually discharged using the third current source I3.

[0068] In one optional embodiment of this disclosure, during the first time period of the clock signal, the upper power transistor is turned on and the lower power transistor is turned off, the first switch S1 is opened, and the charging current of the second current source I2 to the second capacitor C2 is controlled to be less than the discharging current of the third current source I3 to the second capacitor C2, thereby discharging the second capacitor C2 and causing the second slope compensation signal RAMP2 to decrease linearly from the voltage value of the first slope compensation signal RAMP1 before the upper power transistor is turned on. When the second current source I2 is less than the third current source I3, the second capacitor C2 is discharged.

[0069] As shown in path 2 of the second ramp compensation signal RAMP2 in Figure 6, when the clock signal CLK turns on the upper power transistor, the second ramp compensation signal RAMP2 is not pulled low directly like the first ramp compensation signal RAMP1. Instead, the second capacitor C2 is gradually discharged. Due to the small duty cycle and short discharge time, the second capacitor C2 is not completely discharged, and the second ramp compensation signal RAMP2 is not pulled down to 0. When the upper power transistor is turned off and the lower power transistor is turned on, the second ramp compensation signal RAMP2 rises along with the first ramp compensation signal RAMP1, and then this process is repeated periodically.

[0070] In one optional embodiment of this disclosure, when the duty cycle of the clock signal is greater than 0.5, during the first time period of the clock signal, the upper power transistor is turned on and the lower power transistor is turned off, the first switch S1 is opened, and the charging current of the second current source I2 to the second capacitor C2 is controlled to be less than the discharging current of the third current source I3 to the second capacitor C2, so that the second capacitor C2 is discharged, and the second slope compensation signal RAMP2 linearly decreases from the voltage value of the first slope compensation signal RAMP1 before the upper power transistor is turned on to 0, and the voltage value of the second slope compensation signal RAMP2 remains unchanged at 0.

[0071] When the duty cycle is large, greater than 0.5, for example, when the duty cycle is close to 100%, the second slope compensation signal RAMP2 is pulled down to 0 and held for a period of time. The larger the duty cycle, the longer the discharge time. The larger the duty cycle, the longer the turn-on time of the upper power transistor and the longer the discharge time. The second capacitor is completely discharged to 0 and the voltage value is kept at 0 for a period of time.

[0072] Figure 7 is an exemplary waveform diagram of the second slope compensation signal under a large duty cycle provided in the embodiments of this disclosure, where ON is the drive signal or control signal of the upper power transistor, controlling the opening and closing of the upper power transistor; when the upper power transistor is on, the second slope compensation signal RAMP2 will be gradually discharged to 0 and then remain at 0 until the upper power transistor is off and the lower power transistor is on, at which point the second slope compensation signal RAMP2 will become the same as the value of the first slope compensation signal RAMP1.

[0073] The second slope compensation signal RAMP2 does not have a rapid pull-down process, which can solve the problem of instability caused by rapid pull-down under large duty cycles. Furthermore, since both the ripple voltage RIPPLE and the first slope compensation signal RAMP1 are rising when the upper power transistor is turned on, there may be a problem of the slopes being close, which may cause circuit instability. The second slope compensation signal RAMP2 provided in this embodiment remains unchanged or in a downward state when the ripple voltage RIPPLE rises, which can also avoid instability caused by the close slopes and solve the problem of circuit instability.

[0074] In addition, for applications with a duty cycle close to 100%, the charging speed is very slow when the upper power transistor is turned on because the input voltage Vin and the output voltage Vout are close. However, when the upper power transistor is turned off and the lower power transistor is turned on, the discharge is very fast because the output voltage Vout is very high. Without control, this may lead to a large output ripple. Since the second slope compensation signal RAMP2 is quickly pulled up to the first slope compensation signal RAMP1 when the upper power transistor is turned off and the lower power transistor is turned on, CLK can be generated faster, which is equivalent to shortening the fast discharge time and reducing the output ripple voltage.

[0075] In one optional embodiment of this disclosure, during the second time period of the clock signal, the upper power transistor is off and the lower power transistor is on, the first switch S1 is closed, the second capacitor C2 and the first capacitor C1 are shorted together, the first capacitor C1 charges the second capacitor C2, and the voltage of the second capacitor C2 is instantaneously pulled up to be the same as that of the first capacitor C1, wherein the capacitance value of the first capacitor C1 is much larger than the capacitance value of the second capacitor C2. The second time period is during the period when the upper power transistor is off and the lower power transistor is on; when the lower power transistor is on, the first switch S1 is closed, shorting the second capacitor C2 and the first capacitor C1 together, completing the sampling of the waveform of the first capacitor C1 by the second capacitor C2.

[0076] In Figure 5, the slope compensation circuit also includes a third transistor M3;

[0077] The control terminal of the third transistor M3 is coupled to the control terminal and the first terminal of the second transistor M2, respectively. The first terminal of the third transistor M3 is coupled to the working voltage terminal Vdd, and the second terminal of the third transistor M3 is coupled to the voltage divider resistor.

[0078] The second transistor M2 and the third transistor M3 form a current mirror, which is configured to proportionally reduce the voltage value of the second slope compensation signal RAMP2, and generate the third slope compensation signal RAMP3 through a voltage divider resistor. The third slope compensation signal RAMP3, which is proportionally reduced compared to the second slope compensation signal RAMP2, can be generated using the current mirror and the voltage divider resistor.

[0079] In Figure 5, the slope compensation circuit also includes a second switch S2, and the voltage divider resistors include a first resistor r1 and a second resistor r2.

[0080] The first terminal of the second switch S2 is coupled to the second terminal of the first current source I1, and the second terminal of the second switch S2 is coupled to the second terminal of the second current source I2. The second switch S2 is generally in the open state. Optionally, the first switch S1 and the second switch S2 can be closed, and the second current source I2 and the third current source I3 can be removed to restore the existing first slope compensation signal RAMP1.

[0081] The first end of the first resistor r1 is coupled to the second terminal of the third transistor M3. The second end of the first resistor r1 is coupled to the first end of the second resistor r2 via the third node N3. The second end of the second resistor r2 is coupled to the second terminal of the second capacitor C2, the second end of the third current source I3 and the ground terminal respectively. The third slope compensation signal RAMP3 is generated at the third node N3.

[0082] This disclosure also provides a DC-DC converter 100, as shown in FIG8, including a slope compensation circuit 107 for a DC-DC converter as described above. The DC-DC converter further includes a ripple generation circuit 102, a PWM comparator 103, a conduction time control circuit 104, a logic circuit 105, a driver 106, an upper power transistor Q1, a lower power transistor Q2, an inductor Lx, and an output circuit; wherein, the ripple generation circuit 102, the PWM comparator 103, the conduction time control circuit 104, the logic circuit 105, the driver 106, and the slope compensation circuit 107 constitute a control circuit 110.

[0083] The output terminal of the ramp compensation circuit 107 outputs a ramp compensation signal Vramp. The ramp compensation signal Vramp and the reference voltage VREF are superimposed to obtain the output signal Veao.

[0084] The output terminal of the ripple generation circuit 102 outputs a ripple voltage Vripple. The ripple voltage Vripple and the feedback voltage VFB are superimposed to obtain the comparison signal Vcomp. The output voltage Vout is divided by resistors R1 and R2 to obtain the feedback voltage VFB.

[0085] The non-inverting input terminal of PWM comparator 103 receives the output signal Veao, the inverting input terminal of PWM comparator 103 receives the comparison signal Vcomp, and the output terminal of PWM comparator 103 outputs the control signal CTRL to the logic circuit 105.

[0086] The on-time control circuit 104 is configured to set the on-time Ton of the upper power transistor Q1, and the logic circuit 105 is configured to output a PWM signal to the driver 106 according to the on-time Ton and the control signal CTRL. The driver 106 is configured to drive the upper power transistor Q1 and the lower power transistor Q2 according to the PWM signal.

[0087] The first terminal of inductor Lx is coupled to the first terminal of the upper power transistor Q1 and the first terminal of the lower power transistor Q2, respectively. The second terminal of inductor Lx is coupled to the ripple generation circuit 102 and the output circuit, respectively. The output circuit includes an output capacitor Cout, a parasitic series resistor Resr of the output capacitor Cout, a load resistor RL, a first feedback resistor R1, and a second feedback resistor R2.

[0088] In Figure 8, the output voltage Vout is divided by the first feedback resistor R1 and the second feedback resistor R2 to obtain the feedback voltage VFB. The feedback voltage VFB is sent to the non-inverting input of the PWM comparator 103 through an adder. The ripple generation circuit 102 is configured to obtain a ripple voltage Vripple that is synchronized with and in phase with the inductor current of the DC-DC converter 100. The slope compensation circuit 107 is configured to generate a slope compensation signal Vramp. The on-time control circuit 104 is configured to set the on-time Ton of the power transistor Q1. The non-inverting input of the PWM comparator 103 receives the superimposed signal Veao of the reference voltage VREF and the slope compensation signal Vramp, and the inverting input of the PWM comparator 103 receives the ripple signal Vramp. The compensation signal Vcomp is the superposition of the wave voltage Vripple and the feedback voltage VFB. The PWM comparator 103 is configured to compare the signal Veao and the signal Vcomp to generate the conduction control signal CTRL, where Vcomp = Vripple + VFB and Veao = Vramp + VREF. The conduction time control circuit 104 is configured to set the turn-on time Ton of the upper power transistor Q1. The logic circuit 105 is configured to output the PWM signal to the driver 106 according to the turn-on time Ton and the control signal CTRL. The driver 106 is configured to generate the drive signal MAIN_ON for driving the upper power transistor Q1 and the drive signal for driving the lower power transistor Q2 according to the pulse width modulation signal PWM. When the COT-controlled DC-DC converter 100 detects that the output voltage Vout is low, it sends a trigger signal to turn on the main switch (i.e., the upper power transistor Q1) of the DC-DC converter. After the set on time Ton, the upper power transistor Q1 is turned off again. Then, after the set minimum off time Toff-min, if the PWM comparator 103 detects that the output voltage Vout is low again, it triggers the upper power transistor Q1 to turn on again, and the cycle repeats.

[0089] As can be seen from the above description, this disclosure achieves the following technical effects:

[0090] The first transistor in this disclosure generates a first slope compensation signal by momentarily shorting and then disconnecting the first capacitor. Using the first slope compensation signal for compensation can improve the stability of the DC-DC converter circuit and solve the problem of the inability to guarantee circuit stability in related technologies.

[0091] The second slope compensation signal provided in this disclosure does not have a rapid pull-down process, which can solve the problem of instability caused by rapid pull-down under large duty cycles; the second slope compensation signal remains unchanged or downward when the ripple voltage rises, which can avoid instability caused by close slopes and solve the problem of circuit instability.

[0092] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatuses and methods according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0093] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusive. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0094] Further aspects and scope will become apparent from the description provided herein. It should be understood that various aspects of this disclosure may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are intended for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0095] Although embodiments of the present disclosure have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present disclosure, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A slope compensation circuit for a DC-DC converter, wherein, The slope compensation circuit is disposed in the DC-DC converter, and the slope compensation circuit includes a first current source, a first transistor, a first switch, a first capacitor and a second capacitor. The first end of the first current source is coupled to the working voltage terminal, and the second end of the first current source is coupled to the first terminal of the first transistor, the first terminal of the first capacitor and the first terminal of the first switch via the first node. The first current source is configured to charge the first capacitor. The second terminal of the first switch is coupled to the first terminal of the second capacitor; The control electrode of the first transistor receives a clock signal, and the second electrode of the first transistor is coupled to the second electrode of the first capacitor, the second electrode of the second capacitor, and ground. The first transistor is configured such that during the first time period of the clock signal, the upper power transistor in the DC-DC converter is turned on, the lower power transistor is turned off, the first switch is opened, the first capacitor is momentarily short-circuited to discharge the first capacitor momentarily, and then the short circuit to the first capacitor is disconnected, generating a first slope compensation signal at the first node.

2. The slope compensation circuit for a DC-DC converter according to claim 1, wherein the slope compensation circuit further comprises a second current source, a second transistor, and a third current source; The first terminal of the second current source is coupled to the working voltage terminal and the first terminal of the first current source, and the second terminal of the second current source is coupled to the control electrode and the first electrode of the second transistor, respectively. The second current source is configured to charge the second capacitor via the second transistor and the second node. The second terminal of the second transistor is coupled to the second terminal of the first switch, the first terminal of the second capacitor, and the first terminal of the third current source via the second node. The second terminal of the third current source is coupled to the second terminal of the second capacitor, the second terminal of the first capacitor, the second terminal of the first transistor, and the ground terminal, respectively. The third current source is configured to discharge the second capacitor.

3. The ramp compensation circuit for a DC-DC converter according to claim 2, wherein during the first time period of the clock signal, the upper power transistor is turned on, the lower power transistor is turned off, the first switch is opened, and a second ramp compensation signal is generated at the second node.

4. The ramp compensation circuit for a DC-DC converter according to claim 3, wherein during the first time period of the clock signal, the upper power transistor is turned on and the lower power transistor is turned off, the first switch is opened, and the charging current of the second current source to the second capacitor is controlled to be equal to the discharging current of the third current source to the second capacitor, so that the second ramp compensation signal remains unchanged at the voltage value of the first ramp compensation signal before the upper power transistor is turned on.

5. The slope compensation circuit for a DC-DC converter according to claim 3, wherein during the first time period of the clock signal, the upper power transistor is turned on and the lower power transistor is turned off, the first switch is opened, the charging current of the second current source to the second capacitor is controlled to be less than the discharging current of the third current source to the second capacitor, and the second capacitor is discharged, so that the second slope compensation signal decreases linearly from the voltage value of the first slope compensation signal before the upper power transistor is turned on.

6. The slope compensation circuit for a DC-DC converter according to claim 3, wherein when the duty cycle of the clock signal is greater than 0.5, during the first time period of the clock signal, the upper power transistor is turned on and the lower power transistor is turned off, the first switch is opened, the charging current of the second current source to the second capacitor is controlled to be less than the discharging current of the third current source to the second capacitor, and the second capacitor is discharged, so that the voltage value of the second slope compensation signal decreases linearly from the voltage value of the first slope compensation signal before the upper power transistor is turned on to 0, and the voltage value of the second slope compensation signal remains unchanged at 0.

7. The ramp compensation circuit for a DC-DC converter according to claim 2, wherein during the second time period of the clock signal, the upper power transistor is off, the lower power transistor is on, the first switch is closed, the second capacitor and the first capacitor are short-circuited, the first capacitor charges the second capacitor, and the voltage of the second capacitor is instantaneously pulled up to be the same as that of the first capacitor, wherein, The capacitance of the first capacitor is much greater than that of the second capacitor.

8. The slope compensation circuit for a DC-DC converter according to claim 2, wherein the slope compensation circuit further comprises a third transistor; The control terminal of the third transistor is coupled to the control terminal and the first terminal of the second transistor, respectively. The first terminal of the third transistor is coupled to the working voltage terminal, and the second terminal of the third transistor is coupled to a voltage divider resistor. The second transistor and the third transistor form a current mirror, which is configured to proportionally reduce the voltage value of the second slope compensation signal and generate a third slope compensation signal through the voltage divider resistor.

9. The slope compensation circuit for a DC-DC converter according to claim 8, wherein the slope compensation circuit further comprises a second switch, and the voltage divider resistor comprises a first resistor and a second resistor; The first terminal of the second switch is coupled to the second terminal of the first current source, and the second terminal of the second switch is coupled to the second terminal of the second current source. The first end of the first resistor is coupled to the second terminal of the third transistor, the second end of the first resistor is coupled to the first end of the second resistor via a third node, and the second end of the second resistor is coupled to the second terminal of the second capacitor, the second end of the third current source and the ground terminal, respectively, and the third slope compensation signal is generated at the third node.

10. A DC-DC converter, comprising the slope compensation circuit for a DC-DC converter as described in any one of claims 1 to 9, wherein the DC-DC converter further comprises a ripple generation circuit, a PWM comparator, an on-time control circuit, a logic circuit, a driver, an upper power transistor, a lower power transistor, an inductor, and an output circuit; The output terminal of the slope compensation circuit outputs a slope compensation signal, which is superimposed with the reference voltage to obtain the output signal. The output terminal of the ripple generation circuit outputs a ripple voltage, which is superimposed with the feedback voltage to obtain a comparison signal. The output signal is input to the non-inverting input terminal of the PWM comparator, the comparison signal is input to the inverting input terminal of the PWM comparator, and the output terminal of the PWM comparator outputs a control signal to the logic circuit. The on-time control circuit is configured to set the on-time of the upper power transistor, the logic circuit is configured to output a PWM signal to the driver according to the on-time and the control signal, and the driver is configured to drive the upper power transistor and the lower power transistor according to the PWM signal. The first end of the inductor is coupled to the first terminal of the upper power transistor and the first terminal of the lower power transistor, respectively, and the second end of the inductor is coupled to the ripple generation circuit and the output circuit, respectively.

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