Display substrate, intermediate display substrate, and display device

Abstract

A display substrate, an intermediate display substrate, and a display device. The display substrate comprises: a substrate, comprising a display area (100) and a peripheral area (300) surrounding the display area (100), the peripheral area (300) comprising a binding area (200) located on one side of the display area (100); a plurality of sub-pixels, located in the display area (100); a plurality of power pins, located in the binding area (200) and electrically connected to the plurality of sub-pixels, the plurality of power pins being configured to transmit a power signal to the plurality of sub-pixels; and a plurality of power test connection lines (40), located on the side of the plurality of power pins distant from the display area (100) and connected to the plurality of power pins, at least one of the plurality of power test connection lines (40) being made of at least one of titanium and aluminum.

Description

Display substrate, intermediate display substrate and display device

[0001] This application claims priority to Chinese Patent Application No. 202510005695.0, filed on January 2, 2025, entitled “Display Substrate, Intermediate Display Substrate and Display Device”, the contents of which are to be understood as incorporated herein by reference. Technical Field

[0002] This article relates to, but is not limited to, the field of display technology, and in particular to a display substrate, an intermediate display substrate, and a display device. Background Technology

[0003] Organic light-emitting diodes (OLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, and extremely fast response speed. With the continuous development of display technology, display devices that use OLEDs as light-emitting elements and are controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a display substrate, an intermediate display substrate, and a display device.

[0006] On one hand, embodiments of this disclosure provide a display substrate, including:

[0007] A substrate includes a display area and a peripheral area surrounding the display area, the peripheral area including a bonding area located on one side of the display area;

[0008] Multiple sub-pixels are located in the display area;

[0009] Multiple power pins are located in the bonding area and electrically connected to the multiple sub-pixels, and the multiple power pins are configured to transmit power signals to the multiple sub-pixels;

[0010] Multiple power test connection lines are located on the side of the multiple power pins away from the display area and connected to the multiple power pins. At least one of the multiple power test connection lines is made of at least one of titanium and aluminum.

[0011] In some exemplary embodiments, the plurality of power test connection lines are connected one-to-one with the plurality of power pins.

[0012] In some exemplary embodiments, the at least one power test connection line includes a first sub-section and a second sub-section stacked together, wherein the first sub-section and the second sub-section are located on different layers, and the first sub-section is closer to the substrate than the second sub-section.

[0013] In some exemplary embodiments, the orthographic projection of the second sub-part onto the plane where the substrate is located includes the orthographic projection of the first sub-part onto the plane where the substrate is located, and the orthographic projection area of ​​the second sub-part onto the plane where the substrate is located is greater than the orthographic projection area of ​​the first sub-part onto the plane where the substrate is located.

[0014] In some exemplary embodiments, the first sub-part includes a plurality of spaced-apart first connecting portions, at least a portion of the surface of the plurality of first connecting portions on the side away from the substrate contacts the second sub-part; or, the second sub-part includes a plurality of spaced-apart second connecting portions, at least a portion of the surface of the plurality of second connecting portions on the side near the substrate contacts the first sub-part; or, the first sub-part includes a plurality of spaced-apart first connecting portions, and the second sub-part includes a plurality of spaced-apart second connecting portions, at least a portion of the surface of the first connecting portions on the side away from the substrate contacts at least a portion of the surface of the second connecting portions on the side near the substrate.

[0015] In some exemplary embodiments, at least a portion of at least one of the plurality of first connecting portions has a straight orthographic projection onto the plane where the substrate is located; or, at least a portion of at least one of the plurality of first connecting portions has a curved orthographic projection onto the plane where the substrate is located.

[0016] In some exemplary embodiments, at least one of the plurality of first connecting portions includes at least one of a protrusion and a recess; the protrusion protrudes in a direction away from the substrate, and the recess is recessed in a direction closer to the substrate.

[0017] In some exemplary embodiments, the at least one first connecting portion includes a plurality of protrusions and a plurality of recesses; the plurality of protrusions and the plurality of recesses are arranged alternately in sequence.

[0018] In some exemplary embodiments, in a direction perpendicular to the plane where the substrate is located, the bonding region includes a first source / drain metal layer, a first planarization layer, a second source / drain metal layer, and a second planarization layer stacked sequentially, wherein the first sub-part is located in the first source / drain metal layer, and the second sub-part is located in the second source / drain metal layer;

[0019] The first planarization layer has at least one groove that exposes at least a portion of the surface of the first sub-part away from the substrate, and at least a portion of the second sub-part is located within the groove and in contact with the first sub-part; the orthographic projection of the second planarization layer onto the plane of the substrate includes the orthographic projections of the first sub-part and the second sub-part onto the plane of the substrate.

[0020] In some exemplary embodiments, the first sub-part includes a plurality of spaced-apart first connecting parts, each first connecting part including a top wall, a bottom wall and a side wall connected to each other; the top wall is farther from the substrate than the bottom wall, and the side wall is located between the top wall and the bottom wall; the second sub-part is in contact with the top wall, bottom wall and side wall of at least one of the first connecting parts.

[0021] In some exemplary embodiments, the bonding region further includes at least one bonding pin group and at least one first aging pin group; the bonding pin group and the first aging pin group are arranged side by side along a first direction, the first direction being parallel to the plane of the substrate.

[0022] In some exemplary embodiments, at least one of the plurality of sub-pixels includes a transistor, a first planarization layer, a transition electrode, a second planarization layer, and a light-emitting device, wherein the first planarization layer is located on the side of the transistor away from the substrate and covers the transistor, the transition electrode is located on the side of the first planarization layer away from the substrate, and the light-emitting device is located on the side of the second planarization layer away from the substrate;

[0023] The transistor includes an active layer on the substrate, a gate on the side of the active layer away from the substrate, and a source and a drain on the side of the gate away from the substrate. One of the source and the drain is electrically connected to the transition electrode through a via provided in the first planarization layer. The light-emitting device is electrically connected to the transition electrode through a via provided in the second planarization layer.

[0024] The first sub-section is located on the same layer as the source or the drain, and the second sub-section is located on the same layer as the transition electrode.

[0025] In some exemplary embodiments, a plurality of first power lines are also included, the plurality of first power lines being located in the display area and electrically connected to the plurality of sub-pixels, the plurality of first power lines being configured to provide a first voltage signal to the plurality of sub-pixels;

[0026] A first power bus is located in the binding area and is electrically connected to the plurality of first power lines;

[0027] A second power cord is located in the surrounding area and partially surrounds the display area;

[0028] The plurality of power supply pins include at least a first power supply pin and a second power supply pin. The first power supply pin is connected to the first power bus and configured to transmit the first voltage signal to the first power bus. The second power supply pin is connected to the second power line and configured to transmit a second voltage signal to the second power line.

[0029] In some exemplary embodiments, the plurality of power test connection lines include a first power test connection line and a second power test connection line, wherein the first power pin is connected to the first power test connection line and the second power pin is connected to the second power test connection line.

[0030] On the other hand, this disclosure provides an intermediate display substrate, including the display substrate described in any of the above embodiments and a plurality of power test pins located on the side of the plurality of power pins away from the display area; the intermediate display substrate includes a substrate area and a first cutting area located on one side of the substrate area, the first cutting area being located on the side of the bonding area away from the display area, the display substrate being located in the substrate area, and the plurality of power test pins being located in the first cutting area;

[0031] The multiple power test connection lines are located between and connect the multiple power pins and the multiple power test pins.

[0032] In some exemplary embodiments, the plurality of power test connection lines are connected one-to-one with the plurality of power test pins; the plurality of power test connection lines include a first power test connection line and a second power test connection line, and the plurality of power pins include a first power pin and a second power pin;

[0033] The plurality of power test pins include a first power test pin and a second power test pin. The first power test pin is connected to the first power test pin via a first power test connection line; the second power test pin is connected to the second power test pin via a second power test connection line.

[0034] In some exemplary embodiments, at least one second aging pin group is also included, the second aging pin group being located in the first dicing region, the second aging pin group including at least one second aging pin, the second aging pin and the power test pin being arranged side by side along a first direction, the first direction being parallel to the plane of the substrate.

[0035] On the other hand, embodiments of this disclosure provide a display device including the display substrate described in any of the foregoing embodiments.

[0036] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0037] Overview of the attached figures

[0038] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0039] Figure 1 is a schematic diagram of the structure of a display device according to an embodiment of the present disclosure;

[0040] Figure 2 is a plan view of a display substrate according to an embodiment of the present disclosure;

[0041] Figure 3 is a schematic diagram of the arrangement of multiple display substrates in a display motherboard according to an embodiment of the present disclosure;

[0042] Figure 4A is a plan view of an intermediate display substrate according to an embodiment of the present disclosure;

[0043] Figure 4B is a plan view of a display substrate according to an embodiment of the present disclosure;

[0044] Figure 5 is a partial cross-sectional schematic diagram of a sub-pixel of a display area according to an embodiment of the present disclosure;

[0045] Figure 6 is a magnified view of part A marked in Figure 4A;

[0046] Figure 7 is a partially enlarged schematic diagram of an embodiment marked B in Figure 6;

[0047] Figure 8 is a partially enlarged schematic diagram of another embodiment marked B in Figure 6;

[0048] Figure 9 is a partially enlarged schematic diagram of another embodiment marked B in Figure 6;

[0049] Figure 10 is a cross-sectional schematic diagram of an embodiment marked CC in Figure 7;

[0050] Figure 11 is a cross-sectional schematic diagram of another embodiment marked CC in Figure 7;

[0051] Figure 12 is a cross-sectional schematic diagram of an embodiment marked DD in Figure 8.

[0052] Detailed Explanation

[0053] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be changed to one or more forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0054] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0055] The ordinal numbers such as "first," "second," and "third" in this disclosure are used to avoid confusion among the constituent elements, not to limit the quantity. "Multiple" in this disclosure includes two or more quantities.

[0056] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately changed depending on the direction in which the constituent elements are described. Therefore, the description is not limited to the terms used in the specification and may be appropriately replaced as appropriate.

[0057] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0058] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0059] In this disclosure, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0060] In this disclosure, "electrical connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission of electrical signals between the connected constituent elements. Examples of "component having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components having one or more functions.

[0061] In this disclosure, "parallel" refers to a state in which the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore can include a state in which the angle is greater than or equal to -5° and less than 5°. Furthermore, "perpendicular" refers to a state in which the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore can include a state in which the angle is greater than or equal to 85° and less than 95°.

[0062] In this disclosure, the terms "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be replaced with "conductive film". Similarly, sometimes "insulating film" can be replaced with "insulating layer".

[0063] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0064] Figure 1 is a schematic diagram of a display device according to an embodiment of the present disclosure. As shown in Figure 1, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple light-emitting signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, provide clock signals, scan start signals, etc. of specifications suitable for the scan driver to the scan driver, and provide clock signals, transmit stop signals, etc. of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn in pixel rows, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The light-emitting driver can generate transmit signals to be provided to light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from the timing controller. For example, the light-emitting driver can sequentially provide transmit signals with cutoff level pulses to the light-emitting signal lines E1 to Eo. For example, the light-emitting driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals in the form of cutoff level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number. In an exemplary embodiment, a pixel array can be disposed on a display substrate.

[0065] Figure 2 is a planar schematic diagram of a display substrate according to an embodiment of the present disclosure. As shown in Figure 2, the display substrate may include a substrate, a display area 100 located on the substrate, and a peripheral area 300 located on the substrate and surrounding the display area 100. The peripheral area 300 may include a bonding area 200 located on one side of the display area 100 and a border area located on other sides of the display area 100. For example, the bonding area 200 may be the lower border of the display substrate, and the border areas may include the upper border, left border, and right border of the display substrate. In some examples, the display area 100 may be a flat area, and the display area 100 may include a plurality of sub-pixels Pxij constituting a pixel array, the plurality of sub-pixels Pxij being configured to display moving images or still images. In some examples, the display substrate may be a flexible substrate, and thus the display substrate may be deformable, such as rolled, bent, folded, or rolled up.

[0066] In some exemplary embodiments, as shown in FIG2, the display area 100 may include at least a plurality of scan signal lines (S1 to Sm) and a plurality of data signal lines (D1 to Dn). The plurality of scan signal lines may extend along a first direction X, and the plurality of data signal lines may extend along a second direction Y. The first direction X and the second direction Y may intersect, and the plane formed by the first direction X and the second direction Y is parallel to the plane of the substrate; alternatively, the first direction X and the second direction Y may be perpendicular to each other. The orthographic projections of the plurality of scan signal lines and the plurality of data signal lines onto the plane of the substrate intersect to form a plurality of sub-pixel regions, each sub-pixel region containing one sub-pixel. The plurality of data signal lines are electrically connected to the plurality of sub-pixels, and the plurality of data signal lines may be configured to provide data signals to the plurality of sub-pixels. For example, portions of the plurality of data signal lines may extend to the bonding area 200. The plurality of scan signal lines are electrically connected to the plurality of sub-pixels, and the plurality of scan signal lines may be configured to provide gate control signals to the plurality of sub-pixels. In some examples, the gate control signals may include scan signals and light emission control signals.

[0067] In some exemplary embodiments, the display area 100 itself may be symmetrical about a centerline O extending along the second direction Y. For example, the bonding area 200 may be symmetrical about the centerline O. For example, the border area may be symmetrical about the centerline O. For example, the display substrate may be symmetrical about the centerline O. The centerline O may be a straight line that bisects the display area in the first direction X and extends along the second direction Y.

[0068] In some exemplary embodiments, the display area 100 includes a plurality of pixel units, and each pixel unit may include three sub-pixels, namely a red sub-pixel, a green sub-pixel, and a blue sub-pixel. However, this disclosure is not limited thereto. In some examples, a pixel unit may include four sub-pixels, namely a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel.

[0069] In some exemplary embodiments, the shape of a sub-pixel can be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes three sub-pixels, the three sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement. When a pixel unit includes four sub-pixels, the four sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement. However, the embodiments of this disclosure are not limited in this respect.

[0070] In some exemplary embodiments, a sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is connected to a scan signal line, a light-emitting signal line, and a data signal line, respectively. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. The pixel driving circuit may include multiple transistors and at least one capacitor. For example, the pixel driving circuit may be a 3T1C structure, a 7T1C structure, or a 5T1C structure, etc., where the number before the T represents the number of transistors in the pixel driving circuit, and the number before the C represents the number of capacitors in the pixel driving circuit.

[0071] In some exemplary embodiments, the light-emitting device can be any of a light-emitting diode, an organic light-emitting diode, a quantum dot light-emitting diode, or a micro-LED (including mini-LED or micro-LED). For example, the light-emitting device can be an OLED, which can emit red, green, blue, or white light under the drive of its corresponding pixel driving circuit. In some examples, the light-emitting device may include an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting device can be electrically connected to the corresponding pixel driving circuit.

[0072] In some exemplary embodiments, the bezel area may include a circuit area, a power line area, a crack dam area, and a cutting area sequentially arranged along the direction of the display area 100. The circuit area may be connected to the display area 100 and may include at least gate driving circuitry (e.g., including multiple cascaded shift registers), which may be electrically connected to multiple scan signal lines in the display area 100. The power line area is connected to the circuit area and may include at least low-level power lines extending parallel to the edge of the display area and connected to a cathode located in the display area 100. The crack dam area is connected to the power line area and may include at least multiple cracks formed on a composite insulating layer. The cutting area is connected to the crack dam area and may include at least cutting grooves formed on the composite insulating layer. These cutting grooves may be configured to cut along the cutting grooves after all film layers of the display substrate have been prepared.

[0073] In some exemplary embodiments, the binding area 200 and the border area may be provided with a first isolation dam and a second isolation dam. The first isolation dam and the second isolation dam may extend along a direction parallel to the edge of the display area and form a ring structure surrounding the display area 100. The edge of the display area is the edge of the display area close to the binding area and the border area.

[0074] Figure 3 is a schematic diagram of the arrangement of multiple display substrates in a display motherboard according to an embodiment of the present disclosure. As shown in Figure 3, the display motherboard may include multiple substrate regions 400 arranged in a periodic and regular pattern, and a cutting region 500 located outside the substrate regions 400. The substrate regions 400 include at least the display substrates, and the cutting region 500 may be provided with a first cutting track 501 and a second cutting track 502. After all the film layers of the display motherboard are prepared, the cutting equipment can perform rough cutting and fine cutting along the first cutting track 501 and the second cutting track 502, respectively. Fine cutting can also be referred to as module cutting.

[0075] In some possible exemplary embodiments, for a display motherboard, a coarse cutting process can be performed along the EAC (Even After Cell) cutting line to divide the display motherboard into multiple intermediate display substrates (e.g., an intermediate display substrate may include a substrate area, a first cutting area, and a second cutting area). Then, each intermediate display substrate undergoes a lamp-on detection and aging stage. After the detection and aging stages are completed, a fine cutting process can be performed along the module (MDL) cutting line of the intermediate display substrate. Subsequently, a circuit board is bonded onto the intermediate display substrate. In one example, the intermediate display substrate with the circuit board bonded can be edge-cut to obtain the display substrate.

[0076] In some implementations, multiple tests are required during the fabrication of the display substrate. One important test is the Cell Test (CT) Light-on, also known as the ET Light-on test. ET Light-on testing is performed before the display substrate is bonded to the circuit board. A test signal is input to the display substrate, causing its sub-pixels to display color. A defect detection device then checks the quality of each sub-pixel to confirm the presence of defects in the display substrate. Because the fabricated light-emitting devices may have interface instability, another important process for the display substrate is the aging process. The aging process, also known as the aging stage, is a necessary process before the display device is shipped. By illuminating the light-emitting devices with a certain current for a period of time, interface instability is aged out, reducing brightness decay and increasing the lifespan of the light-emitting devices.

[0077] During the aging process, the test current passes through the source / drain metal layer and the gate metal layer. Since the test current for the first power supply voltage (VDD) and the second power supply voltage (VSS) of medium to large-sized display substrates is relatively large, when this large current flows through the high-resistivity gate metal layer, the high resistance of the gate metal layer material (typically molybdenum) generates significant heat at the gate metal layer of the display substrate, potentially causing burn-off damage.

[0078] This disclosure provides a display substrate, including:

[0079] A substrate includes a display area and a peripheral area surrounding the display area, the peripheral area including a bonding area located on one side of the display area;

[0080] Multiple sub-pixels are located in the display area;

[0081] Multiple power pins are located in the bonding area and electrically connected to the multiple sub-pixels, and the multiple power pins are configured to transmit power signals to the multiple sub-pixels;

[0082] Multiple power test connection lines are located on the side of the multiple power pins away from the display area and connected to the multiple power pins. At least one of the multiple power test connection lines is made of at least one of titanium and aluminum.

[0083] In this embodiment of the disclosure, by setting the material of at least one of the multiple power test connection lines to include at least one of titanium and aluminum, since titanium and aluminum have low resistance, excessive heat can be avoided during the testing of the power pins, thus preventing the display substrate from being burned.

[0084] Figure 4A is a plan view of an intermediate display substrate according to an embodiment of the present disclosure. As shown in Figure 4A, only one substrate region 400 is shown. The substrate region 400 may include a display substrate, which may include a substrate, a display region 100, and a peripheral region 300 surrounding the display region 100. The peripheral region 300 may include a bonding region 200 located on one side of the display region 100. The cutting region 500 may be located outside the substrate region 400. For example, the cutting region 500 may include a first cutting region 50a located on the side of the bonding region 200 away from the display region 100. The cutting regions on the other sides of the substrate region are omitted in the embodiments of the present disclosure. The intermediate display substrate is the structure before cutting during the manufacturing process of the display substrate. After completing the lamp detection and aging process, the first cutting region 50a of the intermediate display substrate can be cut off according to the cutting line L1 to obtain the display substrate, as shown in Figure 4B.

[0085] The display substrate can be a flexible substrate or a rigid substrate. Taking a flexible substrate as an example, along the direction away from the display area 100, the bonding area 200 can include a sub-bezel area 201 and a bonding pin area 202. The bonding pin area 202 can be located on the side of the sub-bezel area 201 away from the display area 100. The sub-bezel area 201 can include a first fan-out area 201a, a bending area 201b, a second fan-out area 201c, a first circuit area 201d, a third fan-out area 201e, and a driver chip area 201f arranged sequentially. The first fan-out area 201a can be connected to the display area 100, and can include at least a portion of the first power bus 70, the second power line 72, and a portion of multiple data signal lines (D1 to Dn), which are configured to extend from the data signal lines of the display area in a fan-out routing manner. The first power bus 70 of the first fan-out area 201a can be configured to connect to the first power line 71 of the display area 100, which is a high-level power line or a positive voltage power line, and the second power line 72, which is a low-level power line or a negative voltage power line, located in the peripheral area 300 and partially surrounding the display area 100. The bending area 201b can be connected to the second fan-out area 201c and may include a composite insulating layer with grooves, which can be configured to bend a portion of the bonding area 200 to the back of the display area 100. The second fan-out area 201c may include multiple fan-out traces. The first circuit area 201d may include at least an electrostatic discharge (ESD) circuit 16, which can be configured to prevent ESD damage to the display substrate by eliminating static electricity. The third fan-out area 201e may include multiple fan-out traces. The driver chip area 201f can house a driver chip 17 (Integrated Circuit, IC). The driver chip 17 can be electrically connected to the data signal lines (D1 to Dn) of the display area 100 via fan-out traces. The driver chip 17 can be configured to generate drive signals required to drive sub-pixels Pxij and provide different drive signals to multiple sub-pixels Pxij of the display area 100. For example, the drive signals can be data signals transmitted through the data signal lines (D1 to Dn) or clock signals transmitted through the clock signal lines of the GOA. The pin bonding area 202 can be provided with multiple pins, including multiple access pins, multiple first aging pins, and multiple power supply pins.

[0086] In some exemplary embodiments, the gate drive circuit may include multiple cascaded shift registers GOA0, GOA1…GOAn, which may be electrically connected to multiple scan signal lines (S1 to Sm) in the display area 100. Multiple gate drive signal lines GSTV, GCK, GCB are electrically connected to the gate drive circuit, and each shift register is electrically connected to one scan signal line.

[0087] Figure 5 is a partial cross-sectional schematic diagram of a sub-pixel of a display area according to an embodiment of the present disclosure. Figure 5 is a cross-sectional schematic diagram of the area marked PP in Figure 4A, and Figure 5 illustrates the structure of one sub-pixel of the display area as an example. Figure 5 illustrates the pixel driving circuit of each sub-pixel, including a transistor 21 and a capacitor 22 as an example. The transistor 21 can be a low-temperature polycrystalline silicon thin-film transistor.

[0088] As shown in Figure 5, in a direction perpendicular to the display substrate, the display substrate may include at least a circuit structure layer 12, a light-emitting structure layer 13, and an encapsulation structure layer 14 sequentially disposed on a substrate 11. The circuit structure layer 12 may include at least pixel driving circuits for multiple sub-pixels, and each sub-pixel's pixel driving circuit may include multiple transistors and at least one capacitor. For example, the transistors may be thin-film transistors. The light-emitting structure layer 13 may include at least light-emitting devices for multiple sub-pixels. In other examples, a touch structure layer 15 may be disposed on the side of the encapsulation structure layer 14 away from the substrate 11 to integrate touch functionality.

[0089] In some exemplary embodiments, the circuit structure layer 12 may include a semiconductor layer, a first insulating layer 121, a first gate metal layer, a second insulating layer 122, a second gate metal layer, a third insulating layer 123 (interlayer insulating layer), a first source / drain metal layer 51, a first planarization layer 61, a second source / drain metal layer 52, and a second planarization layer 62, which are stacked sequentially. The semiconductor layer of the display area may include the active layer 210 of the transistor 21 of the pixel driving circuit. The active layer 210 of the transistor 21 may include a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer of the display area may include the gate 213 of the transistor 21 and the first electrode 221 of the capacitor 22. The orthographic projection of the gate 213 of the transistor 21 onto the plane of the substrate 11 may cover the orthographic projection of the channel region 2100 of the active layer 210 onto the plane of the substrate 11. The second gate metal layer may include the second electrode 222 of the capacitor 22. The second electrode 222 and the first electrode 221 of capacitor 22 can at least partially overlap in the plane of substrate 11; for example, they can coincide. The first source-drain metal layer 51 of the display area may include the source 211 and drain 212 of transistor 21. The source 211 of transistor 21 may be electrically connected to the first region 2101 of active layer 210, and the drain 212 may be electrically connected to the second region 2102 of active layer 210. The second source-drain metal layer 52 of the display area may include a transition electrode 214, and one of the source 211 and drain 212 is electrically connected to the transition electrode 214 through a via provided in the first planarization layer 61; for example, the drain 212 is electrically connected to the transition electrode 214 through a via provided in the first planarization layer 61. The transition electrode 214 is configured to be electrically connected to a light-emitting device to realize the electrical connection between the light-emitting device and the pixel driving circuit.

[0090] The light-emitting structure layer 13 may include a pixel definition layer 134 and multiple light-emitting devices. Each light-emitting device may include a stacked first electrode 131, an organic light-emitting layer 132, and a second electrode 133. The first electrode 131 of the light-emitting device can be electrically connected to the transition electrode 214 through a via disposed in the second planarization layer 62. The pixel definition layer 134 is disposed on the side of the first electrode 131 away from the substrate 11, and the pixel definition layer 134 may have multiple pixel openings, each pixel opening exposing at least a portion of the surface of a corresponding first electrode 131. At least a portion of the organic light-emitting layer 132 may be disposed within a pixel opening and connected to the corresponding first electrode 131. The second electrode 133 may be disposed on the side of the organic light-emitting layer 132 away from the substrate 11 and connected to the organic light-emitting layer 132. The organic light-emitting layer 132 can emit light of a corresponding color under the drive of the first electrode 131 and the second electrode 133.

[0091] In some exemplary embodiments, the organic light-emitting layer 132 of the light-emitting device may include at least one emitting layer (EML) and at least one of the following film layers: a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 131 and the second electrode 133, the light-emitting characteristics of the organic material can be utilized to emit light at the required grayscale.

[0092] In some exemplary embodiments, the light-emitting layers of light-emitting devices of different colors can be different. For example, a red light-emitting device includes a red light-emitting layer, a green light-emitting device includes a green light-emitting layer, and a blue light-emitting device includes a blue light-emitting layer. To reduce process complexity and improve yield, the hole injection layer and hole transport layer located on one side of the light-emitting layer can be common layers, and the electron injection layer and electron transport layer located on the other side of the light-emitting layer can be common layers. In some examples, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer can be fabricated in a single process (single vapor deposition process or single inkjet printing process), and isolation can be achieved through surface steps of the formed film layers or through surface treatment. For example, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be formed by vapor deposition using a fine metal mask (FMM) or an open mask, or by inkjet printing.

[0093] In some exemplary embodiments, the encapsulation structure layer 14 may include a first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143 stacked together. The first encapsulation layer 141 and the third encapsulation layer 143 may be made of inorganic materials, such as silicon nitride, silicon oxide, or silicon oxynitride. Inorganic materials have high density, which can prevent the intrusion of water, oxygen, etc., ensuring that external moisture cannot enter the light-emitting device. The second encapsulation layer 142 may be disposed between the first encapsulation layer 141 and the third encapsulation layer 143. The second encapsulation layer 142 may be made of organic materials, for example, it may be a polymer material containing a desiccant or a polymer material that can block moisture, or it may be a polymer resin to planarize the surface of the display substrate and relieve stress on the first encapsulation layer 141 and the third encapsulation layer 143. It may also include a desiccant or other water-absorbing material to absorb water, oxygen, and other substances that have intruded into the interior. However, the embodiments disclosed herein are not limited in this respect. In one example, the encapsulation structure layer may adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0094] Figure 6 is a partially enlarged schematic diagram of area A in Figure 4A. As shown in Figures 4A and 6, the intermediate display substrate may include at least one substrate region 400. The substrate region 400 may include a display substrate, which may include a display region 100 and a bonding region 200 located on one side of the display region 100. The cutting region 500 may be located outside the substrate region 400. For example, the cutting region 500 may include a first cutting region 50a located on the side of the bonding region 200 away from the display region 100. In this embodiment, the cutting regions on the other sides of the substrate region are not shown, and only the first cutting region 50a is shown. The intermediate display substrate is the structure before cutting during the manufacturing process of the display substrate. After completing the lamp detection and aging process, the first cutting region 50a of the intermediate display substrate can be cut off according to the cutting line L1 to obtain the display substrate.

[0095] In some examples, for a display motherboard, it can be first cut along the EAC cutting line to divide the display motherboard into multiple intermediate display substrates. For example, an intermediate display substrate may include a substrate area and a first cutting area. Then, each intermediate display substrate undergoes a lamp-on test and aging process. After the test and aging process is completed, it can be cut along the module cutting line of the intermediate display substrate. Subsequently, a circuit board is bonded to the cut display substrate. The cutting line L1 in Figure 6 is the aforementioned module cutting line. After completing the lamp-on test and aging process, the first cutting area 50a can be cut off along the cutting line L1.

[0096] In some exemplary embodiments, as shown in FIG6, the first cut region 50a may be provided with a plurality of test pin groups 10. Each test pin group may include a plurality of test pins arranged along a first direction X. The test pins may be configured as pins for signal transmission during the lamp-lighting test phase. The plurality of test pins may include at least a plurality of power supply test pins, and the plurality of power supply test pins may include at least a first power supply test pin 101 and a second power supply test pin 102.

[0097] The first cutting region 50a may also be provided with at least one second aging pin group, which may include at least one second aging pin 20. For example, the first cutting region 50a may also be provided with four second aging pin groups, namely second aging pin group 20a, second aging pin group 20b, second aging pin group 20c and second aging pin group 20d. Along the first direction X, the second aging pin groups 20a, second aging pin group 20b, second aging pin group 20c and second aging pin group 20d may be arranged sequentially. For example, the second aging pin group 20a may include two second aging pins 20, the second aging pin group 20b and the second aging pin group 20c may each include one second aging pin 20, and the second aging pin group 20d may include four second aging pins 20. However, this disclosure does not limit this.

[0098] In some exemplary embodiments, the first power test pin 101, the second power test pin 102, and a plurality of second aging pin groups can be arranged side by side along the first direction X, which can optimize the pin layout.

[0099] In some exemplary embodiments, the first cut region 50a may further include multiple power test connection lines 40, which are configured to connect to multiple power test pins. At least one of the power test connection lines 40 is made of at least one of titanium and aluminum, which can reduce resistance, reduce the heat generated by the power test connection lines during testing, and prevent the display substrate from being burned. For example, the multiple power test connection lines may include a titanium-aluminum-titanium three-layer structure.

[0100] In some exemplary embodiments, multiple power test connection lines 40 are connected one-to-one with multiple power test pins. The multiple power test connection lines 40 may include a first power test connection line 41 and a second power test connection line 42, wherein the first power test connection line 41 is connected to a first power test pin 101, and the second power test connection line 42 is connected to a second power test pin 102.

[0101] In some exemplary embodiments, along a direction away from the display area 100, the bonding area 200 may include a sub-bezel area 201 and a bonding pin area 202. The bonding pin area 202 may be located on the side of the sub-bezel area 201 away from the display area 100. The bonding pin area 202 may be provided with a plurality of bonding pin groups 30, a plurality of first aging pin groups, and a plurality of power pins, the plurality of power pins including a plurality of first power pins 111 and a plurality of second power pins 112. The plurality of bonding pin groups 30 and the plurality of first aging pin groups may be arranged side by side along a first direction X. The first power pins 111 are connected to a first power bus 70 and configured to transmit a first voltage signal to the first power bus 70, and the second power pins 112 are connected to a second power line 72 and configured to transmit a second voltage signal to the second power line 72. Multiple power supply pins are configured to correspond one-to-one with multiple power test connection lines 40. The first power supply pin 111 is connected to the first power test pin 101 through the first power test connection line 41, and the second power supply pin 112 is connected to the second power test pin 102 through the second power test connection line 42.

[0102] The bonding pin group 30 may include multiple access pins 31. Taking one bonding pin group 30 as an example, the bonding pin group 30 may include twenty-eight access pins 31. Each bonding pin group can be configured to bond to at least one corresponding circuit board, such as a flexible printed circuit (FPC). The bonding pin area 202 may include four first aging pin groups, namely first aging pin group 20e, first aging pin group 20f, first aging pin group 20g, and first aging pin group 20h. First aging pin group 20e may include two first aging pins 20-1, first aging pin groups 20f and 20g may each include one first aging pin 20-1, and first aging pin group 20h may include four first aging pins 20-1. The first aging pin groups and second aging pin groups can be configured to be used during the aging or testing phase. After the aging and testing phases are completed and the bonding pin group 30 is bonded to the circuit board, the first aging pin group may be retained as invalid pins in the bonding pin area 202. Along the first direction X, the first aging pin group 20e, the first aging pin group 20f, the first aging pin group 20g, and the first aging pin group 20h are arranged sequentially. In this embodiment of the present disclosure, the pins in the first aging pin group, the second aging pin group, and the bonding pin group can extend approximately along the second direction Y and be arranged along the first direction X.

[0103] In some exemplary embodiments, the plurality of first aging pins 20-1 in the first aging pin group, the plurality of access pins 31 in the bonding pin group 30, and the plurality of second aging pins 20 in the second aging pin group can be disposed on the same layer, for example, all of which can be located in the first source-drain metal layer. In other examples, the plurality of first aging pins 20-1, the plurality of second aging pins 20, and the plurality of access pins 31 can be a double-layer stacked structure, for example, a stacked structure of a first gate metal layer and a first source-drain metal layer, or a stacked structure of a second gate metal layer and a first source-drain metal layer, or a stacked structure of a second gate metal layer and a second source-drain metal layer. In one example, the plurality of access pins 31 can be connected to a touch line (not shown) for transmitting touch signals.

[0104] In some exemplary embodiments, the first power pin 111 and the second power pin 112 may both be located in the source / drain metal layer. For example, the first power pin 111 and the second power pin 112 may both be a double-layer stacked structure, specifically a double-layer stacked structure of a first source / drain metal layer and a second source / drain metal layer. Since the material of the source / drain metal layer has low resistance, for example, if the source / drain metal layer uses a titanium-aluminum-titanium stacked structure, and since the test currents of the first power supply voltage (VDD) and the second power supply voltage (VSS) of medium and large-sized display substrates are relatively large, when a large current flows through the low-resistance source / drain metal layer, the heat generated at the first power pin and the second power pin can be reduced due to the low resistance, thus avoiding the risk of the display substrate being burned.

[0105] In some exemplary embodiments, in the plane perpendicular to the display substrate, the bonding pin region 202 may include a first insulating layer 121, a second insulating layer 122, a third insulating layer 123, a first source / drain metal layer (SD1) 51, a first planarization layer (PLN1) 61, a second source / drain metal layer (SD2) 52, and a second planarization layer (PLN2) 62 stacked sequentially.

[0106] The substrate 11 can be a flexible substrate, which may include a first flexible material layer, a first inorganic material layer, and a second flexible material layer stacked on the glass substrate. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, etc. The material of the first inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the entire display substrate. The first inorganic material layer may also be referred to as the first barrier layer.

[0107] In an exemplary embodiment, the materials of the first planarization layer 61 and the second planarization layer 62 may include any one or more of epoxy resin, phenolic resin, urea-formaldehyde resin, melamine-formaldehyde resin, furan resin, silicone resin, polyester resin, polyamide resin, acrylic resin, polyurethane, vinyl resin, hydrocarbon resin, polyether resin, etc., and may be single-layer, multi-layer, or composite layers. The materials of the first insulating layer 121, the second insulating layer 122, and the third insulating layer 123 may include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc., or aluminum oxide (AlOx), hafnium oxide (HfOx), tantalum oxide (TaOx), etc., and may be single-layer, multi-layer, or composite layers.

[0108] In one exemplary embodiment, the display substrate may further include an overcoating (OC). The overcoating is located further away from the substrate 11 than the second planarization layer 62. The orthographic projection of the overcoating onto the plane of the substrate 11 includes the orthographic projection of the plurality of bonding pin groups 30 onto the plane of the substrate 11. The overcoating can protect the plurality of bonding pin groups 30 and improve the display substrate's resistance to water and oxygen.

[0109] Figure 7 is a partially enlarged schematic diagram of an embodiment marked B in Figure 6. As shown in Figure 7, the first power test connection line 41 may include a first sub-part 411 and a second sub-part 412 stacked together. The first sub-part 411 is closer to the substrate 11 than the second sub-part 412. For example, the first sub-part 411 may be located on the first source / drain metal layer (SD1) 51, and the second sub-part 412 may be located on the second source / drain metal layer (SD2) 52. The orthographic projection of the second sub-part 412 onto the plane of the substrate 11 at least partially overlaps with the orthographic projection of the first sub-part 411 onto the plane of the substrate 11. For example, the orthographic projection of the second sub-part 412 onto the plane of the substrate 11 includes the orthographic projection of the first sub-part 411 onto the plane of the substrate 11. In Figure 7, the second sub-part 412 is not colored to facilitate identification of the first sub-part 411.

[0110] The first sub-part 411 may include a plurality of spaced-apart first connecting parts 411a, at least a portion of the surface of the plurality of first connecting parts 411a on the side away from the substrate 11, which contacts the second sub-part 412. In the embodiments of this disclosure, by configuring the first sub-part to include a plurality of spaced-apart first connecting parts, the contact interface between the first sub-part and the second sub-part is separated into a plurality of contact interfaces, which can prevent water, oxygen, etc. from intruding into the bonding area and the display area along the contact interface between the first sub-part and the second sub-part via the cutting line, thereby improving the reliability of the display substrate.

[0111] As shown in Figure 7, the first connecting portion 411a can be a straight line extending along the first direction X, and multiple first connecting portions 411a can be arranged at intervals along the second direction Y. Alternatively, the first connecting portion 411a can be a curved shape extending along the first direction X, and multiple first connecting portions 411a can be arranged at intervals along the second direction Y. Alternatively, the first connecting portion 411a can be a straight line extending along the second direction Y, and multiple first connecting portions 411a can be arranged at intervals along the first direction X. Alternatively, the first connecting portion 411a can be a curved shape extending along the second direction Y, and multiple first connecting portions 411a can be arranged at intervals along the first direction X. Alternatively, the first connecting portion 411a can be a straight line extending along a direction different from the first direction X and the second direction Y. For example, the first connecting portion 411a can be a straight line extending at a 45-degree angle to the first direction X. Alternatively, the first connecting portion 411a can be a curved shape extending along a direction different from the first direction X and the second direction Y.

[0112] In an exemplary embodiment, the plurality of first connecting portions 411a may be arranged in an array, for example, in a rectangular array or a circular array, etc.

[0113] In an exemplary embodiment, the orthographic projection of the first connecting portion 411a onto the plane of the substrate can be a rectangle, a square, a rhombus, or a hexagon, etc.

[0114] Figure 8 is a partially enlarged schematic diagram of another embodiment marked B in Figure 6. As shown in Figure 8, at least one first connecting portion 411a may include at least one protrusion 411b or at least one recess 411c. As shown in Figure 8, multiple protrusions 411b and multiple recesses 411c may be arranged alternately along a first direction X. For example, one protrusion 411b and one recess 411c may be arranged alternately. Alternatively, two protrusions 411b and two recesses 411c may be arranged alternately. Or, one protrusion 411b and two recesses 411c may be arranged alternately, etc. In Figure 8, the second sub-portion 412 is not colored to facilitate identification of the first connecting portion 411a.

[0115] The protrusion 411b protrudes away from the substrate 11, and the recess 411c is recessed towards the substrate 11. In this embodiment, by providing the protrusion or the recess, the irregularity of the contact interface between the first sub-part and the second sub-part can be improved, and water, oxygen, etc. can be prevented from intruding into the bonding area and the display area along the contact interface between the first sub-part and the second sub-part via the cutting line, thereby improving the reliability of the display substrate.

[0116] Figure 9 is a partially enlarged schematic diagram of another embodiment marked B in Figure 6. As shown in Figure 9, the second sub-part 412 may include a plurality of spaced-apart second connecting parts 412a, at least a portion of the surface of the plurality of second connecting parts 412a near the substrate 11 contacts the first connecting part 411a of the first sub-part 411. In Figure 9, the second sub-part 412 is not colored to facilitate identification of the first sub-part 411. The structure of the second connecting part 412a can be referred to the foregoing description of the first connecting part 411a, and will not be repeated here.

[0117] Figure 10 is a cross-sectional schematic diagram of an embodiment marked CC in Figure 7. As shown in Figure 10, in the plane perpendicular to the display substrate, in this embodiment of the present disclosure, the direction of the plane where the substrate 11 is located is marked as the third direction Z. The bonding pin region 202 may include a first insulating layer 121, a second insulating layer 122, a third insulating layer 123, a first source / drain metal layer 51, a first planarization layer 61, a second source / drain metal layer 52, and a second planarization layer 62.

[0118] As shown in FIG. 10, the first planarization layer 61 has at least one groove K, the groove K exposing a portion of the first sub-part 411, and at least a portion of the second sub-part 412 is located within the groove K and in contact with the first sub-part 411. For example, the orthographic projection of the groove K onto the plane of the substrate 11 includes the orthographic projection of the first sub-part 411 onto the plane of the substrate 11. The groove K includes a connected groove bottom K1 and groove wall K2, with the groove bottom K1 closer to the substrate 11 than the groove wall K2. A portion of the first planarization layer 61 forms the groove wall K2, and a portion of the first planarization layer 61 and a portion of the first sub-part 411 together form the groove bottom K1. In this embodiment of the present disclosure, the groove provides protection for the contact interface between the first sub-part and the second sub-part, improving the resistance of the first and second power test connection lines to water and oxygen intrusion, and enhancing the reliability of the display substrate. As shown in FIG. 10, the orthographic projection of the second planarization layer 62 onto the plane of the substrate 11 includes the orthographic projections of the first planarization layer 61, the first source / drain metal layer 51, and the second source / drain metal layer 52 onto the plane of the substrate 11. In this embodiment of the disclosure, the first planarization layer and the second planarization layer can jointly enhance the ability of the first power test connection line and the second power test connection line to block water and oxygen.

[0119] Figure 11 is a cross-sectional view of another embodiment marked CC in Figure 7. As shown in Figure 11, the first planarization layer 61 has at least one groove K, which exposes a portion of the first sub-part 411. At least a portion of the second sub-part 412 is located within the groove K and contacts the first sub-part 411. The groove K is a through-hole extending along a third direction Z. In this embodiment of the present disclosure, the groove provides protection for the contact interface between the first sub-part and the second sub-part, improving the resistance of the first and second power test connection lines to water and oxygen intrusion, and enhancing the reliability of the display substrate.

[0120] In an exemplary embodiment, as shown in FIG11, the first sub-part 411 may include a plurality of spaced-apart first connecting parts 411a, each of which may include a top wall 411d, a bottom wall 411e, and a side wall 411f connected together. The top wall 411d is farther from the substrate 11 than the bottom wall 411e, and the side wall 411f is located between the top wall 411d and the bottom wall 411e. The second sub-part 412 is in contact with the top wall 411d, the bottom wall 411e, and the side wall 411f, or the second sub-part 412 is in contact with both the top wall 411d and the side wall 411f. This increases the contact area between the first sub-part 411 and the second sub-part 412, thereby improving the reliability of the contact between the first sub-part 411 and the second sub-part 412.

[0121] In an exemplary embodiment, the orthographic projection of the groove K onto the plane of the substrate can be a square, rectangle, circle, or hexagon, etc.

[0122] Figure 12 is a cross-sectional schematic diagram of an embodiment marked DD in Figure 8. As shown in Figure 12, at least one first connecting portion 411a may include at least one protrusion 411b and at least one recess 411c. As shown in Figure 12, the plurality of protrusions 411b and the plurality of recesses 411c may be arranged alternately along the first direction X.

[0123] For example, the bonding pin area 202 may have multiple clearance holes K11. The first insulating layer 121 and the second insulating layer 122 located within the clearance holes K11 are etched away. The recessed portion 411c is provided in a one-to-one correspondence with the clearance hole K11, and the recessed portion 411c is located within the clearance hole K11. The protrusion 411b and the clearance hole K11 do not overlap in the orthographic projection on the plane where the substrate 11 is located.

[0124] In one exemplary embodiment, the display substrate may further include at least one circuit board configured to be bonded to at least one set of bonding pins on the display substrate. For example, the circuit board may be a flexible printed circuit (FPC).

[0125] This disclosure also provides a display device, including the display substrate described in any of the foregoing embodiments. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0126] While the embodiments disclosed in this invention have been described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. It should be noted that the above embodiments or implementation methods are merely exemplary and not restrictive. Therefore, this disclosure is not limited to the content specifically shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the implementation without departing from the scope of this disclosure.

Claims

1. A display substrate, comprising: A substrate includes a display area and a peripheral area surrounding the display area, the peripheral area including a bonding area located on one side of the display area; Multiple sub-pixels are located in the display area; Multiple power pins are located in the bonding area and electrically connected to the multiple sub-pixels, and the multiple power pins are configured to transmit power signals to the multiple sub-pixels; Multiple power test connection lines are located on the side of the multiple power pins away from the display area and connected to the multiple power pins. At least one of the multiple power test connection lines is made of at least one of titanium and aluminum.

2. The display substrate as claimed in claim 1, wherein, The multiple power test connection lines are connected one-to-one with the multiple power pins.

3. The display substrate as described in claim 1, wherein, The at least one power test connection line includes a first sub-section and a second sub-section stacked together, wherein the first sub-section and the second sub-section are located on different layers, and the first sub-section is closer to the substrate than the second sub-section.

4. The display substrate as described in claim 3, wherein, The orthographic projection of the second sub-part onto the plane of the substrate includes the orthographic projection of the first sub-part onto the plane of the substrate, and the orthographic projection area of ​​the second sub-part onto the plane of the substrate is greater than the orthographic projection area of ​​the first sub-part onto the plane of the substrate.

5. The display substrate as claimed in claim 3, wherein, The first sub-part includes a plurality of spaced-apart first connecting parts, at least a portion of the surface of the plurality of first connecting parts on the side away from the substrate contacts the second sub-part; or, the second sub-part includes a plurality of spaced-apart second connecting parts, at least a portion of the surface of the plurality of second connecting parts on the side near the substrate contacts the first sub-part; or, the first sub-part includes a plurality of spaced-apart first connecting parts, and the second sub-part includes a plurality of spaced-apart second connecting parts, at least a portion of the surface of the first connecting parts on the side away from the substrate contacts at least a portion of the surface of the second connecting parts on the side near the substrate.

6. The display substrate as claimed in claim 5, wherein, At least a portion of at least one of the plurality of first connecting portions has a straight orthographic projection onto the plane where the substrate is located; or, at least a portion of at least one of the plurality of first connecting portions has a curved orthographic projection onto the plane where the substrate is located.

7. The display substrate as claimed in claim 5, wherein, At least one of the plurality of first connecting portions includes at least one of a protrusion and a recess; the protrusion protrudes in a direction away from the substrate, and the recess is recessed in a direction closer to the substrate.

8. The display substrate as claimed in claim 7, wherein, The at least one first connecting portion includes a plurality of protrusions and a plurality of recesses; the plurality of protrusions and the plurality of recesses are arranged alternately in sequence.

9. The display substrate according to any one of claims 3 to 8, wherein, In a direction perpendicular to the plane of the substrate, the bonding region includes a first source / drain metal layer, a first planarization layer, a second source / drain metal layer and a second planarization layer stacked sequentially, with the first sub-part located in the first source / drain metal layer and the second sub-part located in the second source / drain metal layer. The first planarization layer has at least one groove that exposes at least a portion of the surface of the first sub-part away from the substrate, and at least a portion of the second sub-part is located within the groove and in contact with the first sub-part; the orthographic projection of the second planarization layer onto the plane of the substrate includes the orthographic projections of the first sub-part and the second sub-part onto the plane of the substrate.

10. The display substrate as claimed in claim 9, wherein, The first sub-part includes a plurality of spaced-apart first connecting parts, each first connecting part including a top wall, a bottom wall and a side wall connected to each other; the top wall is farther away from the substrate than the bottom wall, and the side wall is located between the top wall and the bottom wall; the second sub-part is in contact with the top wall, bottom wall and side wall of at least one of the first connecting parts.

11. The display substrate according to any one of claims 1 to 8, wherein, The bonding area further includes at least one bonding pin group and at least one first aging pin group; the bonding pin group and the first aging pin group are arranged side by side along a first direction, which is parallel to the plane of the substrate.

12. The display substrate according to any one of claims 3 to 8, wherein, At least one of the plurality of sub-pixels includes a transistor, a first planarization layer, a transition electrode, a second planarization layer, and a light-emitting device, wherein the first planarization layer is located on the side of the transistor away from the substrate and covers the transistor, the transition electrode is located on the side of the first planarization layer away from the substrate, and the light-emitting device is located on the side of the second planarization layer away from the substrate. The transistor includes an active layer on the substrate, a gate on the side of the active layer away from the substrate, and a source and a drain on the side of the gate away from the substrate. One of the source and the drain is electrically connected to the transition electrode through a via provided in the first planarization layer. The light-emitting device is electrically connected to the transition electrode through a via provided in the second planarization layer. The first sub-section is located on the same layer as the source or the drain, and the second sub-section is located on the same layer as the transition electrode.

13. The display substrate according to any one of claims 1 to 8, further comprising a plurality of first power lines, the plurality of first power lines being located in the display area and electrically connected to the plurality of sub-pixels, the plurality of first power lines being configured to provide a first voltage signal to the plurality of sub-pixels; A first power bus is located in the binding area and is electrically connected to the plurality of first power lines; A second power cord is located in the surrounding area and partially surrounds the display area; The plurality of power supply pins include at least a first power supply pin and a second power supply pin. The first power supply pin is connected to the first power bus and configured to transmit the first voltage signal to the first power bus. The second power supply pin is connected to the second power line and configured to transmit a second voltage signal to the second power line.

14. The display substrate as claimed in claim 13, wherein, The multiple power test connection lines include a first power test connection line and a second power test connection line, with the first power pin connected to the first power test connection line and the second power pin connected to the second power test connection line.

15. An intermediate display substrate, comprising a display substrate as described in any one of claims 1 to 14 and a plurality of power test pins located on the side of the plurality of power pins away from the display area; the intermediate display substrate includes a substrate area and a first cutting area located on one side of the substrate area, the first cutting area being located on the side of the bonding area away from the display area, the display substrate being located in the substrate area, and the plurality of power test pins being located in the first cutting area. The multiple power test connection lines are located between and connect the multiple power pins and the multiple power test pins.

16. The intermediate display substrate as claimed in claim 15, wherein, The multiple power test connection lines are connected one-to-one with the multiple power test pins; the multiple power test connection lines include a first power test connection line and a second power test connection line, and the multiple power pins include a first power pin and a second power pin. The plurality of power test pins include a first power test pin and a second power test pin. The first power test pin is connected to the first power test pin via a first power test connection line; the second power test pin is connected to the second power test pin via a second power test connection line.

17. The intermediate display substrate of claim 15, further comprising at least one second aging pin group, the second aging pin group being located in the first cutting area, the second aging pin group including at least one second aging pin, the second aging pin and the power test pin being arranged side by side along a first direction, the first direction being parallel to the plane of the substrate.

18. A display device comprising a display substrate as described in any one of claims 1 to 14.

Images