Spin-orbit torque magnetic random access memory and manufacturing method therefor

Abstract

A spin-orbit torque (SOT) magnetic random access memory and a manufacturing method therefor, applied to the field of memories. The SOT magnetic random access memory comprises: a bottom electrode structure, an SOT track layer, a magnetic tunnel junction, and a top electrode that are stacked; the bottom electrode structure comprises a bottom dielectric structure corresponding to the SOT track layer and a bottom electrode corresponding to the SOT track layer; there is a height difference between the end of the bottom electrode facing the SOT track layer and the end of the bottom dielectric structure facing the SOT track layer; a buffer layer is provided on the side of the bottom electrode structure facing the SOT track layer, the buffer layer and the bottom electrode structure are combined to form a planar surface facing the SOT track layer, and the bottom electrode is conductively connected to the SOT track layer, correspondingly. In the present invention, the buffer layer is provided, and the buffer layer and the bottom electrode structure are combined to form the planar surface facing the SOT track layer, thereby improving the planarity of the SOT track layer and the magnetic tunnel junction.

Description

A spin-orbit torque magnetic random access memory and its fabrication method

[0001] This application claims priority to Chinese Patent Application No. 202411991763.7, filed on December 31, 2024, entitled "A Spin-Orbit Torque Magnetic Random Access Memory and a Method for its Preparation Thereof", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of memory, and in particular to a spin-orbit torque magnetic random access memory and its fabrication method. Background Technology

[0003] Spin-orbit torque-based magnetic tunnel junction (SOT-MTJ) devices, where MTJ etching stops on a heavy metal spin-orbit material, place high demands on the processing of the SOT layers before and after the SOT orbitals. This is to avoid over-etching that penetrates the orbital layer, leading to device failure, and to prevent MTJ etching from stopping only on the SOT orbitals without sufficient space for over-etching, which can cause difficult-to-clean backsplashes and short-circuit failures. To address these challenges, existing technologies employ a self-aligned SOT etching process, where the SOT orbitals and TJ stack are etched together in a single step. The TJ stack consists of two layers of ferromagnetic material and a non-magnetic insulating layer, avoiding damage to the SOT orbitals during the two-step formation process and minimizing the impact of metal backsplashes on the TJ stack.

[0004] The self-aligned etching process described above avoids etching the material of the lower electrode, but at the same time limits the size of the lower electrode. The main solution is to deposit the SOT orbitals directly on top of the bottom electrode. However, the height difference between the upper surface of the small bottom electrode and the surrounding medium due to the material selectivity during the chemical mechanical planarization (CMP) process affects the performance of the SOT orbitals.

[0005] Therefore, how to provide a magnetic random access memory that can avoid the height difference between the upper surface of the small bottom electrode and the surrounding medium caused by the material selectivity during the chemimechanical planarization process, thereby avoiding affecting the SOT orbital performance, is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0006] In view of this, the purpose of the present invention is to provide a spin-orbit torque magnetic random access memory and its preparation method, which solves the problem in the prior art where the height difference between the upper surface of the small-sized bottom electrode and the surrounding medium caused by the material selectivity during the chemical mechanical planarization (CMP) process affects the SOT orbital performance.

[0007] To solve the above-mentioned technical problems, the present invention provides a spin-orbit torque magnetic random access memory, comprising:

[0008] The stacked bottom electrode structure, SOT orbital layer, magnetic tunnel junction, and top electrode;

[0009] The bottom electrode structure includes a bottom dielectric structure corresponding to the SOT orbital layer and a bottom electrode corresponding to the SOT orbital layer. The bottom dielectric structure is provided with a through hole, and the bottom electrode is disposed in the through hole.

[0010] The bottom electrode is located at one end of the SOT orbital layer, and there is a height difference between the bottom dielectric structure and the end of the bottom dielectric structure located at the SOT orbital layer.

[0011] The bottom electrode structure has a buffer layer on the side facing the SOT track layer. The buffer layer and the bottom electrode structure together form a flat surface facing the SOT track layer, and the bottom electrode is conductively connected to the SOT track layer.

[0012] Optionally, the bottom electrode protrudes from one end of the SOT orbital layer, and the buffer layer exposes at least a portion of the bottom electrode.

[0013] Optionally, the buffer layer is an insulating buffer layer or a high-resistance buffer layer.

[0014] Optionally, the bottom electrode is positioned below the bottom dielectric structure at one end toward the SOT orbital layer, forming a recessed structure.

[0015] The buffer layer is located only at the recessed structure;

[0016] The buffer layer is a conductive buffer layer or a high-resistivity buffer layer.

[0017] Optionally, the buffer layer is a high-resistivity buffer layer;

[0018] The high-resistivity buffer layer covers the entire surface of the bottom electrode structure corresponding to the SOT orbital layer.

[0019] Optionally, the thickness of the high-resistivity buffer layer is from 1 nanometer to 30 nanometers;

[0020] The resistivity of the high-resistivity buffer layer is from 1 milliohm·cm to 50 milliohm·cm.

[0021] Optionally, the high-resistivity buffer layer includes, but is not limited to, one or a mixture of or a stack of multiple of the following: tungsten buffer layer, tungsten nitride buffer layer, titanium nitride buffer layer, tantalum buffer layer, tantalum nitride buffer layer, nickel buffer layer, chromium buffer layer, and silicon buffer layer.

[0022] This invention also provides a method for fabricating a spin-orbit torque magnetic random access memory, comprising:

[0023] A bottom electrode structure is provided, the bottom electrode structure including a bottom dielectric structure and a bottom electrode, the bottom dielectric structure having a through hole, and the bottom electrode being disposed within the through hole; a height difference is formed between the upper end of the bottom electrode and the upper end of the bottom dielectric structure;

[0024] A buffer layer is prepared on the upper side of the bottom electrode structure so that the buffer layer and the bottom electrode structure are combined to form a flat surface; an SOT orbital layer, a magnetic tunnel junction and a top electrode are stacked on the flat surface, and the bottom electrode is conductively connected to the SOT orbital layer.

[0025] Optionally, a buffer layer is prepared on the upper side of the bottom electrode structure so that the buffer layer and the bottom electrode structure combine to form a flat surface, including:

[0026] A high-resistivity buffer layer is prepared on the entire upper surface of the bottom electrode structure, and a flat surface is formed on the side of the high-resistivity buffer layer facing away from the bottom electrode structure.

[0027] Optionally, a high-resistivity buffer layer is formed on the entire upper surface of the bottom electrode structure, and the flat surface is formed on the side of the high-resistivity buffer layer facing away from the bottom electrode structure, including:

[0028] The high-resistivity buffer layer is prepared on the entire upper surface of the bottom electrode structure, and the side of the high-resistivity buffer layer facing away from the bottom electrode structure is subjected to chemical mechanical polishing to form the flat surface.

[0029] As can be seen, the spin-orbit torque magnetic random access memory provided by the present invention includes a stacked bottom electrode structure, a SOT orbital layer, a magnetic tunnel junction, and a top electrode. The bottom electrode structure includes a bottom dielectric structure corresponding to the SOT orbital layer and a bottom electrode corresponding to the SOT orbital layer. The bottom dielectric structure has a through-hole, and the bottom electrode is disposed within the through-hole. One end of the bottom electrode facing the SOT orbital layer forms a height difference with the other end of the bottom dielectric structure facing the SOT orbital layer. A buffer layer is disposed on the side of the bottom electrode structure facing the SOT orbital layer. The buffer layer and the bottom electrode structure together form a flat surface facing the SOT orbital layer, and the bottom electrode is electrically connected to the SOT orbital layer. By providing a buffer layer on the side of the bottom electrode structure facing the SOT orbital layer and combining the buffer layer with the bottom electrode structure to form a flat surface facing the SOT orbital layer, and by electrically connecting the bottom electrode to the SOT orbital layer, the present invention improves the flatness of the SOT orbital layer and the magnetic tunnel junction, reduces the roughness below the SOT orbital, reduces the difficulty of fabrication, improves device performance, and ensures the uniformity of device performance during the fabrication of the SOT orbital layer on this flat surface.

[0030] In addition, the present invention also provides a method for preparing a spin-orbit torque magnetic random access memory, which also has the above-mentioned beneficial effects. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0032] Figure 1 is a schematic diagram of the structure of an existing spin-orbit torque magnetic random access memory;

[0033] Figure 2 is a schematic diagram of another existing spin-orbit torque magnetic random access memory;

[0034] Figure 3 is a schematic diagram of the structure of a spin-orbit torque magnetic random access memory provided in an embodiment of the present invention;

[0035] Figures 4 to 9 are examples of the fabrication of a spin-orbit torque magnetic random access memory provided in an embodiment of the present invention;

[0036] Figure 10 is a schematic diagram of another spin-orbit torque magnetic random access memory provided in an embodiment of the present invention;

[0037] Figures 11 to 15 are examples of the fabrication of another spin-orbit torque magnetic random access memory provided in the embodiments of the present invention;

[0038] Figure 16 is a flowchart of a method for preparing a spin-orbit torque magnetic random access memory according to an embodiment of the present invention;

[0039] In Figures 1 to 15, the reference numerals are explained as follows: 1-hard mask, 2-metal interconnect layer, 3-substrate, 4-protective layer, 11-bottom dielectric structure, 12-bottom electrode, 20-SOT orbital layer, 30-magnetic tunnel junction, 40-buffer layer, 41-high-resistivity buffer layer, 50-top electrode. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0041] Magnetic Tunnel Junction 30 (SOT-MTJ) devices, or SOT-MRAMs, represent a next-generation non-volatile magnetic random access memory. Utilizing spin-orbit torque as the information writing method, SOT devices achieve nanosecond-level write speeds. Their separate read and write modes promise unlimited write cycles. Currently disclosed SOT-MRAM cell architectures are based on MTJ etching stopping at the heavy metal spin-orbit material. This architecture places high demands on the processing of the SOT orbital layers before and after the orbital layer: firstly, the SOT orbital layer 20 is very thin, only a few nanometers, making it easy to over-etch the magnetic tunnel junction 30, causing it to be etched through and resulting in an open circuit, ultimately rendering the device unusable. Therefore, precise control of the etching endpoint of the magnetic tunnel junction 30 is necessary. Secondly, the etching of the magnetic tunnel junction 30 can only stop at the surface of the SOT orbital layer 20, leaving no over-etched space, making it difficult to clean up etching backsplatter and easily leading to short-circuit failure. The specific architecture can be found in Figure 1, which is a schematic diagram of an existing spin-orbit torque magnetic random access memory.

[0042] Self-aligned SOT etching is an effective way to solve the above problems. Its advantage lies in the one-step etching of the SOT orbital layer 20 and the TJ stack, avoiding the damage to the SOT orbital layer 20 caused by the etching of the TJ stack (tunnel junction stack) and the impact of metal backspatter on the TJ stack during the two-step formation process. It can improve yield and save photomasks, effectively reducing costs. Although self-aligned etching avoids etching of the underlying electrode material, it conversely limits the size of the bottom electrode 12. The main solution is to deposit the SOT orbital layer 20 directly on top of the bottom electrode 12 structure. Due to the height difference in material selectivity during the chemical mechanical planarization (CMP) process, the performance of the SOT orbital layer 20 is at risk. This architecture can be referred to in Figure 2, which is a schematic diagram of another existing spin-orbit torque magnetic random access memory structure.

[0043] This invention provides a buffer layer on the side of the bottom electrode 12 structure facing the SOT orbital layer 20, and the buffer layer and the bottom electrode 12 structure are combined to form a flat surface facing the SOT orbital layer 20. The bottom electrode 12 is electrically connected to the SOT orbital layer 20. This improves the flatness of the SOT orbital layer 20 and the magnetic tunnel junction 30 during the fabrication of the SOT orbital layer 20 on this flat surface, reduces the roughness below the SOT orbitals, simplifies the fabrication process, improves device performance, and ensures the uniformity of device performance. See the following embodiment for reference:

[0044] Example 1:

[0045] Please refer to Figure 3, which is a schematic diagram of a spin-orbit torque magnetic random access memory provided in an embodiment of the present invention. This magnetic random access memory may include:

[0046] The structure consists of a stacked bottom electrode 12, an SOT track layer 20, a magnetic tunnel junction 30, and a top electrode 50.

[0047] The bottom electrode 12 structure includes a bottom dielectric structure 11 corresponding to the SOT orbital layer 20 and a bottom electrode 12 corresponding to the SOT orbital layer 20. The bottom dielectric structure 11 is provided with a through hole, and the bottom electrode 12 is disposed in the through hole.

[0048] The bottom electrode 12 is close to one end of the SOT orbital layer 20, and there is a height difference between it and the bottom dielectric structure 11 which is close to the end of the SOT orbital layer 20.

[0049] A buffer layer 40 is provided on the side of the bottom electrode 12 structure facing the SOT track layer 20. The buffer layer 40 and the bottom electrode 12 structure are combined to form a flat surface facing the SOT track layer 20, and the bottom electrode 12 is electrically connected to the SOT track layer 20.

[0050] In this embodiment, during fabrication, the stacked bottom electrode 12 structure, SOT orbital layer 20, magnetic tunnel junction 30, and top electrode 50 are generally arranged sequentially in a vertically upward direction. Specifically, the SOT orbital layer 20 is fabricated above the bottom electrode 12 structure, the magnetic tunnel junction 30 is fabricated above the SOT orbital layer 20, and the top electrode 50 is fabricated above the magnetic tunnel junction 30. In this embodiment, the portion of the bottom electrode 12 structure that is conductively connected to the SOT orbital layer 20 is not completely exposed and requires protection by a corresponding dielectric structure. Therefore, the bottom electrode 12 structure includes a bottom dielectric structure 11 and a bottom electrode 12, with the bottom electrode 12 disposed within a through-hole in the bottom dielectric structure 11. In this embodiment, due to the material selection ratio during the chemical mechanical planarization (CMP) process, a height difference is generated between the upper surface of the bottom electrode 12 and the surrounding bottom dielectric structure 11 after CMP treatment. That is, the end of the bottom electrode 12 that is close to the SOT orbital layer 20 has a height difference with the end of the bottom dielectric structure 11 that is close to the SOT orbital layer 20. In order to eliminate the height difference between the bottom electrode 12 and the bottom dielectric structure 11, this embodiment provides a buffer layer 40 on the side of the bottom electrode 12 structure that is close to the SOT orbital layer 20. The buffer layer 40 can be combined with the bottom electrode 12 structure to form a flat surface close to the SOT orbital layer 20, and at the same time, it can ensure that the bottom electrode 12 in the bottom electrode 12 structure is electrically connected to the SOT orbital layer 20 to realize the functionality of the magnetic random access memory. This embodiment utilizes the buffer layer 40 to optimize the height difference between the bottom electrode 12 and the surrounding bottom dielectric structure 11. Specifically, it optimizes the planarization window below the SOT orbital layer 20, reduces the process difficulty, reduces the roughness below the SOT orbital layer 20, improves the flatness of the SOT orbital layer 20 and MTJ thin film growth, and improves the performance and uniformity of the device.

[0051] This embodiment does not limit the specific way in which the buffer layer 40 and the bottom electrode 12 structure are combined to form a flat surface facing the SOT orbital layer 20, as long as the surfaces of the fabricated SOT orbital layer 20 and the fabricated magnetic tunnel junction 30 are flat, and the bottom electrode 12 in the bottom electrode 12 structure and the SOT orbital layer 20 are properly conductively connected. In this embodiment, a metal interconnect layer 2 can also be provided on the lower side of the bottom electrode 12 structure. The metal interconnect layer 2 is disposed on the upper side of the substrate 3, and the substrate 3 can include active devices or passive devices. In addition, due to process requirements, a hard mask 1 is generally provided above the magnetic tunnel junction 30 in this embodiment. The specific material of the buffer layer 40 is not specified in this embodiment, as long as it meets the above-mentioned functionality. For example, the buffer layer 40 can be made of SiN (silicon nitride), SiO2 (silicon dioxide), and other insulating materials containing, but not limited to, combinations of elements including, but not limited to, Si (silicon), N (nitrogen), O (oxygen), C (carbon), and H (hydrogen). In this embodiment, the magnetic tunnel junction 30 includes a free layer, a barrier layer, and a reference layer, with the free layer located on the side of the magnetic tunnel junction 30 facing the SOT orbital layer 20. The material selected for the bottom electrode 12 may include, but is not limited to, W (tungsten), TiN (titanium nitride), Ta (tantalum), and TaN (tantalum nitride).

[0052] Furthermore, in one feasible embodiment, the bottom electrode 12 protrudes from the bottom dielectric structure 11 and is located near one end of the SOT track layer 20, with the buffer layer 40 exposing at least a portion of the bottom electrode 12.

[0053] It should be noted that in this embodiment, the bottom electrode 12 is positioned at one end of the SOT orbital layer 20, creating a height difference with the bottom dielectric structure 11 at the same end. Specifically, the bottom electrode 12 protrudes from the bottom dielectric structure 11 at the end of the SOT orbital layer 20. In this case, a buffer layer 40 is provided to fill and make up the height difference between the bottom electrode 12 and the bottom dielectric structure 11. However, in order to ensure the conductive connection between the bottom electrode 12 and the SOT orbital layer 20, the buffer layer 40 needs to ensure the flatness of the surface of the SOT orbital layer 20 while exposing at least part of the top surface of the bottom electrode 12, that is, the surface of the bottom electrode 12 at the end of the SOT orbital layer 20.

[0054] The fabrication process of the spin-orbit torque magnetic random access memory (SOTMM) described in this embodiment can be referred to Figures 4 to 9, which are example diagrams of the fabrication of an SOTMM provided by this embodiment of the invention. In Figure 4, the enlarged view of the partial structure marked by a box shows a structure with a height difference between the bottom electrode 12 and the bottom dielectric structure 11 on the upper surface; that is, the bottom electrode 12 protrudes from the bottom dielectric structure 11 towards one end of the SOT orbital layer 20. Figure 5 shows the fabrication of a buffer layer 40 on the surface of the bottom electrode structure. The surface of this buffer layer 40 is uneven and requires subsequent chemical mechanical polishing (CMP) to planarize it, resulting in the structure shown in Figure 6. Figures 7 to 9 show the fabrication of the SOT orbital layer 20, magnetic tunnel junction 30, hard mask 1, and protective layer 4, followed by encapsulation of the fabricated structure using a dielectric material, and the fabrication of the top electrode 50 shown in Figure 9. The protective layer 4 is a structure already present in existing SOTMMs and can be referenced from existing magnetic random access memories.

[0055] Furthermore, in order to ensure that the bottom electrode 12 is electrically connected to the SOT track layer 20 and to avoid short circuits between adjacent bottom electrodes 12, the buffer layer 40 can be set as an insulating buffer layer or a high-resistance buffer layer 41.

[0056] It should be noted that in this embodiment, the buffer layer 40 is set as an insulating buffer layer or a high-resistivity buffer layer 41, which can prevent short circuits between adjacent bottom sub-electrode structures that are electrically connected to the buffer layer 40, thus ensuring the functionality of the magnetic random access memory. It should be further noted that the bottom electrode 12 corresponding to a single magnetic tunnel junction 30 generally includes two independent bottom sub-electrode structures, both of which are in contact with the buffer layer 40. Therefore, setting the buffer layer 40 as an insulating buffer layer or a high-resistivity buffer layer 41 can prevent short circuits between adjacent bottom sub-electrode structures.

[0057] The spin-orbit torque magnetic random access memory provided in this embodiment of the invention includes a bottom electrode 12 structure, a SOT orbital layer 20, a magnetic tunnel junction 30, and a top electrode 50 stacked together. The bottom electrode 12 structure includes a bottom dielectric structure 11 corresponding to the SOT orbital layer 20 and a bottom electrode 12 corresponding to the SOT orbital layer 20. The bottom dielectric structure 11 is provided with a through hole, and the bottom electrode 12 is disposed in the through hole. One end of the bottom electrode 12 is close to the SOT orbital layer 20, and there is a height difference between the bottom electrode 12 and the end of the bottom dielectric structure 11 that is close to the SOT orbital layer 20. A buffer layer 40 is provided on the side of the bottom electrode 12 structure that is close to the SOT orbital layer 20. The buffer layer 40 and the bottom electrode 12 structure are combined to form a flat surface close to the SOT orbital layer 20, and the bottom electrode 12 is electrically connected to the SOT orbital layer 20. The present invention provides a buffer layer 40 on the side of the bottom electrode 12 structure facing the SOT track layer 20, and the buffer layer 40 and the bottom electrode 12 structure are combined to form a flat surface facing the SOT track layer 20, and the bottom electrode 12 is electrically connected to the SOT track layer 20. In order to improve the flatness of the SOT track layer 20 and the magnetic tunnel junction 30 when the SOT track layer 20 is prepared on this flat surface, reduce the roughness below the SOT track, reduce the difficulty of process preparation, improve the performance of the device, and ensure the uniformity of device performance.

[0058] Furthermore, in this embodiment of the invention, by setting the bottom electrode 12 to protrude from the bottom dielectric structure 11 at one end facing the SOT track layer 20, while the buffer layer 40 ensures the flatness of the surface of the SOT track layer 20, the buffer layer 40 exposes at least a portion of the surface of the bottom electrode 12 facing the SOT track layer 20. This ensures the flatness of the SOT track layer 20 and the stability of the conductive connection between the bottom electrode 12 and the SOT track layer 20, even when the bottom electrode 12 protrudes from the bottom dielectric structure 11 and forms a height difference. By setting the buffer layer 40 to an insulating buffer layer or a high-resistivity buffer layer 41, short circuits between adjacent bottom sub-electrode structures conductively connected to the buffer layer 40 can be avoided, ensuring the functionality of the magnetic random access memory.

[0059] Example 2:

[0060] The spin-orbit torque magnetic random access memory provided in this embodiment of the invention differs from that in Embodiment 1 in that:

[0061] The bottom electrode 12 is lower than the bottom dielectric structure 11 at one end near the SOT orbital layer 20, forming a recessed structure.

[0062] Buffer layer 40 is located only in the recessed structure;

[0063] The buffer layer 40 is a conductive buffer layer or a high-resistivity buffer layer 41.

[0064] It should be noted that in this embodiment, the bottom electrode 12 is positioned at one end of the SOT track layer 20, creating a height difference with the bottom dielectric structure 11 at the same end. Specifically, the bottom electrode 12 at the end of the SOT track layer 20 is lower than the bottom dielectric structure 11, forming a recessed structure. Under normal circumstances, there is a risk of poor contact or even no contact between the bottom electrode 12 and the SOT track layer 20. Therefore, when the buffer layer 40 fills the height difference between the bottom electrode 12 and the bottom dielectric structure 11, i.e., when the buffer layer 40 is only located at the aforementioned recessed structure, the buffer layer 40 also needs to be conductive to ensure that the conductive electrode can be conductively connected to the SOT track layer 20. That is, the buffer layer 40 needs to be set as a conductive buffer layer or a high-resistivity buffer layer 41.

[0065] In the spin-orbit torque magnetic random access memory provided in this embodiment of the invention, when the end of the bottom electrode 12 approaching the SOT orbital layer 20 is lower than the bottom dielectric structure 11, forming a recessed structure, the buffer layer 40 is located only at the recessed structure. This fills the height difference between the bottom electrode 12 and the bottom dielectric structure 11, and, combined with the bottom electrode 12 structure, forms a flat surface approaching the SOT orbital layer 20. This ensures the flatness of the SOT orbital layer 20 and the magnetic tunnel junction 30 subsequently fabricated on this flat surface, thus guaranteeing the device performance of the fabricated magnetic random access memory. By setting the buffer layer 40 as a conductive buffer layer or a high-resistivity buffer layer 41, the bottom electrode 12 and the SOT orbital layer 20 can be electrically connected, ensuring stable device operation.

[0066] Example 3:

[0067] Please refer to Figure 10, which is a schematic diagram of another spin-orbit torque magnetic random access memory provided in an embodiment of the present invention. The difference between this magnetic random access memory and that of Embodiment 1 is as follows:

[0068] Buffer layer 40 is a high-resistivity buffer layer 41;

[0069] The high-resistivity buffer layer 41 covers the entire surface of the bottom electrode 12 structure corresponding to the SOT track layer 20.

[0070] In the existing SOT track layer 20, which is in complete contact with the bottom electrode 12, the current density at the edge of the SOT track layer 20 is too low, which is not conducive to the flipping of the free layer in the magnetic tunnel junction. In this embodiment, the buffer layer 40 is set as a high-resistivity buffer layer 41, and this high-resistivity buffer layer 41 is set to cover the entire surface of the SOT track layer 20 corresponding to the bottom electrode 12 structure. On the one hand, it is only necessary to set a high-resistivity buffer layer 41 to cover the entire surface of the SOT track layer 20 corresponding to the bottom electrode 12 structure. The side facing away from the bottom electrode 12 structure is a flat surface. When the SOT track layer 20 is subsequently fabricated on the surface of the high-resistivity buffer layer 41, the flatness of the fabricated SOT buffer layer 40 can be guaranteed, and bending of the SOT track layer 20 can be avoided. On the other hand, the high-resistivity buffer layer 41 can realize the conductive connection between the bottom electrode 12 and the SOT buffer layer 40. At the same time, a two-dimensional leakage current will be formed between the high-resistivity buffer layer 41 and the fabricated SOT track layer 20, which will balance the current density on the lower side of the SOT track layer 20 and improve the performance of the magnetic random access memory. This embodiment utilizes the electrical properties of the high-resistivity buffer layer 41 between the bottom electrode 12 and the SOT orbital layer 20 to optimize the current density distribution within the SOT orbital layer 20, thereby improving the flipping efficiency of the free layer in the magnetic tunnel junction.

[0071] The fabrication process of the spin-orbit torque magnetic random access memory described above in this embodiment can be referred to Figures 11 to 15. Figures 11 to 15 are examples of fabrication of another spin-orbit torque magnetic random access memory provided in this embodiment of the invention. In Figure 11, the enlarged view of the partial structure marked by the box shows the structure with a height difference between the bottom electrode 12 and the bottom dielectric structure 11 on the upper surface. In this embodiment, the bottom electrode 12 protrudes from the bottom dielectric structure 11 at one end towards the SOT orbital layer 20. In fact, this embodiment is also applicable when the bottom electrode 12 forms a depression in the bottom dielectric structure 11 at one end towards the SOT orbital layer 20. Figure 12 corresponds to the preparation of a high-resistivity buffer layer 41 on the surface of the bottom electrode structure. The surface of the high-resistivity buffer layer 41 is not flat and needs to be planarized by subsequent chemical mechanical polishing to obtain the structure shown in Figure 13. Figures 14 to 15 show the encapsulation of the prepared structure using a dielectric material after the SOT orbital layer 20, magnetic tunnel junction 30, hard mask 1 and protective layer 4 are prepared in sequence, and the top electrode 50 shown in Figure 15 is prepared.

[0072] Furthermore, in order to ensure the functionality of the high-resistivity buffer layer 41 and avoid short-circuiting the bottom electrode 12, the thickness of the high-resistivity buffer layer 41 can be set to 1 nanometer to 30 nanometers.

[0073] The resistivity of the high-resistivity buffer layer 41 is from 1 milliohm·cm to 50 milliohm·cm.

[0074] In this embodiment, the thickness of the high-resistivity buffer layer 41 is set to 1 nanometer to 30 nanometers, and the resistivity is set to 1 milliohm·cm to 50 milliohm·cm. This ensures that the high-resistivity buffer layer 41 conducts electricity in the thickness direction and avoids connection to the bottom electrode 12 in the high-resistivity buffer layer 41, while maintaining lateral conductivity. Furthermore, in this embodiment, the thickness of the high-resistivity buffer layer 41 can be further set to 1 nanometer to 5 nanometers.

[0075] Furthermore, in order to ensure the smooth fabrication of the high-resistivity buffer layer 41, the high-resistivity buffer layer 41 may be provided in combination or stacked with one or more of the following: tungsten buffer layer, tungsten nitride buffer layer, titanium nitride buffer layer, tantalum buffer layer, tantalum nitride buffer layer, nickel buffer layer, chromium buffer layer, and silicon buffer layer.

[0076] In this embodiment, a high-resistivity buffer layer 41 is provided, including but not limited to one or more of the following: tungsten buffer layer, tungsten nitride buffer layer, titanium nitride buffer layer, tantalum buffer layer, tantalum nitride buffer layer, nickel buffer layer, chromium buffer layer, and silicon buffer layer, or a mixture or stack of multiple types, to ensure the functionality of the high-resistivity buffer layer 41 and improve the stability of the device.

[0077] By applying the spin-orbit torque magnetic random access memory provided in this embodiment of the invention, the buffer layer 40 is set as a high-resistivity buffer layer 41, and the high-resistivity buffer layer 41 is set to cover the entire surface of the SOT orbital layer 20 corresponding to the bottom electrode 12 structure. On the one hand, the flatness of the prepared SOT buffer layer 40 is ensured, and the bending of the SOT orbital layer 20 is avoided. On the other hand, the bottom electrode 12 and the SOT buffer layer 40 are electrically connected. At the same time, a two-dimensional leakage current is formed between the high-resistivity buffer layer 41 and the prepared SOT orbital layer 20, which balances the current density on the lower side of the SOT orbital layer 20 and improves the performance of the magnetic random access memory. Furthermore, by setting the thickness of the high-resistivity buffer layer 41 to 1 nanometer to 30 nanometers and the resistivity to 1 milliohm·cm to 50 milliohm·cm, the present invention ensures that the high-resistivity buffer layer 41 conducts in the thickness direction and avoids connection to the bottom electrode 12 in the high-resistivity buffer layer 41, thus conducting in the lateral direction. By setting the high-resistivity buffer layer 41 to include, but is not limited to, one or more of the following: tungsten buffer layer, tungsten nitride buffer layer, titanium nitride buffer layer, tantalum buffer layer, tantalum nitride buffer layer, nickel buffer layer, chromium buffer layer, and silicon buffer layer, or a mixture or stack of multiple types, the functionality of the high-resistivity buffer layer 41 is ensured and the stability of the device is improved.

[0078] The following describes a method for preparing a spin-orbit torque magnetic random access memory (MORAM) according to an embodiment of the present invention. The method described below can be referred to in correspondence with the method described above.

[0079] Please refer to Figure 16 for details. Figure 16 is a flowchart of a method for preparing a spin-orbit torque magnetic random access memory according to an embodiment of the present invention, which may include:

[0080] S101: Provides a bottom electrode structure, which includes a bottom dielectric structure and a bottom electrode. The bottom dielectric structure is provided with a through hole, and the bottom electrode is disposed in the through hole. The upper end of the bottom electrode and the upper end of the bottom dielectric structure form a height difference.

[0081] The execution subject of this embodiment is a spin-orbit torque magnetic random access memory (SORM) fabrication device. The bottom electrode structure in this embodiment is the same as the bottom electrode structure in the aforementioned SORM. However, this embodiment provides a bottom electrode structure with a height difference formed by chemical mechanical planarization of the upper end of the bottom electrode and the upper end of the bottom dielectric structure.

[0082] S102: A buffer layer is prepared on the upper side of the bottom electrode structure so that the buffer layer and the bottom electrode structure are combined to form a flat surface; an SOT orbital layer, a magnetic tunnel junction and a top electrode are stacked on the flat surface, and the bottom electrode is conductively connected to the SOT orbital layer.

[0083] In this embodiment, a buffer layer is prepared on the upper side of the bottom electrode structure. This buffer layer can fill the height difference between the bottom electrode and the bottom dielectric structure, and thus combine with the bottom electrode structure to form a flat upper surface. Subsequently, when the SOT orbital layer, magnetic tunnel junction and top electrode are sequentially stacked on this flat surface, the surfaces of each layer in the stacked SOT orbital layer, magnetic tunnel junction and top electrode are flat and there are no bends in each layer, so as to ensure the performance of the magnetic random access memory.

[0084] Furthermore, to improve the ease of fabrication of the magnetic random access memory, the aforementioned preparation of a buffer layer on the upper side of the bottom electrode structure, so that the buffer layer and the bottom electrode structure combine to form a flat surface, may include:

[0085] A high-resistivity buffer layer is prepared on the entire upper surface of the bottom electrode structure, and a flat surface is formed on the side of the high-resistivity buffer layer facing away from the bottom electrode structure.

[0086] It should be noted that in this embodiment, a high-resistivity buffer layer is prepared on the entire upper surface of the bottom electrode structure, eliminating the need for a patterned structure, thus reducing the complexity of buffer layer preparation and improving preparation efficiency.

[0087] Furthermore, to ensure that a flat surface is formed on the side of the high-resistivity buffer layer facing away from the bottom electrode structure, the above-mentioned preparation of a high-resistivity buffer layer on all surfaces of the upper side of the bottom electrode structure, and the formation of a flat surface on the side of the high-resistivity buffer layer facing away from the bottom electrode structure, may include:

[0088] A high-resistivity buffer layer is prepared on the entire upper surface of the bottom electrode structure, and the side of the high-resistivity buffer layer facing away from the bottom electrode structure is subjected to chemical mechanical polishing to form a flat surface.

[0089] It should be noted that in this embodiment, chemical mechanical polishing is used to form a flat surface on the side of the prepared high-resistivity buffer layer that is away from the bottom electrode structure. Since the high-resistivity buffer layer covers the entire surface of the upper side of the bottom electrode structure, the chemical mechanical polishing is only applied to the high-resistivity buffer layer, ensuring that the flat surface is successfully prepared.

[0090] As can be seen, the method for fabricating a spin-orbit torque magnetic random access memory (SOTMM) provided by the present invention includes S101: providing a bottom electrode structure, the bottom electrode structure including a bottom dielectric structure and a bottom electrode, the bottom dielectric structure having a through hole, and the bottom electrode disposed within the through hole; a height difference is formed between the upper end of the bottom electrode and the upper end of the bottom dielectric structure; S102: fabricating a buffer layer on the upper side of the bottom electrode structure, so that the buffer layer and the bottom electrode structure combine to form a flat surface; and fabricating a SOTMM, a magnetic tunnel junction, and a top electrode on the flat surface, with the bottom electrode correspondingly conductively connected to the SOTMM. The present invention, by setting a buffer layer on the side of the bottom electrode structure facing the SOTMM, and setting the buffer layer and the bottom electrode structure to form a flat surface facing the SOTMM, and with the bottom electrode correspondingly conductively connected to the SOTMM, improves the flatness of the SOTMM and the magnetic tunnel junction, reduces the roughness below the SOTMM, reduces the fabrication difficulty, improves device performance, and ensures the uniformity of device performance when fabricating the SOTMM on this flat surface.

[0091] Furthermore, in this embodiment of the invention, a high-resistivity buffer layer is prepared on the entire upper surface of the bottom electrode structure, eliminating the need for patterned structures, thus reducing the complexity of buffer layer preparation and improving preparation efficiency. Chemical mechanical polishing is used to form a flat surface on the side of the prepared high-resistivity buffer layer facing away from the bottom electrode structure, ensuring the smooth preparation of the flat surface of the high-resistivity buffer layer.

[0092] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The methods disclosed in the embodiments are described simply because they correspond to the magnetic random access memory disclosed in the embodiments; relevant details can be found in the method section.

[0093] Furthermore, it should be noted that in this document, relationships such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0094] The present invention provides a detailed description of a spin-orbit torque magnetic random access memory and its preparation method. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A spin-orbit torque magnetic random access memory, characterized in that, include: The stacked bottom electrode structure, SOT orbital layer, magnetic tunnel junction, and top electrode; The bottom electrode structure includes a bottom dielectric structure corresponding to the SOT orbital layer and a bottom electrode corresponding to the SOT orbital layer. The bottom dielectric structure is provided with a through hole, and the bottom electrode is disposed in the through hole. The bottom electrode is located at one end of the SOT orbital layer, and there is a height difference between the bottom dielectric structure and the end of the bottom dielectric structure located at the SOT orbital layer. The bottom electrode structure has a buffer layer on the side facing the SOT track layer. The buffer layer and the bottom electrode structure together form a flat surface facing the SOT track layer, and the bottom electrode is conductively connected to the SOT track layer.

2. The spin-orbit torque magnetic random access memory according to claim 1, characterized in that, The bottom electrode protrudes from one end of the SOT orbital layer and is located near the bottom dielectric structure, and the buffer layer exposes at least a portion of the bottom electrode.

3. The spin-orbit torque magnetic random access memory according to claim 2, characterized in that, The buffer layer is an insulating buffer layer or a high-resistance buffer layer.

4. The spin-orbit torque magnetic random access memory according to claim 1, characterized in that, The bottom electrode is lower than the bottom dielectric structure at the end closest to the SOT orbital layer, forming a recessed structure. The buffer layer is located only at the recessed structure; The buffer layer is a conductive buffer layer or a high-resistivity buffer layer.

5. The spin-orbit torque magnetic random access memory according to claim 1, characterized in that, The buffer layer is a high-resistivity buffer layer; The high-resistivity buffer layer covers the entire surface of the bottom electrode structure corresponding to the SOT orbital layer.

6. The spin-orbit torque magnetic random access memory according to claim 5, characterized in that, The thickness of the high-resistivity buffer layer is 1 nanometer to 30 nanometers; The resistivity of the high-resistivity buffer layer is from 1 milliohm·cm to 50 milliohm·cm.

7. The spin-orbit torque magnetic random access memory according to claim 5, characterized in that, The high-resistivity buffer layer includes, but is not limited to, one or more of the following: tungsten buffer layer, tungsten nitride buffer layer, titanium nitride buffer layer, tantalum buffer layer, tantalum nitride buffer layer, nickel buffer layer, chromium buffer layer, and silicon buffer layer, or a mixture or stack of multiple types.

8. A method for fabricating a spin-orbit torque magnetic random access memory, characterized in that, include: A bottom electrode structure is provided, the bottom electrode structure including a bottom dielectric structure and a bottom electrode, the bottom dielectric structure having a through hole, and the bottom electrode being disposed within the through hole; a height difference is formed between the upper end of the bottom electrode and the upper end of the bottom dielectric structure; A buffer layer is prepared on the upper side of the bottom electrode structure so that the buffer layer and the bottom electrode structure are combined to form a flat surface; an SOT orbital layer, a magnetic tunnel junction and a top electrode are stacked on the flat surface, and the bottom electrode is conductively connected to the SOT orbital layer.

9. The method for preparing a spin-orbit torque magnetic random access memory according to claim 8, characterized in that, A buffer layer is prepared on the upper side of the bottom electrode structure so that the buffer layer and the bottom electrode structure combine to form a flat surface, including: A high-resistivity buffer layer is prepared on the entire upper surface of the bottom electrode structure, and a flat surface is formed on the side of the high-resistivity buffer layer facing away from the bottom electrode structure.

10. The method for preparing a spin-orbit torque magnetic random access memory according to claim 8, characterized in that, A high-resistivity buffer layer is prepared on the entire upper surface of the bottom electrode structure, and a flat surface is formed on the side of the high-resistivity buffer layer facing away from the bottom electrode structure, including: The high-resistivity buffer layer is prepared on the entire upper surface of the bottom electrode structure, and the side of the high-resistivity buffer layer facing away from the bottom electrode structure is subjected to chemical mechanical polishing to form the flat surface.

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