Method for epitaxy from a nucleation layer

Abstract

A stack (1) is provided, the stack (1) comprising a support (100), itself comprising a substrate (10) based on a first semiconductor material, an insulating layer (20), and a nucleation layer (30). The support (100) has a portion that is not covered by the nucleation layer (30), referred to as the exposed portion (150). The exposed portion has an exposed upper face (151) that is formed in this step by the insulating layer (20). The support is then modified such that the upper face of its exposed portion (150) is at least partially formed by a layer based on a third semiconductor material, referred to as the semiconductor layer (10). Epitaxy is then carried out from the nucleation layer (30).

Description

[0001] "Epitaxial process from a nucleation layer"

[0002] TECHNICAL FIELD OF THE INVENTION

[0003] The present invention relates to the fields of microelectronics and optoelectronics. It concerns an epitaxial process using a thin film deposited on a substrate, for example, a thin film of indium phosphide (InP) on a silicon (Si) substrate. The present invention can be used, in particular, for the fabrication of microelectronic or optoelectronic components. Its particularly advantageous applications include high-frequency devices, photonics (3D detection, health monitoring, etc.), and shortwave infrared (SWIR) image sensors.

[0004] STATE OF THE ART

[0005] Components based on III-V materials, particularly indium phosphide (InP), are increasingly used in microelectronics and optoelectronics. They can be manufactured using various processes.

[0006] The current commercial solution involves manufacturing components directly on a bulk InP substrate and then packaging them into chips. In some technology applications, these chips are then transferred to a silicon substrate. A more economically and environmentally friendly approach is to deposit a thin layer of InP onto a silicon wafer, forming an InPOSi substrate, and then grow the components directly on this thin layer. This approach offers numerous advantages. For example, the laser systems fabricated in this way exhibit low-loss evanescent optical coupling with the photonic silicon of the circuits. They can also be manufactured using dense integration to improve chip performance and reduce manufacturing costs.More generally, when this approach is implemented using Smart Cut™ technology, it reduces manufacturing costs. The bulk InP material from which the InP thin layer is derived can be recycled after bonding and separation. Since InP is an expensive material (approximately €700 per 100 mm diameter wafer), material recycling is a significant advantage. Furthermore, by using paved InPOSi structures, it is possible to create much larger substrates, which is not the case with a bulk InP substrate, as these substrates currently have a maximum diameter of 150 mm.

[0007] InPOSi substrates can thus be divided into two categories:

[0008] • InPOSi substrates obtained by full-plate InP transfer (only applicable to small InP bulk substrates, i.e., those with a diameter of 150 mm or less). The substrate thus obtained is illustrated in Figures 1A (top view) and 1B (cross-sectional view). • InPOSi substrates obtained by discontinuous transfer of InP chips from a pseudo-donor substrate. The InP chips typically form a tiling pattern on the Si substrate, as illustrated in Figures 2A and 2B.

[0009] In both configurations, the InP film generally does not extend to the very edge of the Si wafer. This is due to the presence of bevels at the periphery of the substrates and is characteristic of layer transfer techniques based on the molecular bonding of substrates (wafer bonding), of which Smart Cut™ technology is a part. As illustrated in Figures 1A, 1B, 2A, and 2B, a dielectric ring 25 with a width on the order of a few millimeters (usually 1 to 3 mm) extends at the periphery. Furthermore, in the case of an InPOSi substrate with InP tiling, the dielectric is also visible between the InP chips.

[0010] During the epitaxial step performed using the InPOSi substrate, the presence of inactive areas at the periphery and possibly between the InP chips can generate a SAG (selective area growth) effect, i.e., selective growth of the epitaxial cells. This is particularly the case with MOCVD (Metal Organic Chemical Vapor Deposition) chemical vapor deposition techniques using metal-organic precursors. Indeed, two precursor diffusion regimes contribute to the variation in the deposition rate: gas-phase diffusion and surface diffusion, represented by arrows labeled 2 and 3 respectively in Figure 3. These diffusion phenomena cause a variation in the growth rate because both diffusions are dependent on the precursor concentration.As a result, the deposited thicknesses are greater in the vicinity of the dielectric zone, thus resulting in an overthickness 45 in the vicinity of this zone (see figure 3).

[0011] It is also noted that vapor-phase diffusion 2 has a diffusion length much greater than surface diffusion 3 (several hundred microns versus a few micrometers). These diffusion lengths depend on the epitaxial conditions (epitaxial temperature, gas flow rate, pressure, etc.), the desired epitaxial stacking (nature of the materials, layer thickness, total stacking thickness, etc.), and also on the size of the dielectric mask. Thus, although both phenomena are present, they operate at different scales: surface diffusion 3 dominates in the immediate vicinity of the mask, while vapor-phase diffusion 2 becomes predominant as one moves away from the mask.

[0012] In the intended applications, the SAG effect is a drawback. It induces excessive epitaxial growth at the InP edge, and even compositional variations. These areas cannot be used for manufacturing functional components, significantly reducing the wafer's usable surface area. This is exacerbated for paving structures as illustrated in Figures 2A and 2B, where the SAG effect occurs even between the InP chips. Furthermore, for high epitaxial growth, the SAG effect will be amplified and can lead to delamination, crystal defects, cracks, and / or compositional variations, making the InPOSi substrate unsuitable.

[0013] The object of the invention is thus to minimize or even eliminate the SAG effect during epitaxy.

[0014] SUMMARY OF THE INVENTION

[0015] To achieve this objective, a first aspect of the invention relates to an epitaxial process from a nucleation layer comprising the following steps: • providing a stack comprising, stacked along a so-called stacking direction:

[0016] o a support, comprising, stacked according to the stacking direction:

[0017] - a substrate, preferably based on a first semiconductor material, preferably silicon,

[0018] - a layer based on a first electrically insulating material, called the insulating layer, and

[0019] o a layer based on a second semiconductor material, called the nucleation layer, preferably based on an III-V material.

[0020] The support has a portion not covered by the nucleation layer, called the exposed portion, the exposed portion having an exposed upper face, the upper face of the exposed portion being formed at this stage by the insulating layer.

[0021] The process also includes the following steps:

[0022] • modify the support so that the upper face of its exposed portion is at least partly formed by a layer based on a third semiconductor material, called a semiconductor layer, • perform an epitaxy from the nucleation layer.

[0023] The support modification is designed to reduce the selective growth effect of epitaxy between the nucleation layer and the exposed portion of the insulating layer. The support modification step includes a step of forming a layer based on the third semiconductor material, called the cover layer, onto the insulating layer. The semiconductor layer thus acts as the cover layer.

[0024] The modification of the exposed portion is carried out at the level of the crown, at the edge of the wafer, and possibly, in the case of a stack obtained by transferring semiconductor chips, between these chips.

[0025] Modifying the exposed portion so that a semiconductor layer is flush with the surface in this region allows for greater nucleation in this area. By promoting this nucleation, growth during the epitaxial step is homogenized, both in terms of thickness and composition of the epitaxial layer. The layer formed by epitaxy thus exhibits a less pronounced excess thickness than in the prior art, or even a virtually constant thickness. Furthermore, the composition of the epitaxial layer shows less variation. The SAG effect is therefore reduced or even eliminated. Thanks to the process according to the invention, unusable areas for device fabrication are thus reduced or even eliminated.

[0026] A second aspect of the invention relates to a stacking comprising, stacked according to a so-called stacking direction:

[0027] • a support comprising a substrate based on a first semiconductor material, preferably silicon,

[0028] • a layer based on a second semiconductor material, called the nucleation layer, preferably based on an III-V material.

[0029] The support has a portion not covered by the nucleation layer, called the exposed portion, the exposed portion having an exposed upper face, the upper face of the exposed portion being formed by the substrate. The stack further includes a layer based on a semiconductor obtained by epitaxy, called the epitaxial layer, extending above and in contact with the nucleation layer and the substrate.

[0030] A third aspect of the invention relates to a stacking comprising, stacked according to a so-called stacking direction:

[0031] • a support, comprising, stacked according to the stacking direction:

[0032] o a substrate, preferably based on a first semiconductor material, preferably silicon,

[0033] o a layer based on a first electrically insulating material, called the insulating layer, and

[0034] o a coating layer based on a third semiconductor material,

[0035] • a layer based on a second semiconductor material, called the nucleation layer, preferably based on an III-V material.

[0036] The support having a portion not covered by the nucleation layer, called the exposed portion, the exposed portion having an exposed upper face, the upper face of the exposed portion being formed by the covering layer.

[0037] The stack further includes a layer based on a semiconductor produced by epitaxy, called the epitaxial layer, extending above the nucleation layer and the covering layer.

[0038] In one example, the top layer forms the entire upper surface of the exposed portion of the substrate.

[0039] The advantages described with reference to the process according to the first aspect of the invention apply mutatis mutandis to the stacking according to the second aspect of the invention.

[0040] BRIEF DESCRIPTION OF THE FIGURES

[0041] The aims, objects, features and advantages of the invention will become clearer from the detailed description of an embodiment thereof, which is illustrated by the following accompanying drawings in which:

[0042] Figures 1A and 1B represent a substrate obtained by full-plate transfer of a semiconductor thin film onto a support.

[0043] Figures 2A and 2B represent a substrate obtained by transferring a thin semiconductor film in the form of a plurality of chips onto a support.

[0044] Figure 3 illustrates the SAG effect occurring during the epitaxy of a thin film near a dielectric layer.

[0045] Figures 4A to 4E illustrate a first embodiment of the present invention in which the final epitaxy is carried out from a continuous nucleation layer.

[0046] Figures 5A to 5E illustrate a second embodiment of the present invention in which the final epitaxy is carried out from a plurality of nucleation chips that are disjoint from each other.

[0047] Figures 6A and 6B illustrate one embodiment of this disclosure in which the insulating layer is removed locally by etching at the exposed portion of the substrate.

[0048] Figures 7A and 7B illustrate embodiments of this disclosure in which the insulating layer is locally removed by mechanical process at the exposed portion of the support.

[0049] Figures 8A to 8D illustrate an embodiment of the invention in which a topcoat is deposited on the insulating layer at the exposed portion of the substrate, in the case of a continuous nucleation layer. In this example, the topcoat is deposited through a protective mask.

[0050] Figures 9A to 9D illustrate an embodiment of the invention in which a topcoat is deposited on the insulating layer at the exposed portion of the substrate, in the case of a continuous nucleation layer. In this example, the nucleation layer is protected by a protective structure during the deposition of the topcoat.

[0051] Figures 10A to 10C illustrate an embodiment of the invention in which a cover layer is deposited on the insulating layer at the exposed portion of the support, in the case of a nucleation layer in the form of chips.

[0052] Figures 11 A and 11 B are explanatory diagrams illustrating the increase in nucleation at the level of inactive areas and thus the reduction of the SAG effect thanks to the present invention.

[0053] The drawings are provided as examples and are not intended to limit the scope of the invention. They are schematic representations of the principle intended to facilitate understanding of the invention and are not necessarily to scale with practical applications. In particular, the dimensions are not representative of reality.

[0054] DETAILED DESCRIPTION OF THE INVENTION

[0055] Before proceeding with a detailed review of embodiments of the invention, optional features that may be used in combination or alternatively are listed below:

[0056] According to a preferred example, before the support modification step, the exposed top face has an RMS roughness Ri, and after the support modification step, the exposed top face has an RMS roughness R2, with R2>RI.

[0057] According to a preferred example, R2 is greater than or equal to 0.40 nm.

[0058] According to a preferred example, in a transverse plane substantially perpendicular to the stacking direction, the semiconductor layer extends from the nucleation layer.

[0059] According to a preferred example, the semiconductor layer surrounds the nucleation layer, preferably completely.

[0060] According to a preferred example, the nucleation layer is based on an III-V material, for example InP, GaAs or GaN.

[0061] According to one example of an implementation of this disclosure, the substrate modification step includes a step of removing the insulating layer from the exposed portion of the substrate to expose the substrate, and in this embodiment, the semiconductor layer is the substrate. In this embodiment, the third semiconductor material is identical to the first semiconductor material.

[0062] According to one example, the removal of the insulating layer is achieved by etching.

[0063] In one example, the removal of the insulating layer is carried out at least partially by a mechanical process such as grinding, sawing, or laser irradiation. In one embodiment, the substrate modification step includes a step of forming a layer based on the third semiconductor material, called the covering layer, onto the insulating layer, and in this embodiment, the semiconductor layer is the covering layer. In this embodiment, the third semiconductor material is not necessarily identical to the first or second semiconductor material.

[0064] In a preferred example, the third semiconductor material and the second semiconductor material are similar. This allows for greater homogeneity in the epitaxial step.

[0065] In a preferred embodiment, the formation of the coating layer includes a step of immersing the substrate in a colloidal solution containing particles of the third semiconductor material. Immersion in the colloidal solution ensures good coverage of the exposed portions of the insulating layer. This method is particularly well-suited to cases where the nucleation layer is in the form of semiconductor chips. The colloidal solution can easily penetrate the inter-chip spaces, which are difficult to access using other deposition methods.

[0066] According to one embodiment, the process further comprises:

[0067] • before the formation of the cover layer, a step of transferring a protective structure onto the nucleation layer, and,

[0068] • after the formation of the cover layer and before the epitaxial step from the nucleation layer, a step of removal of the protective structure.

[0069] The protective structure helps to protect the nucleation layer during the deposition of the cover layer.

[0070] Selective etching with respect to or etching with selectivity with respect to means etching configured to remove a material A or a layer A with respect to a material B or a layer B, and having an etching speed of material A greater than the etching speed of material B. Selectivity is the ratio of the etching speed of material A to the etching speed of material B. The selectivity between A and B is denoted SA:B.

[0071] It is specified that, within the framework of the present invention, the terms "on", "overcomes", "covers", "underlying", "opposite" and their equivalents do not necessarily mean "in contact with". Thus, for example, the depositing, transferring, gluing, assembling or applying a first layer on a second layer does not necessarily mean that the two layers are directly in contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it or by being separated from it by at least one other layer or at least one other element.

[0072] A layer can also be composed of several sub-layers of the same material or of different materials.

[0073] The term "III-V material" refers to a semiconductor composed of one or more elements from columns III and V of the periodic table. Elements in column III include boron, gallium, aluminum, and indium. Column V contains, for example, nitrogen, arsenic, antimony, and phosphorus. The term "II-VI material" refers to a semiconductor composed of one or more elements from columns II and VI of the periodic table, while the term "IV-IV material" refers to a semiconductor composed of at least two elements from column IV of the periodic table.

[0074] A substrate, layer, or device "based" on a material M is understood to be a substrate, layer, or device comprising only that material M, or that material M and possibly other materials, for example, alloying elements, impurities, or dopants. Thus, a material based on a material III-N may comprise a material III-N with added dopants.

[0075] A material is said to be "electrically insulating" when it has a conductivity preferably less than 10⁻¹⁰ Ω. 8 S / m or a resistivity greater than 10 8 Qm

[0076] A coordinate system, preferably orthonormal, comprising the X, Y, and Z axes is shown in Figures 4A to 10C. This coordinate system can be applied by extension to the other figures. The direction along the Z axis is typically designated as the Z stacking direction.

[0077] In this patent application, the terms thickness for a layer and height for a structure or device will be preferred. Height is measured perpendicular to the transverse plane XY. Thickness is measured in a direction normal to the principal plane of extension of the layer. Thus, a layer typically has a thickness along the Z-axis when it extends primarily along the transverse plane XY, and a projecting element, such as a trench, has a height along the Z-axis. The relative terms "on," "under," and "below" preferentially refer to positions measured along the Z-axis.

[0078] The terms "approximately," "about," and "on the order of" mean "within 10%, preferably within 5%." RMS roughness corresponds to the root mean square of the microscopic peaks and troughs measured on a surface. It is classically measured using an atomic force microscope (AFM) over a 1 pm x 1 pm field.

[0079] The process according to the invention will now be described in more detail.

[0080] A first embodiment of the supply of the stack 1 is illustrated in figures 4A to 4H. This first embodiment relates to a substrate obtained by full-plate transfer of a semiconductor layer onto a support.

[0081] The first phase of the process consists of forming a thin semiconductor film on a substrate. This first phase can notably be carried out using a Smart Cut™ process, as illustrated in Figures 4A to 4E and described in detail below.

[0082] A donor substrate 300 with a top face 301 is first provided (Figure 4A). The donor substrate 300 is based on a semiconductor material, for example, from the II-VI, II-IV (typically InP, GaN, or GaAs), or IV-IV materials. A coating 20' based on an electrically insulating material (for example, SiO2), called the dielectric coating 20', can then be deposited on the top face 301 of the donor substrate 300 (Figure 4B). Ion implantation, for example, of hydrogen ions (H+) and / or helium ions, is then carried out in the donor substrate 300 (Figure 4C). As illustrated in Figure 4D, a receiving substrate, also designated substrate 10, is then provided. This is typically a silicon substrate that has undergone thermal oxidation and thus has an oxide coating 20”. The donor substrate 300 is then bonded to the substrate 10 via the dielectric coating 20' and the oxide coating 20”.This assembly is achieved, for example, by hydrophilic bonding. It is possible to introduce other bonding layers between the dielectric coating 20' and the oxide coating 20”. It is also possible that there may be no intermediate bonding coating or only one of the dielectric coating 20' and the oxide coating 20”, in which case the bonding is achieved respectively between the donor substrate 100 and the oxide coating 20” or between the dielectric coating 20' and the support 10.

[0083] As illustrated by the transition from Figure 4D to Figure 4E, the donor substrate 300 then undergoes annealing, allowing its fracture at the previously ion-implanted site. This fracture leaves only a thin film of semiconductor material on the support 10. The remainder of the donor substrate 300 can be retained for a further iteration of the process according to the invention.

[0084] This results in the stacking 1 illustrated in Figure 4E, comprising: • A support 100 including:

[0085] o Substrate 10, typically silicon-based,

[0086] o An insulating layer 20 extending between the substrate 10 and the nucleation layer 30 and formed from a portion of the oxide coating 20” and the dielectric coating 20',

[0087] • A nucleation layer 30, corresponding to the thin film left on the support after fracture of the donor substrate 300.

[0088] The nucleation layer 30 has a thickness e3o measured along the stacking direction Z. e3o is typically less than or equal to 5 pm.

[0089] Alternatively, stack 1 can be obtained using a conventional disassembly technique (not shown). In this variant, the donor substrate 300 is not implanted and then fractured. After bonding to the substrate 10 via the dielectric coating 20' and optionally the oxide coating 20", the donor substrate 300 undergoes, for example, mechanical thinning by grinding and / or a CMP (chemical-mechanical polishing) step to thin it to the desired thickness e3o. Stack 1 is then obtained.

[0090] Regardless of the method used to obtain the stack 1, in a completely conventional manner, the nucleation layer 30 has smaller lateral dimensions than the support 100, particularly than those of the insulating layer 20 and the substrate 10. Thus, in the transverse XY plane, the support 100 extends beyond the nucleation layer 30. In other words, the support 100 has a portion 150 not covered by the nucleation layer 30. This portion is called the exposed portion 150. It has an upper face 151, also referred to as the exposed upper face 151 or the exposed face 151. At this stage of the process, the exposed face 151 of the support 100 is formed by the insulating layer 20, as can be seen in Figure 4E.

[0091] The exposed portion 150 extends over a dimension hso from the nucleation layer 30. In the classic case where the support 100 and the nucleation layer 30 each have a substantially circular shape in the transverse XY plane, the exposed portion 150 extends radially around the nucleation layer 30 and completely surrounds it. The dimension hso is then measured radially around the nucleation layer 30. hso is, for example, greater than or equal to 500 pm, or greater than or equal to 1 mm, or even 5 mm.

[0092] At this stage, various treatments can be carried out as needed (cleaning, heat treatment, CMP, ...) in order to prepare the nucleation layer 30 for epitaxy.

[0093] In the case of the Smart Cut™ process, a CMP step can be performed to remove the fracture zone, i.e. the area at which the ions had been implanted and the fracture of the donor substrate 100 took place.

[0094] The invention currently involves modifying the nature of the exposed portion 150. The objective of the invention is to promote nucleation at the edges of the wafer in order to homogenize growth by epitaxy. Various embodiments enabling the modification of the exposed portion 150 will be described later.

[0095] A second embodiment of the provision of the stack 1 is illustrated in Figures 5A to 5E. This second embodiment relates to a substrate obtained by transferring a semiconductor layer in the form of a plurality of chips onto a support.

[0096] This second embodiment is particularly advantageous in that it is compatible with supports 10 with a diameter of 200 mm as well as 300 mm.

[0097] First, a so-called pseudo-donor substrate is provided, comprising a support 1000 surmounted by a discontinuous donor substrate 300, forming a plurality of donor chips 350 (Figure 5A). The discontinuous donor substrate 300, and therefore the donor chips 350, are based on a semiconductor material, for example, taken from among the II-VI, III-V (typically InP, GaN, or GaAs) or IV-IV materials.

[0098] A 20' coating based on an electrically insulating material (e.g., SiO2), called a 20' dielectric coating, can then be deposited on the 350 donor chips (Figure 5B). This coating is optional.

[0099] In the Smart Cut™ process, ion implantation, for example of hydrogen ions (H+) and / or helium ions, is then carried out in the donor substrate 300 (Figure 5C). As illustrated in Figure 5D, a recipient substrate, also referred to as substrate 10, is then provided. As in the first embodiment, this is typically a silicon substrate, possibly coated with an oxide layer 20”. The donor chips 350 are then bonded to the substrate 10 via the dielectric layer 20' and the oxide layer 20”. This bonding is achieved, for example, by hydrophilic bonding. It is possible to introduce other bonding layers, for example, between the dielectric layer 20' and the oxide layer 20”.

[0100] As illustrated by the transition from Figure 5D to Figure 5E, the donor chips 350 then undergo thermal annealing, allowing them to fracture at the previously performed ion implantation. This fracture leaves only a discontinuous, semiconducting thin film on the substrate 10, thus forming a plurality of semiconductor chips 35. The remaining donor chips 350 can be retained for a further iteration of the process according to the invention.

[0101] This results in the stacking arrangement 1 illustrated in figure 5E, comprising:

[0102] • A 100 support package including:

[0103] o Substrate 10, typically silicon-based,

[0104] o An insulating layer 20 extending between the support 10 and the nucleation layer 30 and formed from a portion of the oxide coating 20” and the dielectric coating 20',

[0105] • A nucleation layer 30, corresponding to the discontinuous thin film left on the substrate after fracture of the donor chips 350. The nucleation layer 30 is thus formed from a plurality of semiconductor chips 35. The semiconductor chips 35 have a dimension ho. In the case of square-shaped chips in the transverse XY plane, ho corresponds to their side, ho is typically greater than or equal to 0.3 cm, for example approximately equal to 1 cm.

[0106] The semiconductor chips 35 are also spaced at an interchip distance dinter. dj n ter is typically greater than or equal to 100 pm, for example substantially equal to 250 pm.

[0107] As in the first embodiment, alternatively, stack 1 can be obtained by a conventional disassembly technique (not shown). In this variant, the donor chips 350 are not implanted and then fractured. After bonding to the support 10 via the dielectric coating 20' and optionally the oxide coating 20", the donor substrate 300 undergoes mechanical thinning, for example by milling and / or a CMP (chemical-mechanical polishing) step to reduce it to the desired thickness e3o. Stack 1 is then obtained.

[0108] As in the first embodiment, before carrying out an epitaxial step to form an epitaxial layer 40 from the nucleation layer 30, the invention provides for modifying the exposed upper face 151 of the exposed portion 150 of the support 100 to limit or even eliminate the SAG effect.

[0109] Several techniques for modifying the exposed portion 150 will now be described with reference to figures 6A to 11B.

[0110] According to a first example of implementing the modification of the exposed portion 150, the insulating layer 20 is locally removed at the level of the exposed portion 150. This removal exposes the substrate 10. The substrate 10 is indeed based on a first semiconductor material, typically silicon, which is conducive to epitaxy. Advantageously, the insulating layer 20 is removed across the entire width of the exposed portion 150.

[0111] In a first example, the insulating layer 20 is removed by etching. It is possible to perform either wet or dry etching.

[0112] In the case of wet etching, it is not always necessary to protect the nucleation layer 30 during removal. It is possible, in particular, to choose an etching chemistry that provides sufficient selectivity so that the nucleation layer 30 is minimally etched, or not at all affected, or damaged during the removal of the insulating layer 20. For example, in the case of an InP-based nucleation layer 30 and a SiC>2-based insulating layer 20, wet etching with an HF solution offers perfectly satisfactory selectivity. In the case of dry etching, it is preferable to protect the nucleation layer 30. This example is illustrated in Figures 6A and 6B. Figure 6A illustrates the formation of a protective mask 60, typically resin-based, on the nucleation layer 30. The protective mask 60 is defined by conventional photolithography processes.The protective mask 60 can, for example, be based on SiC>2 or SiN. Dry etching is then carried out (Figure 6B), using, for example, an ICP (inductively coupled plasma) etching process. Gases that can be used for this purpose include, for example: CHF3, CF7+O2, CH4+H2, or SiCk. Once the insulating layer 20 is removed, the protective mask 60 is also removed. A chemical cleaning step can be performed after the removal of the protective mask 60 to make the upper surface 31 of the nucleation layer 30 more suitable for a subsequent epitaxial step. Many other dry etching methods are possible, not necessarily under plasma. For example, an ion beam, such as Argon, can be used; bombardment of the insulating layer causes its atomization and thus its etching.The use of such an ion beam can also be associated with the use of a protective mask, or be associated with focusing and / or scanning concentrating the effect of the bombardment on the areas to be engraved.

[0113] According to another example illustrated in Figures 7A and 7B, the insulating layer 20 is removed by a mechanical or mechano-chemical process targeting the exposed portion 150. Several removal methods are possible. For example, a grinding step can be used to polish the insulating layer 20 down to the substrate 10. Another option is to repeatedly cut the exposed portion 150 with a saw. Finally, exposing the exposed portion 150 to laser radiation, for example, nanosecond or picosecond laser radiation, is also a possibility.

[0114] Figure 7A illustrates the mechanical removal of the insulating layer 20 in the case of a continuous nucleation layer 30. A grinding step around the wafer periphery is well suited to this case. Figure 9B illustrates the case of a nucleation layer 30 in the form of semiconductor chips 35. Mechanical treatment with a saw and laser are particularly well suited to this latter case, since they allow precise targeting of the areas where the treatment is effective, thus enabling their use to remove the apparent insulating layer 20 between the semiconductor chips 35.

[0115] As illustrated in Figures 7A and 7B, mechanical treatment typically removes substrate 10. This is advantageous: indeed, the various mechanical removal methods induce an updated topology on face 13 of substrate 10. This topology results in a roughness that is favorable to nucleation and therefore to the reduction of the SAG effect.

[0116] It is possible to combine different mechanical techniques described above, for example by carrying out a grinding step to remove the insulating layer 20 on the periphery of the wafer and a sawing or laser processing step for the inter-chip areas.

[0117] When the insulating layer 20 is removed by a mechanical or mechano-chemical process, it is advantageous to protect the nucleation layer 30 with a protective mask (not shown). This mask can, for example, be based on SiC>2 or Si N.

[0118] Chemical cleaning steps can also be carried out, for example to make the upper face 31 of the nucleation layer 30 more suitable for a subsequent epitaxial step.

[0119] The various examples described above thus allow the substrate 10 to be exposed at the exposed portion 150 of the support 100. In these examples, the semiconductor layer is therefore the substrate 10 and the third semiconductor material corresponds to the first semiconductor material.

[0120] According to a second embodiment of the modification of the exposed portion 150, a covering layer 50 based on a third semiconductor material is deposited on the insulating layer 20 at the level of the exposed portion 150. The third semiconductor material can for example be taken from the following materials: Si, Ge, InP, GaAs, a ternary taken from the following list: InGaP, InGaAs, AIGaN, InGaN, AIGaP, AIGaAs, AllnAs, GaAsN, GaAsP, InAsGa, InAsSb, AIGaSb, AlInSb, InGaSb, or a quaternary taken from the following list: AIGalnP, AIGaAsP, InGaAsP, AllnAsP, AIGaAsN, InGaAsN, InAIAsN, GaAsSbN. In the case of an InP-based coating layer 50, the InP can be amorphous or polycrystalline. Advantageously, the third semiconductor material is similar or even identical to the second semiconductor material on which the nucleation layer 30 is based.

[0121] The cover layer 50 is deposited over a width I50 around the nucleation layer 30. Preferably, I50 is greater than or equal to 10% of I150, preferably I50 is greater than or equal to 75% of I150, and advantageously, I50 = I150. Preferably I50 ≤ 100 µm. Advantageously, the cover layer 50 is deposited over the entire width of the exposed portion 150 (I50 = I150). In the case of a nucleation layer 30 formed by chips 35, the cover layer 50 preferably extends in the transverse XY plane throughout the inter-chip space.

[0122] Different methods of implementing the deposition of the cover layer 50 are envisaged in figures 8A to 10C.

[0123] Figures 8A to 8D on the one hand and 9A to 9D on the other hand illustrate the deposition of the cover layer 50 in the case where the nucleation layer 30 is continuous.

[0124] According to a first example illustrated in figures 8A to 8D, the deposition of the cover layer 50 is carried out after protection of the nucleation layer 30 by a protective mask 60.

[0125] Figure 8A illustrates stack 1, in which the exposed upper face 151 of the exposed portion 150 of the substrate 100 is formed by the insulating layer 20. Figure 8B illustrates the formation of a protective mask 60 on the nucleation layer 30. The protective mask 60 is formed by conventional photolithography and etching steps. It is typically resin-based. As illustrated in Figure 8C, the coating layer 50 is then deposited, typically in a full-plate manner. The coating layer 50 thus covers both the exposed portion 150 and the protective mask 60 at this stage. The coating layer 50 can be deposited, for example, by flash evaporation (or flashing) at room temperature or by immersing the stack in a colloidal solution. Such a colloidal solution contains nanoparticles of the third material, for example InP nanoparticles.As illustrated in Figure 8D, the protective mask 60 and the portion of the cover layer 50 covering it are then removed.

[0126] According to a second example illustrated in figures 9A to 9D, the deposition of the covering layer 50 is carried out by immersion in a colloidal solution after protection of the nucleation layer 30 by a protective structure 70.

[0127] Figure 9A illustrates stacking 1, in which the exposed upper face 151 of the exposed portion 150 of the support 100 is formed by the insulating layer 20. Figure 9B illustrates the transfer of the stacking, via the upper face 31 of the nucleation layer 30, onto a protective structure 70. The protective structure 70 is typically a silicon substrate. Advantageously, the protective structure 70 is bonded directly to the upper face 31 of the layer 30. As illustrated in Figure 9C, the covering layer 50 is then formed by immersion in a colloidal solution. The cover layer 50 thus covers at this stage both the exposed portion 150, the sides of the nucleation layer 30 and the face 71 of the protective structure 70 facing the support 100. As illustrated in Figure 9D, the protective structure 70 and the portion of the cover layer 50 covering it are then removed.

[0128] These two examples can be applied to the case of a nucleation layer 30 formed from semiconductor chips 35. It is thus possible to form the overlay layer 50 after supplying the stack as illustrated in Figure 5E. However, it is preferable to take advantage of the Smart Cut™ steps as described previously to form the overlay layer. Figures 10A to 10C illustrate this advantageous example.

[0129] As illustrated in Figure 10A, the first step involves transferring the pseudo-donor substrate 1000, along with its donor chips 350, onto the substrate 10, before the donor chips 350 are fractured by thermal annealing. The assembly is then immersed in the colloidal solution (Figure 10B), which allows the formation of the covering layer 50 on the insulating layer 20. During this step, the pseudo-donor substrate 1000 protects the donor substrate 300 (and therefore the future semiconductor chips 35). It thus plays the same role as the protective structure 70 in the previous example.

[0130] Thermal annealing is then carried out, allowing the fracture of the donor substrate 300 and the formation of the semiconductor chips 35. This results in the stack illustrated in Figure 10C.

[0131] The formation of the covering layer 50 by immersion in a colloidal solution is particularly suitable for the case illustrated in figures 10A to 10C where the nucleation layer 30 is in the form of semiconductor chips 35. Indeed, the colloidal solution can easily enter the inter-chip spaces.

[0132] In these last three examples, the cover layer 50 forms the upper face 151 of the exposed portion 150 of the support 100. The cover layer 50, by its chemical nature and its mode of deposition, promotes nucleation and a resumption of epitaxy.

[0133] Advantageously, and regardless of the method used to modify the exposed portion 150, before proceeding with the epitaxy step described below, a step is performed to remove a potential native oxide deposited on the exposed portion 150 (on the substrate 10 or on the cover layer 50, depending on the embodiment). This removal can be carried out chemically or thermally.

[0134] Once the modification step of the exposed portion 150 has been carried out (by removing the insulating layer 20 or by forming the covering layer 50), an epitaxy step is carried out from the nucleation layer 30. Preferably, and as permitted by the modification step of the exposed portion 150, the epitaxy is also carried out from the semiconductor layer, which corresponds, according to the embodiment, to the covering layer 50 or to the substrate 10.

[0135] The epitaxy step allows the formation of a layer based on a semiconductor material, called the epitaxial layer 40.

[0136] Figure 11A illustrates the stack obtained after epitaxy on a prior art stack. The nucleation layer 30 exhibits a gentle slope at the plate edge, inducing strong lateral growth during epitaxy. Furthermore, the insulating layer 20 is particularly smooth, thus allowing only a very low density of crystals to grow. These two factors result in a high concentration of growth at the edge of the nucleation layer 30.

[0137] Figure 11B illustrates the stack obtained after epitaxy on a stack according to the present invention, having undergone a modification of the exposed portion, and in particular a local removal of the insulating layer. The fact that the substrate 10 forms the exposed upper face 151 of the support 100 allows for better adhesion and therefore better crystal growth during epitaxy. Furthermore, the local removal of the insulating layer 20 typically results in making the lateral edge of the nucleation layer 30 more abrupt. These two characteristics allow for a more homogenized thickness of the epitaxial layer. The present invention also relates to the stacks obtained by the process according to the invention. Figure 11B is an enlargement of one of the stacks that can be obtained by the process according to the invention.

[0138] It appears from the various embodiments described above that the present invention offers an effective solution for reducing, or even eliminating, the SAG effect. It thus enables the fabrication of high-quality stacks over a larger area, which can be used to manufacture microelectronic and optoelectronic components.

[0139] The invention is not limited to the embodiments previously described and extends to all embodiments covered by the invention.

Claims

DEMANDS 1. Epitaxial process from a nucleation layer comprising the following steps: • provide a stacking (1) comprising, stacked along a so-called stacking direction (Z): o a support (100), comprising, stacked along the stacking direction (Z): a substrate (10), a layer based on a first electrically insulating material, called the insulating layer (20), and a layer based on a second semiconductor material, called the nucleation layer (30), the support (100) having a portion not covered by the nucleation layer (30), called the exposed portion (150), the exposed portion (150) having an exposed upper face (151), the upper face (151) of the exposed portion (150) being formed at this stage by the insulating layer (20), • modify the support (100) so that the upper face (151) of its exposed portion (150) is at least partly formed by a layer based on a third semiconductor material, called a semiconductor layer (10; 50), • perform epitaxy from the nucleation layer (30), the modification of the support (100) being configured to reduce a selective growth effect of epitaxy between the nucleation layer (30) and the exposed portion (150) of the insulating layer (20), the support modification step (100) comprising a step of forming on the insulating layer (20) a layer based on the third semiconductor material, called the covering layer (50), the semiconductor layer being the cover layer (50).

2. Method according to the preceding claim wherein, before the modification step of the support (100), the exposed upper face (151) has an RMS roughness Ri, and after the modification step of the support (100), the exposed upper face (151) has an RMS roughness R2, with R2>RI.

3. Method according to the preceding claim wherein R2 is greater than or equal to 0.40 nm.

4. Method according to any one of the preceding claims wherein, in a transverse plane (XY) substantially perpendicular to the stacking direction (Z), the semiconductor layer (10; 50) extends from the nucleation layer (30).

5. A method according to any one of the preceding claims in which the semiconductor layer (10; 50) surrounds the nucleation layer (30), preferably entirely.

6. A method according to any one of the preceding claims wherein the nucleation layer (30) is InP-based.

7. A method according to any one of the preceding claims wherein the third semiconductor material and the second semiconductor material are identical.

8. A method according to any one of the preceding claims in which the formation of the coating layer (50) comprises a step of immersing the support (100) in a colloidal solution comprising particles of the third semiconductor material.

9. A method according to any one of the preceding claims, further comprising: • before the formation of the cover layer (50), a step of transferring a protective structure (70) onto the nucleation layer (30), and, • after the formation of the cover layer (50) and before the epitaxy step from the nucleation layer (30), a step of removal of the protective structure (70).

10. Stacking (1) comprising, stacked along a so-called stacking direction (Z): • a support (100), comprising: o a substrate (10), o a layer based on a first electrically insulating material, called the insulating layer (20), and o a covering layer (50) based on a third semiconductor material, • a layer based on a second semiconductor material, called the nucleation layer (30), the support (100) having a portion not covered by the nucleation layer (30), called the exposed portion (150), the exposed portion (150) having an exposed upper face (151), the upper face (151) of the exposed portion (150) being formed by the covering layer (50), the stacking (1) further comprising: • a layer based on a semiconductor produced by epitaxy, called the epitaxial layer (40), extending above the nucleation layer (30) and the covering layer (50).

11. Stacking according to the preceding claim in which the cover layer (50) forms entirely the upper face (151) of the exposed portion (150) of the support (100).

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