Display panel and electronic device including same

Abstract

An embodiment of the present invention provides a display panel comprising: a base layer including first areas and a second area surrounding each of the first areas; a pixel circuit layer disposed on the base layer and including pixel circuits and insulating layers disposed in the first areas; light-emitting diodes disposed on the pixel circuit layer and electrically connected to the pixel circuits, respectively; and a connection wire which electrically connects pixel circuits disposed adjacent to each other among the pixel circuits and includes a structure in which a main connection wire including a two-dimensional nanostructure and an auxiliary connection wire including a one-dimensional nanostructure and a zero-dimensional nanostructure are stacked.

Description

Display panel and electronic device including the same

[0001] The present invention relates to a display panel and an electronic device including the same.

[0002] In general, as display panels that visually display electrical signals advance, various display panels with excellent characteristics such as thinness, lightness, and low power consumption, as well as electronic devices containing them, are being introduced. For example, research and development is actively underway on display panels of various structures, such as flexible display panels that can be folded or rolled into a roll shape, and stretchable display panels, as well as electronic devices containing them.

[0003] Embodiments of the present invention aim to provide a display panel with improved stretchability and capable of realizing an image of excellent quality even when stretched, and an electronic device including the same. However, these objectives are exemplary and do not limit the scope of the present invention.

[0004] One embodiment of the present invention provides a display panel comprising: a base layer including first regions and a second region surrounding each of the first regions; a pixel circuit layer disposed on the base layer and including pixel circuits disposed in the first regions and insulating layers; light-emitting diodes disposed on the pixel circuit layer and electrically connected to each of the pixel circuits; and a connecting wire comprising a structure in which a main connecting wire including a two-dimensional nanostructure and an auxiliary connecting wire including a one-dimensional nanostructure and a zero-dimensional nanostructure are stacked to electrically connect pixel circuits disposed adjacent to each other among the pixel circuits.

[0005] The two-dimensional nanostructure of the main connecting wire may include at least one of a nanoflake, a nanosheet, or a nanoplate.

[0006] The one-dimensional nanostructure of the above auxiliary connecting wiring may include at least one of a nanowire, nanofiber, nanotube, nanorod, or nanobelt.

[0007] The zero-dimensional nanostructure of the above auxiliary connecting wiring may include nanoparticles.

[0008] The above two-dimensional nanostructure, the above one-dimensional nanostructure, and the above zero-dimensional nanostructure may each include a metal-based nanostructure.

[0009] The above two-dimensional nanostructure may include silver nanoflakes (Ag nanoflake), the above one-dimensional nanostructure may include silver nanowires (Ag nanowire), and the above zero-dimensional nanostructure may include silver nanoparticles (Ag nanoparticle).

[0010] The above auxiliary connecting wiring may include a mixture of the above one-dimensional nanostructure and the above zero-dimensional nanostructure.

[0011] The above auxiliary connecting wire may include a first auxiliary connecting wire disposed on the main connecting wire and comprising the first dimension nanostructure, and a second auxiliary connecting wire disposed on the first auxiliary connecting wire and comprising the zero dimension nanostructure.

[0012] The display panel may further include a conductive line that is in direct contact with the auxiliary connecting wire and connects the pixel circuits to the connecting wire.

[0013] The above auxiliary connecting wire is disposed on the above main connecting wire, and the connecting wire may further include a third auxiliary connecting wire disposed below the above main connecting wire, comprising a material different from the above main connecting wire and the above auxiliary connecting wire, and comprising a carbon nanostructure.

[0014] The above auxiliary connecting wire is disposed on the main connecting wire, and the connecting wire further comprises: a third auxiliary connecting wire disposed below the main connecting wire and comprising a two-dimensional carbon nanostructure; and a fourth auxiliary connecting wire disposed below the third auxiliary connecting wire and comprising a one-dimensional carbon nanostructure, wherein the third auxiliary connecting wire and the fourth auxiliary connecting wire may each comprise a material different from the main connecting wire and the auxiliary connecting wire.

[0015] The interface where the main connecting wire and the auxiliary connecting wire meet can be surface-treated by polymer treatment or plasma treatment.

[0016] The main connecting wire and the auxiliary connecting wire further include the same elastic polymer material, and the base layer may include the same material as the elastic polymer material of the connecting wire.

[0017] One embodiment of the present invention provides a display panel comprising: a base layer including first regions and a second region surrounding each of the first regions; a first pixel circuit layer disposed on one of the first regions of the base layer and including a transistor and an insulating layer; a second pixel circuit layer disposed on another of the first regions of the base layer and including a transistor and an insulating layer; a first light-emitting diode disposed on the first pixel circuit layer and electrically connected to the transistor of the first pixel circuit layer; a second light-emitting diode disposed on the second pixel circuit layer and electrically connected to the transistor of the second pixel circuit layer; and a connecting wire comprising a main connecting wire and an auxiliary connecting wire, each comprising a nanostructure of a different dimension, electrically connecting the transistor of the first pixel circuit layer and the transistor of the second pixel circuit layer.

[0018] The above main connecting wire includes a two-dimensional nanostructure, and the two-dimensional nanostructure may include at least one of a nanoflake, a nanosheet, or a nanoplate.

[0019] The above auxiliary connecting wire may include at least one one-dimensional nanostructure comprising at least one of a nanowire, nanofiber, nanotube, nanorod, or nanobelt, or at least one zero-dimensional nanostructure comprising a nanoparticle.

[0020] The main connecting wire and the auxiliary connecting wire may comprise the same metal but may comprise different nanostructured materials.

[0021] One embodiment of the present invention provides an electronic device comprising a display panel, wherein the display panel comprises: a base layer comprising first regions and a second region surrounding each of the first regions; a pixel circuit layer disposed on the base layer and comprising pixel circuits disposed in the first regions and insulating layers; light-emitting diodes disposed on the pixel circuit layer and electrically connected to each of the pixel circuits; and a connecting wire comprising a stacked structure comprising a main connecting wire including a two-dimensional nanostructure and an auxiliary connecting wire including a one-dimensional nanostructure and a zero-dimensional nanostructure, which electrically connects pixel circuits disposed adjacent to each other among the pixel circuits.

[0022] The above two-dimensional nanostructure comprises at least one of a nanoflake, a nanosheet, or a nanoplate, the above one-dimensional nanostructure comprises at least one of a nanowire, a nanofiber, a nanotube, a nanorod, or a nanobelt, and the above zero-dimensional nanostructure may comprise a nanoparticle.

[0023] The two-dimensional nanostructure of the main connecting wire and the one-dimensional nanostructure and zero-dimensional nanostructure of the auxiliary connecting wire may contain the same metal.

[0024] According to some embodiments of the present invention, a display panel with improved elasticity and excellent quality image realization and an electronic device including the same can be provided. The aforementioned effects are exemplary and the effects of the present invention are not limited to those described above.

[0025] FIG. 1 is a schematic perspective view of a display panel according to one embodiment of the present invention.

[0026] FIGS. 2A and FIGS. 2B are perspective views showing the display panel of FIG. 1 extended in a first direction.

[0027] FIG. 2c is a perspective view showing the display panel of FIG. 1 extended in a second direction.

[0028] FIG. 2d is a perspective view showing the display panel of FIG. 1 extended in the first direction and the second direction.

[0029] FIG. 2e is a perspective view showing the display panel of FIG. 1 extended in a third direction.

[0030] FIG. 3 is a schematic plan view of a display panel according to one embodiment of the present invention.

[0031] FIG. 4 is a plan view schematically showing the arrangement of pixels of a display panel according to one embodiment of the present invention.

[0032] FIG. 5 is a cross-sectional view schematically showing a part of a display panel according to one embodiment of the present invention.

[0033] FIGS. 6a to 6c are each equivalent circuit diagrams of pixels of a display panel according to an embodiment of the present invention.

[0034] FIGS. 7a and FIGS. 7b are cross-sectional views schematically showing a light-emitting diode of a display panel according to one embodiment of the present invention.

[0035] FIG. 8 is a schematic plan view showing a part of a display panel according to one embodiment of the present invention.

[0036] FIG. 9 is a cross-sectional view schematically showing a part of a display panel according to one embodiment of the present invention.

[0037] FIG. 10 is a perspective view showing the connection wiring of a display panel according to one embodiment of the present invention.

[0038] FIGS. 11a and FIGS. 11b are cross-sectional views schematically showing the connection wiring of a display panel according to one embodiment of the present invention.

[0039] FIG. 12 is a perspective view showing the connection wiring of a display panel according to one embodiment of the present invention.

[0040] FIG. 13 is a cross-sectional view schematically showing the connection wiring of a display panel according to one embodiment of the present invention.

[0041] FIGS. 14a and FIGS. 14b are perspective views showing the connection wiring of a display panel according to one embodiment of the present invention.

[0042] FIG. 15 is a perspective view showing the connection wiring of a display panel according to one embodiment of the present invention.

[0043] FIG. 16a is a schematic perspective view of an embodiment of an electronic device including a display panel according to one embodiment of the present invention.

[0044] FIG. 16b is a block diagram showing an electronic device including a display panel according to one embodiment of the present invention.

[0045] FIGS. 17a to 17i are schematic perspective views illustrating embodiments of an electronic device including a display panel according to one embodiment of the present invention.

[0046] Aspects of some embodiments of the present invention and methods for carrying them out may be more easily understood by referring to the detailed description of the embodiments and the accompanying drawings. The described embodiments are provided as examples to ensure that the present invention is sufficiently complete and thorough and to adequately convey aspects of the invention to those skilled in the art. Accordingly, processes, elements, and techniques that are redundant, irrelevant to the description of the embodiments, or that are not necessarily known to those skilled in the art to fully understand aspects of the invention may be omitted. Unless otherwise noted, the same reference numerals, letters, or combinations thereof represent the same elements in the accompanying drawings and throughout this specification, and repetitive descriptions thereof may be omitted.

[0047] The described embodiments may have various modifications and may be implemented in various forms, and should not be interpreted as being limited only to the embodiments exemplified herein. Expressions such as "can," "may," and "may not" used in describing the embodiments herein correspond to one or more embodiments of the present invention.

[0048] In light of the entire invention, a person skilled in the art will understand that each suitable feature included in the various embodiments of the invention may be combined or combined with one another, either partially or wholly, and may be technically linked and operated in various suitable ways. Furthermore, unless otherwise specified or implied, each embodiment may be implemented independently or in conjunction with one another in any suitable manner.

[0049] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity and / or convenience of explanation. In other words, the sizes and thicknesses of the elements depicted in the drawings are arbitrarily represented for convenience of explanation and are not limited thereto. Furthermore, the cross-hatching and / or shading used in the attached drawings are general methods of indication to clarify the boundaries between adjacent elements. Therefore, unless otherwise specified, the presence or absence of hatching or shading does not indicate or suggest any preference or requirement regarding specific materials, material properties, dimensions, proportions, commonalities between the elements depicted in the drawings, or any other characteristics or attributes.

[0050] Various embodiments are described herein with reference to schematic cross-sectional views of embodiments and / or intermediate structures. Therefore, it should be anticipated that variations differing from the shapes shown in the drawings may occur, for example, due to manufacturing processes and / or process errors. Furthermore, specific structural or functional descriptions disclosed to explain embodiments according to the present invention are merely illustrative. Accordingly, the embodiments disclosed herein should not be interpreted as being limited to the shapes of elements, layers, or regions shown in the drawings, and should be understood to include, for example, shape deviations that occur due to the manufacturing process.

[0051] For example, the ion implantation region depicted as a rectangle actually has rounded corners or a curved shape, and rather than a binary separation between the implanted and non-implanted regions, it is common for there to be a gradient where the implantation concentration gradually changes at the edges. Similarly, in the case of the buried region formed by implantation, some ions may also be implanted into the area between the implantation surface and the buried region.

[0052] Spatial relative terms such as “beneath (beneath, below, lower, lower side, under),” “above (above, upper, over, higher, upper side),” and “side (e.g., sidewall)” may be used for descriptive convenience to explain the relationships between elements or features depicted in the drawings. These spatial relative terms should be understood to include not only the orientation depicted in the drawings but also all various orientations in which the device is used or operated. For example, if the device depicted in the drawings is inverted, an element described as being “below (beneath, beneath, under)” of another element or feature will be located “above” in the opposite direction. Therefore, terms such as “below” and “under” may include orientations in both upward and downward directions. Additionally, the device may be rotated 90 degrees or oriented in various other directions, and accordingly, the spatial relative terms used in this specification should be interpreted with such changes in orientation in mind. Likewise, when the first part is described as being placed "on" the second part, this means that it is not limited only to the "upper" side according to the direction of gravity, but that the first part can be placed on either the upper or lower side of the second part.

[0053] Furthermore, the expression "in a plan view" refers to the case where the subject area is viewed from above, and the expression "in a schematic cross-sectional view" refers to the case where a schematic cross-section obtained by vertically cutting the subject area is viewed from the side. The terms "overlap" or "overlapped" mean that the first object may be located above, below, or to the side of the second object, and include the opposite case. Additionally, the term "overlap" may include all other appropriate meanings that a person skilled in the art can understand, such as stack, face or facing, extending over, covering, and partly covering. Meanwhile, the expression "not overlap" may include other appropriate equivalent concepts that a person skilled in the art can understand, such as "apart from," "set aside from," or "offset from." The terms "face" or "facing" mean that the first object is facing the second object directly or indirectly. For example, even if a third object is interposed between the first object and the second object, the first object and the second object may be understood as facing each other indirectly.

[0054] Where an element, layer, region, or component (e.g., device, circuit, wiring, electrode, terminal, conductive film, etc.) is referred to as being "formed on," "on," "connected to," or "coupled to" another element, layer, region, or component, this means that it may be directly formed, directly located, directly connected, or directly coupled to the other element, layer, region, or component, or may be indirectly formed, indirectly located, indirectly connected, or indirectly coupled in the presence of one or more intermediate elements, layers, regions, or components. Furthermore, this may encompass both direct and indirect coupling or connection, and integral or non-integral coupling or connection. For example, when it is stated that one layer, region, or component is "electrically connected" or "electrically coupled" to another layer, region, or component, this may mean that the two elements are directly electrically connected or coupled, or that one or more layers, regions, or components are interposed between them. The one or more interposed components may include switches, transistors, resistors, inductors, capacitors, diodes, etc. Therefore, the connection is not limited to the connection forms depicted in the drawings or detailed description, but may include various other forms of connection. In describing the embodiments, the term "connection" refers to an electrical connection unless specifically stated as "direct connection," and "directly connected / directly coupled" or "directly on" means that one component is directly connected to, coupled to, or located directly on another component without any intermediate components.

[0055] In addition, when it is stated in this specification that a part of a layer, film, region, plate, etc. is formed on another part, the direction of formation is not limited to the upward direction but includes cases where it is formed in the side or downward direction. Conversely, when it is stated that a part of a layer, film, region, plate, etc. is formed "under" another part, it includes not only cases where the part is located "directly beneath" the other part, but also cases where another part is interposed between them. Meanwhile, other expressions describing the relationship between components, such as "between," "immediately between," "adjacent to," and "directly adjacent to," may be interpreted similarly. When it is mentioned that an element or layer is located "between" between two elements or two layers, this means that the element or layer may be the only element existing between the two elements or layers, or that one or more intermediate elements or layers may exist.

[0056] For the present invention, when expressions such as “at least one of,” “any one of,” or “one or more of” are used prior to a list of elements, they apply to all listed elements and not to each individual element only. For example, “at least one X, Y, and Z,” “at least one X, Y, or Z,” “at least one selected from the group consisting of X, Y, and Z,” or “at least one selected from the group consisting of X, Y, or Z” may include only X, only Y, only Z, or two or more of X·Y·Z (e.g., XYZ, XY, YZ, XZ) and variations thereof. Similarly, expressions such as “at least one A and B” or “at least one A or B” may include A, B, or both A and B. In this specification, “or” generally means “and / or,” and “and / or” means any combination including one or more of the listed items. For example, "A and / or B" includes A, B, or both A and B. Also, prepositional phrases such as "at least one of," "a plurality of," and "one of" modify the entire listed elements, not just individual elements. Furthermore, when written as "C to D," unless otherwise noted, it refers to the range from C to D.

[0057] Even if terms such as "first," "second," and "third" are used in this specification to describe various elements, components, regions, layers, and / or zones, these elements, components, regions, layers, and / or zones should not be limited by such terms. These terms do not imply a specific order, location, or hierarchy, but are used merely to distinguish one element, component, region, zone, layer, or part from another element, component, region, zone, layer, or part. Accordingly, what is described below as the first element, component, region, layer, or zone may be called the second element, component, region, layer, or zone without departing from the spirit and scope of the invention. Furthermore, the designation of an element as the "first" element does not imply that a "second" element or other elements must exist. Terms such as "first" and "second" may also be used to distinguish elements of different categories or sets. For brevity, terms such as "first," "second," etc., may mean "first-category (or first-set)," "second-category (or second-set)," etc.

[0058] In the examples, the x-axis, y-axis, and / or z-axis are not limited to the three axes of an orthogonal coordinate system and may be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis may be perpendicular to each other, or they may represent different directions that are not perpendicular to each other. The same applies to the first, second, and / or third directions.

[0059] The terms used in this specification are for the purpose of describing the embodiments only and are not intended to limit the invention. In this specification, singular forms such as "a" and "an" are understood to include plural forms unless the context clearly indicates otherwise, and plural forms are also understood to include singular forms.

[0060] Additionally, terms used herein such as “comprises,” “comprising,” “have,” “having,” “includes,” and “including” specify the presence of the described configurations, integers, steps, actions, elements, and / or components, but do not exclude the additional presence of one or more other configurations, integers, steps, actions, elements, components, and / or combinations thereof.

[0061] Terms such as "substantially," "about," and "approximately" used in this specification are expressions indicating approximations rather than degrees, and are intended to account for deviations inherently included in measured or calculated values ​​as recognized by a person skilled in the art. For example, "substantially" may include a range of ±5% of the value. "About" or "approximately" includes the stated value and means that it is within an acceptable range of deviation judged by a person skilled in the art, taking into account the limits of the measured value and the measurement system (i.e., measurement error). For example, "about" may be one or more standard deviation ranges or ranges of ±30%, 20%, 10%, or 5% of the stated value. Additionally, "may" used when describing embodiments of the present invention means "one or more embodiments of the present invention." Furthermore, the expression "being the same" can mean "being substantially the same." In other words, the expression "being the same" can encompass the scope acceptable to a person skilled in the art. Other expressions can also be understood as a form in which "substantially" is omitted.

[0062] In some embodiments, to avoid making the various embodiments unnecessarily obscure, known structures and devices may be described in the accompanying drawings in relation to one or more functional blocks (e.g., block diagrams), units, and / or modules. A person skilled in the art will understand that such blocks, units, and / or modules may be physically implemented by logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, line connections, and other electronic circuits. These may be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units, and / or modules implemented by microprocessors or similar hardware may be programmed and controlled using software to perform the various functions discussed herein, and may optionally be driven by firmware and / or software. Additionally, each block, unit, and / or module may be implemented as dedicated hardware to perform a specific function, or as a combination of dedicated hardware to perform some functions and a processor (e.g., one or more programmed microprocessors and related circuits) to perform functions different from those performed by the dedicated hardware. Additionally, in some embodiments, blocks, units, and / or modules may be physically separated into two or more interacting individual blocks, units, and / or modules without departing from the scope of the invention. Additionally, in some embodiments, blocks, units, and / or modules may be physically combined into more complex blocks, units, and / or modules without departing from the scope of the invention.

[0063] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as generally understood by a person skilled in the art to which the present invention pertains. Furthermore, terms defined in commonly used dictionaries should be interpreted in accordance with their meaning in the relevant art and / or context of this specification, and should not be interpreted in an ideal or overly formal sense unless explicitly defined so in this specification.

[0064] FIG. 1 is a schematic perspective view of a display panel (1) according to an embodiment of the present invention. FIG. 2a and FIG. 2b are perspective views showing the display panel (1) of FIG. 1 extended in a first direction. FIG. 2c is a perspective view showing the display panel (1) of FIG. 1 extended in a second direction. FIG. 2d is a perspective view showing the display panel (1) of FIG. 1 extended in the first direction and the second direction. FIG. 2e is a perspective view showing the display panel (1) of FIG. 1 extended in a third direction.

[0065] Referring to FIG. 1, a display panel (1) may include a display area (DA) and a non-display area (NDA). The display area (DA) may include a plurality of pixels. The display panel (1) may provide a predetermined image using light emitted from a plurality of pixels. The non-display area (NDA) may be placed outside the display area (DA). The non-display area (NDA) may completely surround the display area (DA) (e.g., on a plane).

[0066] The display panel (1) can be extended or shortened in various directions. The display panel (1) can be extended in a first direction (e.g., x direction and / or -x direction) by an external force applied by an external object or a user. In one embodiment, as shown in FIGS. 2a and 2b, the display area (DA) and / or non-display area (NDA) of the display panel (1) can be extended in a first direction (e.g., x direction and / or -x direction). For example, as shown in FIG. 2a, it can be extended along the x direction and -x direction, or as shown in FIG. 2b, the display area (DA) and / or non-display area (NDA) can be extended along the x direction while one side of the display panel (1) remains fixed.

[0067] The display panel (1) can be extended in a second direction (e.g., the y direction and / or the -y direction) by an external force applied by an external object or a user. In one embodiment, as shown in FIG. 2c, the display area (DA) and / or non-display area (NDA) of the display panel (1) can be extended in the y direction and the -y direction. In another embodiment, one side of the display panel (1) can be extended in the y direction or the -y direction while remaining fixed.

[0068] The display panel (1) can be extended in multiple directions, such as a first direction (e.g., x direction and / or -x direction) and a second direction (e.g., y direction and / or -y direction), by an external force applied by an external object or a part of a person's body. As shown in FIG. 2d, the display area (DA) and / or non-display area (NDA) of the display panel (1) can be extended in the ±x direction and ±y direction.

[0069] The display panel (1) can be extended in a third direction (e.g., z direction or -z direction) by an external force applied by an external object or a part of a person's body. In one embodiment, FIG. 2e illustrates a part of the display panel (1), such as a part of the display area (DA), protruding in the z direction. In another embodiment, a part of the display panel (1), such as a part of the display area (DA), may protrude along the z direction (or be sunken along the -z direction).

[0070] FIGS. 2a to 2e illustrate a display panel (1) extended in a first direction, a second direction, and / or a third direction, but the present invention is not limited thereto. In other embodiments, the display panel (1) may be deformed into various irregular shapes, such as having two or more axes, such as being bent or twisted.

[0071] FIG. 3 is a schematic plan view showing a display panel (1) according to one embodiment of the present invention.

[0072] Referring to FIG. 3, the display panel (1) may include a display area (DA) and a non-display area (NDA) surrounding the display area (DA) (e.g., on a plane). Pixels (P) are arranged in the display area (DA) of the substrate (100). Each pixel (P) can display an image using light emitted from a light-emitting element, such as a light-emitting diode. Each light-emitting diode can emit light, for example, red, green, or blue.

[0073] Each light-emitting diode may be electrically connected to a pixel circuit, and each pixel circuit may include transistors and a storage capacitor. Each pixel circuit may be electrically connected to peripheral circuits and peripheral wiring located in a non-display area (NDA). Peripheral circuits located in the non-display area (NDA) may include a gate driving circuit (GDC) and a terminal section (PAD). Peripheral wiring may include a driving voltage supply line (W11), a common voltage supply line (W13), and a fan-out line (FW).

[0074] The gate driving circuit (GDC) may include drivers for providing an electrical signal to the gate electrode of each of the transistors electrically connected to the light-emitting elements. Specifically, the gate driving circuit (GDC) may apply a scan signal to each of the pixel circuits corresponding to the pixels (P) through the gate line (GL).

[0075] The gate driving circuit (GDC) may include a first gate driving circuit (GDC1) and a second gate driving circuit (GDC2) positioned on both sides with the display area (DA) in between. The second gate driving circuit (GDC2) may be located on the opposite side of the first gate driving circuit (GDC1) with respect to the display area (DA) and may be approximately parallel to the first gate driving circuit (GDC1). Some of the pixel circuits may be electrically connected to the first gate driving circuit (GDC1), and the rest may be electrically connected to the second gate driving circuit (GDC2). In some embodiments, the second gate driving circuit (GDC2) may be omitted.

[0076] A terminal portion (PAD) may be disposed on one side of the substrate (100). The terminal portion (PAD) is exposed without being covered by an insulating layer and is connected to a display circuit board (30). A display driving portion (32) may be disposed on the display circuit board (30). The display driving portion (32) may generate a control signal to be transmitted to a first gate driving circuit (GDC1) and a second gate driving circuit (GDC2). The display driving portion (32) generates a data signal, and the generated data signal may be transmitted to the pixel circuits of pixels (P) through a fan-out wiring (FW) and a data line (DL) connected to the fan-out wiring (FW).

[0077] The display driving unit (32) can supply a first power supply voltage (VDD, FIG. 6a) to the driving voltage supply wire (W11) and a second power supply voltage (VSS, FIG. 6a) to the common voltage supply wire (W13). The first power supply voltage (VDD, FIG. 6a) is applied to the pixel circuit of the pixel (P) through the driving voltage line (PL) connected to the driving voltage supply wire (W11), and the second power supply voltage (VSS, FIG. 6a) is connected to the common voltage supply wire (W13) and can be applied to the opposing electrode of the light-emitting element. The driving voltage supply wire (W11) may be provided extending along the x-direction from the lower side of the display area (DA). The common voltage supply wire (W13) may have a loop shape with one side open, so as to partially surround the display area (DA).

[0078] FIG. 4 is a plan view schematically showing the arrangement of pixels of a display panel according to one embodiment of the present invention.

[0079] Referring to FIG. 4, the display area (DA) may include first areas (11) and a second area (12) surrounding each of the first areas (11). The first areas (11) may be arranged repeatedly along a first direction (e.g., x-direction) and a second direction (e.g., y-direction).

[0080] The display area (DA) may include a first area (11) and a second area (12) with different elongation rates. For example, the display panel (1) may include a first area (11) with a relatively small elongation rate and a second area (12) with a relatively large elongation rate. In this specification, elongation rate is a numerical value representing the change in length (ΔL / L) by which the display panel (1) can be stretched without physical damage to the display panel (1) when an external force is applied to the display panel (1). Here, ΔL is the amount of change in length of the display panel (1), and L represents the initial length of the display panel (1). Accordingly, the elongation rates of the first area (11) and the second area (12) respectively may represent the change in length of the first area (11) and the second area (12) respectively when the same external force is applied to the first area (11) and the second area (12).

[0081] The fact that the elongation rate of the first region (11) is smaller than the elongation rate of the second region (12) indicates that the deformation of the first region (11) due to external force occurs relatively less. Therefore, the first region (11) can be called a low-deformation region and the second region (12) can be called a high-deformation region.

[0082] The first regions (11) may be spaced apart from each other and arranged two-dimensionally in the display area (DA). The first region (11) may be an area where pixels are placed, and thus, the first region (11) may be referred to as a pixel area or a light-emitting area. One or more pixels may be placed in each first region (11). A pixel unit (PU) comprising a set of pixels may be provided in the first region (11), and each pixel unit (PU) may include a red pixel (PXr), a green pixel (PXg), and a blue pixel (PXb).

[0083] The second region (12) may be located between adjacent first regions (11). As illustrated in FIG. 5, the second region (12) may have a shape that surrounds each first region (11) in a plane. The second region (12) may be an area through which connecting wires pass to electrically connect pixel circuits (PC, FIG. 4) placed in each of the two adjacent first regions (11).

[0084] FIG. 5 is a cross-sectional view schematically showing a part of a display panel according to one embodiment of the present invention.

[0085] Referring to FIG. 5, the display area (DA) may include a first area (11) and a second area (12), and the second area (12) may be an area connecting the first areas (11) that are arranged adjacent to each other. The first area (11) is an area with a relatively smaller elongation rate than the second area (12) and may include a light-emitting diode (LED) and a pixel circuit (PC). The second area (12) is an area with a relatively larger elongation rate than the first area (11) and may include a connecting wire (WL) included in a signal line that supplies a signal to each of the pixel circuits (PC).

[0086] The first region (11) and the second region (12) may be formed on the base layer (400). In other words, the base layer (400) may have the first region (11) and the second region (12) defined respectively. A light-emitting diode (LED) and a pixel circuit (PC) may be placed on the first region (11) of the base layer (400), and a connecting wire (WL) may be placed on the second region (12) of the base layer (400).

[0087] The base layer (400) can absorb stress that may occur during the stretching of the display panel (1). The base layer (400) may include an elastomer (or an elastomer material). For example, the base layer (400) is thermoplastic polyurethane, polyester, silicone, thermoplastic rubbers, elastolefin, thermoplastic olefin, polyamide, polyether block amide, synthetic polyisoprene, polybutadiene, chloroprene rubber, butyl rubber, styrene-butadiene, epichlorohydrin rubber, polyacrylic rubber, silicone rubber, fluorosilicone rubber, fluoroelastomers, ethylene-vinyl acetate, It may include at least one of PDMS (polydimethylsiloxane) and Ecoflex (a registered trademark of Smooth-On, Inc., located in Macungie, Pennsylvania, USA).

[0088] A display layer (200) may be disposed on a first region (11) of a base layer (400). The display layer (200) may include an inorganic insulating layer (IIL), a pixel circuit (PC), an organic insulating layer (OIL), and a light-emitting diode (LED). A pixel circuit (PC) may be disposed on the base layer (400), and an inorganic insulating layer (IIL) may be disposed between electrodes included in the pixel circuit (PC). An organic insulating layer (OIL) may be disposed on the inorganic insulating layer (IIL) to cover the pixel circuit (PC). A light-emitting diode (LED) may be disposed on the organic insulating layer (OIL) and may be electrically connected to the corresponding pixel circuit (PC). The inorganic insulating layer (IIL) may include an inorganic insulating material such as silicon nitride and / or silicon oxide, and the organic insulating layer (OIL) may include an organic insulating material such as polyimide.

[0089] In one embodiment, a pixel unit (PU) may be disposed on a first region (11). As previously described, the pixel unit (PU) may include a red pixel (PXr, FIG. 4), a green pixel (PXg, FIG. 4), and a blue pixel (PXb, FIG. 4). The red pixel (PXr, FIG. 4) may include a first light-emitting diode (LED1), the green pixel (PXg, FIG. 4) may include a second light-emitting diode (LED2), and the blue pixel (PXb, FIG. 4) may include a third light-emitting diode (LED3). For example, the first light-emitting diode (LED1) may emit red light, the second light-emitting diode (LED2) may emit green light, and the third light-emitting diode (LED3) may emit blue light. In some embodiments, the light-emitting diode (LED) may emit white light.

[0090] A connecting wire (WL) may be disposed on the second region (12) of the base layer (400). In one embodiment, as shown in FIG. 5, the connecting wire (WL) may be disposed on the base layer (400) but may be disposed relatively lower than the display layer (200). In other words, the base layer (400) may be disposed to cover the connecting wire (WL) disposed on the back surface of the display layer (200). Accordingly, the thickness of the base layer (400) corresponding to the second region (12) may be smaller than the thickness of the base layer (400) corresponding to the first region (11). However, it is not limited thereto, and in another embodiment, the connecting wire (WL) may be disposed on the base layer (400) but may be disposed on a layer substantially identical to some of the layers of the display layer (200).

[0091] The connecting wire (WL) may include a material having both excellent elasticity and electrical properties. In one embodiment, the connecting wires disposed in the second region (12) may include liquid metal. In another embodiment, the connecting wires may include metal nanostructures and elastic polymers. In yet another embodiment, the connecting wires may include a conductive composite material comprising an elastomer.

[0092] In one embodiment, a protective layer (300) may be disposed on the light-emitting diode (LED). The protective layer (300) may be disposed on both the first region (11) and the second region (12). That is, the protective layer (300) may be disposed to cover the entire display area (DA). The protective layer (300) may cover the light-emitting diode (LED) and the connecting wire (WL). The protective layer (300) may absorb stress that may occur when the display panel (1) is stretched. Specifically, the protective layer (300) may serve to reduce or prevent stress that may occur when the display panel (1) is stretched from being transmitted to the light-emitting diode (LED) and the pixel circuit (PC).

[0093] The protective layer (300) may include an elastic polymer. The protective layer (300) is made of thermoplastic polyurethane, polyester, silicone, thermoplastic rubbers, elastolefin, thermoplastic olefin, polyamide, polyether block amide, synthetic polyisoprene, polybutadiene, chloroprene rubber, butyl rubber, styrene-butadiene, epichlorohydrin rubber, polyacrylic rubber, silicone rubber, fluorosilicone rubber, and fluoroelastomers, ethylene-vinyl acetate, It may include at least one of PDMS (polydimethylsiloxane). In one embodiment, the protective layer (300) may include the same material as the base layer (400). However, it is not limited thereto, and the protective layer (300) may include a different material from the base layer (400).

[0094] FIGS. 6a to 6c are each equivalent circuit diagrams of pixels of a display panel according to an embodiment of the present invention.

[0095] Referring to FIG. 6a, a light-emitting diode (LED) corresponding to a pixel is electrically connected to a pixel circuit (PC), and the pixel circuit (PC) may include a first transistor (T1), a second transistor (T2), and a storage capacitor (Cst). The pixel circuit (PC) may be electrically connected to signal lines and voltage lines. The signal lines may include a gate line (GL, FIG. 3), such as a scan signal line (GWL), and a data line (DL), and the voltage lines may include a first voltage line (VDDL). In this case, the first voltage line (VDDL) may be connected to a driving voltage supply line (W11, FIG. 3), and the second voltage line (VSSL) may be connected to a common voltage supply line (W13, FIG. 3).

[0096] The second transistor (T2) can be electrically connected to the scan signal line (GWL) and the data line (DL). The scan signal line (GWL) can provide a scan signal (GW) to the gate electrode of the second transistor (T2). The second transistor (T2) can transmit a data signal (Dm) input from the data line (DL) to the first transistor (T1) according to the scan signal (GW) input from the scan signal line (GWL).

[0097] The storage capacitor (Cst) is electrically connected to the second transistor (T2) and the first voltage line (VDDL), and can store a voltage corresponding to the difference between the voltage received from the second transistor (T2) and the first power supply voltage (VDD) supplied by the first voltage line (VDDL).

[0098] The first transistor (T1) is a driving transistor and can control the driving current flowing through the light-emitting diode (LED). The first transistor (T1) can be connected to the first voltage line (VDDL) and the storage capacitor (Cst). The first transistor (T1) can control the driving current flowing from the first voltage line (VDDL) to the light-emitting diode (LED) in correspondence with the voltage value stored in the storage capacitor (Cst). The light-emitting diode (LED) can emit light having a predetermined brightness by the driving current. The first electrode of the light-emitting diode (LED) is electrically connected to the first transistor (T1), and the second electrode can be electrically connected to the second voltage line (VSSL) that supplies the second power supply voltage (VSS).

[0099] FIG. 6a illustrates a pixel circuit (PC) comprising two transistors and one storage capacitor, but in other embodiments, the pixel circuit (PC) may comprise three or more transistors.

[0100] Referring to FIG. 6b, the pixel circuit (PC) may include a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a seventh transistor (T7), and a storage capacitor (Cst).

[0101] The pixel circuit (PC) is electrically connected to signal lines and voltage lines. The signal lines may include gate lines (GL, FIG. 3), such as scan signal lines (GWL), bypass control lines (GBL), initialization control lines (GIL), and light emission control lines (EML), and data lines (DL). The voltage lines may include first and second initialization voltage lines (VIL1, VIL2) and a first voltage line (VDDL). In this case, the first voltage line (VDDL) may be connected to a driving voltage supply line (W11, FIG. 3), and the second voltage line (VSSL) may be connected to a common voltage supply line (W13, FIG. 3).

[0102] The first voltage line (VDDL) can transmit a first power supply voltage (VDD) to the first transistor (T1). The first initialization voltage line (VIL1) can transmit a first initialization voltage (Vint) that initializes the first transistor (T1) to the pixel circuit (PC). The second initialization voltage line (VIL2) can transmit a second initialization voltage (Vaint) that initializes the first electrode of the light-emitting diode (LED) to the pixel circuit (PC).

[0103] The first transistor (T1) can be electrically connected to the first voltage line (VDDL) via the fifth transistor (T5) and electrically connected to the light-emitting diode (LED) via the sixth transistor (T6). The first transistor (T1) acts as a driving transistor and receives a data signal (Dm) according to the switching operation of the second transistor (T2) and supplies a driving current to the light-emitting diode (LED).

[0104] The second transistor (T2) is a data write transistor and is electrically connected to the scan signal line (GWL) and the data line (DL). The second transistor (T2) is electrically connected to the first voltage line (VDDL) via the fifth transistor (T5). The second transistor (T2) is turned on according to the scan signal (GW) received through the scan signal line (GWL) and performs a switching operation to transmit the data signal (Dm) transmitted to the data line (DL) to the first node (N1).

[0105] The third transistor (T3) is electrically connected to the scan signal line (GWL) and is electrically connected to the light-emitting diode (LED) via the sixth transistor (T6). The third transistor (T3) is turned on according to the scan signal (GW) received through the scan signal line (GWL) and can diode-connect the first transistor (T1).

[0106] The fourth transistor (T4) is the first initialization transistor and is electrically connected to the initialization control line (GIL) and the first initialization voltage line (VIL1). The fourth transistor (T4) is turned on according to the initialization control signal (GI) received through the initialization control line (GIL) to transmit the first initialization voltage (Vint) from the first initialization voltage line (VIL1) to the gate electrode of the first transistor (T1), thereby initializing the voltage of the gate electrode of the first transistor (T1). The initialization control signal (GI) may correspond to a scan signal of another pixel circuit placed in the previous row of the corresponding pixel circuit (PC).

[0107] The fifth transistor (T5) may be an operation control transistor, and the sixth transistor (T6) may be a light emission control transistor. The fifth transistor (T5) and the sixth transistor (T6) are electrically connected to the light emission control line (EML) and are turned on concurrently or substantially simultaneously according to the light emission control signal (EM) received through the light emission control line (EML) to form a current path so that a driving current can flow from the first voltage line (VDDL) toward the light-emitting diode (LED).

[0108] The seventh transistor (T7) is a second initialization transistor and can be electrically connected to the bypass control line (GBL), the second initialization voltage line (VIL2), and the sixth transistor (T6). The seventh transistor (T7) is turned on according to the bypass control signal (GB) received through the bypass control line (GBL), and can initialize the first electrode of the light-emitting diode (LED) by transmitting the second initialization voltage (Vaint) from the second initialization voltage line (VIL2) to the first electrode of the light-emitting diode (LED).

[0109] The storage capacitor (Cst) includes a first electrode (CE1) and a second electrode (CE2). The first electrode (CE1) is electrically connected to the gate electrode of the first transistor (T1), and the second electrode (CE2) is electrically connected to the first voltage line (VDDL). The storage capacitor (Cst) can maintain the voltage applied to the gate electrode of the first transistor (T1) by storing and maintaining a voltage corresponding to the difference between the voltages of the first voltage line (VDDL) and the gate electrode of the first transistor (T1).

[0110] Referring to FIG. 6c, the pixel circuit (PC) may include a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a seventh transistor (T7), an eighth transistor (T8), a ninth transistor (T9), a storage capacitor (Cst), and an auxiliary capacitor (Ca).

[0111] The pixel circuit (PC) is electrically connected to signal lines and voltage lines. The signal lines may include gate lines (GL, FIG. 3), such as scan signal lines (GWL), bypass control lines (GBL), initialization control lines (GIL), and light emission control lines (EML), and data lines (DL). The voltage lines may include first and second initialization voltage lines (VIL1, VIL2), holding voltage lines (VSL), and first voltage lines (VDDL). In this case, the first voltage line (VDDL) may be connected to a driving voltage supply line (W11, FIG. 3), and the second voltage line (VSSL) may be connected to a common voltage supply line (W13, FIG. 3).

[0112] The first voltage line (VDDL) can transmit a first power supply voltage (VDD) to the first transistor (T1). The first initialization voltage line (VIL1) can transmit a first initialization voltage (Vint) that initializes the first transistor (T1) to the pixel circuit (PC). The second initialization voltage line (VIL2) can transmit a second initialization voltage (Vaint) that initializes the first electrode of the light-emitting diode (LED) to the pixel circuit (PC). The holding voltage line (VSL) can provide a holding voltage (VSUS) to the second electrode (CE2) of the second node (N2), for example, the storage capacitor (Cst), during the initialization period and the data writing period.

[0113] The first transistor (T1) can be electrically connected to the first voltage line (VDDL) via the fifth transistor (T5) and the eighth transistor (T8), and can be electrically connected to the light-emitting diode (LED) via the sixth transistor (T6). The first transistor (T1) acts as a driving transistor and can receive a data signal (Dm) according to the switching operation of the second transistor (T2) and supply a driving current to the light-emitting diode (LED).

[0114] The second transistor (T2) is electrically connected to the scan signal line (GWL) and the data line (DL), and is electrically connected to the first voltage line (VDDL) via the fifth transistor (T5) and the eighth transistor (T8). The second transistor (T2) is turned on according to the scan signal (GW) received through the scan signal line (GWL) and performs a switching operation to transmit the data signal (Dm) transmitted to the data line (DL) to the first node (N1).

[0115] The third transistor (T3) is electrically connected to the scan signal line (GWL) and is electrically connected to the light-emitting diode (LED) via the sixth transistor (T6). The third transistor (T3) is turned on according to the scan signal (GW) received through the scan signal line (GWL) and connects the first transistor (T1) to the diode, thereby compensating for the threshold voltage of the first transistor (T1).

[0116] The fourth transistor (T4) is electrically connected to the initialization control line (GIL) and the first initialization voltage line (VIL1), and is turned on according to the initialization control signal (GI) received through the initialization control line (GIL) to transmit the first initialization voltage (Vint) from the first initialization voltage line (VIL1) to the gate electrode of the first transistor (T1) to initialize the voltage of the gate electrode of the first transistor (T1). The initialization control signal (GI) may correspond to a scan signal of another pixel circuit placed in the previous row of the corresponding pixel circuit (PC).

[0117] The fifth transistor (T5), the sixth transistor (T6), and the eighth transistor (T8) are electrically connected to the light emission control line (EML) and are turned on concurrently or substantially simultaneously according to the light emission control signal (EM) received through the light emission control line (EML) to form a current path so that driving current can flow from the first voltage line (VDDL) toward the light-emitting diode (LED).

[0118] The seventh transistor (T7) is a second initialization transistor and can be electrically connected to the bypass control line (GBL), the second initialization voltage line (VIL2), and the sixth transistor (T6). The seventh transistor (T7) is turned on according to the bypass control signal (GB) received through the bypass control line (GBL) and transmits the second initialization voltage (Vaint) from the second initialization voltage line (VIL2) to the first electrode of the light-emitting diode (LED) to initialize the first electrode of the light-emitting diode (LED).

[0119] The ninth transistor (T9) can be electrically connected to the bypass control line (GBL), the second electrode (CE2) of the storage capacitor (Cst), and the holding voltage line (VSL). The ninth transistor (T9) is turned on according to the bypass control signal (GB) received through the bypass control line (GBL), and can transmit a holding voltage (VSUS) to the second node (N2), such as the second electrode (CE2) of the storage capacitor (Cst), during the initialization period and the data writing period.

[0120] The eighth transistor (T8) and the ninth transistor (T9) can each be electrically connected to the second node (N2), for example, the second electrode (CE2) of the storage capacitor (Cst). In some embodiments, the eighth transistor (T8) may be turned off and the ninth transistor (T9) may be turned on during the initialization period and the data writing period, and the eighth transistor (T8) may be turned on and the ninth transistor (T9) may be turned off during the light emission period. Since the second node (N2) receives the holding voltage (VSUS) during the initialization period and the data writing period, the uniformity of brightness of the display panel (e.g., LRU, Long Range Uniformity) due to the voltage drop of the first voltage line (VDDL) can be improved.

[0121] The storage capacitor (Cst) includes a first electrode (CE1) and a second electrode (CE2). The first electrode (CE1) is electrically connected to the gate electrode of the first transistor (T1), and the second electrode (CE2) is electrically connected to the eighth transistor (T8) and the ninth transistor (T9).

[0122] The auxiliary capacitor (Ca) can be electrically connected to the sixth transistor (T6), the holding voltage line (VSL), and the first electrode of the light-emitting diode (LED). By storing and maintaining a voltage corresponding to the voltage difference between the first electrode of the light-emitting diode (LED) and the holding voltage line (VSL) while the seventh transistor (T7) and the ninth transistor (T9) are turned on, the auxiliary capacitor (Ca) can reduce or prevent the problem of black brightness rising when the sixth transistor (T6) is off.

[0123] FIGS. 7a and FIGS. 7b are cross-sectional views schematically showing a light-emitting diode of a display panel according to one embodiment of the present invention.

[0124] Referring to FIG. 7a, the light-emitting diode (LED, FIG. 6a) may include an inorganic light-emitting diode (230) containing an inorganic material. The inorganic light-emitting diode (230) may include a first semiconductor layer (231), a second semiconductor layer (232), an intermediate layer (233) between the first semiconductor layer (231) and the second semiconductor layer (232), a first electrode (235) electrically connected to the first semiconductor layer (231), and a second electrode (238) electrically connected to the second semiconductor layer (232). The first electrode (235) and the second electrode (238) of the light-emitting diode (LED) may each be electrically connected to a first electrode pad (241) and a second electrode pad (242) disposed on the same layer. The second electrode pad (242) may be a part of the second voltage line (VSSL, FIG. 6a) or a conductive layer electrically connected to the second voltage line (VSSL, FIG. 6a).

[0125] In some embodiments, the first semiconductor layer (231) may include a p-type semiconductor layer. The p-type semiconductor layer may be selected from semiconductor materials having the compositional formula InxAlyGa1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1), such as GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, etc., and may be doped with p-type dopants such as Mg, Zn, Ca, Sr, Ba, etc.

[0126] The second semiconductor layer (232) may include, for example, an n-type semiconductor layer. The n-type semiconductor layer may be selected from semiconductor materials having the composition formula InxAlyGa1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1), for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, etc., and may be doped with n-type dopants such as Si, Ge, and Sn.

[0127] The intermediate layer (233) is a region where electrons and holes recombine, and as electrons and holes recombine, they transition to a lower energy level and can generate light having a corresponding wavelength. The intermediate layer (233) can be formed by including a semiconductor material having, for example, the composition formula InxAlyGa1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1), and can be formed as a single quantum well structure or a multi-quantum well (MQW) structure. Additionally, it may include a quantum wire structure or a quantum dot structure.

[0128] FIG. 7a illustrates that the first semiconductor layer (231) includes a p-type semiconductor layer and the second semiconductor layer (232) includes an n-type semiconductor layer, but the present invention is not limited thereto. In another embodiment, the first semiconductor layer (231) may include an n-type semiconductor layer and the second semiconductor layer (232) may include a p-type semiconductor layer.

[0129] Referring to FIG. 7b, the light-emitting diode (LED, FIG. 6a) may be an organic light-emitting diode (220) containing an organic material. The organic light-emitting diode (220) may include a first electrode (221) disposed on an insulating layer, a second electrode (225) facing the first electrode (221), and a light-emitting layer (223) interposed between the first electrode (221) and the second electrode (225). A first functional layer (222) may be disposed between the first electrode (221) and the light-emitting layer (223), and a second functional layer (224) may be disposed between the light-emitting layer (223) and the second electrode (225).

[0130] The edge of the first electrode (221) may be covered with a bank layer (BKL) containing an insulating material. The bank layer (BKL) may include an opening (B-OP) that overlaps the central portion of the first electrode (221).

[0131] The first electrode (221) may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In another embodiment, the first electrode (221) may include a reflective layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. In another embodiment, the first electrode (221) may further include a layer formed of ITO, IZO, ZnO, AZO, or In2O3 above and below the aforementioned reflective layer.

[0132] The light-emitting layer (223) may include a polymer or low-molecular-weight organic material that emits light of a corresponding color (e.g., a predetermined color). The first functional layer (222) may include a hole transport layer and / or a hole injection layer. The second functional layer (224) may include an electron transport layer and / or an electron injection layer.

[0133] The second electrode (225) may be made of a conductive material with a low work function. For example, the second electrode (225) may include a (semi)transparent layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or alloys thereof. Alternatively, the second electrode (225) may further include a layer such as ITO, IZO, ZnO, AZO, or In2O3 on the (semi)transparent layer comprising the aforementioned materials.

[0134] FIG. 8 is a schematic plan view showing a part of a display panel according to one embodiment of the present invention, and is a schematic drawing of area A of the display panel of FIG. 3.

[0135] Referring to FIG. 8, the display area (DA) may include a plurality of first areas (11) and a second area (12) surrounding the plurality of first areas (11) (e.g., on a plane). The first area (11) may have a smaller elongation rate than the second area (12). Accordingly, when the display panel (1) is stretched, the first area (11) may undergo less deformation than the second area (12). The first area (11) may be referred to as a low-deformation area (or low-deformation part) as previously described. Additionally, the first area (11) may be referred to as a pixel area or a light-emitting area as an area where light-emitting diodes are arranged.

[0136] The second region (12) surrounds the first region (11) and may have a greater elongation rate than the first region (11). The second region (12) may be an area where the main deformation occurs due to the stretching of the display panel. Since the second region (12) is positioned between a plurality of first regions (11), it may be referred to as a connecting part that connects the first regions (11). Additionally, the second region (12) may be referred to as a main deformation area (or peripheral deformation part) or a high deformation area (or high deformation part). The second region (12) may be referred to as a non-pixel area or a non-luminous area, as it is an area within the display region where light-emitting diodes are not positioned.

[0137] A pixel circuit (PC) for driving the light-emitting diode of each pixel may be placed in a first region (11). For example, a first pixel circuit (PC1) for a red pixel (PXr, FIG. 4), a second pixel circuit (PC2) for a green pixel (PXg, FIG. 4), and a third pixel circuit (PC3) for a blue pixel (PXb, FIG. 4) may be placed in the first region (11). The first pixel circuit (PC1), the second pixel circuit (PC2), and the third pixel circuit (PC3) may each include a transistor and a capacitor, as described with reference to FIGS. 6a to 6c.

[0138] Lines electrically connected to the pixel circuit (PC) may be placed in the display area (DA). The aforementioned lines may include voltage lines or signal lines. In one embodiment, FIG. 8 illustrates that a gate line (GL) and a data line (DL) are each placed in the first area (11). The gate line (GL) and the data line (DL) may each be electrically connected to the pixel circuit (PC) through a contact hole.

[0139] The gate line (GL) of FIG. 8 is a line that provides a gate signal to the gate electrode of a transistor. In one embodiment, the gate line (GL) may include a first gate line (GL1), a second gate line (GL2), and a third gate line (GL3). The first to third gate lines (GL1, GL2, GL3) extending in a first direction (e.g., x-direction) are each connected to pixel circuits (PCs) arranged in the same row to transmit different gate signals. For example, the gate line (GL) of FIG. 8 may be a scan signal line (GWL), bypass control line (GBL), initialization control line (GIL), and / or light emission control line (EML) of FIG. 6b or FIG. 6c.

[0140] The data line (DL) of FIG. 8 is a line that provides a data signal to each pixel circuit (PC). The data line (DL) extended in a second direction (e.g., the y-direction) may be electrically connected to pixel circuits (PCs) arranged in the same column. In one embodiment, the data line (DL) may include a first data line (DL1) electrically connected to a first pixel circuit (PC1), a second data line (DL2) electrically connected to a second pixel circuit (PC2), and a third data line (DL3) electrically connected to a third pixel circuit (PC3).

[0141] Two adjacent signal lines placed in each of the two adjacent first regions (11) can be electrically connected by a connecting wire (WL). Specifically, two adjacent data lines (DL) placed in each of the two adjacent first regions (11) can be electrically connected by a first connecting wire (WL1). The first connecting wire (WL1) is placed in the second region (12) and can extend in a second direction (e.g., the y-direction). Each of the data lines (DL) placed on opposite sides of the first connecting wire (WL1) can be connected to the first connecting wire (WL1).

[0142] Two adjacent gate lines (GL) placed in each of two adjacent first regions (11) can be electrically connected by a second connecting wire (WL2). The second connecting wire (WL2) is placed in the second region (12) and can extend in a first direction (e.g., x-direction). Each of the gate lines (GL) placed on opposite sides of the second connecting wire (WL2) can be connected to the second connecting wire (WL2).

[0143] The gate line (GL) and the data line (DL) may intersect each other in the first region (11). In one embodiment, the data line (DL) may include a first part (DLa) and a second part (DLb) separated by the gate line (GL), and a bridge line (BL) positioned between the first part (DLa) and the second part (DLb). The first part (DLa) and the second part (DLb) may be electrically connected by the bridge line (BL).

[0144] A bridge line (BL) is placed in an area where a data line (DL) and a gate line (GL) intersect, and can connect a first part (DLa) and a second part (DLb) of the data line (DL). The bridge line (BL) can be placed on a different layer from the first part (DLa) and the second part (DLb). One end of the bridge line (BL) is connected to the first part (DLa) through a contact hole, and the other end of the bridge line (BL) can be connected to the second part (DLb) through a contact hole.

[0145] FIG. 8 illustrates a data line (DL) connected through a first part (DLa), a second part (DLb), and a bridge line (BL), but the present invention is not limited thereto. In another embodiment, a gate line (GL) may be separated into a first part and a second part and connected through a bridge line.

[0146] The first and second connecting wires (WL1, WL2) placed in the second region (12) can be stretched better than the gate wire (GL) and data wire (DL) placed in the first region (11). The elongation rate of each of the first and second connecting wires (WL1, WL2) can be greater than the elongation rate of each of the gate wire (GL) and data wire (DL).

[0147] The gate line (GL) and the data line (DL) may each comprise one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). In some embodiments, the gate line (GL) and the data line (DL) may each be a single layer or multiple layers comprising the aforementioned metals. In one embodiment, the gate line (GL) and the data line (DL) may each comprise a metal thin film formed as a triple layer of a titanium (Ti) / aluminum (Al) / titanium (Ti) structure.

[0148] As will be described later, the first and second connecting wires (WL1, WL2) may include a conductive composite material comprising a metal nanostructure, an elastic polymer, and / or an elastomer. Accordingly, when the display panel (1) is stretched, high deformation may occur in the first and second connecting wires (WL1, WL2) and the second region (12).

[0149] FIG. 8 illustrates that the gate line (GL) and the data line (DL) are electrically connected to the first connection line (WL1) and the second connection line (WL2), respectively, but the present invention is not limited thereto. As another embodiment, the first initialization voltage line (VIL1), the second initialization voltage line (VIL2), the holding voltage line (VSL), the first voltage line (VDDL), or the second voltage line (VSSL) described with reference to FIG. 6a to 6c may each be placed in the first area (11) and electrically connected to the connection line placed in the second area (12).

[0150] FIG. 9 is a cross-sectional view schematically showing a part of a display panel according to an embodiment of the present invention. FIG. 10 is a perspective view showing the connection wiring of a display panel according to an embodiment of the present invention. FIG. 11a and FIG. 11b are schematic drawings showing the connection wiring of a display panel according to an embodiment of the present invention, respectively.

[0151] Referring to FIG. 9, the display panel (1) may include first regions (11) and a second region (12) between the first regions (11), as previously described with reference to FIG. 8. Since the components of the display panel (1) are placed on a base layer (400), the statement that the display panel (1) includes the first region (11) and the second region (12) corresponds to the base layer (400) including the first region (11) and the second region (12).

[0152] The display panel (1) may include a pixel circuit layer (PCL) and a light-emitting diode (LED) on the pixel circuit layer (PCL) disposed in each of two adjacent first regions (11). The light-emitting diode (LED) shown in FIG. 9 may correspond to any one of the first to third light-emitting diodes (LED1, LED2, LED3) shown in FIG. 5.

[0153] Each pixel circuit layer (PCL) may include an inorganic insulating stack (IIL), a pixel circuit (PC), and an organic insulating layer (OIL). For convenience of explanation, one of the pixel circuit layers (PCLs) disposed in each of two adjacent first regions (11) is referred to as the first pixel circuit layer (PCL1), and the other as the second pixel circuit layer (PCL2).

[0154] The first pixel circuit layer (PCL1) and the second pixel circuit layer (PCL2) may each be disposed on the base layer (400). The first pixel circuit layer (PCL1) and the second pixel circuit layer (PCL2) may each be disposed on the first surface (e.g., the top surface) of the base layer (400).

[0155] The base layer (400) can absorb stress generated during the stretching of the display panel (1). The base layer (400) may include an elastomer (or an elastomer material). The base layer (400) is thermoplastic polyurethane, silicone, thermoplastic rubbers, elastolefin, thermoplastic olefin, polyamide, polyether block amide, synthetic polyisoprene, polybutadiene, chloroprene rubber, butyl rubber, styrene-butadiene, epichlorohydrin rubber, polyacrylic rubber, silicone rubber, fluorosilicone rubber, fluoroelastomers, ethylene-vinyl acetate, PDMS (polydimethylsiloxane), and It may include at least one of Ecoflex (Ecoflex, a registered trademark of Smooth-On, Inc., located in Macungie, Pennsylvania, USA).

[0156] Each of the first pixel circuit layer (PCL1) and the second pixel circuit layer (PCL2) may include an inorganic insulating stack (IIL), a pixel circuit (PC), and an organic insulating layer (OIL). The inorganic insulating stack (IIL) may include a buffer layer (111), a gate insulating layer (113), a first interlayer insulating layer (115), and a second interlayer insulating layer (117). The organic insulating layer (OIL) may include a first organic insulating layer (121) and a second organic insulating layer (123).

[0157] The first pixel circuit layer (PCL1) and the second pixel circuit layer (PCL2) may be spaced apart from each other. The statement that the first pixel circuit layer (PCL1) and the second pixel circuit layer (PCL2) are spaced apart from each other means that the inorganic insulating stack (IIL), pixel circuit (PC), and organic insulating layer (OIL) of the first pixel circuit layer (PCL1) are spaced apart from the inorganic insulating stack (IIL), pixel circuit (PC), and organic insulating layer (OIL) of the second pixel circuit layer (PCL2), respectively.

[0158] The inorganic insulating stack (IIL) may be placed in the first region (11) and may not be placed in the second region (12). The inorganic insulating stack (IIL) may have an isolated shape placed in the first region (11). The inorganic insulating stacks (IIL) placed in each of the first regions (11) may be spaced apart from each other in a plane. For example, the buffer layer (111), gate insulating layer (113), first interlayer insulating layer (115), and second interlayer insulating layer (117) of the first pixel circuit layer (PCL1) may be separated from the buffer layer (111), gate insulating layer (113), first interlayer insulating layer (115), and second interlayer insulating layer (117) of the second pixel circuit layer (PCL2), respectively.

[0159] Likewise, the organic insulating layer (OIL) may be disposed in the first region (11) and not in the second region (12). The organic insulating layer (OIL) may have an isolated shape disposed in the first region (11). For example, the first organic insulating layer (121) and the second organic insulating layer (123) of the first pixel circuit layer (PCL1) may be separated from the first organic insulating layer (121) and the second organic insulating layer (123) of the second pixel circuit layer (PCL2), respectively.

[0160] As illustrated in FIG. 9, the buffer layer (111) is disposed on the base layer (400), and the pixel circuit (PC) can be disposed on the buffer layer (111). The buffer layer (111) may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0161] The thin-film transistor (TFT) of the pixel circuit (PC) may include a semiconductor layer (Act), a gate electrode (GE), a source electrode (SE), and a drain electrode (DE). FIG. 11 illustrates a top-gate type in which the gate electrode (GE) is placed on the semiconductor layer (Act) with the gate insulating layer (113) in between, but according to another embodiment, the thin-film transistor (TFT) may be a bottom-gate type.

[0162] The semiconductor layer (Act) may include polysilicon. Alternatively, the semiconductor layer (Act) may include amorphous silicon, oxide semiconductor, organic semiconductor, etc. The gate electrode (GE) may include a metal thin film composed of a low-resistance metal material. The gate electrode (GE) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials. For example, the gate electrode (GE) may include a metal thin film formed as a triple layer with a titanium (Ti) / aluminum (Al) / titanium (Ti) structure.

[0163] The gate insulating layer (113) between the semiconductor layer (Act) and the gate electrode (GE) may include an inorganic insulating material such as silicon oxide, nitrogen oxide, silicon oxynitride, aluminum oxide, or titanium oxide. The gate insulating layer (113) may be a single layer or a multilayer containing the aforementioned materials.

[0164] The source electrode (SE) and the drain electrode (DE) may be located on the same layer, for example, the second interlayer insulating layer (117), and may contain the same material. The source electrode (SE) and the drain electrode (DE) may contain a metal thin film composed of a low-resistance metal material. The source electrode (SE) and the drain electrode (DE) may contain a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer containing the above materials. For example, the source electrode (SE) and the drain electrode (DE), like the gate electrode (GE), may be provided with a metal thin film formed as a triple layer of titanium (Ti) / aluminum (Al) / titanium (Ti) structure. The second interlayer insulating layer (117) may include an inorganic insulating material such as silicon oxide, nitrogen oxide, silicon oxynitride, aluminum oxide, or titanium oxide, and may be a single layer or a multilayer containing the aforementioned material.

[0165] A storage capacitor (Cst) may include a first electrode (CE1) and a second electrode (CE2) that overlap with a first interlayer insulating layer (115) in between. The storage capacitor (Cst) may overlap with a thin-film transistor (TFT). In this regard, FIG. 7 illustrates that the gate electrode (GE) of the thin-film transistor (TFT) is the first electrode (CE1) of the storage capacitor (Cst). In another embodiment, the storage capacitor (Cst) may not overlap with the thin-film transistor (TFT). The storage capacitor (Cst) may be covered by a second interlayer insulating layer (117).

[0166] The first interlayer insulating layer (115) may be disposed between the gate insulating layer (113) and the second interlayer insulating layer (117). The first interlayer insulating layer (115) and the second interlayer insulating layer (117) may each include an inorganic insulating material such as silicon oxide, nitrogen oxide, silicon oxynitride, aluminum oxide, or titanium oxide, and may be a single layer or a multilayer containing the aforementioned materials.

[0167] The second electrode (CE2) of the storage capacitor (Cst) may include a conductive material and may be formed as a multilayer or single layer. The second electrode (CE2) may include a metal thin film composed of a low-resistance metal material. The second electrode (CE2) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials. For example, the second electrode (CE2) may be provided as a metal thin film formed as a triple layer of a titanium (Ti) / aluminum (Al) / titanium (Ti) structure.

[0168] The first organic insulating layer (121) may be disposed on the second interlayer insulating layer (117). The second organic insulating layer (123) may be disposed on the first organic insulating layer (121). The connecting electrode (CM) and the second voltage line (VSSL) may be disposed on the first organic insulating layer (121). The connecting electrode (CM) may electrically connect the pixel circuit (PC) and the first electrode pad (241). The second voltage line (VSSL) may be electrically connected to the second electrode pad (242).

[0169] The connecting electrode (CM) and the second voltage line (VSSL) may include a metal thin film composed of a low-resistance metal material. The connecting electrode (CM) and the second voltage line (VSSL) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials. For example, the connecting electrode (CM) and the second voltage line (VSSL) may be provided as a metal thin film formed as a triple layer of a titanium (Ti) / aluminum (Al) / titanium (Ti) structure.

[0170] The first electrode pad (241) and the second electrode pad (242) may be disposed on the second organic insulating layer (123). The first electrode pad (241) may be electrically connected to a thin-film transistor (TFT) through a connecting electrode (CM) between the first organic insulating layer (121) and the second organic insulating layer (123).

[0171] The light-emitting diode (LED) on the first electrode pad (241) and the second electrode pad (242) may be the same as the light-emitting diode (LED) described above with reference to FIG. 7a. In another embodiment, the light-emitting diode (LED) may have a structure as shown in FIG. 7b. One side of the light-emitting diode (LED) may be covered with a protective layer (240) containing an organic insulator.

[0172] The first line (L1, or conductive line) may be a signal line or voltage line electrically connected to the pixel circuit (PC) of the first pixel circuit layer (PCL1). The second line (L2, or conductive line) may be a signal line or voltage line electrically connected to the pixel circuit (PC) of the second pixel circuit layer (PCL2). In one embodiment, the first line (L1) and the second line (L2) may include the gate line (GL, FIG. 8) or data line (DL, FIG. 8) described above with reference to FIG. 8. In another embodiment, the first line (L1) and the second line (L2) may be the first voltage line (VDDL) or the second voltage line (VSSL) described with reference to FIG. 6a, or the first initialization voltage line (VIL1), the second initialization voltage line (VIL2), the holding voltage line (VSL), the first voltage line (VDDL), or the second voltage line (VSSL) described with reference to FIG. 6b and FIG. 6c.

[0173] Each of the first line (L1) and the second line (L2) is positioned on the interlayer insulation layer (117) and may extend onto the connecting wire (WL). A portion of the first line (L1) may be located on the corresponding second interlayer insulation layer (117). Another portion of the first line (L1) may extend onto the connecting wire (WL) through the inorganic insulation stack (IIL) and may come into direct contact with the connecting wire (WL). Along the third direction (e.g., the z-direction), a portion of the first line (L1) may be positioned between the second interlayer insulation layer (117) and the first organic insulation layer (121), and another portion of the first line (L1) may be positioned between the third organic insulation layer (119) and the second organic insulation layer (123), which will be described later. Likewise, one part of the second line (L2) is located on the corresponding second interlayer insulation layer (117), and the other part of the second line (L2) extends onto the connecting wire (WL) and can come into direct contact with the connecting wire (WL). Along the third direction (e.g., z-direction), one part of the second line (L2) may be positioned between the second interlayer insulation layer (117) and the first organic insulation layer (121), and the other part of the second line (L2) may be positioned between the third organic insulation layer (119) and the second organic insulation layer (123), which will be described later.

[0174] An inorganic insulating stack (IIL) with an isolated shape on a plane may have a step with respect to the upper surface of the base layer (400) as shown in FIG. 9. In one embodiment, as shown in FIG. 9, the organic insulating layer (OIL) may further include a third organic insulating layer (119) arranged to cover the side of the inorganic insulating stack (IIL). The third organic insulating layer (119) may have a closed-loop shape on a plane to cover the side of the inorganic insulating stack (IIL). The first line (L1) and the second line (L2) may extend onto the connecting wire (WL) through the upper surface of the corresponding third organic insulating layer (119).

[0175] As previously explained, a connecting wire (WL) may be disposed in the second region (12). In one embodiment, the connecting wire (WL) may be disposed on the bottom surface of the pixel circuit layer (PCL). In other words, the base layer (400) may include a recess (400RC) that is concave from the top surface toward the bottom surface, and the connecting wire (WL) may be present within the recess (400RC).

[0176] The connecting wire (WL) includes a first surface (e.g., bottom surface) facing the base layer (400) and a second surface (e.g., top surface) opposite the first surface. The second surface (e.g., top surface) of the connecting wire (WL) may be located on the same surface as the top surface of the base layer (400). Accordingly, the thickness of the base layer (400) overlapping with the connecting wire (WL) may be smaller than the thickness of other parts of the base layer (400) that do not overlap with the connecting wire (WL). That is, as the connecting wire (WL) has a structure embedded in the base layer (400), the base layer (400) can absorb the stress that may be concentrated on the connecting wire (WL) during the stretching of the display panel (1).

[0177] Referring to FIGS. 10, 11a, and 11b, the connecting wire (WL) may include a stacked structure comprising a main connecting wire (WLm) and auxiliary connecting wires (WLs) composed of different materials. As previously described, the connecting wire (WL) is disposed in the second region (12) and may include a material with excellent ductility. For example, the connecting wire (WL) may include a metal nanostructure.

[0178] As shown in FIG. 10, the connecting wire (WL) is disposed within the recess (400RC) of the base layer (400), the main connecting wire (WLm) is disposed within the recess (400RC), and auxiliary connecting wires (WLs) may be disposed on the main connecting wire (WLm). That is, the lower surface of the main connecting wire (WLm) may come into contact with the base layer (400), and the upper surface of the auxiliary connecting wires (WLs) may come into contact with the first line (L1), the second line (L2), and the protective layer (300). However, the connecting wire (WL) is not limited thereto, and in some other embodiments, the connecting wire (WL) may include a structure in which the main connecting wire (WLm) is disposed on the auxiliary connecting wires (WLs).

[0179] In one embodiment, the main connecting wire (WLm) and the auxiliary connecting wire (WLs) may each include nanostructures of different dimensions. For example, the main connecting wire (WLm) may include a two-dimensional nanostructure, and the auxiliary connecting wire (WLs) may include at least one of a one-dimensional nanostructure and a zero-dimensional nanostructure.

[0180] In this specification, a two-dimensional nanostructure may refer to a nanostructure in which the size of one of the two dimensions is significantly larger than that of the other dimension. That is, a two-dimensional nanostructure may be a nanostructure in which the area defined by the two dimensions is significantly larger than the thickness. For example, the two-dimensional nanostructure included in the main connecting wire (WLm) may include at least one of a nanoflake, a nanosheet, and a nanoplate. However, the two-dimensional nanostructure is not limited thereto, and any that can be used as a two-dimensional nanostructure in the relevant technical field may be possible.

[0181] Additionally, in this specification, a one-dimensional nanostructure may refer to a nanostructure in which the size of one dimension is significantly larger than the other two dimensions. That is, a one-dimensional nanostructure may be a nanostructure in which the length defined by one dimension is significantly larger than the remaining dimensions. For example, the one-dimensional nanostructure included in the auxiliary connecting wires (WLs) may include at least one of a nanowire, a nanofiber, a nanotube, a nanorod, and a nanobelt. However, the one-dimensional nanostructure is not limited thereto, and any that can be used as a one-dimensional nanostructure in the relevant technical field may be possible.

[0182] Likewise, in this specification, a zero-dimensional nanostructure may refer to a structure in which all three dimensions have a size at the nanometer level. That is, a zero-dimensional nanostructure may be a nanostructure in the form of a particle with almost no three-dimensional expansion. For example, a zero-dimensional nanostructure included in auxiliary connecting wires (WLs) may include nanoparticles. However, the zero-dimensional nanostructure is not limited thereto, and any that can be used as a zero-dimensional nanostructure in the relevant technical field may be possible.

[0183] In one embodiment, the main connecting wire (WLm) and the auxiliary connecting wire (WLs) may each include a metal nanostructure. The main connecting wire (WLm) and the auxiliary connecting wire (WLs) may include a low-resistance metal such as silver (Ag), copper (Cu), and / or nickel (Ni). In one embodiment, the main connecting wire (WLm) and the auxiliary connecting wire (WLs) may each include a material based on the same metal, having nanostructures of different dimensions. For example, the main connecting wire (WLm) may include silver nanoflakes (Ag nanoflake) as a two-dimensional nanostructure. The auxiliary connecting wire (WLs) may include silver nanowires (Ag nanowire) as a one-dimensional nanostructure and silver nanoparticles (Ag nanoparticle) as a zero-dimensional nanostructure.

[0184] When the main connecting wire (WLm) and the auxiliary connecting wire (WLs) contain a material based on the same metal, not only can the interfacial resistance between the main connecting wire (WLm) and the auxiliary connecting wire (WLs) be lowered, but the bonding strength between the main connecting wire (WLm) and the auxiliary connecting wire (WLs) can also be improved.

[0185] However, the main connecting wire (WLm) and the auxiliary connecting wire (WLs) are not limited thereto, and in other embodiments, the main connecting wire (WLm) may include a low-resistance metal material as it performs the role of the main wiring, and the auxiliary connecting wire (WLs) may include a material having relatively low conductivity but excellent elasticity. For example, the main connecting wire (WLm) may include a metal nanostructure such as silver nanoflake (Ag nanoflake), while the auxiliary connecting wire (WLs) may include a carbon-based nanostructure such as one-dimensional carbon nanotube (Carbon nanotube) and graphene.

[0186] Meanwhile, the main connecting wire (WLm) and the auxiliary connecting wire (WLs) may each further include an elastic polymer material in addition to the metal nanostructure. In one embodiment, the elastic polymer material included in the main connecting wire (WLm) and the auxiliary connecting wire (WLs) may include the same material as the base layer (400) and / or the protective layer (300) described later. For example, if the base layer (400) includes PDMS, the main connecting wire (WLm) and the auxiliary connecting wire (WLs) may include PDMS in addition to the metal nanostructure. Alternatively, if the base layer (400) includes polyurethane, the main connecting wire (WLm) and the auxiliary connecting wire (WLs) may include polyurethane in addition to the metal nanostructure.

[0187] As the main connecting wire (WLm) contains the same elastic polymer material as the base layer (400), the bonding strength between the main connecting wire (WLm) and the base layer (400) can be increased. Similarly, as the auxiliary connecting wire (WLs) contains the same elastic polymer material as the protective layer (300), the bonding strength between the auxiliary connecting wire (WLs) and the protective layer (300) can be increased.

[0188] Here, FIG. 11a is a schematic diagram illustrating the non-stretched state of the connecting wire (WL), and FIG. 11b is a schematic diagram illustrating the stretched state of the connecting wire (WL). As shown in FIG. 11a, since both the main connecting wire (WLm) and the auxiliary connecting wire (WLs) contain a conductive metal nanostructure, both the main connecting wire (WLm) and the auxiliary connecting wire (WLs) can have excellent electrical characteristics when the connecting wire (WL) is in a non-stretched state. However, as shown in FIG. 11b, when the connecting wire (WL) is stretched beyond a corresponding level (e.g., a certain level), cracks may occur on the surface of the main connecting wire (WLm) containing the two-dimensional nanostructure. At this time, auxiliary connecting wires (WLs) including one-dimensional nanostructures and zero-dimensional nanostructures are placed on one side of the main connecting wire (WLm) and can serve as an auxiliary layer that maintains a conductive network.

[0189] For example, the main connecting wire (WLm) of the connecting wire (WL) may include silver nanoflakes as a two-dimensional nanostructure. That is, the main connecting wire (WLm) may include a metal nanostructure having a thin and wide plate-like shape. The auxiliary connecting wires (WLs) of the connecting wire (WL) may be in a state where one-dimensional nanostructures (e.g., silver nanowires) and zero-dimensional nanostructures (e.g., silver nanoparticles) are mixed. That is, the auxiliary connecting wires (WLs) may include a metal nanostructure having a long, thin wire shape and a metal nanostructure having a spherical shape.

[0190] A main connecting wire (WLm) comprising two-dimensional nanostructures, such as silver nanoflakes, may be advantageous for forming a stacked structure of nanostructures within the wire because each nanostructure has a large contact area. That is, since a conductive network can be easily formed within the main connecting wire (WLm), it may be a wire that possesses excellent electrical properties while maintaining flexibility. In one embodiment, the main connecting wire (WLm) may contain silver nanoflakes in an amount of approximately 80 wt% or more and approximately 100 wt% or less. Such a main connecting wire (WLm) can secure an elongation rate of approximately 50% or more, while approximately 10 4 It can have an electrical conductivity of S / cm or higher.

[0191] Auxiliary connecting wires (WLs) containing one-dimensional nanostructures such as silver nanowires can be arranged relatively flexibly within the wires because each nanostructure has a thin, elongated cylindrical shape. That is, even if cracks occur in the main connecting wire (WLm) due to stretching, the auxiliary connecting wires (WLs) can maintain the conductive network within the connecting wire (WL) through the wire-shaped nanostructures.

[0192] For example, the electrical stability of the connecting wires (WLs) can be further improved by including zero-dimensional nanostructures, such as silver nanoparticles, in addition to the auxiliary connecting wires (WLs). Zero-dimensional nanostructures, such as silver nanoparticles, can function as silver precursors (Ag precursors). Silver nanoparticles not only have excellent bonding characteristics with silver nanowires, but also can grow through heat. That is, when heat treatment is applied to the auxiliary connecting wires (WLs), the silver nanoparticles grow, which can increase the contact area of ​​the nanostructures within the auxiliary connecting wires (WLs), thereby making the conductive network within the connecting wires (WLs) robust.

[0193] That is, by placing auxiliary connecting wires (WLs) having one-dimensional nanostructures and zero-dimensional nanostructures on one side of the main connecting wire (WLm) so as to connect cracks that may occur on the surface of the main connecting wire (WLm), the reduction in resistance caused by cracks that may occur in the connecting wire (WL) can be reduced or minimized.

[0194] In addition, the main connecting wire (WLm) is suitable for performing the role of the main wiring because it is easy to form a conductive network. Accordingly, the thickness of the main connecting wire (WLm) may be thicker than the thickness of the auxiliary connecting wire (WLs). For example, the thickness of the main connecting wire (WLm) may be at the level of 20 μm, and the thickness of the auxiliary connecting wire (WLs) may be at the level of 200 nm. That is, the ratio of the thickness of the main connecting wire (WLm) to the thickness of the auxiliary connecting wire (WLs) may be at the level of 100:1. However, it is not limited to this, and the thicknesses of the main connecting wire (WLm) and the auxiliary connecting wire (WLs) may be modified considering electrical characteristics and flexibility.

[0195] In conclusion, a display panel according to one embodiment of the present invention can secure excellent flexibility of the display panel as well as electrical stability by including a main connecting wire (WLm) and an auxiliary connecting wire (WLs) having nanostructures of different dimensions in the connecting wire (WL). That is, by arranging an auxiliary connecting wire (WLs) including a 0-dimensional nanostructure and a 1-dimensional nanostructure on one side of a main connecting wire (WLm) with high conductivity, changes in the electrical characteristics of the connecting wire (WL) can be minimized even when the display panel is stretched.

[0196] In particular, as explained above, when the main connecting wire (WLm) and the auxiliary connecting wire (WLs) contain materials based on the same metal, the auxiliary connecting wire (WLs) having different materials can be utilized as a conductive bridge, while also improving the bonding strength and electrical characteristics of the main connecting wire (WLm) and the auxiliary connecting wire (WLs).

[0197] Referring again to FIG. 9, a light-emitting diode (LED) may be placed on a corresponding pixel circuit layer (PCL). For example, a light-emitting diode (LED) electrically connected to a pixel circuit (PC) of a first pixel circuit layer (PCL1) may be placed on the corresponding first pixel circuit layer (PCL1), and a light-emitting diode (LED) electrically connected to a pixel circuit (PC) of a second pixel circuit layer (PCL2) may be placed on the corresponding second pixel circuit layer (PCL2). One side (e.g., one side) of each light-emitting diode (LED) may be covered by a protective layer (240). The protective layer (240) may include an organic insulating material such as polyimide.

[0198] A protective layer (300) may be disposed on the light-emitting diode (LED) and the connecting wire (WL). The protective layer (300) may cover the light-emitting diode (LED) and the connecting wire (WL). The protective layer (300) may absorb stress that may be transmitted to the light-emitting diode (LED) and the connecting wire (WL) during the stretching of the display panel (1), and may flatten the upper surface of the display panel (1). The protective layer (300) may include an elastomer. For example, the protective layer (300) is thermoplastic polyurethane, polyester, silicone, thermoplastic rubbers, elastolefin, thermoplastic olefin, polyamide, polyether block amide, synthetic polyisoprene, polybutadiene, chloroprene rubber, butyl rubber, styrene-butadiene, epichlorohydrin rubber, polyacrylic rubber, silicone rubber, fluorosilicone rubber, fluoroelastomers, ethylene-vinyl acetate, It may include at least one of PDMS (polydimethylsiloxane) and Ecoflex (a registered trademark of Smooth-On, Inc., located in Macungie, Pennsylvania, USA).

[0199] The protective layer (300) can come into direct contact with the upper surface of the connecting wire (WL) and can come into direct contact with a portion of the upper surface of the base layer (400). In one embodiment, if the material of the protective layer (300) and the material of the base layer (400) are the same, the bonding strength between the protective layer (300) and the base layer (400) can be increased, thereby maintaining the airtightness of the display panel (1) more effectively.

[0200] FIG. 12 is a perspective view showing the connection wiring of a display panel according to another embodiment of the present invention. FIG. 13 is a cross-sectional view schematically showing the connection wiring of a display panel according to another embodiment of the present invention. Referring to FIG. 12 and FIG. 13, other features are the same as those described in FIG. 9 to FIG. 11b, except for the features regarding auxiliary connection wiring (WLs). Among the components of FIG. 12 and FIG. 13, identical reference numerals are replaced with those previously described with reference to FIG. 9 to FIG. 11b, and the differences will be described below.

[0201] Referring to FIGS. 12 and 13, the connecting wire (WL) may include a stacked structure comprising a main connecting wire (WLm) and an auxiliary connecting wire (WLs) composed of different materials. In this case, the auxiliary connecting wire (WLs) may include a first auxiliary connecting wire (WLs1) and a second auxiliary connecting wire (WLs2), each comprising a nanostructure of different dimensions.

[0202] As shown in FIG. 12, the connecting wire (WL) is placed within the recess (400RC, FIG. 9) of the base layer (400), and the main connecting wire (WLm), the first auxiliary connecting wire (WLs1), and the second auxiliary connecting wire (WLs2) can be sequentially stacked within the recess (400RC, FIG. 9). That is, the first auxiliary connecting wire (WLs1) can be placed on the main connecting wire (WLm), and the second auxiliary connecting wire (WLs2) can be placed on the first auxiliary connecting wire (WLs1). Accordingly, the lower surface of the main connecting wire (WLm) can come into contact with the base layer (400), and the upper surface of the second auxiliary connecting wire (WLs2) can come into contact with the first line (L1), the second line (L2), and the protective layer (300, FIG. 9).

[0203] The main connecting wire (WLm), the first auxiliary connecting wire (WLs1), and the second auxiliary connecting wire (WLs2) may each include nanostructures of different dimensions. In one embodiment, the main connecting wire (WLm) may include a two-dimensional nanostructure, the first auxiliary connecting wire (WLs1) may include a one-dimensional nanostructure, and the second auxiliary connecting wire (WLs2) may include a zero-dimensional nanostructure. The two-dimensional nanostructure may include at least one of a nanoflake, a nanosheet, and a nanoplate. The one-dimensional nanostructure may include at least one of a nanowire, a nanofiber, a nanotube, a nanorod, and a nanobelt, and the zero-dimensional nanostructure may include a nanoparticle.

[0204] In one embodiment, the main connecting wire (WLm), the first auxiliary connecting wire (WLs1), and the second auxiliary connecting wire (WLs2) may each have nanostructures of different dimensions and may each include a material based on the same metal. For example, the main connecting wire (WLm) may include silver nanoflakes (Ag nanoflake), the first auxiliary connecting wire (WLs1) may include silver nanowires (Ag nanowire), and the second auxiliary connecting wire (WLs2) may include silver nanoparticles (Ag nanoparticle).

[0205] Meanwhile, the main connecting wire (WLm), the first auxiliary connecting wire (WLs1), and the second auxiliary connecting wire (WLs2) may each further include an elastic polymer material in addition to a metal nanostructure. In one embodiment, the elastic polymer material included in the main connecting wire (WLm), the first auxiliary connecting wire (WLs1), and the second auxiliary connecting wire (WLs2) may include the same material as the base layer (400) and / or the protective layer (300, FIG. 9). For example, if the base layer (400) includes PDMS, the main connecting wire (WLm), the first auxiliary connecting wire (WLs1), and the second auxiliary connecting wire (WLs2) may include PDMS in addition to a metal nanostructure.

[0206] As shown in FIG. 13, the main connecting wire (WLm) contains silver nanoflakes, so that a conductive network can be easily formed within the wire, allowing it to have flexibility while possessing excellent electrical properties. The first auxiliary connecting wire (WLs1) contains silver nanowires, so that the conductive network within the connecting wire (WL) can be maintained even if cracks occur in the main connecting wire (WLm). The second auxiliary connecting wire (WLs2) contains silver nanoparticles, so that the conductive network within the connecting wire (WL) can be made more robust.

[0207] In conclusion, a display panel according to one embodiment of the present invention can secure excellent flexibility of the display panel as well as electrical stability, as the connecting wire (WL) includes a main connecting wire (WLm), a first auxiliary connecting wire (WLs1), and a second auxiliary connecting wire (WLs2) having nanostructures of different dimensions.

[0208] FIGS. 14a and FIGS. 14b are perspective views showing the connection wiring of a display panel according to another embodiment of the present invention. Referring to FIGS. 14a and FIGS. 14b, other features are the same as those described in FIGS. 9 to 13, except for the features regarding the auxiliary connection wiring (WLs). Among the components of FIGS. 14a and FIGS. 14b, identical reference numerals are substituted as those previously described with reference to FIGS. 9 to 13, and the following description focuses on the differences.

[0209] First, referring to FIG. 14a, the connecting wire (WL) may include a stacked structure of a main connecting wire (WLm) and an auxiliary connecting wire (WLs) composed of different materials. In this case, the auxiliary connecting wire (WLs) may include a first auxiliary connecting wire (WLs1) and a second auxiliary connecting wire (WLs2), each comprising a nanostructure of different dimensions. In one embodiment, the auxiliary connecting wire (WLs) may further include a third auxiliary connecting wire (WLs3) comprising a material different from the main connecting wire (WLm), the first auxiliary connecting wire (WLs1), and the second auxiliary connecting wire (WLs2).

[0210] The third auxiliary connecting wire (WLs3) may include a material having lower conductivity than the first auxiliary connecting wire (WLs1) and the second auxiliary connecting wire (WLs2), which include metal nanostructures, but higher elasticity. In one embodiment, the third auxiliary connecting wire (WLs3) may include a carbon-based nanostructure. The third connecting wire (WLs3) may include at least one of a one-dimensional carbon nanostructure and a two-dimensional nanostructure. As a one-dimensional carbon nanostructure, the third connecting wire (WLs3) may include at least one of a carbon nanotube, a carbon nanowire, a carbon nanofiber, a carbon nanobelt, and a carbon nanorod. The third connecting wire (WLs3) may include at least one of graphene, graphene oxide, graphene nanoplate, and carbon nanosheet among two-dimensional nanostructures.

[0211] As shown in FIG. 14a, the connecting wire (WL) is placed within the recess (400RC, FIG. 9) of the base layer (400), and the third auxiliary connecting wire (WLs3), the main connecting wire (WLm), the first auxiliary connecting wire (WLs1), and the second auxiliary connecting wire (WLs2) can be sequentially stacked within the recess (400RC, FIG. 9). That is, the third auxiliary connecting wire (WLs3) can be placed below the main connecting wire (WLm), and the first auxiliary connecting wire (WLs1) and the second auxiliary connecting wire (WLs2) can be placed above the main connecting wire (WLm).

[0212] Next, referring to FIG. 14b, the connecting wire (WL) may include a stacked structure of a main connecting wire (WLm) and auxiliary connecting wires (WLs) composed of different materials. In this case, the auxiliary connecting wires (WLs) may include a first auxiliary connecting wire (WLs1) and a second auxiliary connecting wire (WLs2), each comprising a nanostructure of different dimensions. In one embodiment, the auxiliary connecting wires (WLs) may further include a third auxiliary connecting wire (WLs3) and a fourth auxiliary connecting wire (WLs4) comprising materials different from the main connecting wire (WLm), the first auxiliary connecting wire (WLs1), and the second auxiliary connecting wire (WLs2).

[0213] The third auxiliary connecting wire (WLs3) and the fourth auxiliary connecting wire (WLs4) may include a material having lower conductivity than the first auxiliary connecting wire (WLs1) and the second auxiliary connecting wire (WLs2), which include metal nanostructures, but higher elasticity. In one embodiment, the third auxiliary connecting wire (WLs3) and the fourth auxiliary connecting wire (WLs4) may include carbon-based nanostructures. In one embodiment, the third auxiliary connecting wire (WLs3) may include a carbon-based two-dimensional nanostructure, and the fourth auxiliary connecting wire (WLs4) may include a carbon-based one-dimensional nanostructure.

[0214] The third connecting wire (WLs3) may include at least one of graphene, graphene oxide, graphene nanoplate, and carbon nanosheet among two-dimensional nanostructures. The fourth connecting wire (WLs4) may include at least one of carbon nanotube, carbon nanowire, carbon nanofiber, carbon nanobelt, and carbon nanorod as a one-dimensional carbon nanostructure. The third connecting wire (WLs3) may include at least one of graphene, graphene oxide, graphene nanoplate, and carbon nanosheet among two-dimensional nanostructures.

[0215] As shown in FIG. 14b, the connecting wire (WL) is placed within the recess (400RC, FIG. 9) of the base layer (400), and the fourth auxiliary connecting wire (WLs4), the third auxiliary connecting wire (WLs3), the main connecting wire (WLm), the first auxiliary connecting wire (WLs1), and the second auxiliary connecting wire (WLs2) can be sequentially stacked within the recess (400RC, FIG. 9). That is, the third auxiliary connecting wire (WLs3) and the fourth auxiliary connecting wire (WLs4) can be placed below the main connecting wire (WLm), and the first auxiliary connecting wire (WLs1) and the second auxiliary connecting wire (WLs2) can be placed above the main connecting wire (WLm).

[0216] As shown in FIGS. 14a and 14b, the main connecting wire (WLm) may include silver nanoflakes to have flexibility while possessing excellent electrical properties. The first auxiliary connecting wire (WLs1) and the second auxiliary connecting wire (WLs2) may each include silver nanowires and silver nanoparticles, respectively, thereby maintaining a conductive network within the connecting wire (WL). Additionally, the third auxiliary connecting wire (WLs3) and / or the fourth auxiliary connecting wire (WLs4), which are positioned below the main connecting wire (WLm), may have relatively lower conductivity than the first auxiliary connecting wire (WLs1) and the second auxiliary connecting wire (WLs2), which include metal nanostructures, but may be advantageous in terms of flexibility.

[0217] In conclusion, a display panel according to one embodiment of the present invention can efficiently achieve electrical stability and excellent flexibility simultaneously (concurrently or substantially simultaneously) by arranging an auxiliary wiring comprising a metal-based nanostructure on one side of a main connecting wiring (WLm) and an auxiliary wiring comprising a carbon-based nanostructure on the other side.

[0218] FIG. 15 is a perspective view showing the connection wiring of a display panel according to another embodiment of the present invention. Referring to FIG. 15, other features are the same as those described in FIG. 9 to FIG. 11b, except for the features regarding the connection wiring (WL). Among the components of FIG. 15, identical reference numerals are replaced with those previously described with reference to FIG. 9 to FIG. 11b, and the following description focuses on the differences.

[0219] Referring to FIG. 15, the connecting wire (WL) is placed within the recess (400RC, FIG. 9) of the base layer (400), and the main connecting wire (WLm) and auxiliary connecting wire (WLs) can be sequentially placed within the recess (400RC). Accordingly, the lower surface of the main connecting wire (WLm) can come into contact with the base layer (400), the upper surface of the main connecting wire (WLm) can come into contact with the lower surface of the auxiliary connecting wire (WLs), and the upper surface of the auxiliary connecting wire (WLs) can come into contact with the protective layer (300, FIG. 9). At this time, the interface between the auxiliary connecting wire (WLs) and the protective layer (300, FIG. 9) can be referred to as the first interface (F1), the interface between the auxiliary connecting wire (WLs) and the main connecting wire (WLm) can be referred to as the second interface (F2), and the interface between the main connecting wire (WLm) and the base layer (400) can be referred to as the third interface (F3).

[0220] In one embodiment, the first to third interfaces (F1, F2, F3) may each be surface-treated to increase the bonding strength of the connecting wire (WL), base layer (400), and protective layer (300, FIG. 9). For example, the first to third interfaces (F1, F2, F3) may each be surface-treated through polymer treatment. Here, surface treatment through polymer treatment may mean forming a self-assembled monolayer (SAM) on the first to third interfaces (F1, F2, F3). When a self-assembled monolayer is formed on the first to third interfaces (F1, F2, F3), molecules having specific functional groups are aligned on the surface to form a monolayer structure, thereby modifying the surface and improving the interfacial bonding strength.

[0221] Alternatively, the first to third interfaces (F1, F2, F3) may each be surface-treated through plasma treatment. Plasma treatment is a surface treatment technology that alters the surface of a material using a gas in a plasma state, and methods such as low-pressure plasma or radio-frequency plasma may be used. When the first to third interfaces (F1, F2, F3) are surface-treated through plasma treatment, the surfaces of the first to third interfaces (F1, F2, F3) are modified, and the interfacial bonding strength may be improved.

[0222] That is, as the display panel according to one embodiment of the present invention includes surface-treated interfaces for the connecting wire (WL), it can increase not only the bonding strength between the main connecting wire (WLm) and the auxiliary connecting wire (WLs), but also the bonding strength between the connecting wire (WL) and the base layer (400) and the bonding strength between the connecting wire (WL) and the protective layer (300). The display panel according to one embodiment of the present invention can maintain the airtightness of the display panel more efficiently through a surface treatment process.

[0223] FIG. 16a is a schematic perspective view of an electronic device (1000) including a display panel according to one embodiment of the present invention, and FIG. 16b is a schematic block diagram of an electronic device (1000) including a display panel (1) according to one embodiment of the present invention.

[0224] Referring to FIG. 16a, the electronic device (1000) can be freely deformed in three dimensions and can provide a three-dimensional image surface through the display area (DA). The statement that the electronic device (1000) can be freely deformed in three dimensions is distinguished from the operation of an electronic device having a rollable display panel, such as when a part of the rolled-up display area is visible to the user, and then another part of the rolled-up display area is unfolded so that the entire display area is visible to the user (or when the entire unfolded display area is visible to the user, and then the display area is rolled up so that only a part of the display area is visible to the user). The electronic device (1000) according to embodiments of the present invention may exhibit a deformation such as the area of ​​the entire display area (DA) increasing or decreasing again as the electronic device (1000) is deformed in the x direction, y direction, and / or z direction.

[0225] Referring to FIG. 16b, the electronic device (1000) may include a processor (1100), memory (1200), input module (1300), display module (1400), power module (1500), built-in module (1600), and external module (1700). According to one embodiment, at least one of the above-described components may be omitted from the electronic device (1000), or one or more other components may be added. According to one embodiment, some of the above-described components (e.g., built-in module (1600)) may be integrated into another component (e.g., display module (1400)).

[0226] The processor (1100) can execute software to control at least one other component (e.g., a hardware or software component) of an electronic device (1000) connected to the processor (1100) and can perform various data processing or operations. According to one embodiment, as at least part of the data processing or operations, the processor (1100) can store commands or data received from other components (e.g., an input module (1300), a sensor module (1610), or a communication module (1730)) in a volatile memory (1210), process the commands or data stored in the volatile memory (1210), and store the resulting data in a non-volatile memory (1220).

[0227] The processor (1100) may include a main processor (1110) and an auxiliary processor (1120). The main processor (1110) may include at least one of a central processing unit (1111, CPU) and an application processor (AP). The main processor (1110) may further include at least one of a graphic processing unit (1112, GPU), a communication processor (CP), and an image signal processor (ISP). The main processor (1110) may further include a neural processing unit (1113, NPU). The neural processing unit is a processor specialized for processing artificial intelligence models, and the artificial intelligence model may be generated through machine learning. The artificial intelligence model may include a plurality of artificial neural network layers. An artificial neural network may be a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), a deep Q-network, or a combination of two or more of the above, but is not limited to the examples described above. In addition to the hardware structure, the artificial intelligence model may include a software structure, either additionally or substantially. At least two of the processing unit and processor described above may be implemented as a single integrated configuration (e.g., a single chip), or each may be implemented as an independent configuration (e.g., multiple chips).

[0228] The auxiliary processor (1120) may include a controller (1121). The controller (1121) may include an interface conversion circuit and a timing control circuit. The controller (1121) receives a video signal from the main processor (1110), converts the data format of the video signal to match the interface specifications with the display module (1400), and outputs video data. The controller (1121) may output various control signals required for driving the display module (1400).

[0229] The auxiliary processor (1120) may further include data processors (e.g., data processing circuits), such as a data conversion circuit (1122), a gamma correction circuit (1123), and a rendering circuit (1124). The data conversion circuit (1122) receives image data from the controller (1121) and can compensate the image data so that the image is displayed at a desired brightness according to the characteristics of the electronic device (1000) or the user's settings, or can convert the image data to reduce power consumption or compensate for afterimages. The gamma correction circuit (1123) can convert image data or gamma reference voltage, etc. so that the image displayed on the electronic device (1000) has desired gamma characteristics. The rendering circuit (1124) receives image data from the controller (1121) and can render the image data by considering the pixel arrangement of the display panel (1) applied to the electronic device (1000). At least one of the data conversion circuit (1122), gamma correction circuit (1123), and rendering circuit (1124) may be integrated into another component (e.g., main processor (1110) or controller (1121)). In one embodiment, the auxiliary processor (1120) may be integrated into the data driver (1430).

[0230] The memory (1200) can store various data used by at least one component of the electronic device (1000) (e.g., a processor (1100) or a sensor module (1610)) and input or output data for commands related thereto. The memory (1200) may include at least one of a volatile memory (1210) and a non-volatile memory (1220).

[0231] The input module (1300) can receive commands or data to be used for components of the electronic device (1000) (e.g., processor (1100), sensor module (1610) or sound output module (1630)) from outside the electronic device (1000) (e.g., user or external electronic device (2000)).

[0232] The input module (1300) may include a first input module (1310) into which commands or data are input from a user and a second input module (1320) into which commands or data are input from an external electronic device (2000).

[0233] The first input module (1310) may include a microphone, a mouse, a keyboard, or a pen (e.g., a passive pen or an active pen). The first input module (1310) may include mechanical input means or touch input means, such as a button, a dome switch, a jog wheel, a jog switch, etc., located on the rear or side of the electronic device (1000). The touch input means may include a touchscreen layer of the display panel (1).

[0234] The second input module (1320) can be connected to various types of external electronic devices (2000) connected to the electronic device (1000) via wired or wireless connection. According to one embodiment, the second input module (1320) may include a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, an SD card interface, or an audio interface. The second input module (1320) may include a connector capable of physically connecting the electronic device (1000) to the external electronic device (2000), for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector). The electronic device (1000) can perform appropriate control related to the connected external electronic device (2000) in response to the external electronic device (2000) being connected to the second input module (1320).

[0235] The display module (1400) provides information visually to the user. The display module (1400) may include a display panel (1), a scan driver (1420), and a data driver (1430).

[0236] The display panel (1) displays (outputs) information processed by the electronic device (1000). The display panel (1) can display information on the execution screen of an application running on the electronic device (1000), or UI (User Interface) and GUI (Graphic User Interface) information based on the execution screen information.

[0237] The scan driver (1420) may be mounted on the display panel (1) as a driving chip. Alternatively, the scan driver (1420) may be formed directly on the display panel (1). For example, the scan driver (1420) may include an ASG (Amorphous Silicon TFT Gate driver circuit), an LTPS (Low Temperature Polycrystalline Silicon) TFT Gate driver circuit, or an OSG (Oxide Semiconductor TFT Gate driver circuit) embedded in the display panel (1). The scan driver (1420) receives a control signal from the controller (1121) and outputs scan signals to the display panel (1) in response to the control signal.

[0238] The display panel (1) may further include a light emission control driver. The light emission control driver outputs a light emission control signal to the display panel (1) in response to a control signal received from the controller (1121). The light emission control driver may be formed separately from the scan driver (1420) or may be integrated into the scan driver (1420).

[0239] The data driver (1430) receives a control signal from the controller (1121), converts the image data into an analog voltage data voltage in response to the control signal, and then outputs the data voltages to the display panel (1).

[0240] The data driver (1430) may be integrated with some components of the auxiliary processor (1120). For example, the data driver (1430) may be provided as a timing controller embedded driver integrated circuit (Timing controller embedded driver IC) including a controller (1121).

[0241] The data driver (1430) may be mounted on the display panel (1) as a driving chip. Alternatively, the data driver (1430) may be formed directly on the display panel (1). If the scan driver (1420) and the data driver (1430) are formed directly on the display panel (1), the display panel (1) may effectively be a display module (1400).

[0242] The power module (1500) supplies power to the components of the electronic device (1000). The power module (1500) may include a battery that charges the power voltage. Additionally, the power module (1500) is provided with a connection port, and the connection port may be included in a second input module (1320) to which an external charger that supplies power for charging the battery is connected. Alternatively, the power module (1500) may include a wireless power transmission and reception member so that the battery can be charged wirelessly. The wireless power transmission and reception member may include a plurality of coil-shaped antenna radiators. The power module (1500) may include a PMIC (power management integrated circuit). The PMIC supplies optimized power to each of the components of the electronic device (1000).

[0243] The electronic device (1000) may further include an internal module (1600) and an external module (1700). The internal module (1600) may include a sensor module (1610), an antenna module (1620), and an audio output module (1630). The external module (1700) may include a camera module (1710), a light module (1720), and / or a communication module (1730).

[0244] The sensor module (1610) may include touch electrodes of the touchscreen layer of the display panel (1) and a touch sensor driver. The sensor module (1610) may detect input by the user's body or input by a pen and generate an electrical signal or data value corresponding to the input. The sensor module (1610) may include at least one of a touch sensor (1611), a biosensor (1612), and a strain sensor (1613).

[0245] The touch sensor (1611) can generate data values ​​corresponding to coordinate information of input by the user's body (e.g., finger, etc.) or input by a pen. The touch sensor (1611) can generate data values ​​of a change in capacitance, a change in pressure, or an electromagnetic change resulting from the input.

[0246] The biosensor (1512) can generate data values ​​that recognize a part of the user's body (e.g., fingerprint, iris, face, etc.) or generate data values ​​corresponding to body information (e.g., blood pressure, water content, heart rate, body composition, etc.). The biosensor (1512) can use an optical method, an ultrasonic method, or a capacitive method.

[0247] The strain sensor (1613) may include layers, patterns, or wirings in which a measurable physical quantity changes according to the stretching of the display panel (1). For example, the strain sensor (1613) may include layers, patterns, or wirings in which pressure, resistance, and / or capacitance changes due to the stretching of the display panel (1). In another embodiment, the strain sensor (1613) may include an optical layer or optical pattern in which transmittance and / or reflectance changes due to the stretching of the display panel (1).

[0248] Based on the change in physical quantity due to the stretching of the display panel (1) measured by the strain sensor (1613), the electronic device (1000) can improve the quality of the image implemented on the display panel (1) or control the display panel (1). The control operation of the display panel (1) may include, for example, displaying an operation image for protecting the display panel (1), cutting off the voltage for driving the display panel (1), or stopping the stretching operation of the display panel (1).

[0249] In one embodiment, at least one of a touch sensor (1611), a biosensor (1612), or a strain sensor (1613) may be embedded in the display panel (1). For example, at least one of the touch sensor (1611), the biosensor (1612), or the strain sensor (1613) may be formed through a process that is continuous with the process of forming the pixel driving circuit and / or light-emitting element of the display panel (1). As a result, the display panel (1) may function as one of the input modules (1300) providing an input interface between the electronic device (1000) and the user, and simultaneously function as a display module (1400) providing an output interface between the electronic device (1000) and the user.

[0250] In one embodiment, at least two of the touch sensor (1611), biosensor (1612), and strain sensor (1613) may be formed to be integrated into a single sensing panel through the same process. In one embodiment, the sensing panel may be positioned between the display panel (1) and the window cover positioned on the front of the display panel (1), but the present invention is not limited thereto.

[0251] The antenna module (1620) may include one or more antennas for transmitting a signal or power to the outside or receiving it from the outside. According to one embodiment, the communication module (1730) may transmit a signal to an external electronic device or receive it from an external electronic device through an antenna suitable for a communication method. The antenna pattern of the antenna module (1620) may be integrated into one component of the display module (1400) (e.g., a display panel (1)) or a biosensor (1612), etc.

[0252] The sound output module (1630) is a device for outputting sound signals to the outside of the electronic device (1000), and can output sound data received from the communication module (1730) or stored in the memory (1200) in call signal reception, call mode or recording mode, voice recognition mode, broadcast reception mode, etc. The sound output module (1630) can output sound signals related to functions performed in the electronic device (1000) (e.g., call signal reception sound, message reception sound, etc.). The sound output module (1630) may include a receiver and a speaker. At least one of the receiver and the speaker may be a sound generating device attached to the rear of the display panel (1) to vibrate the display panel (1) and output sound. The sound generating device may be a piezoelectric element or a piezoelectric actuator that contracts and expands according to an electric signal, or an exciter that generates magnetic force using a voice coil to vibrate the display panel (1).

[0253] The camera module (1710) can capture still images and video. According to one embodiment, the camera module (1710) may include one or more lenses, image sensors, or image signal processors. The camera module (1710) may further include an infrared camera capable of measuring the presence or absence of a user, the location of the user, the user's gaze, etc.

[0254] The light module (1720) can use light from a light source to output a signal to indicate the occurrence of an event or provide light for image acquisition. Here, examples of event occurrences may include receiving a message, receiving a call signal, a missed call, an alarm, a schedule notification, receiving an email, or receiving battery charge capacity information notifications. The light module (1720) may include a light-emitting diode or a xenon lamp. The light module (1720) may emit single-color or multiple-color light toward the front or rear of the electronic device (1000). The light module (1720) may operate in conjunction with the camera module (1710) or operate independently.

[0255] The communication module (1730) can support the establishment of a wired or wireless communication channel between an electronic device (1000) and an external electronic device (2000), and the performance of communication through the established communication channel. The communication module (1730) may include one or all of a wireless communication module such as a cellular communication module, a short-range wireless communication module, or a GNSS (global navigation satellite system) communication module, and a wired communication module such as a LAN (local area network) communication module or a power line communication module. The communication module (1730) can transmit and receive wireless signals over an internet network using at least one of WLAN (Wireless LAN), Wi-Fi (Wireless-Fidelity, Wi-Fi® is a registered trademark of the non-profit organization Wi-Fi Alliance), Wi-Fi® (Wireless Fidelity) Direct, and DLNA (Digital Living Network Alliance) technology. Additionally, the communication module (1730) can support short-range communication using at least one of the following technologies: Bluetooth (Bluetooth®, a registered trademark of Bluetooth Sig, Inc., located in Kirkland, Washington, USA), RFID (Radio Frequency Identification), infrared communication (Infrared Data Association; IrDA), UWB (Ultra Wideband), ZigBee® (Zigbee®, a registered trademark of CONNECTIVITY STANDARDS ALLIANCE, located in Davis, California, USA), NFC (Near Field Communication), Wi-Fi® (Wireless-Fidelity), Wi-Fi Direct® (Wi-Fi Direct®, a registered trademark of the non-profit organization Wi-Fi Alliance), and Wireless USB (Wireless Universal Serial Bus).The various types of communication modules (1730) described above may be implemented as a single chip or as separate chips.

[0256] FIGS. 17a to 17i are schematic perspective views illustrating embodiments of an electronic device including a display panel according to one embodiment of the present invention.

[0257] Referring to FIG. 17a, a display panel according to one embodiment of the present invention can be utilized in a wearable electronic device (1000A) that can be worn on a part of a user's body. The wearable electronic device (1000A) may include a body part (3110) and a display part (3120) provided in the body part (3110). The display panel according to embodiments of the present invention can be used as the display part (3120) of the wearable electronic device (1000A). As illustrated in FIG. 17a, the wearable electronic device (1000A) may be modified. In one embodiment, it can be used as a smart watch or a smartphone depending on the user's choice.

[0258] FIG. 17b illustrates a medical electronic device (1000B). In one embodiment, the medical electronic device (1000B) may include a body portion (3210) and a light-emitting portion (3220). A display panel according to embodiments of the present invention may be used as the light-emitting portion (3220) of the medical electronic device (1000B). The light-emitting portion (3220) may emit light of a specific wavelength band (e.g., infrared, visible light, etc.) to the patient's body. In one embodiment, the body portion (3210) may have a stretchable fiber material and may have a structure that can be worn on the user's body.

[0259] FIG. 17c illustrates an educational electronic device (1000C). In one embodiment, the educational electronic device may include a display unit (3320) provided within a body unit (3310). The display unit (3320) may utilize a display panel according to embodiments of the present invention. The display unit (3320) may provide images such as a sea with waves, a snow-covered mountain, or a volcano with flowing lava, wherein the display unit (3320) may extend in the height direction (e.g., z-direction) to reflect the height of the waves, mountain, or volcano. In some embodiments, a portion of the display unit (3320) may sequentially vary in height along the direction of the lava flow to show the movement of the lava in three dimensions. The educational electronic device (1000C) may include a plurality of pins (or stroke units, 3330) arranged on the back of the display unit (3320) so that the display unit (3320) extends in the height direction. The pins (3330) can be implemented to move along a third direction (e.g., z direction or -z direction) so that the image displayed on the display unit (3320) has a three-dimensional height. FIG. 17c describes an educational electronic device (1000C), but its use is not limited as long as it provides a certain image information.

[0260] FIGS. 17d and FIGS. 17e illustrate the use of a display panel in a wearable electronic device (1000D-1, 1000D-2), such as a smart watch.

[0261] In one embodiment, as illustrated in FIG. 17d, the display panel corresponding to the display unit (3320) of the electronic device (1000D-1) can be stretched three-dimensionally, so it can provide various haptic information to the user in addition to visual information through images. In one embodiment, the electronic device (1000D-1) can provide haptic information such as Braille markings for the visually impaired or tactile stimulation linked to images by using a plurality of pins (or stroke unit, 3330) placed below the display unit (3320). Since the display panel forming the display unit (3320) can be stretched three-dimensionally, it can provide the aforementioned haptic information to the user. The electronic device (1000D-1) may include a body part (3310) comprising a housing (3314) in which a display panel forming a display part (3320) and pins (or stroke part, 3330) are housed, and a frame (3312) that can be coupled to the housing (3314) with the display panel in between. In some embodiments, the frame (3312) may be formed integrally with the housing (3314).

[0262] The electronic device (1000D-2) of FIG. 17e may include a body part (3310) as in FIG. 15d and a display part (3320) that is housed in the body part (3310) and can provide visual information. In some embodiments, the display panel corresponding to the display part (3320) may include a dome-shaped display part (3320) because it is stretchable in three dimensions. In one embodiment, the display panel may be assembled on a dome-shaped body frame during the manufacturing process of the electronic device (1000D-2), and since the display panel is stretchable in three dimensions, it may be assembled in a stretched state along the shape of a hemispherical body frame.

[0263] FIG. 17f illustrates that in one embodiment of the present invention, another electronic device (1000E) includes a robot. The robot can recognize movement or objects using a camera module (3470) and can display a predetermined image to a user through a display unit (3420, 3430).

[0264] As some embodiments, display panels according to one embodiment of the present invention can be assembled to a body frame having a hemispherical shape because they can be extended in various directions as described above, and thus the robot may include a hemispherical display unit (3420, 3430).

[0265] FIG. 17g illustrates a vehicle display device (1000F) as another electronic device in one embodiment of the present invention. The vehicle display device (1000F) may include a cluster (3510), a Center Information Display (CID) (3520), and / or a co-driver display (3530). Since the display panel according to the embodiment of the present invention can be extended in various directions, it can be used for the cluster (3510), the Center Information Display (CID) (3520), and / or the co-driver display (3530) without being constrained by the shape of the vehicle's internal frame.

[0266] FIG. 17g illustrates the cluster (3510), the Center Information Display (CID) (3520), and / or the co-driver display (3530) being separated, but the invention is not limited thereto. In another embodiment, two or more selected from the cluster (3510), the Center Information Display (CID) (3520), and the co-driver display (3530) may be connected as a single unit.

[0267] In some embodiments, the vehicle display device (1000F) may include a button (3540) capable of displaying a predetermined image. Referring to the enlarged view of FIG. 17g, the hemispherical button (3540) may include an object (3542) that provides a sense of use of the button while moving in the z-direction or -z-direction, and a display panel placed on the object (3542). In some embodiments, if the object (3542) has a three-dimensionally rounded surface, the display panel may also have a three-dimensionally rounded surface.

[0268] FIG. 17h illustrates that an electronic device according to one embodiment of the present invention is an electronic device (1000G) for advertising or display. In some embodiments, the electronic device (1000G) for advertising or display may be installed on a fixed structure (3610), such as a wall or a column. If the structure (3610) includes an uneven surface as shown in FIG. 17h, the electronic device (1000G) for advertising or display may also be placed along the uneven surface of the structure (3610). In some embodiments, the electronic device (1000G) for advertising or display may be installed on the structure (3610) using a heat shrink film or the like.

[0269] FIG. 17i illustrates that an electronic device (1000H) according to one embodiment of the present invention is a controller. The controller may include image-type buttons. For example, the controller may include first to third button areas (3720, 3730, 3740) in which a portion of the display portion (3710) protrudes in the z-direction or protrudes in the -z-direction (or is recessed in the z-direction). In some embodiments, the first and third button areas (3720, 3740) may protrude in the z-direction, and the second button area (3730) may protrude in the -z-direction (or be recessed in the z-direction).

[0270] The present invention has been described with reference to the embodiments illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims.

Claims

1. A base layer comprising first regions and a second region surrounding each of the first regions; A pixel circuit layer comprising pixel circuits and insulating layers disposed on the base layer and disposed in the first regions; Light-emitting diodes disposed on the pixel circuit layer and electrically connected to each of the pixel circuits; and A display panel comprising: a connecting wire comprising a structure in which a main connecting wire including a two-dimensional nanostructure and an auxiliary connecting wire including a one-dimensional nanostructure and a zero-dimensional nanostructure are stacked, electrically connecting pixel circuits arranged adjacently among the pixel circuits above; 2. In Paragraph 1, A display panel in which the two-dimensional nanostructure of the main connecting wire comprises at least one of a nanoflake, a nanosheet, or a nanoplate.

3. In Paragraph 1, A display panel comprising at least one of a nanowire, a nanofiber, a nanotube, a nanorod, or a nanobelt, wherein the one-dimensional nanostructure of the auxiliary connecting wiring described above comprises a nanowire, a nanofiber, a nanotube, a nanorod, or a nanobelt.

4. In Paragraph 1, A display panel in which the zero-dimensional nanostructure of the above auxiliary connecting wiring comprises nanoparticles.

5. In Paragraph 1, A display panel comprising the above two-dimensional nanostructure, the above one-dimensional nanostructure, and the above zero-dimensional nanostructure, wherein the two-dimensional nanostructure, the above one-dimensional nanostructure, and the above zero-dimensional nanostructure comprise a metal-based nanostructure.

6. In Paragraph 5, A display panel comprising: the above-described two-dimensional nanostructure including silver nanoflakes (Ag nanoflake), the above-described one-dimensional nanostructure including silver nanowires (Ag nanowire), and the above-described zero-dimensional nanostructure including silver nanoparticles (Ag nanoparticle).

7. In Paragraph 1, The above auxiliary connecting wiring comprises a mixture of the above one-dimensional nanostructure and the above zero-dimensional nanostructure, a display panel.

8. In Paragraph 1, A display panel comprising: a first auxiliary connecting wire disposed on the main connecting wire and including the first dimensional nanostructure; and a second auxiliary connecting wire disposed on the first auxiliary connecting wire and including the zero dimensional nanostructure.

9. In Paragraph 1, A display panel further comprising a conductive line that is in direct contact with the auxiliary connecting wire and connects the pixel circuits and the connecting wire.

10. In Paragraph 1, The above auxiliary connecting wire is placed on the above main connecting wire, and A display panel comprising a third auxiliary connecting wire that is positioned below the main connecting wire, comprises a material different from that of the main connecting wire and the auxiliary connecting wire, and further comprises a carbon nanostructure.

11. In Paragraph 1, The above auxiliary connecting wire is placed on the above main connecting wire, and The above connecting wiring is, A third auxiliary connecting wire disposed below the main connecting wire and comprising a two-dimensional carbon nanostructure; and Further comprising a fourth auxiliary connecting wire disposed below the third auxiliary connecting wire and including a one-dimensional carbon nanostructure; A display panel in which the third auxiliary connecting wire and the fourth auxiliary connecting wire each comprise a material different from the main connecting wire and the auxiliary connecting wire.

12. In Paragraph 1, A display panel in which the interface where the main connecting wire and the auxiliary connecting wire meet is surface-treated by polymer treatment or plasma treatment.

13. In Paragraph 1, The above main connecting wire and the above auxiliary connecting wire further include the same elastic polymer material, and A display panel in which the above base layer comprises the same material as the elastic polymer material of the above connecting wire.

14. A base layer comprising first regions and a second region surrounding each of the first regions; A first pixel circuit layer disposed on any one of the first regions of the base layer and comprising transistors and insulating layers; A second pixel circuit layer disposed on another first region among the first regions of the base layer, comprising transistors and insulating layers; A first light-emitting diode disposed on the first pixel circuit layer and electrically connected to the transistor of the first pixel circuit layer; A second light-emitting diode disposed on the second pixel circuit layer and electrically connected to the transistor of the second pixel circuit layer; and A display panel comprising: a main connecting wire and an auxiliary connecting wire, each comprising a nanostructure of a different dimension, for electrically connecting the transistor of the first pixel circuit layer and the transistor of the second pixel circuit layer.

15. In Paragraph 14, The above main connecting wiring includes a two-dimensional nanostructure, and A display panel comprising at least one of a nanoflake, a nanosheet, or a nanoplate, wherein the above-described two-dimensional nanostructure.

16. In Paragraph 14, The above auxiliary connecting wiring is a one-dimensional nanostructure comprising at least one of a nanowire, nanofiber, nanotube, nanorod, and nanobelt, or A display panel comprising at least one of a zero-dimensional nanostructure including a nanoparticle.

17. In Paragraph 14, A display panel in which the main connecting wire and the auxiliary connecting wire comprise the same metal but different nanostructured materials.

18. In an electronic device including a display panel, The above display panel is, A base layer comprising first regions and a second region surrounding each of the first regions; A pixel circuit layer comprising pixel circuits and insulating layers disposed on the base layer and disposed in the first regions; Light-emitting diodes disposed on the pixel circuit layer and electrically connected to each of the pixel circuits; and An electronic device comprising: a connecting wire comprising a structure in which a main connecting wire comprising a two-dimensional nanostructure and an auxiliary connecting wire comprising a one-dimensional nanostructure and a zero-dimensional nanostructure are stacked, and which electrically connects pixel circuits arranged adjacently among the pixel circuits above.

19. In Paragraph 18, The above two-dimensional nanostructure comprises at least one of a nanoflake, a nanosheet, or a nanoplate, and The above one-dimensional nanostructure comprises at least one of a nanowire, nanofiber, nanotube, nanorod, or nanobelt, and The above zero-dimensional nanostructure is an electronic device comprising nanoparticles.

20. In Paragraph 18, An electronic device in which the two-dimensional nanostructure of the main connecting wire and the one-dimensional nanostructure and zero-dimensional nanostructure of the auxiliary connecting wire comprise the same metal.

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