Devices and methods involving diamond-based thermal management in semiconductor-circuit devices

Abstract

Exemplary methods of the present disclosure are directed to: growing a diamond layer by using a mold that is used to structure the diamond layer so that it conforms to a circuit device. The circuit device has a heat-sink side and another side to connect with a signal and power routing redistribution region, and the method further includes: planarizing one or two surfaces of the diamond layer to realize a surface roughness (on one or both sides) that is sufficient to set a thermal boundary resistance (e.g., less than 20 m2K / GW and / or less than 50 nm RMS); applying a gap-filling thermal interface material (TIM) layer to fill gaps along the surface(s); and positioning a heat sink on the heat-sink side of the circuit device, wherein the surface roughness of the diamond layer and the gap-filling TIM layer are cooperatively arranged to facilitate transfer of heat from the circuit device into the heat sink.

Description

DEVICES AND METHODS INVOLVING DIAMOND-BASED THERMAL MANAGEMENT IN SEMICONDUCTOR-CIRCUIT DEVICESBACKGROUND(0001] Aspects of the present disclosure are related generally to the field of semiconductor devices and, more particularly, to management of heat generated by active circuits of semiconductor devices.

[0002] As electronic devices become increasingly powerful and compact, managing heat dissipation becomes a critical challenge. High-Performance Computing (HPC) systems and Silicon (Si) 3D High-Intensity (3DHI) devices are particularly susceptible to thermal issues due to their high-power densities. Effective thermal management is essential to maintain performance and reliability. Diamond heat spreaders have emerged as a promising solution to address these thermal challenges. Diamond, with its exceptional thermal conductivity (exceeding 2000 Watts per meter-Kelvin (W / mK)), can efficiently spread and dissipate heat, reducing the maximum chip temperature significantly. This capability is crucial for Si 3DHI and HPC systems, where localized hotspots can lead to non-uniform temperature distributions and potential device failure. By integrating diamond heat spreaders, these systems can achieve higher power and speed operations while maintaining thermal stability.

[0003] Recent studies have demonstrated the effectiveness of diamond heat spreaders in various applications. For instance, a hybrid Si micro-cooler combined with a diamond heat spreader was shown to reduce the maximum chip temperature by over forty percent compared to conventional cooling methods. Additionally, diamond heat spreaders have been successfully applied to Gallium Nitride (GaN) devices among others, showcasing their potential in high-power electronics. In order to address the self-heating issue in semiconductor devices, diamond heat spreaders are designed that can be applied at different stages of the manufacturing process including, as examples, chiplet-level, package-level, and board-level.

[0004] Specific aspects of the present disclosure are directed to overcoming the selfheating issue in semiconductor devices in the above and other contexts.SUMMARY OF VARIOUS ASPECTS AND EXAMPLES

[0005] Various examples / embodiments presented by the present disclosure are directed to issues such as those addressed above and / or others which may become apparent from the following disclosure. For example, some of these disclosed aspects are directed to methods and devices that use or leverage from using a mold to grow a diamond (or diamond-like) layer, planarizing a surface of the diamond layer, and patterning the diamond layer to provide a conformal cover.

[0006] In certain examples, methods of the present disclosure are directed to: growing a diamond (or diamond-like) layer by using a mold that conforms to a circuit device having a heat-sink side and having another side to connect with a signal and power routing redistribution region (e.g., in which the low-temperature diamond dielectric material exhibits breakdown strength greater than 5 MV / cm); planarizing a surface of the diamond layer to realize an RMS surface roughness that is less than 50 nm; applying a gap-filling thermal interface material (TIM) layer to fill gaps along at least one of the heat-sink side and the other side; and positioning a heat sink on the heat-sink side of the circuit device, wherein the RMS surface roughness of the diamond layer and the gap-filling TIM layer are cooperatively arranged to facilitate transfer of heat from the circuit device into the heat sink. For example, the TIM layer can be implemented to include multiple sublayers of differing viscosities to accommodate non-planar geometries.[0007 J In more specific examples that may build on the above-discussed aspects, the step of growing the diamond (or diamond-like) layer includes using a low temperature diamondgrowth (e.g., in a range from 20 to 400°C or (ultra-low) from 20 to 300°C), wherein the mold is a carrier substrate. It is noted that growth at temperatures below 150°C yields unexpected crystalline continuity suitable for back-end-of-line (BEOL) integration. The gap-filling TIM layer has an average thickness in a range from 1 to 200 um, and / or the method further includes transferring the diamond layer as grown from the carrier substrate to be positioned for conforming to at least one portion of the circuit device not facing the signal and power routing redistribution region.

[0008] In certain other examples which may also build on the above-discussed aspects, the step of applying a gap-filling TIM layer includes using the gap-filling TIM layer to fill gaps along each of the heat-sink side of the circuit device and the other side of circuit device, and the signal and pow er routing redistribution region may include low-temperature-grown diamond dielectric material in each of a plurality of layers that form at least part of the signal and power routing redistribution region. In specific examples, the molded diamond (ordiamond-like) layer is a low-temperature poly crystalline diamond characterized by growth temperature below 400°C, grain size less than 500 nm, and / or Raman peak broadening relative to high-temperature CVD diamond.[00091 In other more specific examples related to the above methodology and / or devices (also useful in building on one or more of the above aspects), the step of planarizing includes planarizing a first surface of the diamond (or diamond-like) layer to realize an RMS surface roughness at the first surface that is less than 50 nm, and planarizing a second surface of the diamond layer, on a side of the diamond layer opposite the first surface, to realize an RMS surface roughness at the second surface that is less than 50 nm.

[0010] In yet other examples, the present disclosure is directed to an apparatus comprising: a circuit device; a diamond-like layer; a gap-filling thermal interface material (TIM) layer; and a heat sink. The circuit device has a heat-sink side and another side to connect with a signal and power routing redistribution region. The diamond-like layer is shaped to conform to the circuit device, and includes a thermally-conductive material and at least one planarized surface to provide a surface roughness corresponding to a certain thermal boundary' resistance. The gap-filling TIM layer is to fill gaps along at least one of the heatsink side and another side of the circuit device. The heat sink is positioned on the heat-sink side of the circuit device, wherein the surface roughness of the diamond-like layer and the gap-filling TIM layer are cooperatively arranged to facilitate transfer of heat from the circuit device into the heat sink.[0011 ) The above discussion is not intended to describe each aspect, embodiment or every implementation of the present disclosure. The figures and detailed description that follow also exemplify various embodiments.BRIEF DESCRIPTION OF FIGURES

[0012] Various example embodiments, including experimental examples, may be more completely understood in consideration of the following detailed description and in connection with the accompanying drawings, each in accordance with the present disclosure, in which:

[0013] FIGs. 1A, IB, 1C and ID are side-view diagrams of IC packages, each according to certain exemplary aspects of the present disclosure and showing how a thermal interface material (TIM) layer may be used to conform to a circuit device (e.g., with one or more chiplets) of the corresponding IC package;

[0014] FIGs. 2A, 2B and 2C are side-view diagrams of IC packages, each according to certain exemplary aspects of the present disclosure and showing diamond material grown over and conforming to a circuit device (e g., with one or more chiplets) of the corresponding IC package;

[0001] FIGs. 3A-3F are diagrams of IC packages, each according to certain exemplary aspects of the present disclosure and with FIGs. 3A, 3B and 3C being side-view depictions to show how as-grown diamond material on a carrier may be formed for conforming to a circuit device of the IC package, and with FIGs. 3D, 3E and 3F showing the formed diamond material transferred over, for conformance with, chiplets of the circuit device;

[0016] FIGs. 4A and 4B are diagrams of board-level IC package structures, each according to certain exemplary aspects of the present disclosure and each with a diamond mold used to conform to a circuit device of the corresponding IC package structure;

[0017] FIGs. 5A and 5B are side-view diagrams of IC packages, each according to certain exemplary aspects of the present disclosure and depicting how a diamond-composite material may be formed and used to conform to a circuit device (e g., with one or more chiplets) of the corresponding IC package, with FIG. 5A showing the diamond-composite material as a single layer and FIG. 5B showing the diamond-composite material as multiple layers;

[0018] FIGs. 6A, 6B and 6C are respective SEM images of example experimental diamond-composite TIM grown in an ultra-low temperature range and on uneven surfaces;

[0019] FIGs. 7A and 7B are respective bar graphs, also for example experimental diamond-composite TIM grown according to the present disclosure, with FIG. 7A depicting use of conventional thermal paste and FIG. 7B depicting use of exemplary thermal paste according to aspects of the present disclosure;

[0020] FIGs. 8A and 8B are simulation diagrams also showing comparisons as in FIGs. 7 A and 7B, with conventional thermal paste as in FIG. 8 A, and with thermal paste according to the present disclosure;

[0021] FIGs. 9A and 9B are graphs, each showing plots of simulation data to depict temperature-versus-distance parameters for two sets of thermal paste according to experimental aspects of the present disclosure versus another type of conventional thermal paste;

[0022] FIGs. 10A and 10B are diagrams depicting a board-level demonstrative example of a semiconductor device, according to certain exemplary experimental aspects of the present disclosure, using a thermal dielectric heat spreading (HS) material, with FIG. 10A as a generalized schematic and FIG. 10B as a graph showing plots of simulation data;

[0023] FIG. 11 A is a diagram depicting another board-level demonstrative example of a semiconductor device, according to certain exemplary experimental aspects of the present disclosure; and

[0024] FIG. 1 IB is a graph showing plots of simulation data for the semiconductor device depicted in FIG. 11 A.

[0025] While various embodiments discussed herein are amenable to modifications and alternative forms, aspects thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the disclosure to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the disclosure including aspects defined in the claims. In addition, the term “example” as used throughout this application is only by way of illustration, and not limitation.DETAILED DESCRIPTION

[0026] Aspects of the present disclosure are believed to be applicable to a variety of different types of apparatuses, systems and methods involving devices characterized at least in part by diamond-like material used as athermal conductor for managing and / or transferring heat from hot spots of circuit devices with active circuitry (e.g., field-effect transistors, “FET”). Certain aspects of the present disclosure are believed to be particularly beneficial when the diamond-like material is at least predominantly a diamond material and when used in connection with High-Performance Computing (HPC) systems and Silicon (Si) 3D High-Intensity (3DHI) devices, which are particularly susceptible to thermal issues due to their high-power densities. While the present disclosure is not necessarily limited to such aspects, an understanding of specific examples in the following description may be understood from discussion in such specific contexts.[00271 Accordingly, in the following description various specific details are set forth to describe specific examples presented herein. It should be apparent to one skilled in the art, however, that one or more other examples and / or variations of these examples may be practiced without all the specific details given below. In other instances, well known features have not been described in detail so as not to obscure the description of the examples herein. For ease of illustration, the same connotation and / or reference numerals may be used in different diagrams to refer to the same elements or additional instances of the same element. Consistent with the above aspects, such a manufactured device or method of such manufacture may involve aspects presented and claimed in U.S. Provisional Application Serial No. 63 / 740,197 filed on December 30, 2024 (CMAT.102P1), to which priority’ is claimed. To the extent permitted, such subject matter is incorporated by reference in its entirety' generally and to the extent that further aspects and examples (such as experimental and / more-detailed embodiments) may be useful to supplement and / or clarity’. Although aspects and features may in some cases be described in individual figures, it will be appreciated that features from one figure or embodiment can be combined with features of another figure or embodiment even though the combination is not explicitly shown or explicitly described as a combination.

[0028] Exemplary aspects of the present disclosure are directed to methods in which: a diamond layer is grown by using a mold for conforming to a circuit device, wherein on one side of the circuit device there is a heat-sink side and on another side there are connections with a signal and power routing redistribution region. The methods further include planarizing one or two surfaces of the diamond layer to realize an RMS surface roughness(on one or both sides) in a range from a few to several nm (e.g., from 10 to 20 nm) with an upper bound in the range being not greater than 50 nm; and applying a gap-filling thermal interface material (TIM) layer to fill gaps along the surface(s). Finally, a heat sink is positioned on the heat-sink side of the circuit device, such that the RMS surface roughness of the diamond layer and the gap-filling TIM layer are cooperatively arranged to facilitate transfer of heat from the circuit device into the heat sink. In a more specific example, diamond is grown directly against portions (e.g., exposed sides and top) of the circuit device, therein forming an in-situ bonded interface with thermal resistance less than 10% of a conventional TIM-only interface. Optionally, this diamond growth may be directly against a surface of the circuit device (e.g., disposed directly against bare silicon, fused silica glass, gorilla glass, GaN, or HBM surfaces) without an intervening dielectric.

[0029] Accordingly, in different example embodiments, diamond-like thermally conductive material is molded, for example, using a carrier substrate to help grow the material so as to have a certain shape for device conformance by at least one portion of the material and / or by using manufacturing processing (e g., patterning, etching, etc.) to effect a desired conformance shape after the diamond-like thermally conductive material is grown. In each instance, gaps on at least one side of the diamond-like thermally conductive material are removed by a planarization step to realize a certain degree of minimal roughness (e.g., less than about 50 nm) and / or a thin thermally -conductive material (e.g., applied in the form of a paste, a gel, or a curable resin, a composite, or a combination of two or more thereof) is applied to fill in such gaps. This type of conformal processing may be carried out on one or more sides (e.g. opposing sides) of the diamond-like thermally-conductive material, with such diamond-like thermally-conductive material being poly crystalline, nanocrystalline, or single-crystal diamond, wherein the cooperative arrangement involving this material sets a certain thermal boundary’ resistance (e.g., less than 20 m2K / GW and / or less than 50 nm RMS).

[0030] A ”diamond-like ‘ material, as used in this disclosure, is exemplified by or refers to one or more from a class of thermally conductive solids that exhibit thermal conductivities in the range of approximately 400 to 1800 W / m K, which is substantially higher than conventional packaging dielectrics and metals used in semiconductor assemblies. The term encompasses several options: poly crystalline synthetic diamond films grown at low temperature for conformal coverage; nanocrystalline or amorphous carbon composites with mixed sp2 / sp3bonding that achieve intermediate conductivity; isotopically enriched single-cry stal diamond w ith conductivities approaching the upper bound of the range; and / ordiamond-based composites or analogous ceramics such as cubic boron nitride, boron arsenide, silicon carbide, and aluminum nitride, which can be engineered to fall within the stated conductivity7window. Collectively, these “diamond-like” materials provide the necessary' balance of manufacturability', integration compatibility, and high thermal transport to serve as effective heat spreaders or dielectric layers in advanced semiconductor packaging.[0031 j In certain implementations, aspects of the present disclosure are directed to an IC-type apparatus in one or more stages during or after formation of an IC package. In certain post-processing (or post-manufacture) stages, the IC-type apparatus is in the form of chipl et- level device, a package-level device, or a board-level device. In each instance, the IC-type apparatus comprises: a heat-sink side; and a circuit device (e.g., including an active region such as in a transistor) that has one side to face the heat-sink side and another side to connect with a signal and power routing redistribution region. The IC-ty pe apparatus further comprises a molded diamond layer, and a gap-filling thermal interface material (TIM) layer. The molded diamond layer is configured to conform to the circuit device and it has a planarized surface (e.g., corresponding to an RMS surface roughness that is less than 50 nm). The gap-filling TIM layer is used to fill gaps along the heat-sink side and / or the other side. One or multiple TIM layers in such examples may be anisotropic in composition to direct heat preferentially toward the heat-sink side. Moreover, the heat sink may be configured to be positioned on the heat-sink side of the circuit device, wherein the RMS surface roughness of the diamond layer and the gap-filling TIM layer are cooperatively arranged to facilitate transfer of heat from the circuit device into the heat sink.

[0032] In different examples of the present disclosure, the structured (e.g.. molded or over-grown) diamond-hke thermally conductive layer is shaped to conform via toleration of gaps not greater than approximately 100 pm In more specific examples, such toleration of gaps is not greater than approximately 50 pm, or not greater than approximately 10 pm (e.g., depending on thermal conductivity' requirements and / or coarseness of the interface surface).

[0033] In more specific configurations of the present disclosure, the apparatus may include a Si region (“Si interposer”) integrated between a set of one or more chiplets and a package substrate. This interposer is to support the inter-chiplet signal and power routing redistribution layer (RDL) region and various related signals down to the package substrate. The interposer may include a plurality of layers (e.g., from 3 to 8 layers). For conductors, each such layer may include Cu routing that is insulated by interlayer dielectric (ILD) material. To effectively manage the heat in a standard HPC chiplet, low-temperature-grown diamond (LTD) is integrated as an interlayer dielectric (Di-ILD) in the RDL portion of theinterposer. Compared to known porous SiCOH (in which the TC < 1 W / mK) using state-of-the-art HPC ILDs, this type of Di-ILD approach, according to the present disclosure, realizes an improved TC by more than 1000X (wherein TC is for thermal conductivity), thereby allowing for significantly improved heat spreading from both the hotspots in the chiplet circuitry as well as high current density in the RDL where heat accumulates and causes failure. Additionally, more specific implementations according to the present disclosure integrate diamond-through-Si-vias (Di-TSV) to provide a high thermal conductivity path through the interposer to the package substrate.(0034] FIGs. 1A-1D are side-view diagrams of IC packages, each according to certain exemplary aspects of the present disclosure and showing how a circuit device at the chiplet- level (e.g., with one or more chiplets) may be implemented as part of a corresponding IC package. Consistent with each of these similarly-annotated depictions, a chiplet-level device 100 in FIG. 1A (100’, 100” and 100”' in FIGs. IB- ID) includes a set of one or more chiplets 105 (e.g., Chiplet #1, Chiplet #2, etc.). One approach for realizing such a chiplet- level device 100 in FIG. 1 A is by building the chiplet-to-chiplet communications signal and redistribution layers 110, overlapping with the interposer region 115, on top of the substrate 120 (e.g.. Si-diamond composite substrate such as poly crystalline or single-crystalline). In conventional approaches, this substrate is often implemented using glass and / or Si-only interposers adjacent to the chiplets; whereas in this example, a thermal interface material (TIM) layer 125 is configured to conform to each chiplet (e.g., #1 and #2) of the circuit device. Conductors 112 are used to electrically connects circuit nodes of the chiplets 105 with conductors in the signal and redistribution layers 110. At the bottom of the depicted apparatus, the substrate 120 is mounted, via solder balls 135 (in such an exemplary ball grid array package), to a printed circuit board (PCB) 140, and on the opposite side a heat sink 135 is secured to a side of the TIM layer 125 opposite the side that conforms to the chiplets.

[0035] As also shown in each of FIGs. 1A, IB, IC and ID, some parts of the interposer region 115 can be replaced by diamond-through-Si-vias (Di-TSVs) of different densities (e.g., 100-2000 via / mm2) and of any various geometries (e.g., cylindrical, rectangular, cone, triangular, etc.). Each of FIGs. 1A and IB are implemented with the same type of the interposer region 115, being Si based with Cu conductors for signal / routing paths, which are insulated by ILD material 145. In FIG. IC, the amount of Si in the interposer region 115 is significantly reduced, being replaced by additional ILD material around the Cu signal / routing paths.

[0036] In FIG. ID, the vast majority or all of Si-based interposer has been replaced using diamond, so to form a diamond-based interposer region. In one example, the thickness of the diamond interposer is between 50 and 500 pm, and copper-through-diamond-vias (Cu-TDVs) are used for signal / power routings with 1-50 pm diameter and the density of 100-2000 via / mm2

[0037] In each of FIGs. 1A-1D, the particular processing for conforming the TIM layer over the chiplets (e.g., by growing diamond over the chipl ets, and / or by patterning and etching to fit the chiplets) is apparent in the post-manufactured apparatus. For example, if etching is used to fit the chiplets, by removing the TIM layer from the heat-sink-facing side of the chiplet(s), the etched surface of the TIM layer would be apparent from conventional imaging (e.g., from scanning electron microscopy or atomic force microscopy).

[0038] Similarly, in the event that diamond-like material (e.g., at least predominantly poly crystalline diamond) is grown over the chiplets without use of etching to fit the chiplets, this approach would also be apparent by use of such imaging. FIGs. 2A-2C are presented to illustrate such an alternative method, also in accordance with aspects of the present disclosure. In each of FIGs. 2A-2C, a package-level apparatus is depicted similarly to that shown in the respective views of FIGs. 1A-1D. Using FIG. 2A to depict the general aspects shown in each of FIGs. 2A-2C, the package-level apparatus is implemented as a ball-grid array package that includes, from top to bottom: a heat sink 210, a TIM layer 220, as-grown diamond-like material 230, a set of chiplets 240, interposer region 250, a package substrate 260, solder balls 270, and a PCB 280.

[0039] As in representative FIG. 2A, an exemplary method for forming the apparatus is by growing low-temperature polycrystallme diamond 230 on top of the set of chiplets 240, and then attaching the heat sink 210 (or alternatively, a housing or casing member that may be less ideal for heat dissipation but is also considered as a heat sink). For the material 230, the temperature for diamond growth is in a range from 200 °C to 450 °C, with more precise temperature control being based on the thermal budget of the set of chiplets 240 (the material 230 is depicted in FIGs. 2A-2C as LTD referring to exemplary low-temperature diamond). After the growth, the TIM layer 220 is formed by covering the heat-sink-facing surface of the diamond-like material 230 with a thermal interface material, such as a thermal paste, w hich is effective to cover gaps between the diamond-like material 230 and the heat sink 210.Accordingly, the material 230 provides conformal coverage, by such low-temperature growth, over the set of chiplets 240 to optimize thermal conductivity from the active regions in each chiplet into the material 230, and the TIM layer 220 further facilitates thermalconductivity for heat transfer from the material 230 into the heat sink 210. In specific experimental examples according to the present disclosure, the gap-filling TIM layer fills gaps along at least one of the heat-sink side and the redistribution side, and in some example embodiments, both sides.

[0040] FIGs. 2B and 2C illustrate variations, also in accordance with exemplary aspects of the present disclosure, of the method discussed in connection with FIG. 2A. For example, in FIG. 2B, after growing low-temperature poly crystalline diamond on top of the set of chiplets, the surface of the diamond is polished to eliminate a degree of roughness and minimization of gaps (e.g., to realize a roughness below a certain RMS value of 30 nm, 50 nm and 75 nm in different examples). In one such approach, after the polishing step, there is no TIM layer used (in contrast to TIM layer 220 of FIG. 2 A) before attaching the heat sink. As a slight further variation, after growing the low-temperature material on top of the set of chiplets and after the polishing step, a thermal paste may be selectively used to form a TIM layer or segments of a TIM layer (not shown in FIGs. 2B and 2C).

[0041] The structure depicted in FIG. 2C is also different from that shown in FIGs. 2A and 2B in that, in place of the set of chiplets, the circuit device being conformally covered by the material 230 includes a system-on-chip (SoC) 290 and a high-bandwidth memory (HBM) circuit 295.

[0042] It is appreciated that careful inspection of such post-processing apparatuses enables one to discern that certain processing steps used to form the polished and / or etched surfaces of the material 230 (e.g., as conforming over the circuit device). As one discernment approach, reverse engineering may be used in this regard to remove the TIM layer(s) from the chiplets, and thereafter conventional imaging (as noted above) may be used to reveal whether such polishing and / or etching was used in creating the surface(s) such as at upper- and / or lower-facing sides of the surface material 230. As examples, such surfaces processed as such would result in a polished surface (e.g., as apparent by the surface’s smoothness and / or tips of diamond grains being truncated as by a certain polishing technique and / or by a certain etching technique. It is also noted that in other example implementations, also consistent with the examples depicted in FIGs. 1A-1D and FIGs. 2A-2C, the conformal-covered circuit device may include a variety of circuitry types including any one type or a combination of types (e.g., chiplet(s), SoC, high-bandwidth memory (HBM) circuit, etc.)

[0043] Yet another variation, also in accordance with exemplary aspects of the present disclosure, includes patterning and etching to effect the diamond-like material conformallycovering the circuit device. FIGs. 3A-3F illustrate an example of such a process for making and applying diamond mold at the package level.

[0044] More particularly, FIGs. 3A-3F are diagrams of IC packages, each according to certain exemplary aspects of the present disclosure, showing how diamond-like material (e.g., poly crystalline diamond) can be processed to provide a diamond-like material that conformally covers a circuit device, in the form of differently-sized circuit types. In FIG. 3A, the as-grown diamond is shown after being grown on a carrier 305 (e.g., while shown as being a Si-based carrier substrate, in other examples, the carrier substrate is SiC, Quartz, Glass, Fused Silica, or Gorilla Glass). The growth temperature of the as-grown diamond 310 need not be a low temperature as the diamond is not necessarily grown directly on the circuit device. In FIG. 3B, the upper surface 315, on the side opposite the carrier 305, is shown after a polishing step Next, as shown in FIG. 3C, patterning and etching steps are depicted, with the patterning step being used to define the portion of upper surface (315) to be exposed for the removal of the selected portions of the as-grown diamond 310 via the etching step. As an example, the etching step can be implemented by way of chemical etching. Such chemical etching may be implemented using, for example, a dry etching method as exemplified by any of various etching methods. Such etching methods may include, as examples, high-density plasma-based etching methods, as may be applied to etch through polycrystalline diamond, and including for example, inductively-coupled plasma-reactive ion etching (ICP-RIE), using reactive gases such as oxygen, hydrogen, or fluorine compounds. Alternatively, for planarizing such etching methods may include chemical-mechanical polishing, plasma- assisted etching, and / or ion-beam smoothing.

[0045] FIG. 3C shows versions of the polished diamond after being structured (e.g., patterned and etched) to conform to the targeted circuit device (e.g., chiplets), once being removed from the carrier 305. To the left of FIG. 3C, one etched surface 320 is shown for chiplet #1 of FIG. 3D, and another etched surface 330 is shown for chiplet #2 of FIG. 3D. To the right of FIG. 3C. an alternative version of the carrier 320 is shown with the carrier 320 and the structured material 340 being separated (e.g., by cutting the carrier 320) into two distinct parts 340A and 340B for the respective conformal fittings over the chiplets shown in FIG 3D.

[0046] FIGs. 3D, 3E and 3F show the formed diamond material transferred over, for conformance with, the chiplets (#1 and #2) of the circuit device. This step of transferring includes, for example, detaching the diamond layer by mechanical, chemical, or laser-assisted release.

[0047] In FIG. 3D, with the chiplets mounted to the interposer and / or package substrate 342, a first TIM (#1) layer 350 is formed by application of a thermal material (e.g., paste or liquid) directly over each of the chiplets. With the carrier removed from the structured polished diamond material 340, after formation of the TIM layer 350, the structured polished diamond material (as shown as respective versions at the left or to the right of FIG. 3C) is situated over the TIM-layered top of the chiplets. In FIG. 3E, in certain more specific embodiments, a second TIM layer 352 may be formed, by similar application as with the first TIM layer, on the side of the structured polished diamond material 340 which was previously against the carrier 305. A heat sink is then secured (e.g., using the second TIM layer 352 as an intervening layer to fill gaps) to the outwardly -facing side of the structured polished diamond material 340. FIG. 3F shows two final stages of the packaging apparatus, with the stages respectively showing the structured polished diamond material 340 just before being secured between the interposer / substrate 342 and the heat sink 352 (depicted on the left of FIG. 3E) and after being secured between the interposer / substrate 342 and the heat sink 352 (depicted on the right of FIG. 3E).

[0048] This type of conformal-fitting device-covering method can be implemented in both package-level as in FIGs. 3D-3F, and also in board-level integration as in FIGs. 4A-4B. First, high quality low-temperature or high-temperature diamond was grown on a Si carrier substrate. Then the surface of the diamond was polished to roughness below 30 nm RMS value. Then using etching and milling techniques a diamond mold was fabricated to the exact dimensions and shape of the chiplets. The side w alls of the diamond mold can be slanted at any angle or has different etch planes to fit any complicated geometry . Before applying the diamond mold on top, a thermal interface material (TIM #1) was used to fill the gaps and non-idealities of the mold. Then the diamond mold was placed on top of the chiplets followed by another layer of thermal interface material (TIM #2). At the end, the heat sink or the metallic case were attached to TIM #2.

[0049] FIGs. 4A and 4B are diagrams of board-level IC package structures, each according to certain exemplar}' aspects of the present disclosure and each with a diamond mold used to conform to a circuit device of the corresponding IC package structure. In experimental efforts, successfully carried out in accordance w ith the example embodiments discussed herein, the above types of methods have been implemented (e.g.. using a single layer, and in some instances, multiple layers, of TIM) at both package-level integration as in FIGs. 3E and 3F, and board-level integration as in FIG. 4A and 4B.

[0050] In these experimental efforts and as shown in FIG. 4 A. TIM#1 and TIM#2 were used before and after diamond mold attachment as applied to respective sides for the interface with the diamond (or diamond-like) material. In examples involving the experimental efforts, the thickness of the TIM layers (TIM #1 and TIM #2) varies within a range from 10 pm to 300 pm. In one such example, the diamond mold was applied to mobile SoC chips between the SoC and mobile case / chassis as shown in FIG. 4A. In another example and as shown in FIG. 4B, the diamond mold was applied to GPU chips by covering the sidewalls and top surfaces (e.g., using TIM) before attaching the heat sink.

[0051] Three steps in the upper portion of FIG. 4A show an exemplary’ manner for forming the board-level integration of FIG. 4A for a SOC as part of a motherboard (e.g., for smartphone or GPU) or part of an Al accelerator board. In the encircled step "T”, a first TIM layer is formed (on the upper side of the circuit device) by an injected application of a thermal paste from a syringe. In the encircled step “2”, the structured diamond (or diamondlike) material is secured over the top and sides of the circuit device (in this example being a A18_SOC type circuit device). In the encircled step “3”, a second TIM layer is formed on the upper side of the structured diamond (or diamond-like) material by another injected application of a thermal paste also from a syringe.

[0052] Similarly, three steps in the upper portion of FIG. 4B show: as encircled step “1”, an exemplary manner for forming the board-level integration of FIG. 4B for a general processing unit (GPU), for example, as might be used in another type of circuit as part of a PCB (as a form of an IC board that may include, for example, embedded diamond vias for vertical heat spreading). In the encircled step “1” of FIG. 4B, a first TIM layer is formed on the upper side of the GPU-type circuit device, by an injected application of athermal paste from a syringe. In the encircled step “2”, the structured diamond (or diamond-like) material is show n as being secured over the top and sides of the GPU-type circuit device. In the encircled step “3”, a second TIM layer is formed on the upper side of the structured diamond (or diamond-like) material by another injected application of athermal paste, also from a syringe.

[0053] Also according to certain exemplary aspects of the present disclosure, FIGs. 5A and 5B depict two types of fabrication processes for implementing a diamond composite thermal interface material (TIM) in which the diamond is grown using an ultra-low temperature, with the exact temperatures being limited by the tolerance or budget afforded by the circuit device (e.g., as chiplets #1 and #2). FIG. 5A showing three side-view diagrams (respectively corresponding to three processing stages) of an IC package having a single layerdiamond composite and FIG. 5B having a multiple-layer diamond composite, with each diamond-composite material being formed to conform with the shape (along the top and sides) of a circuit device. In these examples of FIG. 5 A and FIG. 5B, the circuit device is shown with two chiplets although different numbers of chiplets and / or types of circuits may be alternatively used.

[0054] More particularly, for the single-layer process of FIG. 5 A, the first depiction (far left) depicts a diamond deposition step in which 5 nm to 100 nm of diamond is formed by depositing (or seeding) diamond along the sides and over the top of the chiplets for growth at an ultra-low temperature (e.g., in a range from 20 °C to 300 °C). The second depiction (middle) depicts an application of a gap-filling material (e.g., AIN, SiC, SiCh, A12O32, SiNx, graphite, resin, and / or polymer) to provide a thin layer (from a few to several nm to an order of mm) over the previously -formed diamond and also along the sides and over the top, again to fill any gaps for a subsequent attachment at the interface involving the previously -formed diamond. The third depiction (right) depicts a bonding and annealing process (at low or high pressure), which may be performed in an atmosphere of a gas or plasma (e.g., H2, O2, CO2, Ar, N2, Air, or any combination thereof) and at a temperature in a range from 100 °C to 400 °C.

[0055] In certain example implementations according to the present disclosure, diamond growth at one or more temperatures in the range of 20 °C - 300 °C is advantageous, because each packaging material has a limited thermal budget that cannot withstandhigher-temperature CVD processes as would be conventionally practiced. As examples: silicon chiplets and SoCs are not subjected to temperatures above approximately 300 °C to protect backend-of-line interconnects and low-k dielectrics; glass, quartz, and fused silica carriers can tolerate somewhat higher temperatures themselves but are bonded to temperature-sensitive dies and redistribution layers that cannot tolerate such higher temperatures; similarly, silicon interposers with copper RDLs risk diffusion and delamination above approximately 250 °C - 300 °C; organic package substrates such as BT resin or epoxy composites soften above approximately 250 °C; and board-level PCBs with FR-4 laminates and solder joints degrade or reflow above approximately 200 °C - 220 °C. By keeping diamond deposition (e.g., growth) within 20 °C - 300 °C, the process remains compatible across chiplet-. package-, and board-level assemblies, thereby enabling conformal integration of diamond heat spreaders without damaging surrounding circuitry while still delivering the thermal conductivity advantage essential for high-performance computing and 3DHI devices.

[0056] The multiple-layer process of FIG. 5B tracks closely with the single-layer process of FIG. 5 A, except that before the application of a gap-filling material as in the middle depiction of FIG. 5 A, the diamond deposition step (corresponding to the left depiction of FIG. 5A) is repeated until a desirable thickness is realized by an effective stacking of layers. For example, the thickness may be in a range from 5 nm to 100 pm, and in some example embodiments in a range from 20 nm to 10 pm for BEOL compatibility. In a more specific example of this type, the TIM layer is implemented to include multiple sublayers of differing viscosities to accommodate non-planar geometries.

[0057] For both FIGs. 5A and 5B, a final step may include securing a structured diamond-like material (e.g., post-mold or carrier) or heat sink over the TIM layer. It is appreciated that while this methodology uses Si technology as an example material in various contexts, the methodology is also compatible with and beneficial for thermal management of semiconductor devices and integrated circuits that use GaN and / or G iO- technologies.

[0058] In such experimental examples, such a diamond composite TIM was successfully used to provide a lower thermally -resistive interface between the diamond mold and both top surfaces of the heat sink and chiplets. As shown in each of FIGs. 5 A and 5B, the TIM layer conformally covers the chiplet (e.g., or the upper portion of the diamond mold if such structured diamond-like material is also used). In a particular one of these experimental examples, a single layer of TIM consists of a diamond layer (in a thickness range from 5 nm to 100 um, porous or fully coalesced), a dielectric layer (deposited with ALD, PECVD, LPCVD, or sputtering with a thickness range from 5 nm to 100 um) followed by an optional annealing stage in H2, O2, CO2, Ar, N2, or Air at low or high pressures with a temperature between 100 and 400° C.

[0059] Consistent with each of the examples of the present disclosure, the structured (e.g., grown over or molded) diamond layer can be configured to provide a conformal fitting to the circuit device topography within a few7to several nm deviation (e.g., various experimental examples provide deviation ranges corresponding respectively to ±7 nm, ±10 nm, ±15 nm and ±20) and in such examples, the apparatus achieves junction-to-ambient thermal resistance reduction of at least 20% compared to copper-only interfaces. Moreover, in certain of examples in such experimental efforts, the plurality of chiplets are arranged in a 2.5D or 3D stacked configuration.

[0060] Consistent with the above-discussed examples of the present disclosure, experimental efforts have been conducted (some simulated) successfully to confirm these disclosed advantageous aspects, as supported by the depictions show n from FIGs. 6A-6Cthrough FIGs. 11A-1 IB. For example, FIGs. 6A, 6B and 6C are respective SEM images of example experimental diamond-composite TIM grown in an ultra-low temperature range and on uneven surfaces, in contrast to aspects (e.g., polished low -temperature-grow th surface) according to the present disclosure.

[0061] FIGs. 7A and 7B are bar graphs, also for example experimental diamondcomposite TIM grown according to the present disclosure, with FIG. 7A depicting temperature measurements using a conventional type of thermal paste (e.g., consistent with Furmark® 3d PC thermal paste). In comparison, FIG. 7B depicts temperature measurements using an example thermal paste developed according to aspects of the present disclosure.

[0062] FIGs. 8A and 8B are simulation diagrams also showing comparisons as in FIGs. 7A and 7B. More specifically, FIG. 8B, which corresponds to thermal paste being used as in FIG. 7B and according to certain exemplary7experimental aspects of the present disclosure, depicts simulation data under 1000W workload for a single chip, in which simulated hot spots are added based on 150 W / cm2 power density. The simulations demonstrate hot spot temperatures in a range of 90 °C - 100 °C for conventional thermal paste (FIG. 8A), and having dropped to less than 60 °C when using such thermal paste according to the present disclosure (FIG. 8B). Further, the simulations demonstrate that hot spot temperatures at the Si chip edge are reduced by approximately 50% as consistent with the temperature bar map on the right of FIGs. 8A-8B.

[0063] FIGs. 9A and 9B are graphs, each showing plots of simulation data to depict temperature-versus-distance parameters for tw o sets of thermal paste according to experimental aspects of the present disclosure versus another type of conventional thermal paste. More specifically, such conventional thermal paste corresponds to an example commercially-available thermal paste, GB 200 available from Blackwell®. The two lower- temperature plots in each of FIGs. 9A and 9B depict use of thermal paste developed according to the present disclosure, with such thermal paste annotated as “1stGen’" and “2ndGen” in FIG. 9A and "‘3rdGen” and “4thGen” in FIG. 9B.

[0064] FIGs. 10A and 10B are diagrams depicting a board-level demonstrative example of a semiconductor device, using a thermal dielectric heat spreading (HS) material according to certain exemplary experimental aspects of the present disclosure. FIG. 10A is a generalized schematic that shows the device having an Si substrate, an array of experiment- emulated hotspots and the HS material. FIG. 10B is a graph showing plots of simulation data to depict temperature-versus-distance parameters for the semiconductor device without the HS material and with the HS material.

[0065] FIG. 11 A is a diagram depicting another board-level demonstrative example of a semiconductor device, according to certain exemplary experimental aspects of the present disclosure, using a thermal dielectric HS material at the bottom layer and with through-Si vias (TSVs) extending upwardly from the HS material to distribute heat from the hot spots as simulated via a test heater on a top layer.

[0066] FIG. 1 IB is a graph showing plots of simulation data to depict temperature versus power density for the semiconductor device depicted in FIG. 11 A, with the illustrated uppertemperature plot showing the control-temperature hotspot and with the illustrated lower- temperature plot showing the effect of the HS material.

[0067] As examples, the specification describes and / or illustrates aspects useful for implementing the claimed disclosure by way of various circuits or circuitry which may be illustrated as or using terms such as blocks, modules, device, system, unit, controller, optical elements and / or other circuit-related depictions and materials and / or layers (e.g., materials and / or layers which are semiconductive, conductive, metallic or semi- metallic). Such circuits (or circuitry), materials and the like are used together with other elements to exemplify how certain embodiments may be carried out in the form of structures, steps, functions, operations, activities, etc. For example, in certain of the embodiments discussed herein, one or more modules may be discrete logic circuits or programmable logic circuits configured and arranged for implementing these operations / activities, as may be earned out in the approaches shown in the figures.

[0068] It is recognized and appreciated that as specific examples, the abovecharacterized figures and discussion are provided to help illustrate certain aspects (and advantages in some instances) which may be used in the manufacture of such structures and devices. These structures and devices include the exemplary structures and devices described in connection with each of the figures as well as other devices, as each such described embodiment has one or more related aspects which may be modified and / or combined with the other such devices and examples as described hereinabove may also be found in the above-referenced Provisional.

[0069] The skilled artisan would also recognize various terminology as used in the present disclosure by way of their plain meaning. As examples, the Specification may describe and / or illustrates aspects useful for implementing the examples by way of various semiconductor materials / circuits which may be illustrated as or using terms such as layers, blocks, modules, device, system, unit, controller, and / or other circuit-type depictions. Such semiconductor and / or semiconductive materials (including portions of semiconductorstructure) and circuit elements and / or related circuitry may be used together with other elements to exemplify how certain examples may be carried out in the form or structures, steps, functions, operations, activities, etc. As a more specific example relevant to the abovedisclosed examples involving the management of heat in a circuit device, such terminology (e.g.. “circuit device’7) refers to semiconductor circuitry in which circuitry has one or more active regions that heats up during operation (e g., as in a FET). It would also be appreciated that terms to exemplify' orientation, such as upper / lower, lefit / right, top / bottom and above / below, may be used herein to refer to relative positions of elements as shown in the figures. It should be understood that the terminology is used for notational convenience only and that in actual use the disclosed structures may be oriented different from the orientation shown in the figures. Thus, the terms should not be construed in a limiting manner. As other examples, reference to a noun in the singular refers to one from among one or more of, unless otherwise indicated (e.g., “a layer” in various contexts is the same as referring to “at least one layer”), and reference to “example” is not intended to be limiting (e.g., “example” and “nonlimiting example” are synonymous). Further, methods as exemplified in the figures may involve steps carried out in various orders, with one or more aspects of the embodiments herein retained, or may involve fewer or more steps.

Claims

What is claimed is:

1. A method comprising:forming a diamond-like layer, as a thermally conductive material, to conform to a circuit device on a heat-sink side of the circuit device, wherein another side of the circuit device is to connect with a signal and power routing redistribution region;planarizing at least one surface of the diamond-like layer to realize a surface roughness corresponding to a certain thermal boundary resistance;applying a gap-filling thermal interface material (TIM) layer to fill gaps along at least one of the heat-sink side and the other side of the circuit device; andpositioning a heat sink on the heat-sink side of the circuit device, wherein the planarized diamond-like layer and the gap-filling TIM layer are cooperatively arranged to facilitate transfer of heat from the circuit device towards the heat sink.

2. The method of claim 1, wherein the planarizing realizes an RMS surface roughness less than 75 nm, and the certain thermal boundary resistance is not greater than 20 m2K / GW.

3. The method of claim 2, wherein the RMS surface roughness is less than 50 nm.

4. The method of claim 2, wherein the RMS surface roughness is less than 30 nm.

5. The method of claim 1, wherein the diamond-like layer is low-temperature poly crystalline diamond grown at a temperature below 300 °C.

6. The method of claim 1, wherein the TIM layer comprises multiple sublayers of differing viscosities to accommodate non-planar geometries.

7. The method of claim 1 , wherein the step of forming includes growing the diamond-like layer by using a mold, and the gap-filling TIM layer is applied as at least one of: a paste, a gel, a resin, and a composite.

8. The method of claim 1, wherein the step of forming a diamond-like layer includes using a mold as a carrier substrate, and wherein the gap-filling TIM layer has an average thickness in a range from 1 to 200 um; and the method further includes transferring thediamond-like layer as grown from the carrier substrate to be positioned for conforming, via the mold, to at least one portion of the circuit device not facing the signal and power routing redistribution region.

9. The method of claim 1, wherein the step of forming a diamond-like layer includes using at least part of the circuit device to shape the diamond-like layer, and the step of grow ing diamond includes growing diamond directly against said at least part of the circuit device, and therein forming an in-situ bonded interface with a thermal resistance being improved by at least two fold.10 The method of claim 1, wherein the step of applying a gap-filling TIM layer includes using the gap-filling TIM layer to fill gaps along each of the heat-sink side of the circuit device and the other side of circuit device.

11. The method of claim 1, wherein the gap-filling TIM layer is applied as least one of: a paste, a gel, a resin, a curable resin, and a composite.

12. The method of claim 1, wherein the signal and power routing redistribution region includes diamond dielectric material grown at a temperature not to exceed 400 °C in each of a plurality of layers that form at least part of the signal and pow er routing redistribution region, and wherein the diamond dielectric material exhibits breakdown strength greater than 5 MV / cm.

13. The method of claim 1, wherein the step of planarizing includes planarizing a first surface of the diamond-like layer to realize an RMS surface roughness at the first surface that is less than 50 nm, and planarizing a second surface of the diamond-like layer, on a side of the diamond-like layer opposite the first surface, to realize an RMS surface roughness at the second surface that is less than 50 nm.

14. The method of claim 1, wherein the step of growing the diamond-like layer includes using a diamond-growth temperature in a range from 20 to 300°C.

15. The method of claim 1 , wherein the step of applying a gap-filling TIM layer includes using the gap-filling TIM layer to fill gaps along the heat-sink side of the circuit device.

16. The method of claim 1, wherein the step of applying a gap-filling TIM layer includes using the gap-filling TIM layer to fill gaps along the other side of the circuit device.

17. An apparatus comprising:a circuit device having a heat-sink side and having another side to connect with a signal and power routing redistribution region;a diamond-like layer, shaped to conform to the circuit device, including a thermally -conductive material and including at least one planarized surface to provide a surface roughness corresponding to a certain thermal boundary resistance;a gap-filling thermal interface material (TIM) layer to fill gaps along at least one of the heat-sink side and another side of the circuit device; anda heat sink positioned on the heat-sink side of the circuit device, wherein the surface roughness of the diamond-like layer and the gap-filling TIM layer are cooperatively arranged to facilitate transfer of heat from the circuit device into the heat sink.

18. The apparatus of claim 17, wherein the TIM layer has a thickness in a range from 1 pm to 200 pm. wherein the TIM layer has a thickness in a range from 10 pm to 300 pm and is part of a thermal interface integrated in a board-level integration, and the certain thermal boundary resistance is not greater than 20 m2K / GW.

19. The apparatus of claim 17, wherein the diamond-like layer is a low-temperature poly crystalline diamond (LTD), grown via one or more temperatures in a range from 20 to 300 °C and characterized by grain size less than 500 nm and Raman peak broadening relative to high-temperature CVD diamond, wherein the diamond-like layer includes over-grown diamond material shaped to conform via toleration of gap not greater than approximately 100 pm.

20. The apparatus of claim 17, wherein the diamond-like layer is positioned for conforming to at least one portion of the circuit device including chiplets, SoC, or HBM regions not facing the signal and power routing redistribution region.

21. The apparatus of claim 17, further including: one layer of the gap-filling TIM layer situated to fill gaps along the heat-sink side of the circuit device; and another layer of thegap-filling TIM layer situated to fill gaps along the other side of circuit device, wherein at least one of the TIM layers has an anisotropic composition to direct heat preferentially toward the heat-sink side.

22. The apparatus of claim 17. wherein the step of applying a gap-filling TIM layer includes using the gap-filling TIM layer to fill gaps along the other side of circuit device.

23. The apparatus of claim 17, wherein the step of applying a gap-filling TIM layer includes using the gap-filling TIM layer to fill gaps along the heat-sink side of the circuit device.

24. The apparatus of claim 17, wherein the diamond-like layer is integrated as part of an IC-package that includes the circuit device and the signal and power routing redistribution region, wherein the diamond-like layer has a polished low-temperature-growth surface that is directly against a surface of the circuit device and without an intervening dielectric layer.

25. The apparatus of claim 17, wherein the circuit device includes or corresponds to at least one of: a plurality of chiplets, system-on-chip (SoC) package, and high-bandwidth memory (HBM) circuit.

26. The apparatus of claim 17, further including an integrated-circuit (IC) board electrically connected with the circuit device, wherein the diamond-like layer is secured to the IC board at least in part by embedded diamond vias to transfer heat from the circuit device.

27. The apparatus of claim 17, further including an integrated-circuit (IC) board electrically connected with the circuit device, wherein the IC board is one of: a GPU motherboard, a smartphone motherboard, and an Al accelerator board.

28. The apparatus of claim 17, wherein the diamond-like layer is a single-layer or multilayer composite, and the TIM layer has a thickness in a range from 5 nm to 100 um.

29. The apparatus of claim 17. further includinga diamond-like thermally conductive interlayer dielectric (Di-ILD) integrated into the redistribution layers, the Di-ILD having thermal conductivity greater than 1000 W / mK; and a plurality of diamond-through-silicon vias (Di-TSVs) with densities in a range from 100 to 2000 vias / mm2;wherein the circuit device includes at least one chiplet mounted to the package substrate or otherwise secured to or integrated with the signal and power routing redistribution region, and the heat sink is thermally coupled to the at least one chiplet through the diamond-like thermally conductive interlayer dielectric and the plurality of Di-TSVs.

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