Encoding / decoding method and apparatus

Abstract

An encoding / decoding method and apparatus. The encoding method comprises: a first device (e.g., a sending end) determining a first row range on the basis of a code rate for encoding and a first base matrix; shifting the first row range to obtain a second row range; and on the basis of a second base matrix corresponding to the second row range, encoding information to be encoded. In the first basis matrix, the orthogonality between different rows is enhanced as a downward shift progresses (i.e., as a row index increases). The orthogonality of the second base matrix corresponding to the second row range is enhanced with respect to the base matrix corresponding to the first row range. Furthermore, due to enhanced orthogonality, the throughput (e.g., peak throughput) of information transmission can be improved. For example, the peak throughput can reach 100 Gbps.

Description

An encoding / decoding method and apparatus

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202510037581.4, filed on January 7, 2025, entitled “An Encoding / Decoding Method and Apparatus”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of communication technology, and in particular to an encoding / decoding method and apparatus. Background Technology

[0004] Low-density parity-check (LDPC) codes are channel coding schemes very close to the Shannon limit, characterized by high performance and low complexity. They have been selected by the 3rd Generation Partnership Project (3GPP) as the coding and decoding scheme for data channels in 5G communication. Mainstream LDPC codes have a quasi-cyclic (QC) structure, which avoids bad structures such as short cycles and improves code distance by setting the shift amount of each block. The corresponding LDPC code can be represented using a basis matrix. How to use the basis matrix of the LDPC code for encoding is a research direction. Summary of the Invention

[0005] This application provides an encoding / decoding method and apparatus to enhance the orthogonality of the basis matrix used for encoding, thereby improving the throughput (such as peak throughput) of transmitted information.

[0006] Firstly, an encoding method is provided. The executing entity of this method can be a first device (e.g., a terminal device or an access network device), a component within the first device (e.g., a communication module, processor, circuit, chip, or chip system), or a logic module or software capable of implementing all or part of the functions of the first device. The method includes: determining a first row interval based on the encoding code rate and a first base matrix, wherein the first row interval is composed of the indices of some rows contained in the first base matrix; encoding the information to be encoded according to a second base matrix corresponding to a second row interval to obtain encoded information, wherein the second row interval is obtained by shifting the first row interval, and the second base matrix is ​​composed of the rows indicated by the second row interval in the first base matrix.

[0007] Through the above design, the first device (such as the transmitter) determines the first row interval based on the encoding code rate and the first base matrix; the first row interval is shifted to obtain the second row interval; and the information to be encoded is encoded according to the second base matrix corresponding to the second row interval. In the first base matrix, the orthogonality between different rows is enhanced with downward shift (i.e., the row index increases). The second base matrix corresponding to the second row interval has enhanced orthogonality relative to the base matrix corresponding to the first row interval. Furthermore, due to the enhanced orthogonality, read / write conflicts during decoding are reduced, resulting in low decoding latency and high decoding throughput, such as a peak decoding throughput of 100Gbps.

[0008] In one possible implementation, the second row interval is obtained by shifting the first row interval, including: adding a first value to the index of each row indicated by the first row interval to obtain the second row interval; and extracting the rows indicated by the second row interval from the first base matrix to obtain the second base matrix.

[0009] The above design allows us to obtain the second row interval by shifting the first row interval, and further obtain the second basis matrix corresponding to the second row interval. The second basis matrix corresponding to the bit rate can be obtained by shifting (or nesting), which is simple to implement and facilitates hardware implementation.

[0010] In one possible implementation, the second row interval is obtained by shifting the first row interval based on the first sequence, wherein the length of the first sequence is equal to the number of rows contained in the first base matrix, and the elements contained in the first sequence are 0 or 1.

[0011] In one possible implementation, the first value is equal to the difference between the second row value and the first row value, the first row value is the index of the largest row in the first row interval, and the second row value is the index of the largest row in the second row interval.

[0012] In one possible implementation, the method further includes: determining a first row value based on the code rate of the encoding and the number of information columns contained in the first base matrix; and determining a second row value based on the first row value and the first sequence.

[0013] In one possible implementation, the process of determining the second row value based on the first row value and the first sequence satisfies the following: x + y = row'; x + y / 2 = row;

[0014] Where row represents the first row value, row' represents the second row value, x represents the number of elements in the first base matrix from row 1 to row' with a value of 0 in the first sequence, and y represents the number of elements in the first base matrix from row 1 to row' with a value of 1 in the first sequence.

[0015] In one possible implementation, the row index range of the first row interval is 1 to the first row value; the row index range of the second row interval is (second row value - first row value + 1) to the second row value.

[0016] In one possible implementation, the first base matrix or the second base matrix satisfies the following conditions: in the first sequence, when the value of the element corresponding to the i-th row is equal to 1, the column weight of the extended check column corresponding to the i-th row is equal to 2 or 1, and among the two adjacent rows of the i-th row, only one row satisfies the following first condition: the row contains the extended check column associated with the i-th row, where i is an integer greater than zero; wherein, the length of the first sequence is equal to the number of rows contained in the first base matrix, and the elements contained in the first sequence are 0 or 1.

[0017] With the above design, in the adjacent rows of row i (such as row i+1 and row i-1), only one row satisfies the first condition. Row i and the row that satisfies the first condition can be considered to satisfy / maintain codeword nesting, that is, high code rate codeword bits can be used as a subset of low code rate codeword bits, thus having nesting property. All code rates are uniform, and incremental redundancy-hybrid automatic repeat request (IR-HARQ) is supported.

[0018] In one possible implementation, the first basis matrix or the second basis matrix further satisfies the following condition: except for the extended check column, the elements of the i-th row are orthogonal to the elements of the 1-th row that satisfies the first condition.

[0019] Through the above design, the scheme has better orthogonality, fewer read and write conflicts in decoding, and thus lower decoding latency and higher decoding throughput.

[0020] In one possible implementation, the first basis matrix or the second basis matrix further satisfies the following condition: except for the extended check column, the union of the elements of the i-th row and the elements of the 1-th row that satisfies the first condition is the same as the elements of the i'-th row, where i' is an integer less than i.

[0021] In one possible implementation, the first basis matrix or the second basis matrix further satisfies the following condition: when the element in the m-th row and j-th column is 1, the value of m is equal to i, or m is the index of the 1st row that satisfies the first condition, the translation value of the m-th row and j-th column is the same as the translation value of the i'-th row and j-th column, or the two differ by a constant C, where C is independent of the row index and / or column index, and i' is an integer less than i.

[0022] With the above design, the shift value of the m-th row and j-th column is the same as the shift value of the i'-th row and j-th column. The m-th row and j-th column and the i'-th row and j-th column can be considered to satisfy / preserve codeword nesting, that is, the high code rate codeword bits can be used as a subset of the low code rate codeword bits, thus having nesting property, uniform code rates, and supporting incremental redundant retransmission (such as IR-HARQ).

[0023] In one possible implementation, when the value of the first row is row-1, the corresponding second row interval is represented as H. row-1 When the value of the first row is row, the corresponding second row interval is represented as H. row The second row interval H row-1 With the second row interval H row The relationship between them is related to the value of the element corresponding to the i-th row in the first sequence, where i is the interval H in the second row. row-1 The corresponding maximum row index + 1, where i is an integer greater than zero.

[0024] In one possible implementation, when the value of the element corresponding to the i-th row in the first sequence is equal to 0, the second row interval H... row-1 With the second row interval H row The relationship between them satisfies the following: in the second row interval H row-1 Based on the above, add the i-th row to form the second row interval H. row .

[0025] In one possible implementation, when the value of the element corresponding to the i-th row in the first sequence is equal to 1, the second row interval H... row-1 With the second row interval H row The relationship between them satisfies the following: in the second row interval H row-1 Based on this, add the i-th row and the (i+1)-th row, and delete the interval H of the second row. row-1 The first row in the second row constitutes the interval H. row .

[0026] With the above design, regardless of the value of the element corresponding to the i-th row in the first sequence (such as β(i)), the number of rows added each time is 1. For example, when β(i) = 0, 1 row is added (such as the i-th row); when β(i) = 1, 2 rows are added (such as the i-th row and the (i+1)-th row), and one row is deleted (such as H). row-1 The first line in the code is essentially an additional line, thus supporting flexible bitrates that are completely consistent with NR-LDPC.

[0027] Secondly, regarding the decoding side corresponding to the first aspect, and referring to the description of the first aspect, a decoding method is provided. The executing entity of this method can be a second device (e.g., a terminal device or an access network device), a component within the second device (e.g., a communication module, processor, circuit, chip, or chip system), or a logic module or software capable of implementing all or part of the functions of the second device. The method includes: acquiring information to be decoded; determining a first row interval based on the encoded code rate and a first base matrix, wherein the first row interval is composed of the indices of some rows contained in the first base matrix; and decoding the information to be decoded according to a second base matrix corresponding to the second row interval to obtain decoded information, wherein the second row interval is obtained by shifting the first row interval, and the second base matrix is ​​composed of the rows indicated by the second row interval in the first base matrix.

[0028] In one possible implementation, the second row interval is obtained by shifting the first row interval, including: adding a first value to the index of each row indicated by the first row interval to obtain the second row interval; and extracting the rows indicated by the second row interval from the first base matrix to obtain the second base matrix.

[0029] In one possible implementation, the second row interval is obtained by shifting the first row interval based on the first sequence, wherein the length of the first sequence is equal to the number of rows contained in the first base matrix, and the elements contained in the first sequence are 0 or 1.

[0030] In one possible implementation, the first value is equal to the difference between the second row value and the first row value, the first row value is the index of the largest row in the first row interval, and the second row value is the index of the largest row in the second row interval.

[0031] In one possible implementation, the method further includes: determining a first row value based on the code rate of the encoding and the number of information columns contained in the first base matrix; and determining a second row value based on the first row value and the first sequence.

[0032] In one possible implementation, the process of determining the second row value based on the first row value and the first sequence satisfies the following: x + y = row'; x + y / 2 = row;

[0033] Where row represents the first row value, row' represents the second row value, x represents the number of elements in the first base matrix from row 1 to row' with a value of 0 in the first sequence, and y represents the number of elements in the first base matrix from row 1 to row' with a value of 1 in the first sequence.

[0034] In one possible implementation, the row index range of the first row interval is 1 to the first row value; the row index range of the second row interval is (second row value - first row value + 1) to the second row value.

[0035] In one possible implementation, the first base matrix or the second base matrix satisfies the following conditions: in the first sequence, when the value of the element corresponding to the i-th row is equal to 1, the column weight of the extended check column corresponding to the i-th row is equal to 2 or 1, and among the two adjacent rows of the i-th row, only one row satisfies the following first condition: the row contains the extended check column associated with the i-th row, where i is an integer greater than zero; wherein, the length of the first sequence is equal to the number of rows contained in the first base matrix, and the elements contained in the first sequence are 0 or 1.

[0036] In one possible implementation, the first basis matrix or the second basis matrix further satisfies the following condition: except for the extended check column, the elements of the i-th row are orthogonal to the elements of the 1-th row that satisfies the first condition.

[0037] In one possible implementation, the first basis matrix or the second basis matrix further satisfies the following condition: except for the extended check column, the union of the elements of the i-th row and the elements of the 1-th row that satisfies the first condition is the same as the elements of the i'-th row, where i' is an integer less than i.

[0038] In one possible implementation, the first basis matrix or the second basis matrix further satisfies the following condition: when the element in the m-th row and j-th column is 1, the value of m is equal to i, or m is the index of the 1st row that satisfies the first condition, the translation value of the m-th row and j-th column is the same as the translation value of the i'-th row and j-th column, or the two differ by a constant C, where C is independent of the row index and / or column index, and i' is an integer less than i.

[0039] In one possible implementation, when the value of the first row is row-1, the corresponding second row interval is represented as H. row-1When the value of the first row is row, the corresponding second row interval is represented as H. row The second row interval H row-1 With the second row interval H row The relationship between them is related to the value of the element corresponding to the i-th row in the first sequence, where i is the interval H in the second row. row-1 The corresponding maximum row index + 1, where i is an integer greater than zero.

[0040] In one possible implementation, when the value of the element corresponding to the i-th row in the first sequence is equal to 0, the second row interval H... row-1 With the second row interval H row The relationship between them satisfies the following: in the second row interval H row-1 Based on the above, add the i-th row to form the second row interval H. row .

[0041] In one possible implementation, when the value of the element corresponding to the i-th row in the first sequence is equal to 1, the second row interval H... row-1 With the second row interval H row The relationship between them satisfies the following: in the second row interval H row-1 Based on this, add the i-th row and the (i+1)-th row, and delete the interval H of the second row. row-1 The first row in the second row constitutes the interval H. row .

[0042] Thirdly, an encoding method is provided. The executing entity of this method can be a first device (e.g., a terminal device or an access network device), a component within the first device (e.g., a communication module, processor, circuit, chip, or chip system), or a logic module or software capable of implementing all or part of the functions of the first device. The method includes: encoding the information to be encoded according to a first base matrix and a first sequence to obtain encoded information; wherein the first sequence contains at least an i-th segment and an (i+1)-th segment, and the elements contained in the (i+1)-th segment include: the elements contained in the i-th segment and the index of the elements contained in the i-th segment, where i is a positive integer; the length of the first sequence is equal to the number of rows contained in the first base matrix; and the index of the element contained in the i-th segment or the (i+1)-th segment is the index of the corresponding row in the first base matrix.

[0043] Through the above design, the information to be encoded can be encoded based on the first sequence and the first basis matrix. For example, a second basis matrix can be generated based on the first sequence and the first basis matrix; the information to be encoded can then be encoded using the second basis matrix. Since the elements contained in the next segment (e.g., segment i+1) of the first sequence can be composed of the elements contained in its previous segment (e.g., segment i) and the index corresponding to the previous segment, that is, the elements contained in the next segment can be inferred based on the elements contained in the previous segment and the index of the first sequence. Thus, only the elements contained in the first segment of the first sequence and its corresponding index need to be defined. The corresponding device can then infer the elements contained in each segment of the first sequence based on the relationship between the next segment and the previous segment, making the acquisition of the first sequence more flexible and simple.

[0044] In one possible implementation, the number of elements contained in the i-th segment or the (i+1)-th segment is related to the number of core check rows contained in the first base matrix.

[0045] In one possible implementation, the i-th segment contains the index of the element, satisfying the following: (M*2) i-1 +1,M*2 i-1 +2,…,M*2 i )

[0046] Where M represents the number of core check rows contained in the first base matrix.

[0047] In one possible implementation, the elements contained in the (i+1)th segment, including the elements contained in the i-th segment and their indices, satisfy the following: M*2 i-1 +1, θ(M*2) i-1 +1), M*2 i-1 +2, θ(M*2) i-1 +2), ..., M*2 i ,θ(M*2 i )}

[0048] Where M*2 i-1 +1, M*2 i-1 +2, ..., M*2 i θ(M*2) represents the index of the element contained in the i-th segment; i-1 +1), θ(M*2) i-1 +2), …, θ(M*2) i ) represents the elements contained in the i-th segment, and M represents the number of core check rows contained in the first base matrix.

[0049] Fourthly, regarding the decoding side corresponding to the third aspect, and referring to the description of the third aspect, a decoding method is provided. The executing entity of this method can be a second device (e.g., a terminal device or an access network device), a component within the second device (e.g., a communication module, processor, circuit, chip, or chip system), or a logic module or software capable of implementing all or part of the functions of the second device. The method includes: acquiring information to be decoded; decoding the information to be decoded according to a first base matrix and a first sequence to obtain decoded information; wherein the first sequence contains at least an i-th segment and an (i+1)-th segment, and the elements contained in the (i+1)-th segment include: the elements contained in the i-th segment and the index of the elements contained in the i-th segment, where i is a positive integer; the length of the first sequence is equal to the number of rows contained in the first base matrix; and the index of the element contained in the i-th segment or the (i+1)-th segment is the index of the corresponding row in the first base matrix.

[0050] In one possible implementation, the number of elements contained in the i-th segment or the (i+1)-th segment is related to the number of core check rows contained in the first base matrix.

[0051] In one possible implementation, the i-th segment contains the index of the element, satisfying the following: (M*2) i-1 +1,M*2 i-1 +2,…,M*2 i )

[0052] Where M represents the number of core check rows contained in the first base matrix.

[0053] In one possible implementation, the elements contained in the (i+1)th segment, including the elements contained in the i-th segment and their indices, satisfy the following:

[0054] M*2 i-1 +1, θ(M*2) i-1 +1), M*2 i-1 +2, θ(M*2) i-1 +2), ..., M*2 i ,θ(M*2 i )}

[0055] Where M*2 i-1 +1, M*2 i-1 +2, ..., M*2 i θ(M*2) represents the index of the element contained in the i-th segment; i-1 +1), θ(M*2) i-1 +2), …, θ(M*2) i ) represents the elements contained in the i-th segment, and M represents the number of core check rows contained in the first base matrix.

[0056] Fifthly, an apparatus is provided capable of implementing the methods described in the first or third aspect above. For example, the apparatus includes modules, units, or components corresponding to the methods described in the first or third aspect. The modules, units, or components may be implemented in hardware, software, or a combination of hardware and software.

[0057] In one design, the device includes a unit that performs the methods described in the first or third aspect.

[0058] In one design, the device includes a processor for implementing the methods of the first or third aspect described above. Optionally, the device further includes a memory, with the processor coupled to the memory, and the processor for executing computer programs or instructions stored in the memory, causing the device to implement the methods of the first or third aspect described above.

[0059] In one design, the device includes a processor and an interface circuit. The interface circuit is used to receive signals from other devices outside the device and transmit them to the processor, or to send signals from the processor to other devices outside the device. The processor implements the methods of the first or third aspect described above through logic circuits or executing code instructions.

[0060] In one design, the device may be a first device, or a module, unit, or component (e.g., a chip, chip system, circuit, or processor, etc.) that corresponds one-to-one with the method / operation / step / action described in the first or third aspect of the first device, or a device that can be used in conjunction with the first device.

[0061] Sixthly, an apparatus is provided capable of implementing the methods of the second or fourth aspect described above. For example, the apparatus includes modules, units, or components corresponding to the methods described in the second or fourth aspect. The modules, units, or components may be implemented in hardware, software, or a combination of hardware and software.

[0062] In one design, the device includes a unit that performs the methods described in the second or fourth aspect above.

[0063] In one design, the device includes a processor for implementing the methods of the second or fourth aspect described above. Optionally, the device further includes a memory, with the processor coupled to the memory, the processor executing computer programs or instructions stored in the memory, such that the device implements the methods of the second or fourth aspect described above.

[0064] In one design, the device includes a processor and an interface circuit. The interface circuit is used to receive signals from other devices outside the device and transmit them to the processor, or to send signals from the processor to other devices outside the device. The processor implements the methods of the second or fourth aspect described above through logic circuits or executing code instructions.

[0065] In one design, the device may be a second device, or a module, unit, or component (e.g., a chip, chip system, circuit, or processor, etc.) that corresponds one-to-one with the methods / operations / steps / actions described in the second or fourth aspect of the second device, or a device that can be used in conjunction with the second device.

[0066] In a seventh aspect, a computer-readable storage medium is provided, storing a computer program or instructions that, when executed on a computer, cause the computer to implement the methods of any one of the first to fourth aspects described above.

[0067] Eighthly, a computer program product is provided, comprising a computer program or instructions that, when executed by a computer, cause the methods of any one of the first to fourth aspects to be performed.

[0068] A ninth aspect provides a chip including a processor for implementing the methods of any one of the first to fourth aspects described above. Optionally, the chip further includes a memory, the processor being coupled to the memory, the processor executing a computer program or instructions stored in the memory, causing the chip to implement the methods of any one of the first to fourth aspects described above.

[0069] In a tenth aspect, a communication system is provided, comprising: a first communication device and a second communication device; wherein the first communication device is used to implement the method of the first or third aspect described above; and the second communication device is used to implement the method of the second or fourth aspect described above. Attached Figure Description

[0070] Figure 1 is a schematic diagram of a communication system applicable to this application;

[0071] Figure 2 is a schematic diagram of an ORAN system applicable to this application;

[0072] Figure 3 is a schematic diagram of the network element function division and protocol layer structure of an O-RAN device applicable to this application;

[0073] Figure 4 is a schematic diagram of different cyclic shift numbers;

[0074] Figure 5 is a schematic diagram of the basis matrix in LDPC codes;

[0075] Figure 6 is a schematic diagram of the verification matrix;

[0076] Figure 7 is a schematic diagram of the basis matrix structure;

[0077] Figure 8 is a schematic diagram of the matrix regions corresponding to different bit rates;

[0078] Figure 9 is a flowchart of the communication system applicable to this application;

[0079] Figure 10 is a flowchart of the encoding method;

[0080] Figure 11 is a schematic diagram of the first basis matrix;

[0081] Figures 12a and 12b are schematic diagrams of the first row interval and the second row interval, respectively, when the first row value row = 5.

[0082] Figure 13 is a schematic diagram showing the correspondence between the first basis matrix and the first sequence (β sequence);

[0083] Figure 14 is a flowchart of the decoding method;

[0084] Figure 15 is a schematic diagram of the structure of the "first basis matrix" or the "second basis matrix";

[0085] Figures 16a and 16b are schematic diagrams of the first row interval and the second row interval, respectively, when the first row value row = 6.

[0086] Figure 17 is a schematic diagram of the first row interval when the first row value row = 4;

[0087] Figure 18 is a schematic diagram of the second row interval when the first row value row = 7;

[0088] Figure 19 is a schematic diagram of the second row interval when the first row value row = 8;

[0089] Figure 20 is another flowchart of the encoding method;

[0090] Figure 21 is a schematic diagram showing the correspondence between the rows of the first basis matrix and the first sequence;

[0091] Figure 22 is another flowchart of the decoding method;

[0092] Figure 23 is a schematic diagram of the simulation results;

[0093] Figures 24 and 25 are schematic diagrams of the device;

[0094] Figure 26 is a schematic diagram of the chip structure. Detailed Implementation

[0095] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings. The specific operating methods and functional descriptions in the method embodiments can also be applied to the device embodiments or system embodiments.

[0096] In the description of this application, unless otherwise specified, the number of nouns refers to "singular nouns or plural nouns," that is, "one or more." "At least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, or B exists alone, where A and B can be singular or plural. In the textual description of this application, the character " / " generally indicates that the related objects before and after are in an "or" relationship; in the formulas of this application, the character " / " indicates that the related objects before and after are in a "division" relationship. "Including at least one of A, B, or C" or similar expressions can mean: including A; including B; including C; including A and B; including A and C; including B and C; including A, B, and C, where A, B, and C can be singular or plural.

[0097] In the description of this application, the various numerical designations are used for ease of description and are not intended to limit the scope of the embodiments of this application. The order of the process numbers does not imply the order of execution; the execution order of each process should be determined by its function and internal logic. The ordinal numbers such as "first" and "second" used in the embodiments of this application are used to distinguish multiple objects and do not limit the size, order, timing, priority, or importance of the multiple objects.

[0098] In the description of this application, "for indicating" can include both direct indication (or explicit indication) and indirect indication (or implicit indication). For example, when describing a certain indication information for indicating information I, it can include whether the indication information directly indicates I or indirectly indicates I, but does not necessarily mean that the indication information carries I.

[0099] In the description of this application, "when," "if," and "if" all refer to the fact that the device will take corresponding actions under certain objective circumstances, and are not limited to a specific time, nor do they require the device to perform a judgment action, nor do they imply any other limitations. Unless otherwise specified, "if" and "if" are interchangeable, "when" is interchangeable with "in the case of," and "when" can also be replaced with "when," or "after," etc., and "when" can also be replaced with "if" / "if," etc. The words "exemplary" or "for example" are used to indicate that they are examples, illustrations, or explanations. Any embodiment or design that is described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of the words "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0100] Figure 1 illustrates a possible, non-limiting schematic diagram of a communication system. As shown in Figure 1, the communication system 1000 includes a radio access network (RAN) 100 and a core network (CN) 200. RAN 100 includes at least one RAN node (110a and 110b in Figure 1, collectively referred to as 110) and at least one terminal device (120a-120j in Figure 1, collectively referred to as 120). RAN 100 may also include other RAN nodes, such as wireless relay devices and / or wireless backhaul devices (not shown in Figure 1). Terminal device 120 is wirelessly connected to RAN node 110. RAN node 110 is wirelessly or wired connected to core network 200. The core network devices in core network 200 and RAN node 110 in RAN 100 can be different physical devices, or they can be the same physical device integrating core network logical functions and radio access network logical functions. Optionally, the communication system 1000 also includes an Internet 300.

[0101] RAN 100 can be a cellular system related to the 3rd Generation Partnership Project (3GPP), such as 4G, 5G mobile communication systems, or future-oriented communication systems (such as 6G mobile communication systems). RAN 100 can also be an open access network (O-RAN or ORAN), a cloud radio access network (CRAN), or a wireless fidelity (WiFi) system. RAN 100 can also be a communication system that integrates two or more of the above systems.

[0102] RAN node 110, sometimes also referred to as access network equipment, RAN entity, or access node, constitutes part of the communication system and is used to help terminal equipment achieve wireless access. Multiple RAN nodes 110 in communication system 1000 can be of the same type or different types. In some scenarios, the roles of RAN node 110 and terminal equipment 120 are relative. For example, network element 120i in Figure 1 can be a helicopter or drone, which can be configured as a mobile base station. For terminal equipment 120j accessing RAN 100 through network element 120i, network element 120i is a base station; but for base station 110a, network element 120i is a terminal equipment. RAN node 110 and terminal equipment 120 are sometimes both referred to as communication devices. For example, network elements 110a and 110b in Figure 1 can be understood as communication devices with base station functions, and network elements 120a-120j can be understood as communication devices with terminal equipment functions.

[0103] In one possible scenario, a RAN node can be a base station, an evolved NodeB (eNodeB), an access point (AP), a transmission reception point (TRP), a next-generation NodeB (gNB), a base station in a future communication network, or an access node in a WiFi system. A RAN node can be a macro base station (as shown in Figure 1, 110a), a micro base station or indoor station (as shown in Figure 1, 110b), a relay node or donor node, or a radio controller in a CRAN scenario. Optionally, a RAN node can also be a server, wearable device, vehicle, or in-vehicle equipment. For example, the access network equipment in vehicle-to-everything (V2X) technology can be a roadside unit (RSU). All or part of the functions of the RAN node in this application can also be implemented through software functions running on hardware, or through virtualization functions instantiated on a platform (e.g., a cloud platform). The RAN node in this application can also be a logical node, logical module, or software capable of implementing all or part of the RAN node functions.

[0104] In another possible scenario, multiple RAN nodes collaborate to assist terminal devices in achieving wireless access, with different RAN nodes each implementing a portion of the base station's functions. For example, RAN nodes can be central units (CUs), distributed units (DUs), CU-control plane (CPs), CU-user plane (UPs), or radio units (RUs), etc. CUs and DUs can be set up separately or included in the same network element, such as a baseband unit (BBU). RUs can be included in radio frequency equipment or radio frequency units, such as remote radio units (RRUs), active antenna units (AAUs), or remote radio heads (RRHs).

[0105] In different systems, CU (or CU-CP and CU-UP), DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an ORAN system, CU can also be called O-CU (open CU), DU can also be called O-DU, CU-CP can also be called O-CU-CP, CU-UP can also be called O-CU-UP, and RU can also be called O-RU. For ease of description, this application uses CU, CU-CP, CU-UP, DU, and RU as examples. Any of the units among CU (or CU-CP, CU-UP), DU, and RU in this application can be implemented through software modules, hardware modules, or a combination of software and hardware modules.

[0106] Terminal devices can also be called terminals, user equipment (UE), mobile stations, mobile terminal devices, etc. They can be widely used in various scenarios, such as device-to-device (D2D), vehicle-to-everything (V2X) communication, machine-type communication (MTC), the Internet of Things (IoT), virtual reality, augmented reality, industrial control, autonomous driving, telemedicine, smart grids, smart furniture, smart offices, smart wearables, smart transportation, and smart cities. Terminal devices can include mobile phones, tablets, computers with wireless transceiver capabilities, wearable devices, vehicles, drones, helicopters, airplanes, ships, robots, robotic arms, and smart home devices.

[0107] Currently, some examples of terminal devices include: mobile phones, satellite mobile terminal devices, cellular phones, smartphones, tablets, laptops, PDAs, mobile internet devices (MIDs), wearable devices (such as smartwatches, smart bracelets, pedometers, smart glasses, etc.), in-vehicle devices (such as cars, bicycles, electric vehicles, airplanes, ships, trains, high-speed trains, etc.), satellite terminal devices, virtual reality (VR) devices, augmented reality (AR) devices, smart point-of-sale (POS) machines, customer-premises equipment (CPE), wireless terminal devices in industrial control, wireless terminal devices in self-driving cars, wireless terminal devices in remote medical surgery, wireless terminal devices in smart grids, wireless terminal devices in transportation safety, wireless terminal devices in smart cities, and smart homes. Wireless terminal devices in the home (e.g., refrigerators, televisions, air conditioners, electricity meters, etc.), intelligent robots, robotic arms, cellular phones, cordless phones, session initiation protocol (SIP) phones, wireless local loop (WLL) stations, personal digital assistants (PDAs), handheld devices with wireless communication capabilities, computing devices or other processing devices connected to a wireless modem, flying devices (e.g., intelligent robots, hot air balloons, drones, airplanes), terminal devices in 5G networks, or terminal devices in future evolved public land mobile networks (PLMNs), etc. The embodiments of this application do not limit the device form of the terminal devices.

[0108] RAN node 110 and terminal device 120 can be fixed or mobile. RAN node 110 and terminal device 120 can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; they can also be deployed on water; and they can be deployed in the air on aircraft, balloons, and satellites. This application embodiment does not limit the application scenarios of RAN node 110 and terminal device 120. RAN node 110 and terminal device 120 can be deployed in the same or different scenarios. For example, RAN node 110 and terminal device 120 can be deployed simultaneously on land; or RAN node 110 can be deployed on land and terminal device 120 can be deployed on water, etc., and so on.

[0109] RAN node 110 and terminal device 120 can communicate via licensed spectrum, unlicensed spectrum, or both simultaneously. For example, RAN node 110 and terminal device 120 can communicate via spectrum below 6 GHz, spectrum above 6 GHz, or both simultaneously. The embodiments of this application do not limit the spectrum resources used for wireless communication.

[0110] It is understood that RAN nodes are used to help terminal devices achieve wireless access, and they can also be referred to in other different ways, such as RAN entity, ORAN device, access node, access network device, etc. In the following description of the embodiments of this application, unless otherwise specified, the node or device that helps the terminal device achieve wireless access will be described as "access network device".

[0111] It is understood that terminal equipment and access network equipment are sometimes referred to as communication devices. For example, terminal equipment can be understood as a communication device with terminal equipment functions, and access network equipment can be understood as a communication device with access network equipment functions. In the method of this application, the functions of the access network equipment can also be performed by modules, units, or components (such as chips) within the access network equipment, or by a control subsystem containing access network equipment functions. This control subsystem containing access network equipment functions can be a control center in the aforementioned application scenarios such as smart grids, industrial control, intelligent transportation, and smart cities. Similarly, the functions of the terminal equipment can also be performed by modules, units, or components (such as chips or modems) within the terminal equipment, or by a device containing terminal equipment functions.

[0112] Figure 2 illustrates a possible, non-limiting ORAN system. As shown in Figure 2, the ORAN system includes core network equipment, access network equipment, and terminal equipment. The access network equipment communicates with the core network equipment via a backhaul link and with the terminal equipment via an air interface.

[0113] The access network equipment includes BBUs and RUs. A BBU communicates with at least one RU via a fronthaul link. The BBU and RU may or may not be co-located. Specifically, the BBU communicates with core network equipment via a backhaul link, and the RU communicates with terminal equipment via an air interface. A BBU includes at least one CU and at least one DU, which can communicate via at least one midhaul link.

[0114] Figure 3 shows a schematic diagram of a possible, non-limiting O-RAN device's network element function division and protocol layer structure.

[0115] In this context, O-RAN equipment can be understood as access network equipment using the O-RAN architecture, used to enable wireless access for terminal devices. It is understood that communication between O-RAN equipment and terminal devices follows a specific protocol layer structure. This protocol layer structure can include a control plane protocol layer structure and a user plane protocol layer structure. For example, the control plane protocol layer structure can include the functions of protocol layers such as Radio Resource Control (RRC), Packet Data Convergence Protocol (PDCP), Radio Link Control (RLC), Media Access Control (MAC), and the physical layer. Similarly, the user plane protocol layer structure can include the functions of protocol layers such as PDCP, RLC, MAC, and the physical layer. In one possible implementation, a Service Data Adaptation Protocol (SDAP) layer can be added above the PDCP layer.

[0116] As shown in Figure 3, the O-RAN equipment includes logical nodes such as CU, DU, and RU. The CU can connect to the core network via an interface, for example, the E2 interface. Optionally, the CU can have some core network functions. The CU can control at least one DU, and the CU can connect to the DU via an interface, for example, the F1 interface. Further, the control plane (CP) interface can be called F1-C, and the user plane (UP) interface can be called F1-U. The DU can control at least one RU, and the DU can connect to the RU via an interface, for example, the fronthaul interface.

[0117] 1. CU

[0118] A CU can be a logical node that carries the RRC layer, SDAP layer, PDCP layer, and other control functions. In other words, a CU can implement the functions of the RRC layer, SDAP layer, PDCP layer, and certain control functions.

[0119] Furthermore, the CU can be divided into CU-CP and CU-UP. Referring to Figure 3, CU-CP is a logical node carrying the control plane (control plane part of PDCP, PDCP-C) of the RRC and PDCP layers, used to implement the CU's control plane functions. CU-CP can interact with network elements in the core network used to implement control plane functions. These network elements in the core network can be access and mobility function network elements, such as the access and mobility management function (AMF) in a 5G communication system. Continuing to refer to Figure 3, CU-UP is a logical node carrying the data plane (user plane part of PDCP, PDCP-U) of the SDAP and PDCP layers, used to implement the CU's user plane functions. CU-UP can interact with network elements in the core network used to implement user plane functions, such as the user plane function (UPF) in a 5G communication system.

[0120] 2. DU

[0121] A DU can be a logical node that carries the RLC layer, MAC layer, higher physical layer (Higher PHY) layer, and other functions. For example, the higher physical layer may include some of the processing functions of the PHY layer, such as forward error correction (FEC) encoding and decoding, scrambling, modulation, and demodulation. In other words, a DU can implement the functions of the RLC layer, MAC layer, higher physical layer, and other functions.

[0122] It is understood that the above CU and DU configurations are merely examples, and the functions of the CU and DU can be configured as needed. For instance, the CU or DU can be configured to have more protocol layer functions, or it can be configured to have only some protocol layer processing functions. For example, some functions of the RLC layer and the protocol layer functions above the RLC layer can be placed in the CU, while the remaining functions of the RLC layer and the protocol layer functions below the RLC layer can be placed in the DU. Furthermore, the functions of the CU or DU can be divided according to service type or other system requirements, such as by latency, placing functions that need to meet low latency requirements in the DU and functions that do not need to meet such latency requirements in the CU.

[0123] 3. RU

[0124] An RU can be a logical node that carries both lower physical layer (PHY) and radio frequency (RF) chain processing. For example, the lower physical layer includes some of the processing functions of the physical layer, such as fast Fourier transform (FFT), inverse fast Fourier transform (IFFT), digital beamforming, and filtering. In other words, an RU can implement both physical layer and RF functions.

[0125] In one possible implementation, the RU can be a 3GPP transmission reception point (TRP), a remote radio head (RRH), or other similar entity. The RU communicates with one or more terminal devices via a wireless link.

[0126] The DU and RU can be co-located or non-co-located, without restriction. Referring to Figure 3, the O-RAN control user and synchronization (CUS-Plane) and management plane (M-Plane) can be included between the DU and RU. The O-RAN CUS plane can be simply referred to as the CUS plane, and the O-RAN management plane can be simply referred to as the management plane. Further, the CUS plane can be divided into a control plane (C-Plane) and a user plane (U-Plane). Optionally, the control plane refers to the real-time control plane between the DU and RU. The management plane refers to the non-real-time management operations between the DU and RU.

[0127] Referring to Figure 3, the DU and RU exchange control plane and user plane information via the lower-layer split CUS-Plane (LLS-CUS) interface through the fronthaul link. Furthermore, the LLS-CUS interface may include an LLS-C interface corresponding to the control plane and an LLS-U interface corresponding to the user plane. The DU and RU exchange management plane information through the LLS-M interface of the fronthaul link. Referring to Figure 3, the LLS-M interface can also connect to an external management system.

[0128] It is understandable that DUs and RUs can cooperate to implement physical layer functions. A DU can be connected to one or more RUs. The functions of DUs and RUs can be configured in various ways depending on the design. For example, a DU can be configured to implement baseband functions, and an RU can be configured to implement mid-RF functions. Another example is that a DU can be configured to implement higher-level functions in the physical layer, and an RU can be configured to implement lower-level functions in the physical layer, or to implement both lower-level and RF functions. Higher-level functions in the physical layer may include a portion of the physical layer's functions that are closer to the MAC layer, while lower-level functions may include another portion of the physical layer's functions that are closer to the mid-RF side.

[0129] For ease of description, some communication terms or terminology involved in this application are explained. It is understood that this explanation is for understanding the method of this application and is not intended to limit the embodiments of this application.

[0130] I. Information to be encoded

[0131] The information to be encoded can refer to information to be channel-coded. For example, the process of obtaining the information to be encoded may include: generating a sequence of information bits to be transmitted from the source at the transmitting end. The transmitting end can perform source coding on the sequence of information bits to be transmitted to obtain the corresponding information. This corresponding information can be used as the information to be encoded in this application. Using the method of this application, the information to be encoded can be encoded to obtain the encoded information. Unless otherwise specified, "encoding" in this application can specifically refer to channel coding, and more specifically, LDPC coding.

[0132] For example, the information to be encoded can be a sequence of multiple bits. For instance, if the bits to be encoded are 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 1, then the information to be encoded can be: 10101100101.

[0133] II. Code Length

[0134] Code length refers to the length of the encoded information (such as the bit sequence to be transmitted) obtained by encoding the information to be encoded (such as the information bit sequence). The code length is greater than or equal to the length of the information bit sequence.

[0135] III. Bitrate

[0136] The code rate is the ratio of the length of the information to be encoded (such as the length of the information bit sequence) to the code length (such as the length of the encoded information).

[0137] The length, code length, and code rate of the information to be encoded can be pre-configured by higher-layer signaling, MAC layer signaling, or downlink physical layer signals, and can also be obtained or calculated by the transmitting and receiving devices. For example, the transmitting and receiving devices can determine the code length based on the encoding method, the frame structure used to transmit information bits, the number of layers, and the modulation scheme. For example, the transmitting and receiving devices can obtain the code rate based on higher-layer signaling, MAC layer signaling, or downlink physical layer signals, or determine the code rate based on the modulation and coding scheme (MCS).

[0138] IV. Low-Density Parity Check (LDPC) Codes

[0139] LDPC codes are a channel coding scheme very close to the Shannon limit, characterized by high performance and low complexity. They have been adopted by 3GPP as the coding and decoding scheme for 5G communication data channels. Mainstream LDPC codes have a quasi-cyclic (QC) structure, which avoids bad structures such as short cycles and improves code distance by setting the shift amount of each block.

[0140] LDPC codes can be represented using a basis matrix, where elements are either 0 or 1. Expanding the basis matrix by adding 1s results in a Zc*Zc cyclic shift matrix, and expanding by adding 0s results in a Zc*Zc zero matrix. This expansion yields a parity-check matrix, which can be used for encoding or decoding. Zc can be referred to as the expansion factor, lifting factor, expansion value, expansion coefficient, lifting size, etc. The basis matrix can be represented as H. BG BG is an abbreviation for base graph. A basis matrix can also be represented by a base graph, and the two have a corresponding relationship.

[0141] For example, if the element in the i-th row and j-th column of the basis matrix is ​​1 and corresponds to a shifting value (SV), it can be represented by P. i,j This represents the shift value corresponding to the i-th row and j-th column. A single shift value can be used to calculate the corresponding number of cyclic shifts.

[0142] Taking Zc=4 as an example, the matrix obtained by cyclically shifting the 4*4 identity matrix to the right by 1, 2, 3, and 0 times respectively is shown in Figure 4. That is, the number of cyclic shifts are 1, 2, 3, and 0 respectively.

[0143] The following example illustrates this. Figure 5 shows an example of the basis matrix in an LDPC code. This basis matrix is ​​a 3x3 matrix, and we assume Zc = 4, and P 0,0 The corresponding right circular shift count is 1, P 0,1 The corresponding right circular shift count is 2, P 1,0 The corresponding number of right circular shifts is 3, P 1,2 The corresponding number of right circular shifts is 3, P 2,2 The corresponding right circular shift count is 1. After expanding the base matrix, we can obtain the parity check matrix as shown in Figure 6.

[0144] Currently, the 3GPP 38.212 protocol defines various values ​​for the lift size (Zc) as shown in Table 1.

[0145] Table 1

[0146] Referring to Table 1, the values ​​of the lifting dimension Zc can be... Where j represents the j-th row in Table 1, j = 0, 1, 2, 3, 4, 5, 6, 7, and a0, a1, a2, a3, a4, a5, a6, a7 are 2, 3, 5, 7, 9, 11, 13, 15 respectively, which is the value of the first element in the lifting size set of each row. k j The value of traverses from 0 to max(k) j), where max(k0), max(k1), max(k2), max(k3), max(k4), max(k5), max(k6), and max(k7) are 7, 7, 6, 5, 5, 5, 4, and 4, respectively.

[0147] For example, if j = 0, then a0 = 2, and k0 iterates through 0 to 7, so the value of Zc can be 2*2. 0 ,2*2 1 ,2*2 2 ,2*2 3 ,2*2 4 ,2*2 5 ,2*2 6 ,2*2 7 That is, 2, 4, 8, 16, 32, 64, 128, 256. The cases where j takes values ​​from 1 to 7 are similar and will not be elaborated further.

[0148] The protocol also stipulates that each row of Zc in Table 1 corresponds to a set of SV. When constructing the parity check matrix, the size of Zc is first determined, then the set of SV corresponding to that Zc is determined, and then the parity check matrix is ​​constructed based on Zc and SV.

[0149] Table 2 below shows some examples of a set of SVs defined in the 3GPP 38.212 protocol.

[0150] Table 2

[0151] Table 2 shows the basis matrix H. BG The translation values ​​SV corresponding to the elements with a value of 1 in row 0 i,j The set index i in Table 2 LS That is, the set index i in Table 1 LS Furthermore, the basis matrix H BG The cyclic shift value corresponding to each element with a value of 1 in row 0 can be obtained by taking the modulo of Zc using the corresponding translation value.

[0152] It should be noted that Table 2 only shows the translation values ​​corresponding to each element in row 0. In practice, it also includes the translation values ​​corresponding to each element in other rows (such as row 1, row 2, etc.).

[0153] Referring to Table 2, when Zc takes the values ​​2, 4, 8, 16, 32, 64, 128, or 256, then i LS =0, basis matrix H BGThe SV values ​​of the elements with a value of 1 in row 0 are 250, 69, 226, 159, 100, 10, 59, 229, 110, 191, 9, 195, 23, 190, 35, 239, 31, 1, 0. Assuming Zc = 4, then the basis matrix H... BG The cyclic shift counts corresponding to the elements with a value of 1 in row 0 are 250 mod 4, 69 mod 4, 226 mod 4, 159 mod 4, 100 mod 4, 10 mod 4, 59 mod 4, 229 mod 4, 110 mod 4, 191 mod 4, 9 mod 4, 195 mod 4, 23 mod 4, 190 mod 4, 35 mod 4, 239 mod 4, 31 mod 4, 1 mod 4, 0 mod 4, which are 2, 1, 2, 3, 0, 2, 3, 1, 2, 3, 1, 3, 3, 2, 3, 3, 3, 1, 0. This means that the 4x4 identity matrix is ​​cyclically shifted 2, 1, 2, 3, 0, 2, 3, 1, 2, 3, 1, 3, 3, 2, 3, 3, 3, 1, 0 times to obtain the base matrix H. BG The elements in row 0 that have a value of 1 correspond to a 4x4 matrix. For the basis matrix H... BG The elements in the 0th row that have a value of 0 correspond to a zero matrix of size 4*4.

[0154] Similarly, for other values ​​of Zc, there are corresponding translation values ​​and cyclic shift counts, as detailed in Table 2.

[0155] Similarly, for the basis matrix H BG The rows other than row 0 are also determined using a similar method to determine the corresponding Zc*Zc matrix.

[0156] In this embodiment, the lifting and translation operations of the LDPC code are described as follows: For a given lifting size Zc, from the basis matrix H... BG Upgraded to the parity check matrix H, specifically, the basis matrix H BG t in i,j (where t) i,j =1) will be replaced with a Zc×Zc matrix I(P) i,j ), where I(P i,j ) is a cyclic shift of the identity matrix I of Zc×Zc by P i,j One (either left or right circular shift is possible) or circular shift P i,j A matrix of degree mod Zc, P i,j The translation value corresponding to the i-th row and j-th column; basis matrix H BG The zeros in H will be replaced with a Zc×Zc matrix of all zeros. It can be seen that the purpose of lifting is to improve the basis matrix H. BGTo transform it into a larger parity check matrix H, the translation aims to shift each H... BG The identity matrix corresponding to the non-zero elements is cyclically shifted into a predefined matrix.

[0157] V. Basis Matrix of 5G LDPC Codes

[0158] The basis matrices of the 5G LDPC code include BG1 and BG2. BG1 is a 46x68 matrix, and BG2 is a 42x52 matrix. Both BG1 and BG2 have the matrix structure shown in Figure 7. Region A corresponds to high-rate information columns, region B corresponds to the core checksum for high-rate data, region C is a zero matrix, region D is the incremental redundancy portion of the basis matrix corresponding to low-rate data, and region E is the incremental redundancy region and is an identity matrix. The values ​​of the basis matrices are either 0 or 1; a value of 0 represents an empty element, and a value of 1 represents an edge in the basis graph or an association between the checksum and the variable.

[0159] To improve the bit rate, LDPC encoding supports puncturing. For example, referring to Figure 7, the first two columns of the matrices BG1 and BG2 are punctured columns. In terms of matrix characteristics, the column weight of the punctured column is relatively large, where column weight refers to the number of non-zero elements in a column. In terms of transmission characteristics, the bits corresponding to the punctured column are not transmitted, and the receiver does not need to pay attention to the received information of this part. Its log-likelihood ratio is set to 0, and it is recovered through decoding.

[0160] It should be noted that BG1 and BG2 are designed for the lowest bit rate. When different bit rates need to be supported, the transmitter can truncate the upper left portion of BG1 or BG2; alternatively, the transmitter can always use the matrix with the lowest bit rate for encoding, meaning the transmitter does not perform matrix truncation, and uses the complete matrix to obtain the entire codeword bit sequence, but only sends a portion of the bits. The sent bits actually correspond to the columns of the truncated matrix. Figure 8 shows a schematic diagram of the matrix regions corresponding to different bit rates. This matrix can be BG1 or BG2. When rows and columns of the high bit rate region shown in the figure are selected from BG1 or BG2 to form the base matrix, the bit rate of this base matrix is ​​the highest, hence it is also called the highest bit rate matrix. When more rows and columns than the high bit rate region are selected from BG1 or BG2 to form the base matrix, the bit rate of this base matrix is ​​lower than the highest bit rate. Furthermore, as the number of rows and columns increases, the bit rate of the corresponding matrix region gradually decreases. Referring to Figure 8, the rows and columns of each dashed box region form a base matrix. As the area of ​​the dashed box increases, the bit rate of the corresponding base matrix gradually decreases.

[0161] In one method, when performing LDPC encoding, the first device (e.g., the transmitter) determines the first row interval based on the encoding rate and the first base matrix. For example, the first row interval is the first N rows of the first base matrix. For instance, when the first row value (e.g., row) equals 5, the first row interval is the first five rows of the first base matrix, i.e., rows 1 to 5. The first device uses the base matrix corresponding to the first row interval to encode the information to be encoded, obtaining the encoded information. The disadvantages of this method are as follows: 1. Poor orthogonality. 2. Lower throughput (e.g., peak throughput).

[0162] In view of the above, this application provides an encoding / decoding method and apparatus. The encoding method includes: a first device (e.g., a transmitter) determining a first row interval based on the encoding code rate and a first basis matrix; shifting the first row interval to obtain a second row interval; and encoding the information to be encoded based on the second basis matrix corresponding to the second row interval. In the first basis matrix, the orthogonality between different rows is enhanced with downward shifting (i.e., increasing the row index). The second basis matrix corresponding to the second row interval has enhanced orthogonality relative to the basis matrix corresponding to the first row interval. Furthermore, due to the enhanced orthogonality, the throughput of transmitted information can be improved (e.g., peak throughput), such as a peak throughput reaching 100Gbps.

[0163] It is understood that the methods described in [Example 1] or [Example 2] below can be applied to downlink or uplink communication: In downlink communication, the access network device acts as the transmitter, encodes the information to be encoded, obtains the encoded information, and transmits the encoded information. The terminal device acts as the receiver, receives the information to be decoded, and decodes the information to be decoded. In Example 1 or Example 2 below, the first device can be an access network device, and the second device can be a terminal device. In uplink communication, the terminal device acts as the transmitter, encodes the information to be encoded, obtains the encoded information, and transmits the encoded information. The access network device acts as the receiver, receives the information to be decoded, and decodes the information to be decoded. In Example 1 or Example 2 below, the first device can be a terminal device, and the second device can be an access network device.

[0164] Figure 9 provides a flowchart of a communication system applicable to this application. As shown in Figure 9, at the transmitting end: the information source can output the information bits to be transmitted; then, the information bits to be transmitted are sequentially subjected to source encoding, channel encoding, and modulation processes, and the corresponding information is transmitted through the air interface. The receiving end receives the information through the air interface, and sequentially performs demodulation, channel decoding, and source decoding processes on the received information to obtain the corresponding information, which is then output to the sink. The encoding / decoding method shown in [Embodiment 1] or [Embodiment 2] of this application is a channel encoding / decoding process. In practical applications, in addition to performing the encoding / decoding shown in [Embodiment 1] or [Embodiment 2] on the corresponding information, source encoding / decoding, modulation / demodulation, and other processes can also be performed without limitation. In one understanding, the processes of source, source encoding, channel encoding, and modulation can be executed within the first device. For example, the source can be the application layer of the first device, the application layer can generate the information bits to be transmitted, and source encoding, channel encoding, and modulation are implemented by the corresponding processor of the first device. Similarly, processes such as source recovery, channel decoding, and demodulation can be performed within the second device. For example, source recovery, channel decoding, and demodulation can be implemented by the corresponding processor of the second device, and the source can be the application layer of the second device.

[0165] It is understood that the method provided in this application will be described using examples of a first device or a second device as the executing entity. It is also understood that the operations performed by the first device or the second device can be implemented by the processor, circuit, chip, or chip system of the corresponding device, or by a functional module, component, or unit. Furthermore, the processing performed by a single executing entity can be divided among multiple executing entities, which can be logically and / or physically separated. For example, when the first device or the second device is an access network device, the processing performed by the access network device can be divided among at least one of a CU, DU, RU, etc.

[0166] In the description of this application, "sending information (such as encoded information) to (such as a second device)" can be understood as the destination of the information being the second device. This can include sending information directly or indirectly to (such as a second device). "Receiving information (such as information to be decoded) from (such as a first device)" can be understood as the source of the information being the first device, and can include receiving information directly or indirectly from the first device. Information may undergo necessary processing between the source and destination, such as format changes, but the destination can understand the valid information from the source. Similar expressions in this application can be understood in a similar way, and will not be elaborated further here.

[0167] In the description of this application, "transmit" or "receive" indicates the direction of information / signals. "Transmit" or "receive" can also be understood as "input" or "output." "Transmit" or "receive" can occur between devices, for example, between a first device and a second device via a wireless channel. "Transmit" or "receive" can also occur within a device, for example, between components, modules, chips, software modules, or hardware modules within the device via a bus, wiring, or interface. For example, "transmit" can also be understood as the "output" of a chip interface, and "receive" can be understood as the "input" of a chip interface.

[0168] Example 1

[0169] Figure 10 provides a flowchart of an encoding method, which includes:

[0170] Step 1010: The first device determines the first row interval based on the encoded code rate and the first base matrix.

[0171] The encoding rate, often simply called the code rate, can be represented by R. For example, R = K / N, or R = floor(K / N), where floor() represents the floor function, or R = ceil(K / N), where ceil() represents the floor function. Here, K represents the length of the information bits to be encoded, and N represents the length of the codeword (e.g., the codeword being sent), often simply called the code length. The codeword can be understood as the encoded information bits, and the code length can be understood as the length of the encoded information bits.

[0172] The bitrate can be predefined by the protocol, or determined by the first device and notified to the second device, such as the first device sending first indication information to the second device to indicate the bitrate; there is no limitation. The first base matrix can be predefined by the protocol, or determined by the first device and notified to the second device, such as the first device sending second indication information to the second device to indicate the first base matrix. For example, the first base matrix can be associated with at least one of the following: code length, bitrate, or application scenario. For example, the first device can determine the first base matrix based on at least one of the following: code length, bitrate, or application scenario. Alternatively, the first device and the second device can use the same method to each determine the first base matrix, so that both can obtain the same first base matrix. This same method can be agreed upon in advance or predefined by the protocol. The characteristics of the first base matrix can be found in the following description.

[0173] In one possible implementation, the first device determines the first row value `row` based on the encoding code rate `R` and the number of information columns `kb` contained in the first base matrix. The following conditions must be met between `R`, `kb`, and `row`:

[0174] For example, the first device obtains the encoding rate R and the number of information columns kb contained in the first base matrix. The first device inputs R and kb into Formula 1 above to obtain the first row value row.

[0175] It is understandable that Formula 1 above does not consider the case where the first base matrix is ​​punctured, i.e., the first base matrix does not contain punctured columns. If the first base matrix contains punctured columns, the first device can determine the first row value `row` based on the encoding rate `R`, the number of information columns `kb` in the first base matrix, and the number of punctured columns `pb` in the first base matrix. The following conditions must be met between `R`, `kb`, `pb`, and `row`:

[0176] Alternatively, in another possible implementation, the first row value `row` satisfies the following:

[0177] Where Zc is the smallest lift value in the set of lift values ​​that satisfy kb*Zc≥K, the meanings of kb and pb can be referred to above, and ceil() represents the floor function.

[0178] The first device can determine a first row interval based on the first row value `row`. This first row interval consists of the indices of a subset of rows contained in the first base matrix. These rows can be rows with consecutive indices, meaning the first row interval is composed of the indices of a subset of consecutive rows contained in the first base matrix. Alternatively, these rows can be rows with non-consecutive indices, meaning the first row interval is composed of the indices of a subset of non-consecutive rows contained in the first base matrix. In one interpretation, the first row interval can be understood as a set of row indices containing the indices of one or more rows. Alternatively, if the first row interval includes consecutive row indices, it can be understood as containing a start row index and an end row index. The row index is used to uniquely identify a row in the first base matrix. "Index" can also be replaced with other names, such as number or identifier, without restriction.

[0179] For example, referring to Figure 11, the first base matrix contains 8 rows, each with a corresponding index, and the indices of the 8 rows are 1 to 8 respectively.

[0180] As can be understood, in Figure 11, the first column represents the index of each row. In the schematic diagram of Figure 11, the row indices start from "1". It can also be understood that the row indices can start from other values, such as "0". In this case, the indices of the 8 rows contained in the first base matrix would be 0 to 7 respectively. That is to say, in the schematic diagram shown in Figure 11, the row indices "1 to 8" corresponding to the first column can be replaced with "0 to 7".

[0181] In the first base matrix shown in Figure 11, the first row interval can be determined based on the first row value 'row'. For example, the first row interval is row 1 to row 'row' in the first base matrix. If the first row value 'row' is equal to 5, as shown in Figure 12a, the first five rows (i.e., row 1 to row 5) can be captured in the first base matrix. The first row interval contains the row indices of the first five rows (1, 2, 3, 4, and 5), or the first row interval contains the starting row index (1) and the ending row index (5).

[0182] Subsequently, the first device can shift the first row interval to obtain the second row interval; that is, the second row interval is obtained by shifting the first row interval. Optionally, the shifting process can refer to adding a value (such as a first value) to the row index indicated by the first row interval. In other words, the first device can add a first value to the index of each row indicated by the first row interval to obtain the second row interval. Similar to the understanding of the first row interval, the second row interval can be composed of the indices of a portion of the rows in the first base matrix. These rows can be rows with consecutive indices or rows with non-consecutive indices, without restriction. The second row interval can be a set of row indices. For example, if the second row interval contains one or more row indices, these one or more row indices can be considered as a set of row indices. Alternatively, if the second row interval includes consecutive row indices, the second row interval includes a start row index and an end row index.

[0183] For example, referring to Figure 12a above, the first row interval indicates the first 5 rows of the first base matrix (i.e., rows 1 to 5). By incrementing the index of each row indicated by the first row interval by a first value (e.g., the first value equals 1), the second row interval is obtained. Referring to Figure 12b, the second row interval indicates rows 2 to 6 in the first base matrix.

[0184] In one interpretation, the first and second row intervals can be considered as intervals of rows. The process of obtaining the second row interval from the first row interval can be understood as: averaging the first row interval to obtain the second row interval. As shown in Figure 12a, the first row interval contains rows 1 to 5. The first row interval is then shifted downwards by the row corresponding to the first value (e.g., row 1) to obtain the second row interval. As shown in Figure 12b, the second row interval contains rows 2 to 6.

[0185] In one possible implementation, the process of translating the first row interval can be related to the first sequence. For example, the first device can translate the first row interval based on the first sequence to obtain the second row interval; that is, the second row interval is obtained by translating the first row interval based on the first sequence. In another description, it can also be described as follows: the second row interval is determined based on the first row interval and the first sequence; that is, the first device can determine the second row interval based on the first row interval and the first sequence.

[0186] In this sequence, the length of the first sequence is equal to the number of rows in the first base matrix. The length of the first sequence can refer to the number of elements it contains; that is, the number of elements in the first sequence is equal to the number of rows in the first base matrix. Furthermore, the elements in the first sequence have two values, such as 0 or 1. For example, the first sequence can be called the β sequence, and any element in this sequence can be called β(i), where i is a positive integer greater than or equal to zero.

[0187] Figure 13 illustrates the correspondence between the first basis matrix and the first sequence (β sequence). The first column in Figure 13 represents the first sequence (β sequence), which contains 11 elements: {0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1}. Each row of the first basis matrix contains a corresponding element within the first sequence. As shown in Figure 13, the first basis matrix contains 11 rows. Rows 1 to 4 contain elements of 0, rows 5 to 8 contain elements of 1, row 9 contains elements of 0, and rows 10 and 11 contain elements of 1.

[0188] In one description, any row in the first basis matrix can be denoted as row i. In the first sequence (β sequence), the element corresponding to the i-th row can be denoted as β(i). In the example of Figure 13, the first basis matrix contains 11 rows, and the first sequence (β sequence) can be represented as {β(1), β(2), β(3), β(4), β(5), β(6), β(7), β(8), β(9), β(10), β(11)}. In the specific example of Figure 13, the values ​​of β(1) to β(4) are 0, the values ​​of β(5) to β(8) are 1, the value of β(9) is 0, and the values ​​of β(10) and β(11) are 1.

[0189] It should be noted that in a possible implementation, when the value of β(i) is equal to 1, it means that the column weight of the extended check column corresponding to the i-th row in the first base matrix is equal to A (such as 2). Or, when the value of β(i) is equal to 0, it means that the column weight of the extended check column corresponding to the i-th row in the first base matrix is equal to B (such as 1). That is, the value of an element in the first sequence (β sequence) essentially represents the type of the extended check column corresponding to the corresponding row in the first base matrix, such as a column weight of 2 or a column weight of 1. In this application, there may or may not be a concept of "first sequence". For example, the first device (transmitter) or the second device (receiver) can infer that the corresponding β value is 1 or 0 based on the column weight of the extended check column of a certain row in the first base matrix. Further, it should be noted that when an element of the first sequence (β sequence) has a value of "1", it essentially means that the column weight of the extended check column corresponding to this element's row is A (such as 2). When an element of the first sequence (β sequence) has a value of "0", it essentially means that the column weight of the extended check column corresponding to this element's row is B (such as 1). It can be understood that A and B are positive integers with different values.

[0190] It can be understood that in the description of this application, it is mainly described by taking the values of the elements of the first sequence (β sequence) as 1 or 0 as an example, and there is no restriction on this. For example, the first sequence includes value 1 or value 2. When an element of the first sequence has a value of value 1 (such as 1), it essentially means that the column weight of the extended check column corresponding to this element's row is A (such as 2). When an element of the first sequence has a value of value 2 (such as 0), it essentially means that the column weight of the extended check column corresponding to this element's row is B (such as 1).

[0191] For example, the first device can determine the second row value according to the first row value and the first sequence. Regarding the determination process of the first row value (row), reference can be made to the previous description. For example, the process of determining the second row value according to the first row value and the first sequence satisfies the following: x + y = row′; (Formula 3) x + y / 2 = row; (Formula 4)

[0192] Among them, row represents the first row value, row’ represents the second row value, x represents the number of elements with a value of 0 corresponding to the first row to the row’-th row of the first base matrix in the first sequence, and y represents the number of elements with a value of 1 corresponding to the first row to the row’-th row of the first base matrix in the first sequence.

[0193] In one understanding, as the second row value (row’) increases, x and y increase monotonically. When it increases to a certain extent and satisfies Formula 4 (x + y / 2 = row), obtain the values of x and y at this time. Further, according to the values of x and y and Formula 3 (x + y = row′), obtain the value of the second row value (row’).

[0194] Among them, the first value can be determined according to the second row value and the first row value. For example, the first value is equal to the difference between the second row value and the first row value. For example, if the second row value is represented as row’ and the first row value is represented as row, then the first value = row’ - row. As an example in Figure 12a above, the first row value (row) is equal to 5: According to Formula 3, it can be obtained that the value of x is equal to 4 and the value of y is equal to 2. According to Formula 4, it can be obtained that the value of row’ (row’) is equal to 6. Then the first value is equal to 1 (row’ - row). Based on the first row interval shown in Figure 12a, translate it downward by 1 row to obtain the second row interval (refer to Figure 12b). The row range indicated by the first row interval is from the 1st row to the 5th row, and the row range indicated by the second row interval is from the 2nd row to the 6th row.

[0195] In one understanding, when the row index of the first basis matrix starts from 1, the first row value (row) is essentially the index of the largest row indicated by the first row interval, and the row index range indicated by the first row interval is: 1 to the first row value (row). The second row value (row’) is essentially the index of the largest row indicated by the second row interval, and the row index range indicated by the second row interval is: (the second row value - the first row value + 1) to the second row value, that is, the row index range included in the second row interval is: row′ - row + 1 to row′.

[0196] The rows indicated by the second row interval in the first basis matrix can form a second basis matrix. For example, the first device can intercept the rows indicated by the second row interval in the first basis matrix to obtain the second basis matrix in the first basis matrix. As shown in Figure 12b, in the first basis matrix, intercept the 2nd to 6th rows indicated by the second row interval to obtain the second basis matrix, that is, the second basis matrix is composed of the 2nd to 6th rows indicated by the second row interval.

[0197] Step 1020: The first device encodes the information to be encoded according to the second basis matrix corresponding to the second row interval to obtain the encoded information.

[0198] For example, the first device can perform processes such as lifting and shifting on the second base matrix to obtain the parity check matrix H. For an explanation of lifting and shifting, please refer to the relevant explanation in Part IV (LDPC code) of the terminology section above. The first device solves for Hx = 0 to obtain the parity bits. The information to be encoded is then encoded based on the parity bits to obtain the encoded information. It can be understood that the information to be encoded can refer to the information bits to be sent, such as information bits generated by the application layer, or information bits obtained after source encoding of information bits generated by the application layer, etc., without restriction. For example, the information to be encoded can be represented as s = [s(0), s(2), ..., s(K-1)], the parity information can be represented as p = [p(0), p(1), ..., p(M-1)], and the encoded information can be represented as c = [sp]. In one understanding, the information to be encoded s can be understood as a sequence of K-1 bits, where the K-1 bits are s(0), s(2), ..., s(K-1) in sequence. The check information p can be understood as a sequence of M-1 bits, where the M-1 bits are [p(0), p(1), ..., p(M-1)]. The length of the information to be encoded s can be the same as or different from the length of the check information p, that is, the values ​​of K and M can be the same or different.

[0199] In this application, the first basis matrix and the second basis matrix can be used to represent LDPC codes, and the first basis matrix and the second basis matrix can also be referred to as the first LDPC matrix and the second LDPC matrix. The encoding involved in the method of this application can refer to LDPC encoding, such as the first device performing LDPC encoding on the information to be encoded to obtain the encoded information.

[0200] It should be noted that the method shown in Figure 11 may also include the following steps: the first device sends the encoded information; or, the first device may perform corresponding processing on the encoded information, such as modulation, and then send the processed information. Correspondingly, the second device receives the corresponding information. The information received by the second device may include other information besides the information sent by the first device, such as noise information. The method shown in Figure 11 focuses on describing the encoding process of the information by the transmitting end (first device). The decoding process of the information after the second device receives it can be referred to the description of the method shown in Figure 14 below.

[0201] Figure 14 provides a flowchart of a decoding method, including:

[0202] Step 1410: The second device acquires the information to be decoded.

[0203] For example, the second device can receive information from the first device, which can be understood as a physical signal received via the air interface. The second device processes the received information accordingly, such as noise reduction and demodulation, to obtain information to be decoded. This information to be decoded can be equivalent to the encoded information sent by the first device, or it can include other information, such as noise information, in addition to the encoded information sent by the first device. The second device can decode the information to be decoded to obtain the decoded information. For the specific decoding process, please refer to the descriptions of steps 1420 and 1430 below.

[0204] Step 1420: The second device determines the first row interval based on the encoded code rate and the first base matrix.

[0205] The encoding rate, often simply referred to as the code rate (R), can be predefined by the protocol or indicated by the first device to the second device, such as when the second device receives first indication information from the first device to indicate the code rate. The first base matrix can also be predefined by the protocol or indicated by the first device to the second device, such as when the second device receives second indication information from the first device to indicate the first base matrix. Alternatively, the second device can determine the first base matrix itself, for example, based on at least one of the following: code rate, code length, or scenario.

[0206] The process by which the second device determines the first row interval based on the bit rate and the first base matrix can be described in step 1010 of the method shown in Figure 10. It can be understood that the first row interval is composed of the indices of a portion of the rows contained in the first base matrix. The second device can shift the first row interval to obtain the second row interval; that is, the second row interval is obtained by shifting the first row interval. The second device extracts the rows indicated by the second row interval from the first base matrix to obtain the second base matrix, which is composed of the rows indicated by the second row interval in the first base matrix. The process of shifting the first row interval and obtaining the second base matrix based on the second row interval can also be described in step 1010 of the method shown in Figure 10.

[0207] Step 1430: The second device decodes the information to be decoded according to the second base matrix corresponding to the second row interval, and obtains the decoded information.

[0208] For example, the first and second basis matrices are used to represent LDPC codes, and LDPC decoding can be performed on the information to be decoded to obtain the decoded information. There are no restrictions on the algorithm used for LDPC decoding. For example, it can be a minimum-sum decoding algorithm (MS) or a belief-propagation decoding algorithm (BP), etc.

[0209] Figure 15 shows a schematic diagram of the structure of the "first basis matrix" or "second basis matrix". In the description of this application, the first basis matrix or the second basis matrix can be collectively referred to as the basis matrix, or simply the matrix. As shown in Figure 15, the columns of the matrix include information columns and check columns. The number of information columns corresponds to the number of information bits (such as the information bits corresponding to the information to be encoded), which can be expressed as kb. The number of check columns corresponds to the number of check bits. In the schematic diagram of Figure 15, the order of the matrix columns is information columns first, then check columns, but the method of this application does not limit this. For example, the order of the matrix columns can also be check columns first, then information columns. Furthermore, the check columns can be divided into core check columns and extended check columns. The core check columns can be understood as the columns corresponding to region B, and the extended check columns can be understood as the columns corresponding to region C or region E (the schematic diagram of Figure 15 mainly describes this division method). Alternatively, the first 4 columns of the check columns can be defined as core check columns, and the remaining columns as extended check columns. Furthermore, the rows of the matrix include core check rows and extended check rows.

[0210] For example, the parity check matrix can include a high-rate region, an all-zero region, an incremental redundancy region, and a raptor-like region. The high-rate region can include parts A and B as shown in Figure 15. Part A corresponds to information bits (or information digits, system bits, etc.), and part B is a square matrix corresponding to the core parity bits (or core parity digits). The core parity can be the parity corresponding to the highest bit rate, or it can be a parity with a degree greater than or equal to 2, or it can be the parity node corresponding to the row set with the largest row weight (row weight significantly higher than other rows). The all-zero region can correspond to part C as shown in Figure 15 and is an all-zero matrix. The incremental redundancy region can correspond to part D as shown in Figure 15. The raptor-like region can correspond to part E as shown in Figure 15 and can be an identity matrix corresponding to the parity bits of the low-rate extension. Part B and Part E are both verification parts. Part B is defined as the core verification region, and its features can be non-lower triangular coding parts (i.e., values ​​above the diagonal are not all 0) or coding parts with column weight greater than 1. Part E is defined as the extended verification region, and its features can be lower triangular coding parts (i.e., values ​​above the diagonal are all 0) or diagonal matrices.

[0211] The parity-check matrix of the LDPC code adopts a "raptor-like" structure and can be gradually extended from a high code-rate core matrix to a low code-rate one. In actual use, the first X rows and the first Y columns of the parity-check matrix can be intercepted. As the code rate decreases from high to low, X and Y gradually increase, and the area of the matrix used also gradually expands.

[0212] The columns of the LDPC base matrix (such as the first base matrix or the second base matrix involved in this application) consist of information columns and parity-check columns.

[0213] Information column: Corresponding to information bits (or information positions, systematic bits, etc.), it is the column corresponding to part A.

[0214] Parity-check column: Corresponding to parity-check bits (or parity-check positions, etc.), it is the column corresponding to parts B and C, and can include a core parity-check column and an extended parity-check column. Among them, the core parity-check column is the column corresponding to part B, and the extended parity-check column is the column corresponding to part C or part E. The extended parity-check column can also be called a raptor-like column. Or, the core parity-check column is the parity-check column in part B with a column weight greater than 1 (there are 1 elements both above and below the diagonal of part B), and the extended parity-check column is the remaining columns in the parity-check columns except the core parity-check column.

[0215] Core row: The core row of the LDPC base matrix is the row corresponding to the core parity-check bits. In other words, the core row is the row corresponding to the high code-rate area, or the row corresponding to part A, part B, or part C.

[0216] Core column: It can include all information columns and all core parity-check columns. In other words, the core column is the column corresponding to the high code-rate area, or the column corresponding to part A + part B.

[0217] Core Matrix: It is the matrix area composed of all core rows and all core columns of the LDPC base matrix. In other words, the core matrix is the high code-rate area of the LDPC base matrix, or the part composed of part A and part B.

[0218] The "first base matrix" or "second base matrix" in this application satisfies the following conditions:

[0219] In the first sequence (such as the β sequence), when the value of the corresponding element in the i-th row is equal to 1, the column weight of the extended parity-check column corresponding to the i-th row is equal to 2 or 1, and among the 2 adjacent rows of the i-th row (i.e., the i + 1-th row and the i - 1-th row), only 1 row (if and only if 1 row) satisfies the following condition (which can be called the first condition): This row contains the extended parity-check column associated with the i-th row. For example, the element with a value of 1 in the extended parity-check column of the i-th row also has a value of 1 in this row, and i is an integer greater than zero.

[0220] For information on extended validation columns, please refer to the previous explanation. If the extended validation column is a column corresponding to Part C or Part E, it can also be called a raptor-like column. Alternatively, if the core validation column is a validation column in Part B with a column weight greater than 1 (Part B has 1 element both above and below its diagonal), the extended validation columns are the remaining validation columns excluding the core validation column.

[0221] Here, column weight refers to the number of non-zero elements in a column. When i equals 5, it corresponds to the 5th row of the first basis matrix. Referring to Figure 13 above, the elements of the first sequence (β sequence) corresponding to the 5th row of the first basis matrix have a value of 1. The column weight of the extended parity column in the 5th row of the first basis matrix is ​​2, and among the two adjacent rows of the 5th row (i.e., the 4th and 6th rows), only one row (specifically the 6th row in the schematic diagram of Figure 13) includes an element with a value of 1. At this time, the 6th row can be considered as the row that satisfies the first condition. It can be seen that the 5th and 6th rows contain the same extended parity column, and the column weight of this extended parity column is equal to 2.

[0222] Optionally, the first basis matrix or the second basis matrix further satisfies any one of the following conditions:

[0223] Condition 1: Except for the extended check column, the elements in the i-th row are orthogonal to the elements in the 1-th row that satisfy the first condition.

[0224] As mentioned earlier, the row satisfying the first condition can be either row i+1 or row i-1. That is, excluding the extended check column, the elements of row i are orthogonal to the elements of row i+1 or row i-1. Orthogonality can be understood as the positions where the element value is 1 in these two rows are disjoint. Continuing with the previous example, the elements of the β sequence corresponding to row 5 of the first basis matrix are equal to 1, and row 6 of the first basis matrix is ​​the row satisfying the first condition. Referring to Figure 13, excluding the extended check column, the elements of row 5 are [001100110000000011], and the elements of row 6 are [110011000101111000]. The elements of row 5 and row 6 are orthogonal.

[0225] In one description, the i-th row and the row that satisfies the first condition can be called a pairing row. That is, the i-th row and the (i+1)-th or (i-1)-th row can also be called a pairing row.

[0226] Condition 2: Except for the extended check column, the union of the elements in row i and row 1 that satisfies the first condition is the same as the elements in row i'.

[0227] In other words, excluding the extended check column, the union of the elements of row i and the adjacent rows i+1 or i-1 is the same as the elements of row i'. Here, i' is an integer less than i, and the specific value of i' is not restricted. Optionally, row i' is H. row-1 The first row. It can be understood that when the value of the first row is equal to row, using the method of this application, the obtained second row interval can be represented as H. row When the value of the first row is equal to row-1, the second row interval obtained using the method of this application can be represented as H. row-1 That is to say, H row-1 It refers to the second row interval when the value of the first row is equal to row-1.

[0228] For example, as shown in Figure 12b, when the value of the first row (e.g., row) is equal to 5, the value of the second row interval (e.g., H) is... row The range includes row indices from 2 to 6. When the first row value is equal to 4 (e.g., row-1), the second row range (e.g., H) contains row indices from 2 to 6. row-1 If the indexes contained in the second row are 1 to 4, then the interval H is... row The index of the first row is 1, meaning the i'th row is the first row, and the value of i' is equal to 1. Continuing with the previous example, the value of i is 5. The element of the first sequence corresponding to the 5th row is equal to 1. Among the two adjacent rows of the 5th row, the 6th row is the row that satisfies the first condition. Referring to Figure 13, excluding the extended check column, the element of the 5th row is [001100110000000011], and the element of the 6th row is [110011000101111000]. The union of the elements of the 5th and 6th rows is [111111110101111011], which is the same as the element of the 1st row.

[0229] Condition 3: If the element in row m and column j has a value of 1, the shift value in row m and column j is the same as the shift value in row i' and column j, or the difference between them is a constant C. It can be understood that the constant C can be equal to 0; when the constant C is equal to 0, the shift values ​​are considered to be the same.

[0230] Where m takes the value i, in which case row m is row i, or m takes the index of the first row that satisfies the first condition, in which case row m can be the (i+1)th row adjacent to row i, or row i-1, etc. Optionally, j takes the index of any column other than the extended check column, such as column j being any column other than the extended check column. Taking row m as an example of row i:

[0231] For example, if the translation value of the i-th row and j-th column is denoted as SV(i,j) and the translation value of the i'-th row and j-th column is denoted as SV(i′,j), then the following condition is met: SV(i,j)=SV(i′,j) (Formula 5)

[0232] Alternatively, SV(i,j) = SV(i′,j) + C (Formula 6)

[0233] Wherein, C is a constant, and the value of C is independent of the row index i and / or column index j. For example, C is a fixed value, and the value of C does not change with the row index i and / or column index j. That is to say, no matter what the row index i and / or column index j are specifically, C is a fixed value in the above formula 6.

[0234] In formulas 5 and 6, i' is an integer less than i, and the specific value of i' is not restricted. As explained in condition 2, the i'th row is H. row-1 The first row of the array. It can be understood that at this point, the i'th row and jth column is H. row-1 The first row and j-th column of the array. That is, in condition 3, when the element in the i-th row and j-th column is 1, the shift value of the i-th row and j-th column is related to H. row-1 The translation values ​​of the i'th row and jth column are the same, or the two differ by a constant C.

[0235] In the method shown in Figure 10 or Figure 14, when the first row value is 'row', the row index indicated by the first row interval includes the row indices from row 1 to row '. It can be understood that when the index of the first row of the first base matrix starts from 0, the row index indicated by the first row interval specifically includes 0 to row-1. When the index of the first row of the first base matrix starts from 1, the row index indicated by the first row interval specifically includes 1 to row (of course, this application mainly uses this case for illustration, and the following description will continue to use this case as an example).

[0236] For example, when the value of the first row is 5, its corresponding first row interval can be seen in Figure 12a, and its corresponding second row interval can be seen in Figure 12b. As another example, when the value of the first row is 6, as shown in Figure 16a, the row indices indicated by the first row interval can be 1 to 6. In the method shown in Figure 10 or Figure 14, the calculated first value is 2. Then, the first row interval can be shifted down two rows to obtain the second row interval, as shown in Figure 16b, where the row indices indicated by the second row interval are 3 to 8.

[0237] For example, when the value of the first row is 4, as shown in Figure 17, the row indices of the corresponding first row interval are rows 1 to 4. In the first base matrix, rows 1 to 4 are the rows corresponding to region A (or the core check rows). In this case, shifting the first row interval is no longer necessary, and the first device can use the base matrix corresponding to the first row interval (such as the third base matrix) to encode the information to be encoded. Alternatively, it can be understood that the second row interval is the same as the first row interval.

[0238] It should be noted that in the method shown in Figure 10 or Figure 14: if the row indicated by the first row interval is determined according to the encoding rate and the first base matrix, and the row is the row corresponding to region A or the core check row, then the encoding and decoding can be performed according to the first row interval, and the process of shifting the first row interval is not required.

[0239] In one possible implementation, when the value of the first row is row-1, the corresponding interval of the second row is represented as H. row-1 When the value of the first row is row, the corresponding interval of the second row is represented as H. row The second row interval H row-1 With the second row interval H row The relationship is related to the value of the element corresponding to the i-th row in the first sequence, where i is the interval H in the second row. row-1 The corresponding maximum row index + 1, where i is an integer greater than zero.

[0240] For example, when the value of the element corresponding to the i-th row in the first sequence is equal to 0, the interval H in the second row... row-1 With the second row interval H row The relationship between them satisfies the following: in the second row interval H row-1 Based on the above, add the i-th row to form the second row interval H. row .

[0241] Taking the first row value of 'row' as an example, the specific explanation is provided by H. row-1 Get H row The process: When the value of the first row, row, is equal to 7, the value of row-1 is equal to 6, as shown in Figure 16b. The second row interval H... row-1 The indicated row index is 3 to 8. The second row interval H... row-1 The next line is the 9th line, where i takes the value 9. As shown in Figure 18, the element in the first sequence corresponding to the 9th line is 0, that is, β(i) = β(9) = 0. At this time, we can find the value in the second line interval H. row-1 Based on the second row interval corresponding to row=6 (see the second row interval shown in Figure 16b), add a 9th row to form the second row interval H. row The second row interval H rowThe indicated row indices are 3 to 9, see Figure 18.

[0242] For example, when the value of the element corresponding to the i-th row in the first sequence is equal to 1, the interval H in the second row... row-1 With the second row interval H row The relationship between them satisfies the following: in the second row interval H row-1 Based on this, add the i-th row and the (i+1)-th row, and delete the interval H in the second row. row-1 The first row in the second row constitutes the interval H. row .

[0243] Taking the first row value of 'row' as an example, the specific explanation is provided by H. row-1 Get H row The process: When the value of the first row, row, is equal to 8, the value of row-1 is equal to 7, as shown in Figure 18. The second row interval H... row-1 The indicated row index is 3 to 9. The second row interval H... row-1 The next row is row 10, where i takes the value 10. As can be seen from the first column of Figure 19, the element in the first sequence corresponding to row 10 is 1, i.e., β(i) = β(10) = 1. At this point, we can determine the value of i in the second row interval H. row-1 Based on the second row interval corresponding to row=7 (see Figure 18 for the second row interval), add rows 10 and 11, and delete H. row-1 The first row (i.e., deleting the 3rd row) forms the second row interval H. row The second row interval H row The indicated row indices are 4 to 11, see Figure 19.

[0244] In the method of this application, the second row interval H corresponding to row-1 is used. row-1 It can be deduced that the second row interval H corresponds to row. row For example, we can first obtain the second row interval H. row-1 The index of the next row, such as the i-th row. When the element corresponding to the i-th row in the first sequence is 0 (i.e., β(i) = 0), then in H... row-1 Based on this, add extended check columns for the i-th row and the i-th row corresponding to it, forming the second row interval H corresponding to row. row Alternatively, when the element corresponding to the i-th row in the first sequence is 1 (i.e., β(i) = 1), then in H... row-1 Based on this, add the i-th row, the (i+1)-th row, and the extended validation columns corresponding to the i-th row and the (i+1)-th row respectively, and delete the interval H in the second row. row-1 The first row in the second row constitutes the interval H. rowFurthermore, as can be seen from the above description, regardless of the value of β(i), the number of rows added each time is 1. For example, when β(i) = 0, 1 row is added (such as the i-th row); when β(i) = 1, 2 rows are added (such as the i-th row and the (i+1)-th row), and one row is deleted (such as H). row-1 The first line in the code is essentially an additional line, thus supporting flexible bitrates that are completely consistent with NR-LDPC.

[0245] It should be noted that in condition 1 above, the concept of paired rows was defined. A paired row can refer to the i-th row and a row that satisfies the first condition; specifically, a paired row refers to the i-th row and the (i+1)-th row, or the i-th row and the (i-1)-th row. When the paired row specifically refers to the i-th row and the (i+1)-th row, it can be seen that when β(i) = 1 in the first sequence, the i-th row and the (i+1)-th row both appear in the second row interval H. row Of course, depending on the value of i, the first basis matrix can include multiple pairs of paired rows, and these multiple pairs of paired rows can simultaneously appear in the second row interval H. row Either the second basis matrix, or, simultaneously, not appearing in the second row interval H. row Or the second basis matrix. In one description, the second row interval H is... row If the maximum included row index is defined as the second row value row', then the paired rows can appear simultaneously or not appear simultaneously in rows 1 to row'.

[0246] With the above design, when the first row interval consists of consecutive row indices, a second row interval is obtained by shifting the first row interval. The second row interval also consists of consecutive row indices. The second row interval indicates a row-consecutive region in the first base matrix, and the corresponding second base matrix is ​​a row-consecutive region. This allows for the extraction of a continuous region from the first base matrix to form the second base matrix for encoding. Furthermore, the above shifting method is simple to implement in hardware, and it is easy to obtain matrices corresponding to different code rates.

[0247]

Example 2

[0248] Figure 20 provides a flowchart of another encoding method, which includes:

[0249] Step 2010: The first device encodes the information to be encoded according to the first base matrix and the first sequence to obtain the encoded information.

[0250] For example, the first base matrix is ​​used to represent the LDPC code. The first base matrix can also be called an LDPC matrix or a split LDPC matrix. The first base matrix can be predefined by the protocol, or determined by the first device and indicated to the second device, such as when the first device sends first indication information to the second device to indicate the first base matrix. The first sequence can also be called a split sequence. The first sequence can be predefined by the protocol, or determined by the first device and indicated to the second device, such as when the first device sends second indication information to the second device to indicate the first sequence. Alternatively, the first device and the second device can obtain the same first base matrix or first sequence based on the same method. This same method can be predefined by the protocol or agreed upon by both in advance, without limitation. For example, the first device or the second device can determine the first base matrix based on at least one of code length, code rate, or application scenario. For example, the first device and the second device can generate the same first sequence according to the method of this application. In this application, the first device as the sending end and the second device as the receiving end can obtain the same first base matrix and first sequence.

[0251] The first sequence can be represented by a sequence θ. The characteristics of the first sequence θ are described below. It is understood that the first sequence θ in this application can satisfy at least one of the following conditions:

[0252] 1) The length of the first sequence is equal to the number of rows in the first basis matrix. For any row i in the first basis matrix, there exists a corresponding θ(i) in the first sequence. For example, the first sequence θ = {θ(1), θ(2), θ(3)...θ(N)}, where N can be the number of rows in the first basis matrix. Figure 21 provides a schematic diagram of the correspondence between rows of the first basis matrix and the first sequence. The first column in Figure 21 is the first sequence θ. It can be seen that each row of the first basis matrix has a corresponding θ value. Specifically, referring to Figure 21, the θ values ​​corresponding to the first few rows of the first basis matrix are all 0, and the θ values ​​corresponding to the subsequent rows are 2, 5, 6, 4, etc.

[0253] 2) Any element θ(i) in the first sequence θ can be an integer less than i (i.e., θ(i) < i), or it can be a special character, such as 0 or -1, without restriction. For example, any row i in the first base matrix corresponds to element θ(i) in the first sequence θ. If θ(i) is equal to 4, it means that in the first base matrix, the element of row i is eliminated by the element of row 4, generating a new element of row i. It can be understood that if the θ value corresponding to a row is a special symbol, it means that the row does not need to be eliminated and can be considered a row that is normally expanded. It can be understood that if the row index of the first base matrix starts from 1, the special character can be represented by 0. If the row index of the first base matrix starts from 0, the special character needs to be represented by a character other than 0, such as -1.

[0254] In one interpretation, any element θ(i) in the first sequence θ can take the value of a row number in the first basis matrix or a special character. A special character can be understood as a character that is not a row number, such as -1 or 0 as in the previous example. The process of segmenting the first sequence and generating the next segment from the previous segment does not consider the case where the first sequence contains special characters. That is, the following description applies to the case where there are no special characters in the first sequence. Alternatively, if the first sequence contains special characters, it is necessary to first extract non-special characters at the corresponding positions in the first sequence. The extracted non-special characters satisfy the segmentation description of the first sequence in this application. For example, if the first sequence is 0, 0, 0, 0, 1, 2, 3, 4, 0, 0, 5, 1, 6, 2, 7, 3, 8, 4, where 0 is a special character, then extracting non-special characters at the corresponding positions in the first sequence yields 1, 2, 3, 4, 5, 1, 6, 2, 7, 3, 8, 4. The first sequence after truncation satisfies the features described in this application. For example, the first segment can be regarded as 1, 2, 3, 4, and the second segment can be regarded as 5, 1, 6, 2, 7, 3, 8, 4.

[0255] 3) In the first basis matrix, the position in the i-th row that has a value of 1 also has a value of 1 in the corresponding position in the θ(i) row, and the translation value of the i-th row is equal to that of the θ(i) row.

[0256] In one possible implementation, the first device can generate a second basis matrix based on a first basis matrix and a first sequence. For example, for the i-th row of the first basis matrix, the following process is performed: in the first sequence, determine θ(i) corresponding to the i-th row; eliminate elements of the i-th row with elements of the θ(i)-th row to generate new elements of the i-th row; where, in the first basis matrix, the value of i traverses sequentially from 1 to N, and N is the number of rows in the first basis matrix. The basis matrix generated in the above manner can be called the second basis matrix. The first device uses the second basis matrix to encode the information to be encoded, obtaining the encoded information. The second basis matrix can also be called an LDPC matrix, or a split LDPC matrix. The "encoding" mentioned here can refer to LDPC encoding. For example, LDPC encoding is performed on the information to be encoded to obtain the encoded information.

[0257] It is understood that the above description and explanation of the features of the first sequence do not constitute a limitation on this application. That is, the first sequence in the embodiments of this application may satisfy any one of the features in 1) to 3) above, or may not satisfy the features in 1) to 3) above. This application focuses on the following features of the first sequence:

[0258] The first sequence contains at least two segments, each containing at least one element. The elements in the next segment can be inferred from the elements in the previous segment. For example, the elements in the next segment are specifically the elements in the previous segment and their indices. Two adjacent segments in the first sequence can be represented as the i-th segment and the (i+1)-th segment, where i is a positive integer. The elements in the (i+1)-th segment can be inferred from the elements in the i-th segment. For example, the elements in the (i+1)-th segment are specifically the elements in the i-th segment and their indices. It can be understood that the index of the element in the i-th or (i+1)-th segment is the index of the corresponding row in the first base matrix. For example, the elements contained in the i-th segment are: element i1, element i2, ..., element in, and the indices of element 1, element 2, ..., element n are index i1, index i2, ..., index in, respectively. Then the elements contained in the (i+1)-th segment are: index i1, element i1, index i2, element i2, ..., index in, element in.

[0259] In one possible implementation, the following description is used: the indices of elements contained in any segment i of the first sequence satisfy the following: (M*2) i-1 +1,M*2 i-1 +2,…,M*2 i )(Formula 7)

[0260] Where M represents the number of core check rows contained in the first base matrix.

[0261] In one description, as shown in Formula 7 above, the index of the element contained in the i-th segment can be represented as {M*2}. i-1 +1, M*2 i-1 +2, ..., M*2 i The elements contained in the i-th segment can be represented as {θ(M*2}). i-1 +1), θ(M*2) i-1 +2), …, θ(M*2) i Then the elements contained in the (i+1)th segment satisfy the following:

[0262] {M*2 i-1 +1, θ(M*2) i-1 +1), M*2 i-1 +2, θ(M*2) i-1 +2), ..., M*2 i ,θ(M*2 i )}(Formula 8)

[0263] The number of elements in any segment i (or i+1) of the first sequence is related to the number of core check rows M in the first base matrix. For example, the structure of the first base matrix can be seen in Figure 15, which shows that the first base matrix contains core check rows and extended check rows. The number of core check rows can be represented by M, where M is a positive integer. For example, the number of elements in any segment i of the first sequence satisfies the following: M*2 i-1 .

[0264] For example, the first base matrix contains core check rows and extended check rows. The indices of the core check rows are 1, 2, ..., M, and the indices of the extended check rows are M+1, M+2, ..., etc. The core check rows do not need to be extended; instead, they are extended starting from row M+1, based on the first sequence θ. For example, the first sequence θ can be represented as {θ(M+1), θ(M+2), θ(M+3), ...}. During the elimination process, row M+1 of the first base matrix is ​​eliminated by row θ(M+1), generating a new row M+1. The elimination process for other rows in the first base matrix, such as row M+2 and row M+3, is similar and will not be described further. It can be understood that, in the description of this application, the index of the element in the first sequence essentially refers to the row index in the first base matrix corresponding to each element. For example, the row index of element θ(M+1) is M+1, and the row indices of elements θ(M+2) and θ(M+3) are M+2 and M+3 respectively.

[0265] In this application, the elements contained in the first sequence θ are segmented, and each segment contains M*2 elements. i-1There are 3 elements. Assuming M equals 3, when i = 1, the corresponding first segment contains 3 elements; when i = 2, the corresponding second segment contains 6 elements; when i = 3, the corresponding third segment contains 12 elements, and so on, without further reasoning.

[0266] In one description, the first sequence θ satisfies the following: θ = {1,2,…,M}∪{M+1,1,M+2,2,…,2M,M}∪{2M+1,M+1,1,2M+2,M+2,2,…,4M,3M,M},…,

[0267] As can be understood, in the above description, the first sequence θ contains at least one segment. The first segment contains elements {1,2,…,M}, the second segment contains elements {M+1,1,M+2,2,…,2M,M}, and the third segment contains elements {2M+1,M+1,1,2M+2,M2,2,…,4M,3M,M}. Taking the first segment as an example, the elements in the first segment are {1,2,…,M}. The index corresponding to element 1 is M+1, meaning θ(M+1) = 1. The index corresponding to element 2 is M+2, meaning θ(M+2) = 2, and so on. The index corresponding to element M is M+M, meaning θ(M+M) = M.

[0268] In a specific example, the first base matrix contains 3 core check rows and 20 extended check rows. The 3 core check rows are indexed from 1 to 3, and the 20 extended check rows are indexed from 4 to 24. The first base matrix contains 3 core check rows, where M is equal to 3. The first 3 core check rows do not require extension; rows 4 through 20 are extended according to the first sequence.

[0269] Since M = 3, then according to M*2 i-1 From this, we can deduce that the length of the first segment is M = 3, meaning it contains 3 elements. The indices of these 3 elements are 4 to 6, corresponding to rows 4 to 6 of the first base matrix. The length of the second segment is 2M = 6, meaning it contains 6 elements. The indices of these 6 elements are 7 to 12, corresponding to rows 7 to 12 of the first base matrix. The length of the third segment is 4M = 12, meaning the indices of these 12 elements are 13 to 24, corresponding to rows 13 to 24 of the first base matrix. The following explains the specific process of determining the elements contained in each segment:

[0270] For example, if the first segment contains the elements {1, 2, 3}, as described above, their corresponding indices are 4, 5, and 6. Therefore, based on the elements in the first segment and their indices, the elements in the second segment can be determined, such as {4, 1, 5, 2, 6, 3}. Similarly, if the indices of the elements in the second segment are 7, 8, 9, 10, 11, 12, then the elements in the third segment can be determined, such as {7, 4, 8, 1, 9, 5, 10, 2, 11, 6, 12, 3}. Likewise, as described above, the indices of the elements in the third segment are 13 to 24.

[0271] Rows 1 to 3 of the first base matrix are core check rows and do not require expansion. Rows 4 to 24 of the first base matrix are expanded check rows, which can be expanded according to the first sequence. The expansion process for row 4 is as follows: If the element corresponding to index 4 in the first sequence is 1 (specifically, the first element 1 in the first segment), the elements of row 1 and row 4 can be eliminated to generate new elements for row 4. The expansion process for row 5 is as follows: If the element corresponding to index 5 in the first sequence is 2 (specifically, the second element 2 in the first segment), the elements of row 5 can be eliminated to generate new elements for row 5. The expansion process for rows 6 to 24 of the first base matrix is ​​similar to the above process and will not be repeated.

[0272] It should be noted that the method shown in Figure 20 also includes the following steps:

[0273] Optionally, in step 2020: the first device sends the encoded information.

[0274] For example, the first device may directly send the encoded information, or the first device may process the encoded information accordingly (such as modulation) and then send the processed information. It is understood that the processed information contains at least the encoded information.

[0275] Accordingly, the second device receives the corresponding information. For example, the information received by the second device includes: the information sent by the first device, and further includes noise information superimposed on the information.

[0276] Figure 22 provides a flowchart of another decoding method, including:

[0277] Step 2210: The second device acquires the information to be decoded.

[0278] For example, the second device can receive information from the first device, which can be understood as a physical signal received via the air interface. The second device performs corresponding processing on the received information, such as noise reduction and demodulation, to obtain information to be decoded. This information to be decoded can be understood as the encoded information sent by the first device, or the information to be decoded may contain other information besides the encoded information sent by the first device, such as noise information.

[0279] Step 2220: The second device decodes the information to be decoded based on the first base matrix and the first sequence to obtain the decoded information.

[0280] For example, the second device determines the second basis matrix based on the first basis matrix and the first sequence. This process, as well as the generation method of the first sequence, can be seen in the description of the encoding side shown in Figure 20. The second device decodes the information to be decoded based on the second basis matrix to obtain the decoded information.

[0281] It is understood that the second device and the first device can obtain the same first base matrix and first sequence. For example, the first base matrix and first sequence can be predefined by the protocol. Alternatively, the first device can determine the first base matrix or first sequence and indicate it to the second device. For example, the second device may receive first indication information from the first device for indicating the first base matrix, or second indication information for indicating the first sequence, etc. Alternatively, the first and second devices can obtain or generate the same first base matrix or first sequence in the same way; this same method can be predefined by the protocol, or agreed upon in advance by both parties, without restriction.

[0282] For example, the first or second basis matrix can be used to represent the LDPC code, and the information to be decoded can be LDPC decoded to obtain the decoded information. There are no restrictions on the decoding algorithm for the LDPC code. For example, it can be a min-sum decoding algorithm (MS) or a belief-propagation decoding algorithm (BP), etc.

[0283] For example, the method of Embodiment 1 or Embodiment 2 of this application can be compared with the current NR BG1 method through simulation: As shown in Figure 23, the horizontal axis represents the code rate, and the vertical axis represents the difference in signal-to-noise ratio (SNR). Specifically, the vertical axis can be the difference in SNR when the condition of BLER@1e-3 is met. Here, BLER stands for Block Error Rate, and 1e-3 is scientific notation, representing 10^6 ohms. -3The solid circle ● represents the curve corresponding to the difference in SNR of the actual transmitted information between the method of this application (such as the method of Embodiment 1 or Embodiment 2) and the method of NR BG1 when LDPC decoding iteration is 20 times (Literation = 20). The hollow circle ○ represents the curve corresponding to the difference in SNR of the actual transmitted information between the method of this application (such as the method of Embodiment 1 or Embodiment 2) and the method of NR BG1 when LDPC decoding is equivalently 20 times (Equivalent Literation = 20). It can be understood that when the difference is greater than zero, it means that the method shown in Embodiment 1 or Embodiment 2 has better performance, and vice versa, it means that the method of NR BG1 has better performance. As can be seen from Figure 23, regardless of the decoding conditions, in each code rate range, the method shown in Embodiment 1 or Embodiment 2 has a performance gain compared to the NR BG1 scheme.

[0284] In the embodiments provided above, the methods provided by the embodiments of this application have been described from the perspective of the interaction between the first device and the second device. To implement the functions of the methods provided by the embodiments of this application, the first device and the second device may include hardware structures and / or software modules, implementing the above functions in the form of hardware structures, software modules, or a combination of hardware structures and software modules. Whether a particular function is executed in the form of hardware structures, software modules, or a combination of hardware structures and software modules depends on the design constraints of the specific application of the technical solution.

[0285] Based on the same design concept as the above-described method embodiments, Figures 24 and 25 are schematic diagrams of possible communication devices provided in the embodiments of this application. These communication devices can realize the functions implemented by the first device or the second device in the above-described method embodiments, and therefore may achieve the beneficial effects of the above-described method embodiments. In the embodiments of this application, the communication device may be the first device or the second device, or a unit, module, or component (such as a chip, chip system, circuit, processor, or others) applied in the first device or the second device. In the following description, the term "unit" will be used as an example. For example, in the following description, the communication device includes a processing unit and a transceiver unit as an example. The processing unit in the following description can also be replaced by: processing module or processing component, etc. The transceiver unit can also be replaced by: transceiver unit or transceiver component. For example, the transceiver component may refer to a communication module.

[0286] As shown in Figure 24, the communication device 2400 includes a processing unit 2410 and a transceiver unit 2420. The communication device 2400 is used to implement the function of the first device in the method shown in Figure 10 or Figure 20, or to implement the function of the second device in the method shown in Figure 14 or Figure 22.

[0287] Optionally, the transceiver unit 2420 may also be referred to as an output unit, an interface unit, or a communication unit, etc. In one possible implementation, the transceiver unit 2420 includes at least one of a transmitting unit or a receiving unit. The transmitting unit and the receiving unit may be integrated together, or they may be two independent units, etc.

[0288] When the communication device 2400 is used to implement the function of the first device in the method shown in FIG10, specifically: the processing unit 2410 is used to determine a first row interval according to the encoding code rate and the first base matrix, wherein the first row interval is composed of the indices of a portion of the rows contained in the first base matrix; the processing unit 2410 is also used to encode the information to be encoded according to the second base matrix corresponding to the second row interval to obtain encoded information, wherein the second row interval is obtained by shifting the first row interval, and the second base matrix is ​​composed of the rows indicated by the second row interval in the first base matrix. Optionally, the transceiver unit 2420 is used to transmit the encoded information.

[0289] When the communication device 2400 is used to implement the function of the second device in the method shown in FIG14, specifically: the processing unit 2410 is used to acquire the information to be decoded; the processing unit 2410 is also used to determine a first row interval according to the encoding code rate and the first base matrix, wherein the first row interval is composed of the indices of some rows contained in the first base matrix; the processing unit 2410 is also used to decode the information to be decoded according to the second base matrix corresponding to the second row interval to obtain decoded information, wherein the second row interval is obtained by shifting the first row interval, and the second base matrix is ​​composed of the rows indicated by the second row interval in the first base matrix. Optionally, the transceiver unit 2420 is used to receive the information to be decoded.

[0290] When the communication device 2400 is used to implement the function of the first device in the method shown in FIG20, specifically: the processing unit 2410 is used to encode the information to be encoded according to the first base matrix and the first sequence to obtain the encoded information; wherein, the first sequence contains at least the i-th segment and the (i+1)-th segment, and the elements contained in the (i+1)-th segment include: the elements contained in the i-th segment and the index of the elements contained in the i-th segment, where i is an integer greater than zero, the length of the first sequence is equal to the number of rows contained in the first base matrix, and the index of the element contained in the i-th segment or the (i+1)-th segment is the index of the corresponding row in the first base matrix. Optionally, the transceiver unit 2420 is used to transmit the encoded information.

[0291] When the communication device 2400 is used to implement the function of the second device in the method shown in FIG22, specifically: the processing unit 2410 is used to acquire the information to be decoded; the processing unit 2410 is also used to decode the information to be decoded according to the first base matrix and the first sequence to obtain decoded information; wherein, the first sequence contains at least the i-th segment and the (i+1)-th segment, the elements contained in the (i+1)-th segment include: the elements contained in the i-th segment and the index of the elements contained in the i-th segment, i is an integer greater than zero, the length of the first sequence is equal to the number of rows contained in the first base matrix, and the index of the element contained in the i-th segment or the (i+1)-th segment is the index of the corresponding row in the first base matrix. Optionally, the transceiver unit 2420 is used to receive the information to be decoded.

[0292] For details on the specific implementation process of the processing unit 2410 and the transceiver unit 2420, please refer to the description of the method shown in Figures 10, 14, 20 or 22 of the previous method embodiments, which will not be repeated here.

[0293] It is understood that the division of units in this application embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods. In addition, the functional units in this application embodiment can be integrated into a physical device (e.g., in a processor), or each functional unit can be a separate physical device, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional module, etc.

[0294] As shown in Figure 25, the communication device 2500 includes a processor 2510 and an interface circuit 2520. The processor 2510 and the interface circuit 2520 are coupled to each other. It is understood that the interface circuit 2520 can be a transceiver or an input / output interface. Optionally, the communication device 2500 may also include a memory 2530 for storing instructions executed by the processor 2510, or storing input data required by the processor 2510 to execute instructions, or storing data generated after the processor 2510 executes instructions.

[0295] When the communication device 2500 is used to implement the method shown in FIG10, FIG14, FIG20 or FIG22, the processor 2510 is used to implement the function of the processing unit 2410, and the interface circuit 2520 is used to implement the function of the transceiver unit 2420.

[0296] When the aforementioned communication device is a chip / module applied to the first device, the chip / module implements the functions of the first device in the above method embodiments. The chip / module receives information sent to the first device by the second device through other modules in the first device; or, the chip / module sends information to other modules in the first device, which is information sent from the first device to the second device.

[0297] When the aforementioned communication device is a chip / module applied to the second device, the chip / module implements the functions of the second device in the above method embodiments. The chip / module receives information from other modules in the second device, which is information sent from the first device to the second device; or, the chip / module sends information to other modules in the second device, which is information sent from the second device to the first device.

[0298] This application embodiment also provides a chip, which can be a chip applied in a first device, simply referred to as a first device chip, used to implement the function of the first device in the method shown in FIG10 or FIG20. Alternatively, the chip can be a chip applied in a second device, simply referred to as a second device chip, used to implement the function of the second device in the method shown in FIG14 or FIG22. For example, the chip can be a modem chip, also known as a baseband chip, or a system-on-chip (SoC) chip containing a modem core, or a system-in-package (SIP) chip. As shown in FIG26:

[0299] The chip includes at least one processor for implementing the functions of the first or second device in the methods shown in Figures 10, 14, 20, or 22. For example, in Figure 26, the plurality of processors are represented as processors #1 to #N, where N is an integer greater than or equal to 1. For example, the processor may be a microprocessor, such as an X256 or ARM, a microcontroller, DSP, FPGA, GPU, programmable logic device, state machine, gated logic, discrete hardware circuitry, and other suitable hardware configured to perform the appropriate functions.

[0300] Optionally, the chip may further include at least one memory for storing computer program instructions and / or data. The memory is coupled to the processor. The coupling in this embodiment is an indirect coupling or communication connection between devices, units, or modules, which may be electrical, mechanical, or other forms, used for information exchange between devices, units, or modules. The processor and memory operate collaboratively; the processor executes the program instructions stored in the memory to implement the method of the first or second device shown in Figures 10, 14, 20, or 22 of this embodiment. At least one of the at least one memory may be included in the processor.

[0301] The chip may also include at least one communication interface for communicating with other devices via a transmission medium. In this embodiment, the communication interface may be a transceiver, circuit, bus, module, or other type of communication interface, and may be referred to as a bus interface. In this embodiment, when the communication interface is a transceiver, the transceiver may include an independent receiver, an independent transmitter, or a transceiver with integrated transceiver functions, or an interface circuit.

[0302] In this embodiment, the connection medium between the processor, memory, and communication interface is not limited. Optionally, in Figure 26, the processor, memory, and communication interface are connected via a bus. The bus may include an address bus, a data bus, and a control bus, etc. In Figure 26, only a single thick line is used to represent this, but this does not indicate that there is only one bus or one type of bus. In one possible implementation, the bus may include any number of interconnect buses and bridges, depending on the specific application of the chip and overall design constraints. The bus couples various circuits together, such as the processor, memory, and communication interface. The bus can also link various other circuits, such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further.

[0303] This application also provides a communication device, which includes a processor for implementing the function of the first device in the method shown in FIG10 or FIG20, or the function of the second device in the method shown in FIG14 or FIG22. Optionally, the communication device further includes a memory, with the processor coupled to the memory. The processor is used to execute computer programs or instructions stored in the memory to implement the function of the first device in the method shown in FIG10 or FIG20, or the function of the second device in the method shown in FIG14 or FIG22. Optionally, the communication device may be a chip or a chip system.

[0304] This application embodiment also provides a communication device, including a processor and an interface circuit. The interface circuit is used to receive signals from other devices outside the device and transmit them to the processor, or to send signals from the processor to other devices outside the device. The processor is used to implement the function of the first device in the method shown in FIG10 or FIG20, or the function of the second device in the method shown in FIG14 or FIG22, through logic circuits or execution code instructions.

[0305] This application also provides a computer-readable storage medium storing instructions, which may also be referred to as a computer program, computer program code, etc. These instructions, when executed on a computer, cause the computer to perform the function of the first device in the method shown in FIG10 or FIG20, or the function of the second device in the method shown in FIG14 or FIG22.

[0306] This application also provides a computer program product, including a computer program or instructions, which, when run on a computer, implement the function of the first device in the method shown in FIG10 or FIG20, or the function of the second device in the method shown in FIG14 or FIG22.

[0307] It is understood that the processor in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor or any conventional processor.

[0308] The memory in the embodiments of this application may be random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), register, hard disk, portable hard disk, CD-ROM, or any other form of storage medium known in the art.

[0309] The method steps in the embodiments of this application can be implemented in hardware or in software instructions executable by a processor. The software instructions can consist of corresponding software modules, which can be stored in random access memory, flash memory, read-only memory, programmable read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium well known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. The storage medium can also be a component of the processor. The processor and the storage medium can reside in an ASIC.

[0310] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. This computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of this application are performed entirely or partially. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a second device, a user equipment, or other programmable device. The computer program or instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, the computer program or instructions can be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center integrating one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a digital video optical disc; or it can be a semiconductor medium, such as a solid-state drive. The computer-readable storage medium may be a volatile or non-volatile storage medium, or may include both types of storage media.

[0311] In the various embodiments of this application, unless otherwise specified or in case of logical conflict, the terminology and / or descriptions of different embodiments are consistent and can be referenced by each other. The technical features of different embodiments can be combined to form new embodiments according to their inherent logical relationship.

Claims

1. An encoding method, characterized in that, include: Based on the encoding bitrate and the first base matrix, the first row interval is determined, and the first row interval is composed of the indices of a portion of the rows contained in the first base matrix; The information to be encoded is encoded according to the second base matrix corresponding to the second row interval to obtain the encoded information. The second row interval is obtained by shifting the first row interval. The second base matrix is ​​composed of the rows indicated by the second row interval in the first base matrix.

2. A decoding method, characterized in that, include: Obtain the information to be decoded; Based on the encoding bitrate and the first base matrix, the first row interval is determined, and the first row interval is composed of the indices of a portion of the rows contained in the first base matrix; The information to be decoded is decoded according to the second base matrix corresponding to the second row interval to obtain the decoded information. The second row interval is obtained by shifting the first row interval. The second base matrix is ​​composed of the rows indicated by the second row interval in the first base matrix.

3. The method as described in claim 1 or 2, characterized in that, The second row interval is obtained by shifting the first row interval, including: The index of each row indicated by the first row interval is incremented by a first value to obtain the second row interval; In the first base matrix, the row indicated by the second row interval is extracted to obtain the second base matrix.

4. The method according to any one of claims 1 to 3, characterized in that, The second row interval is obtained by shifting the first row interval based on the first sequence. The length of the first sequence is equal to the number of rows contained in the first base matrix, and the elements contained in the first sequence are either 0 or 1.

5. The method as described in claim 3 or 4, characterized in that, The first value is equal to the difference between the second row value and the first row value. The first row value is the index of the largest row in the first row interval, and the second row value is the index of the largest row in the second row interval.

6. The method as described in claim 5, characterized in that, Also includes: The value of the first row is determined based on the code rate of the encoding and the number of information columns contained in the first base matrix; The second row value is determined based on the first row value and the first sequence.

7. The method as described in claim 6, characterized in that, The process of determining the second row value based on the first row value and the first sequence satisfies the following: x + y = row'; x + y / 2 = row; Where row represents the first row value, row' represents the second row value, x represents the number of elements in the first base matrix from row 1 to row' with a value of 0 in the first sequence, and y represents the number of elements in the first base matrix from row 1 to row' with a value of 1 in the first sequence.

8. The method according to any one of claims 5 to 7, characterized in that, The first row interval contains a row index range from 1 to the first row value; the second row interval contains a row index range from (second row value - first row value + 1) to the second row value.

9. The method according to any one of claims 1 to 8, characterized in that, The first basis matrix or the second basis matrix satisfies the following condition: In the first sequence, when the value of the element corresponding to the i-th row is equal to 1, the column weight of the extended check column corresponding to the i-th row is equal to 2 or 1, and among the two adjacent rows of the i-th row, only one row satisfies the following first condition: the row contains the extended check column associated with the i-th row, where i is an integer greater than zero; The length of the first sequence is equal to the number of rows in the first base matrix, and the elements in the first sequence are either 0 or 1.

10. The method as described in claim 9, characterized in that, The first basis matrix or the second basis matrix also satisfies the following condition: Apart from the extended check column, the elements in the i-th row are orthogonal to the elements in the 1-th row that satisfy the first condition.

11. The method as described in claim 9 or 10, characterized in that, The first basis matrix or the second basis matrix also satisfies the following condition: In addition to the extended verification column, the union of the elements of the i-th row and the elements of the 1-th row that satisfy the first condition is the same as the elements of the i'-th row, where i' is an integer less than i.

12. The method according to any one of claims 9 to 11, characterized in that, The first basis matrix or the second basis matrix also satisfies the following condition: If the element in row m and column j is 1, then the value of m is equal to i, or m is the index of row 1 that satisfies the first condition. The shift value of row m and column j is the same as the shift value of row i' and column j, or the difference between them is a constant C, where C is independent of the row index and / or column index, and i' is an integer less than i.

13. An encoding method, characterized in that, include: Based on the first basis matrix and the first sequence, the information to be encoded is encoded to obtain the encoded information. The first sequence contains at least an i-th segment and an (i+1)-th segment. The elements contained in the (i+1)-th segment include the elements contained in the i-th segment and the index of the elements contained in the i-th segment, where i is an integer greater than zero. The length of the first sequence is equal to the number of rows contained in the first base matrix. The index of the element contained in the i-th segment or the (i+1)-th segment is the index of the corresponding row in the first base matrix.

14. A decoding method, characterized in that, include: Obtain the information to be decoded; The information to be decoded is decoded based on the first basis matrix and the first sequence to obtain the decoded information; The first sequence contains at least an i-th segment and an (i+1)-th segment. The elements contained in the (i+1)-th segment include the elements contained in the i-th segment and the index of the elements contained in the i-th segment, where i is an integer greater than zero. The length of the first sequence is equal to the number of rows contained in the first base matrix. The index of the element contained in the i-th segment or the (i+1)-th segment is the index of the corresponding row in the first base matrix.

15. The method as described in claim 13 or 14, characterized in that, The number of elements contained in the i-th segment or the (i+1)-th segment is related to the number of core check rows contained in the first base matrix.

16. The method according to any one of claims 13 to 15, characterized in that, The index of the element contained in the i-th segment satisfies the following: (M*2) i-1 +1,M*2 i-1 +2,…,M*2 i ) Where M represents the number of core check rows contained in the first base matrix.

17. The method according to any one of claims 13 to 16, characterized in that, The elements contained in the (i+1)th segment, including the elements contained in the i-th segment and their indices, satisfy the following: M*2 i-1 +1, θ(M*2) i-1 +1), M*2 i-1 +2, θ(M*2) i-1 +2), ..., M*2 i ,θ(M*2 i )} Where M*2 i-1 +1, M*2 i-1 +2, ..., M*2 i θ(M*2) represents the index of the element contained in the i-th segment; i-1 +1), θ(M*2) i-1 +2), …, θ(M*2) i ) represents the elements contained in the i-th segment, and M represents the number of core check rows contained in the first base matrix.

18. A communication device, characterized in that, Includes units for implementing the method as described in any one of claims 1, 3 to 12, or units as described in any one of claims 13, 15 to 17.

19. A communication device, characterized in that, Includes a processor configured to cause the communication device to perform the method as claimed in any one of claims 1, 3 to 12, or the method as claimed in any one of claims 13, 15 to 17.

20. A communication device, characterized in that, Includes units for implementing the method as described in any one of claims 2 to 12, or units for implementing the method as described in any one of claims 14 to 17.

21. A communication device, characterized in that, Includes a processor configured to cause the communication device to perform the method as described in any one of claims 2 to 12, or the method as described in any one of claims 14 to 17.

22. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores instructions that, when executed, cause the communication device to perform the method as claimed in any one of claims 1, 3 to 12, or the method as claimed in any one of claims 2 to 12, or the method as claimed in any one of claims 13, 15 to 17, or the method as claimed in any one of claims 14 to 17.

23. A computer program product, characterized in that, The computer program product includes instructions that, when executed, cause the communication device to perform the method as claimed in any one of claims 1, 3 to 12, or the method as claimed in any one of claims 2 to 12, or the method as claimed in any one of claims 13, 15 to 17, or the method as claimed in any one of claims 14 to 17.

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