Printed wiring board
The printed circuit board design addresses connection failures by using overlapping and offset lands with connecting conductor layers within through-holes, reducing defects and improving electrical connectivity.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- SUMITOMO ELECTRIC PRINTED CIRCUITS INC
- Filing Date
- 2025-01-17
- Publication Date
- 2026-07-23
AI Technical Summary
The formation of through-holes in multilayer printed circuit boards leads to increased defects in connecting conductive layers, particularly as the depth of the through-holes increases, resulting in higher likelihood of connection failures between lands.
A printed circuit board design that includes specific arrangements of conductor and dielectric layers, with overlapping and offset lands, and the use of connecting conductor layers within through-holes to reduce the depth of connections, thereby minimizing defects in the formation of connecting conductor layers on inner walls.
The design suppresses connection failures between lands by reducing the depth of through-holes required for electrical connections, enhancing the reliability of land connections.
Smart Images
Figure JP2025001326_23072026_PF_FP_ABST
Abstract
Description
Printed wiring board
[0001] The present disclosure relates to a printed wiring board.
[0002] The printed wiring board described in Japanese Patent Application Laid-Open No. 2000-216603 (Patent Document 1) has a dielectric layer and a first signal pattern. The first dielectric layer has a first main surface and a second main surface which is the opposite surface of the first main surface. The signal pattern is disposed on the first main surface. A high-frequency signal flows through the signal pattern.
[0003] Japanese Patent Application Laid-Open No. 2000-216603
[0004] The printed wiring board of the present disclosure includes a first dielectric layer having a first main surface and a second main surface which is the opposite surface of the first main surface, a first conductor layer disposed on the first main surface, a second conductor layer disposed on the second main surface, a second dielectric layer disposed on the first main surface so as to cover the first conductor layer and having a third main surface facing the first main surface and a fourth main surface which is the opposite surface of the third main surface, a third dielectric layer disposed on the second main surface so as to cover the second conductor layer and having a fifth main surface facing the second main surface and a sixth main surface which is the opposite surface of the fifth main surface, a third conductor layer disposed on the fourth main surface, and a fourth conductor layer disposed on the sixth main surface. The third conductor layer has a first signal pattern and a first land connected to the first signal pattern. The fourth conductor layer has a second signal pattern and a second land connected to the second signal pattern. The first land and the second land are electrically connected to the lands of each of the first conductor layer and the second conductor layer.
[0005] Figure 1 is a first plan view of the printed circuit board 100. Figure 2 is a first bottom view of the printed circuit board 100. Figure 3 is a second plan view of the printed circuit board 100. Figure 4 is a second bottom view of the printed circuit board 100. Figure 5 is a third bottom view of the printed circuit board 100. Figure 6 is a cross-sectional view of the printed circuit board 100 along VI-VI in Figure 1. Figure 7 is a manufacturing process diagram of the printed circuit board 100. Figure 8 is a cross-sectional view illustrating the patterning process S2. Figure 9 is a cross-sectional view illustrating the interlayer connection process S3. Figure 10 is a cross-sectional view illustrating the dielectric layer attachment process S4. Figure 11 is a cross-sectional view illustrating the patterning process S5. Figure 12 is a cross-sectional view illustrating the interlayer connection process S6. Figure 13 is a cross-sectional view of the printed circuit board 100 according to Modification 1. Figure 14 is a cross-sectional view of the printed circuit board 100 according to Modification 2.
[0006] [Problems this disclosure aims to solve] When multilayering printed circuit boards, it is necessary to form through-holes that penetrate multiple dielectric layers and to connect lands by forming connecting conductive layers within these through-holes. However, as the depth of the through-holes increases, defects in the formation of the connecting conductive layer on the inner wall surface of the through-holes become more likely, and consequently, connections between lands become more likely. This disclosure has been made in view of the problems of the prior art described above. More specifically, this disclosure provides a printed circuit board that can suppress connections between lands.
[0007] [Effects of this disclosure] According to the printed circuit board of this disclosure, connection failures between lands can be suppressed.
[0008] [Outline of Embodiments] First, embodiments of the present disclosure will be listed and described.
[0009] (1) A printed circuit board according to one embodiment comprises: a first dielectric layer having a first main surface and a second main surface opposite to the first main surface; a first conductor layer disposed on the first main surface; a second conductor layer disposed on the second main surface; a second dielectric layer disposed on the first main surface so as to cover the first conductor layer and having a third main surface facing the first main surface and a fourth main surface opposite to the third main surface; a third dielectric layer disposed on the second main surface so as to cover the second conductor layer and having a fifth main surface facing the second main surface and a sixth main surface opposite to the fifth main surface; a third conductor layer disposed on the fourth main surface; and a fourth conductor layer disposed on the sixth main surface. The third conductor layer has a first signal pattern and a first land connected to the first signal pattern. The fourth conductor layer has a second signal pattern and a second land connected to the second signal pattern. The first land and the second land are electrically connected to the lands of the first conductor layer and the second conductor layer, respectively. According to the printed circuit board described in (1) above, poor connections between pads can be suppressed.
[0010] (2) In the printed circuit board described in (1) above, the first conductor layer may have a third land. The second conductor layer may have a fourth land. The first land, second land, third land and fourth land may be arranged to overlap each other in a plan view.
[0011] (3) In the printed circuit board described in (1) above, the first conductor layer may have a third land. The second conductor layer may have a fourth land. The third and fourth lands may be arranged so as to overlap each other in a plan view. The first and second lands may be arranged so that only one of the first and second lands overlaps the third and fourth lands in a plan view.
[0012] (4) In the printed circuit board described in (1) above, the first conductor layer may have fifth and sixth lands which are offset from each other in a plan view, and the second conductor layer may have seventh and eighth lands which are offset from each other in a plan view. The first and fifth lands may be arranged to overlap each other in a plan view. The sixth and seventh lands may be arranged to overlap each other in a plan view. The second and eighth lands may be arranged to overlap each other in a plan view.
[0013] (5) In the printed circuit boards described in (1) to (4) above, the first signal pattern and the second signal pattern may form a single-line signal line.
[0014] (6) In the printed circuit boards described in (1) to (4) above, the first signal pattern and the second signal pattern may constitute one of a pair of differential signal lines.
[0015] [Details of Embodiments] Next, the details of embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and redundant descriptions will not be repeated. The printed circuit board according to the embodiment will be referred to as printed circuit board 100.
[0016] (Configuration of the printed circuit board 100) The configuration of the printed circuit board 100 is described below.
[0017] Figure 1 is a first plan view of the printed circuit board 100. Figure 2 is a first bottom view of the printed circuit board 100. Figure 3 is a second plan view of the printed circuit board 100. In Figure 3, the dielectric layer 40 and the structure above it are not shown. Figure 4 is a second bottom view of the printed circuit board 100. In Figure 4, the dielectric layer 80 and the structure below it are not shown. Figure 5 is a third bottom view of the printed circuit board 100. In Figure 5, the dielectric layer 60 and the structure below it are not shown. Figure 6 is a cross-sectional view of the printed circuit board 100 along VI-VI in Figure 1. As shown in Figures 1 to 6, the printed circuit board 100 has a dielectric layer 10, a conductor layer 20, a conductor layer 30, a dielectric layer 40, a conductor layer 50, a dielectric layer 60, a conductor layer 70, a dielectric layer 80, and a conductor layer 90.
[0018] The dielectric layer 10 has a main surface 10a and a main surface 10b. The main surface 10b is the opposite surface to the main surface 10a. The main surfaces 10a and 10b are end faces in the thickness direction of the dielectric layer 10. The dielectric layer 10 is made of a dielectric material. The dielectric layer 10 is made of, for example, a fluororesin.
[0019] The conductor layer 20 is arranged on the main surface 10a. The conductor layer 20 is made of a conductive material. For example, the conductor layer 20 is made of copper or a copper alloy. The conductor layer 20 has a signal pattern 21 and a ground pattern 22. In a plan view, the signal pattern 21 extends along the first direction DR1. The conductor layer 20 also has lands 21a and lands 21b. Lands 21a and 21b are connected to one end and the other end of the signal pattern 21 in the first direction DR1, respectively.
[0020] In a plan view, the ground pattern 22 surrounds the signal pattern 21. There is a gap between the ground pattern 22 and the signal pattern 21. That is, the main surface 10a is exposed between the ground pattern 22 and the signal pattern 21.
[0021] The conductor layer 30 is arranged on the main surface 10b. The conductor layer 30 is made of a conductive material. For example, the conductor layer 30 is made of copper or a copper alloy. The conductor layer 30 has a signal pattern 31 and a ground pattern 32. The signal pattern 31 extends along the first direction DR1. The conductor layer 30 also has lands 31a and lands 31b. Lands 31a and 31b are connected to one end and the other end of the signal pattern 31 in the first direction DR1, respectively. In a plan view, land 31a overlaps with land 21b.
[0022] Through holes 10c are formed in the land 31a and the dielectric layer 10. Land 21b is exposed through the through holes 10c. The printed circuit board 100 further has a connecting conductor layer 33. The connecting conductor layer 33 is formed within the through holes 10c. More specifically, the connecting conductor layer 33 is arranged on the land 21b exposed from the through holes 10c, on the inner wall surface of the through holes 10c, and on the land 31a. The connecting conductor layer 33 electrically connects the land 21b and the land 31a to each other. The connecting conductor layer 33 is made of, for example, copper or a copper alloy.
[0023] In a plan view, the ground pattern 32 surrounds the signal pattern 31. There is a gap between the ground pattern 32 and the signal pattern 31. That is, the main surface 10b is exposed between the ground pattern 32 and the signal pattern 31.
[0024] The dielectric layer 40 is arranged on the main surface 10a so as to cover the conductor layer 20 (signal pattern 21, ground pattern 22). The dielectric layer 40 has a first layer 41 and a second layer 42. The first layer 41 is a layer formed of adhesive. The first layer 41 is arranged on the main surface 10a so as to cover the conductor layer 20. The second layer 42 is a layer formed of, for example, fluororesin. The second layer 42 is formed on the first layer 41. The dielectric layer 40 has a main surface 40a and a main surface 40b. The main surface 40a is opposite to the main surface 10a. The main surfaces 40a and 40b are end faces in the thickness direction of the dielectric layer 40. The first layer 41 forms the main surface 40a, and the second layer 42 forms the main surface 40b.
[0025] The conductor layer 50 is arranged on the main surface 40b. The conductor layer 50 is made of a conductive material. For example, the conductor layer 50 is made of copper or a copper alloy. The conductor layer 50 has a signal pattern 51 and a ground pattern 52. The signal pattern 51 extends along the first direction DR1. The conductor layer 50 also has lands 51a. The lands 51a are connected to one end of the signal pattern 51 in the first direction DR1.
[0026] Land 51a overlaps with land 21a in a plan view. Through holes 40c are formed in land 51a and the dielectric layer 40. Land 21a is exposed through the through holes 40c. The printed circuit board 100 further has a connecting conductor layer 53. The connecting conductor layer 53 is formed within the through holes 40c. More specifically, the connecting conductor layer 53 is arranged on land 21a exposed from the through holes 40c, on the inner wall surface of the through holes 40c, and on land 51a. Land 21a and land 51a are electrically connected to each other by the connecting conductor layer 53. The connecting conductor layer 53 is made of, for example, copper or a copper alloy.
[0027] In a plan view, the ground pattern 52 surrounds the signal pattern 51. There is a gap between the ground pattern 52 and the signal pattern 51. That is, the main surface 40b is exposed between the ground pattern 52 and the signal pattern 51.
[0028] The dielectric layer 60 is arranged on the main surface 10b so as to cover the conductor layer 30 (signal pattern 31, ground pattern 32). The dielectric layer 60 has a first layer 61 and a second layer 62. The first layer 61 is a layer formed of adhesive. The first layer 61 is arranged on the main surface 10b so as to cover the conductor layer 30. The second layer 62 is a layer formed of, for example, fluororesin. The second layer 62 is formed on the first layer 61. The dielectric layer 60 has a main surface 60a and a main surface 60b. The main surface 60a is opposite to the main surface 10b. The main surfaces 60a and 60b are end faces in the thickness direction of the dielectric layer 60. The first layer 61 forms the main surface 60a, and the second layer 62 forms the main surface 60b.
[0029] The conductor layer 70 is arranged on the main surface 60b. The conductor layer 70 is made of a conductive material. For example, the conductor layer 70 is made of copper or a copper alloy. The conductor layer 70 has a signal pattern 71 and a ground pattern 72. The signal pattern 71 extends along the first direction DR1. The conductor layer 70 also has lands 71a. The lands 71a are connected to one end of the signal pattern 71 in the first direction DR1.
[0030] Land 71a overlaps with land 31b in a plan view. Through holes 60c are formed in land 71a and the dielectric layer 60. Land 31b is exposed through the through holes 60c. The printed circuit board 100 further has a connecting conductor layer 73. The connecting conductor layer 73 is formed within the through holes 60c. More specifically, the connecting conductor layer 73 is arranged on land 31b exposed from the through holes 60c, on the inner wall surface of the through holes 60c, and on land 71a. Land 51a and land 31b are electrically connected to each other by the connecting conductor layer 73. The connecting conductor layer 73 is made of, for example, copper or a copper alloy.
[0031] In a plan view, the ground pattern 72 surrounds the signal pattern 71. There is a gap between the ground pattern 72 and the signal pattern 71. That is, the main surface 60b is exposed between the ground pattern 72 and the signal pattern 71.
[0032] The dielectric layer 80 is arranged on the main surface 60b so as to cover the conductor layer 70 (signal pattern 71, ground pattern 72). The dielectric layer 80 has a first layer 81 and a second layer 82. The first layer 81 is a layer formed of adhesive. The first layer 81 is arranged on the main surface 60b so as to cover the conductor layer 70. The second layer 82 is a layer formed of, for example, fluororesin. The second layer 82 is formed on the first layer 81. The dielectric layer 80 has a main surface 80a and a main surface 80b. The main surface 80a is opposite to the main surface 60b. The main surfaces 80a and 80b are end faces in the thickness direction of the dielectric layer 80. The first layer 81 forms the main surface 80a, and the second layer 82 forms the main surface 80b.
[0033] The conductor layer 90 is arranged on the main surface 80b. The conductor layer 90 is made of a conductive material. For example, the conductor layer 90 is made of copper or a copper alloy. The conductor layer 90 has a ground pattern 91. It covers the entire surface of the main surface 80b.
[0034] Although not shown in the diagram, through-holes are formed in the ground pattern 91, dielectric layer 80, ground pattern 72, dielectric layer 60, ground pattern 32, dielectric layer 10, ground pattern 22, dielectric layer 40, and ground pattern 52. Although not shown in the diagram, connecting conductor layers are formed on the inner wall surface of these through-holes, on the ground pattern 52 located around these through-holes, and on the ground pattern 91 located around these through-holes. As a result, the ground patterns 91, 72, 32, 22, and 52 are electrically connected to each other.
[0035] Signal pattern 51 and signal pattern 71 are connected via land 51a, land 21a, connecting conductor layer 53, signal pattern 21, land 21b, land 31a, connecting conductor layer 33, signal pattern 31, land 31b, land 71a, and connecting conductor layer 73 to form a single signal line or one of a pair of differential signal lines.
[0036] (Method for manufacturing the printed circuit board 100) The method for manufacturing the printed circuit board 100 will be described below.
[0037] Figure 7 is a diagram illustrating the manufacturing process of the printed circuit board 100. As shown in Figure 7, the manufacturing method of the printed circuit board 100 includes a preparation step S1, a patterning step S2, an interlayer connection step S3, a dielectric layer attachment step S4, a patterning step S5, an interlayer connection step S6, and a dielectric layer attachment step S7.
[0038] In preparation step S1, the dielectric layer 10 is prepared. At this stage, the dielectric layer 10 has unpatterned conductive layers 20 and 30 on the main surface 10a and main surface 10b, respectively. After preparation step S1, patterning step S2 is performed. Figure 8 is a cross-sectional view illustrating patterning step S2. As shown in Figure 8, in patterning step S2, the conductive layers 20 and 30 are patterned to form signal pattern 21, ground pattern 22, signal pattern 31 and ground pattern 32. Conductor layer 20 is patterned by etching the conductive layer 20 through openings in a resist pattern formed on the conductive layer 20. The resist pattern is formed by attaching a dry film resist to the conductive layer 20 and then exposing and developing the dry film resist. Conductor layer 30 is patterned in the same manner. After patterning step S2, interlayer bonding step S3 is performed.
[0039] Figure 9 is a cross-sectional view illustrating the interlayer bonding process S3. As shown in Figure 9, in the interlayer bonding process S3, through holes 10c and connecting conductor layers 33 are formed. In the interlayer bonding process S3, firstly, through holes 10c are formed in the land 31a and dielectric layer 10. The through holes 10c are formed, for example, by laser processing. Secondly, the connecting conductor layer 33 is formed in the through holes 10c, for example, by electroless plating. After the interlayer bonding process S3, the dielectric layer bonding process S4 is performed.
[0040] Figure 10 is a cross-sectional view illustrating the dielectric layer attachment process S4. As shown in Figure 10, in the dielectric layer attachment process S4, dielectric layers 40 and 60 are attached to the dielectric layer 10. In the dielectric layer attachment process S4, firstly, dielectric layers 40 and 60 are prepared. At this stage, dielectric layer 40 has an unpatterned conductive layer 50 on its main surface 40b, and dielectric layer 60 has an unpatterned conductive layer 70 on its main surface 60b. At this stage, the first layer 41 and the first layer 61 are uncured. Secondly, the dielectric layer 10 is hot-pressed with dielectric layers 40 and 60 sandwiched between them, such that the first layer 41 is in contact with the main surface 10a and the first layer 61 is in contact with the main surface 10b. As a result, the first layer 41 and the first layer 61 are cured, and dielectric layers 40 and 60 are attached to the dielectric layer 10. After the dielectric layer application process S4, the patterning process S5 is performed.
[0041] Figure 11 is a cross-sectional view illustrating the patterning process S5. As shown in Figure 11, in the patterning process S5, the conductor layer 50 and the conductor layer 70 are patterned to form the signal pattern 51, the ground pattern 52, the signal pattern 71, and the ground pattern 72. The conductor layer 50 is patterned by etching the conductor layer 50 through openings in the resist pattern formed on the conductor layer 50. The resist pattern is formed by attaching a dry film resist to the conductor layer 50 and then exposing and developing the dry film resist. The conductor layer 70 is patterned in the same manner. After the patterning process S5, the interlayer bonding process S6 is performed.
[0042] FIG. 12 is a cross-sectional view for explaining the interlayer connection step S6. As shown in FIG. 12, in the interlayer connection step S6, through-holes 40c and connection conductor layers 53 are formed. In the interlayer connection step S6, first, through-holes 40c are formed in the land 51a and the dielectric layer 40. The through-holes 40c are formed, for example, by laser processing. Second, for example, by electroless plating, the connection conductor layer 53 is formed on the inner wall surface of the through-holes 40c, on the land 21a exposed from the through-holes 40c, and on the land 51a. In the interlayer connection step S6, in the same manner, through-holes 60c and connection conductor layers 73 are formed. After the interlayer connection step S6, a dielectric layer pasting step S7 is performed.
[0043] In the dielectric layer pasting step S7, the dielectric layer 80 is pasted onto the dielectric layer 60. In the dielectric layer pasting step S7, first, the dielectric layer 80 is prepared. At this stage, the dielectric layer 80 has a conductor layer 90 on the main surface 80b. At this stage, the first layer 81 is uncured. Second, hot pressing is performed in a state where the dielectric layer 80 is arranged so that the first layer 81 contacts the main surface 60b. As a result, the first layer 81 is cured, and the dielectric layer 80 is pasted onto the dielectric layer 60.
[0044] Note that after the dielectric layer pasting step S7, through-holes are formed in the ground pattern 91, the dielectric layer 80, the ground pattern 72, the dielectric layer 60, the ground pattern 32, the dielectric layer 10, the ground pattern 22, the dielectric layer 40, and the ground pattern 52, for example, by drilling. On the inner wall surface of these through-holes, on the ground pattern 52 located around these through-holes, and on the ground pattern 91 located around these through-holes, connection conductor layers are formed, for example, by electroless plating. Thus, the structure of the printed wiring board 100 shown in FIGS. 1 to 6 is formed.
[0045] (Effect of the printed wiring board 100) The effect of the printed wiring board 100 will be described below.
[0046] In the printed wiring board 100, the land 51a is electrically connected to the land 21a, the land 71a is electrically connected to the land 31b, and the land 21b is electrically connected to the land 31a. That is, the lands of the conductor layer 50, the lands of the conductor layer 70, and the lands of each of the plurality of conductor layers located between the conductor layer 50 and the conductor layer 70 are electrically connected to each other. Therefore, in the printed wiring board 100, compared with the case where through holes are formed so as to penetrate the dielectric layer 10, the dielectric layer 40, and the dielectric layer 60, and the land 51a and the land 71a are connected by the connection conductor layer formed in the through holes, the depth of the through holes for connecting the lands becomes smaller.
[0047] As the depth of the through holes for connecting the lands increases, it becomes more difficult to appropriately form the connection conductor layer on the inner wall surface of the through holes, and connection failures between the lands are likely to occur. Therefore, according to the printed wiring board 100, formation failures of the connection conductor layer on the inner wall surface of the through holes formed for connecting the lands are suppressed, and thus the occurrence of connection failures between the lands is suppressed.
[0048] (Modification Example 1) The configuration of the printed wiring board 100 according to Modification Example 1 will be described below.
[0049] FIG. 13 is a cross-sectional view of the printed wiring board 100 according to Modification Example 1. As shown in FIG. 13, in the printed wiring board 100 according to Modification Example 1, no through hole 10c is formed, and through holes 10d are formed in the land 21b and the dielectric layer 10. The conductor layer 30 has a land 31c instead of the signal pattern 31, the land 31a, and the land 31b. The land 31c overlaps the land 21b in a plan view. The land 31c is exposed from the through hole 10d.
[0050] The printed circuit board 100 according to Modification 1 has a connecting conductor layer 23 instead of a connecting conductor layer 33. The connecting conductor layer 23 is formed inside the through hole 10d. More specifically, the connecting conductor layer 23 is arranged on the inner wall surface of the through hole 10d, on the land 31a and land 21b exposed from the through hole 10d. The connecting conductor layer 23 electrically connects the land 21b to the land 31c. In the printed circuit board according to Modification 1, the through hole 60c is formed so as to overlap with the land 31c (through hole 10d) in a plan view. The land 31c is exposed from the through hole 60c. The connecting conductor layer 73 is formed inside the through hole 60c. More specifically, the connecting conductor layer 73 is arranged on the inner wall surface of the through hole 60c, on the land 31c and land 71a exposed from the through hole 60c. Land 71a is electrically connected to land 31c by a connecting conductor layer 73.
[0051] In this case as well, compared to the case where through holes are formed to penetrate the dielectric layer 10, dielectric layer 40, and dielectric layer 60, and the land 51a and land 71a are connected by a connecting conductor layer formed within the through holes, the depth of the through holes for connecting the lands is reduced. As a result, defects in the formation of the connecting conductor layer on the inner wall surface of the through holes formed to connect the lands are suppressed, and consequently, the occurrence of connection defects between the lands is suppressed.
[0052] (Modification 2) The configuration of the printed circuit board 100 according to Modification 2 is described below.
[0053] Figure 14 is a cross-sectional view of a printed circuit board 100 according to Modification 2. As shown in Figure 14, in the printed circuit board 100 according to Modification 2, through holes 40c are not formed, but through holes 40d are formed in the land 51a and the dielectric layer 40. The conductor layer 20 has land 21c instead of signal pattern 21, land 21a and land 21b. In a plan view, land 21c overlaps with land 51a. The connecting conductor layer 53 is formed in the through hole 40d. The connecting conductor layer 53 electrically connects land 21c to land 31c. In this case as well, compared to the case where through holes are formed to penetrate the dielectric layer 10, dielectric layer 40 and dielectric layer 60, and land 51a and land 71a are connected by a connecting conductor layer formed in the through holes, the depth of the through holes for connecting the lands is smaller. As a result, defects in the formation of the connecting conductor layer on the inner wall surface of the through holes formed to connect the lands are suppressed, and consequently, the occurrence of connection defects between lands is suppressed.
[0054] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of the present invention is indicated by the claims rather than by the embodiments described above, and all modifications within the meaning and scope of equivalents of the claims are intended to be included.
[0055] 10 Dielectric layer, 10a, 10b Main surface, 10c, 10d Through hole, 20 Conductor layer, 21 Signal pattern, 21a Land, 21b Land, 21c Land, 22 Ground pattern, 23 Connecting conductor layer, 30 Conductor layer, 31 Signal pattern, 31a Land, 31b Land, 31c Land, 32 Ground pattern, 33 Connecting conductor layer, 40 Dielectric layer, 40a, 40b Main surface, 40c Through hole, 40d Through hole, 41 First layer, 42 Second layer, 50 Conductor layer, 51 Signal pattern, 51a Land, 52 Ground pattern, 53 Connecting conductor layer, 60 Dielectric layer, 60a, 60b Main surface, 60c Through hole, 61 First layer, 62 Second layer, 70 Conductor layer, 71 Signal pattern, 71a Land, 72 Ground pattern, 73 connecting conductor layer, 80 dielectric layer, 80a, 80b main surface, 81 first layer, 82 second layer, 90 conductor layer, 91 ground pattern, 100 printed circuit board, 200 printed circuit board, DR1 first direction, S1 preparation process, S2 patterning process, S3 interlayer connection process, S4 dielectric layer attachment process, S5 patterning process, S6 interlayer connection process, S7 dielectric layer attachment process.
Claims
1. A first dielectric layer having a first main surface and a second main surface opposite to the first main surface; a first conductor layer disposed on the first main surface; a second conductor layer disposed on the second main surface; a second dielectric layer disposed on the first main surface so as to cover the first conductor layer and having a third main surface facing the first main surface and a fourth main surface opposite to the third main surface; a third dielectric layer disposed on the second main surface so as to cover the second conductor layer and having a fifth main surface facing the second main surface and a sixth main surface opposite to the fifth main surface; a third conductor layer disposed on the fourth main surface; and a fourth conductor layer disposed on the sixth main surface, wherein the third conductor layer has a first signal pattern and a first land connected to the first signal pattern; and the fourth conductor layer has a second signal pattern and a second land connected to the second signal pattern. A printed circuit board in which the first land and the second land are electrically connected to the lands of the first conductor layer and the second conductor layer, respectively.
2. The printed circuit board according to claim 1, wherein the first conductor layer has a third land, the second conductor layer has a fourth land, and the first land, the second land, the third land and the fourth land are arranged to overlap each other in a plan view.
3. The printed circuit board according to claim 1, wherein the first conductor layer has a third land, the second conductor layer has a fourth land, the third land and the fourth land are arranged to overlap each other in a plan view, and the first land and the second land are arranged such that only one of the first land and the second land overlaps the third land and the fourth land in a plan view.
4. The printed circuit board according to claim 1, wherein the first conductor layer has fifth and sixth lands that are offset from each other in a plan view, the second conductor layer has seventh and eighth lands that are offset from each other in a plan view, the first and fifth lands are arranged to overlap each other in a plan view, the sixth and seventh lands are arranged to overlap each other in a plan view, and the second and eighth lands are arranged to overlap each other in a plan view.
5. The printed circuit board according to any one of claims 1 to 4, wherein the first signal pattern and the second signal pattern form a single-line signal line.
6. The printed circuit board according to any one of claims 1 to 4, wherein the first signal pattern and the second signal pattern constitute one of a pair of differential signal lines.