Solid-state imaging element

Abstract

Aa solid-state imaging element (1) comprises: a quantity of n light-receiving elements (102); a storage unit (M) that has a quantity of m storage elements associated with the light-receiving elements; an external signal input reception unit (43) that receives input of an imaging instruction signal and an imaging end signal; an imaging execution unit (44) that generates an imaging control signal obtained by delaying the imaging instruction signal, executes one cycle of an imaging sequence that includes accumulating electric charges in the light-receiving elements, transferring electric charges generated in the light-receiving elements to the storage unit, and resetting the light-receiving elements, and maintains an imaging standby state until the next imaging control signal is generated; a storage operation control unit (45) that causes the output from each light-receiving element to be held in the respective storage element in a prescribed order after one cycle of the imaging sequence has been completed; and a signal readout unit (46) that receives input of the imaging end signal and reads out the signal held in the storage element to the outside.

Description

Solid-state imaging device

[0001] The present invention relates to a solid-state imaging device.

[0002] A solid-state imaging device is used for high-speed continuous shooting of phenomena that occur at high speed within a short period of time (for example, Patent Documents 1 to 3). The solid-state imaging device includes a light-receiving element provided corresponding to each of a plurality of pixels constituting an image, and a storage unit having a plurality of storage elements provided corresponding to each light-receiving element. The solid-state imaging device has a reference clock inside, and based on a control signal generated at a predetermined timing based on the reference clock, charge accumulation in the light-receiving element (shooting of an object), transfer of the charge accumulated in the light-receiving element to the storage unit, and reset processing of the light-receiving element are sequentially performed for all pixels, and a cycle (frame) of processing is repeatedly executed. Among the execution time of one cycle, the time excluding the time required for charge transfer from the light-receiving element and reset processing of the light-receiving element is allocated to shooting of the object.

[0003] Japanese Patent Application Laid-Open No. 2009-296323, Japanese Patent Application Laid-Open No. 2013-247137, Japanese Patent Application Laid-Open No. 2020-057962

[0004] Generally, a phenomenon occurring in an object to be photographed by a solid-state imaging device occurs at a timing independent of the reference clock of the solid-state imaging device. Therefore, a phenomenon to be photographed may occur during a time period when charge is read from the light-receiving element or reset processing of the light-receiving element is performed in the solid-state imaging device, and part or all of the phenomenon may not be photographed.

[0005] The problem to be solved by the present invention is to provide a technique capable of photographing a phenomenon occurring in an object at a desired timing at a timing independent of the solid-state imaging device.

[0006] To solve the above problems, the present invention provides a solid-state image sensor comprising: n light-receiving elements (where n is an integer of 2 or more); a storage unit associated with each of the n light-receiving elements, each having m memory elements (where m is an integer of 2 or more); an external signal input receiving unit that receives input of a shooting instruction signal that indicates the timing of each shooting in a series of shootings and a shooting end signal that indicates the end of the series of shootings; a delay processing unit that generates a shooting control signal by delaying the shooting instruction signal by a predetermined time, and uses the shooting control signal to execute a one-cycle shooting sequence for all light-receiving elements, including the accumulation of charge in each light-receiving element, the transfer of the charge generated by the light-receiving element to the storage unit, and the reset processing of the light-receiving element, and maintains a shooting standby state until the next shooting control signal is generated; and a storage operation control unit that, after the completion of the one-cycle shooting sequence, stores the output from each of the n light-receiving elements in a predetermined order in the m memory elements of the storage unit corresponding to the light-receiving element. The system includes a signal readout unit that, upon receiving the aforementioned shooting completion signal, reads out the signals held in the m memory elements to the outside.

[0007] In the solid-state image sensor according to the present invention, a signal governing the phenomenon to be photographed occurring on the object is input to the external signal input receiving unit as a shooting instruction signal. When the shooting instruction signal is input, the shooting execution unit generates a shooting control signal by delaying the shooting instruction signal by a predetermined time using a delay processing unit, and executes a one-cycle shooting sequence for all n pixels. After each cycle of the shooting sequence is executed, the memory operation control unit stores the output from the light-receiving element corresponding to each pixel in a predetermined order in m memory elements of the memory unit corresponding to that light-receiving element. The shooting execution unit maintains a shooting standby state until the next control instruction signal is generated. Then, when the shooting completion signal is input, the signal reading unit reads out the signals held in the m memory elements of the memory unit corresponding to each light-receiving element to the outside. In the solid-state image sensor according to the present invention, by setting the predetermined time (delay time when generating the shooting control signal from the shooting instruction signal) based on the results of prior preliminary measurements, phenomena occurring on the object can be photographed at a desired timing independently of the solid-state image sensor.

[0008] A schematic diagram of one embodiment of the solid-state image sensor according to the present invention. A diagram illustrating the pixel circuit section constituting each pixel of the solid-state image sensor of this embodiment. A diagram illustrating the configuration of the memory area in the solid-state image sensor of this embodiment. A diagram illustrating the control and processing unit of the solid-state image sensor of this embodiment. A diagram illustrating the delay processing unit of the solid-state image sensor of this embodiment. A diagram illustrating the shooting operation and the control signal for one cycle in the solid-state image sensor of this embodiment. A diagram illustrating another example of the shooting operation in the solid-state image sensor of this embodiment. A flowchart illustrating the sequence of the shooting operation in the solid-state image sensor of this embodiment. A diagram illustrating another example of the delay circuit in the solid-state image sensor of this embodiment. A diagram illustrating a synchronous shooting system combining the solid-state image sensor of this embodiment with another solid-state image sensor. A diagram illustrating another example of a synchronous shooting system combining the solid-state image sensor of this embodiment with another solid-state image sensor.

[0009] One embodiment of the solid-state image sensor according to the present invention will be described below with reference to the drawings.

[0010] Figure 1 is a schematic diagram showing the overall configuration of the solid-state image sensor 1 of this embodiment. The solid-state image sensor 1 comprises a main body 10 and a control / processing unit 4. Figure 1 is a plan view of the main body 10 and schematically shows the arrangement of pixels and memory areas on the light-receiving surface.

[0011] The light-receiving surface of the main unit 10 has 480 pixels P arranged two-dimensionally in the first direction (vertical direction in Figure 1) and 640 pixels P arranged in the second direction (horizontal direction in Figure 1). A memory area M corresponding to each pixel P is also provided. Although not shown in Figure 1, a light-shielding portion is provided in each memory area M to prevent light from entering the memory area M.

[0012] The control and processing unit 4 has the function of generating control signals that control operations related to reading out pixel signals generated in pixels P provided on the main unit 10, operations to hold said pixel signals in memory elements in the memory area M, and operations to read out the pixel signals held in said memory elements, as well as outputting the read-out pixel signals to external devices such as personal computers.

[0013] Figure 2 shows the configuration of the pixel circuit section 100 for each pixel P. Each pixel P's pixel circuit section 100 includes a light sensor pixel circuit 101a and an in-pixel correlated double sampling circuit (In-pixel CDS) 101b. In this embodiment, the pixel circuit section 100 is capable of performing correlated double sampling, but a pixel circuit section that does not perform correlated double sampling may also be used.

[0014] The light sensor pixel circuit 101a includes a light-receiving element (PD) 102, a transfer transistor (T) 103, a reset transistor (R) 104, a first source follower transistor (SF1) 105, a first selection transistor (X1) 106, and a first current source transistor (NB1) 107. In Figure 2, a photodiode (PD) is shown as one preferred example of the light-receiving element 102, but other elements such as a phototransistor may also be used.

[0015] The interphase dual sampling circuit 101b includes an interphase dual sampling coupling capacitor (CC) 110, an interphase dual sampling sample-and-hold capacitor (CSH) 111, an interphase dual sampling reset transistor (NS) 112, a second source follower transistor (SF2) 113, a second selection transistor (X2) 114, a second selection transistor (X2') 115, and a second current source transistor (NB2) 116. The interphase dual sampling circuit 101b is wired with a pixel signal output line (PIXEL_OUT) 117 for outputting a pixel signal to a memory area M corresponding to the pixel P.

[0016] Furthermore, the pixel circuit section 100 is provided with the following terminals for applying control signals to operate the light sensor: a terminal 118 for pixel reset voltage, terminals 119a and 119b for power supply voltage, a terminal 120 for interphase double sampling circuit reset voltage within the pixel, a terminal 121 for first current source bias voltage (VNB1), a terminal 122 for second current source bias voltage (VNB2), a terminal 123 for pixel transfer pulse (ΦT), a terminal 124 for pixel reset pulse (ΦR), a terminal 125 for first pixel selection pulse (ΦX1), a terminal 128 for second pixel selection pulse (ΦX2), a terminal 129 for second pixel selection pulse (ΦX2'), and a terminal 130 for interphase double sampling reset pulse (ΦNS).

[0017] Since the configuration and operation of the pixel circuit section 100 in the solid-state image sensor 1 of this embodiment are the same as those conventionally known, a detailed explanation of the signals applied to each terminal and the configuration and operation of the pixel circuit section 100 will be omitted, except for those that are characteristic of this embodiment, which will be described later.

[0018] Figure 3 shows the configuration of the memory area M.

[0019] Each memory area M contains 256 memory units 202. Each memory unit 202 has a memory selection switch (SW) 203 and a memory capacitor (CAM) 204. In Figure 3, only the two memory units at both ends of the 128 memory units 202 arranged in the first direction are shown.

[0020] A single pixel signal transfer line 205 extends in the first direction through the memory area M, and 128 memory units 202 are connected to each side of the pixel signal transfer line 205.

[0021] Each memory selection switch (SW) 203 in the memory area M is connected to a memory selection line 208. The memory selection lines 208 are arranged in pairs, with 128 pairs provided in the first direction (the same number of pairs as the memory units 202 arranged in the first direction within the memory area M; a total of 256 lines).

[0022] The pixel signal output from each pixel P is sent to the memory area M via the pixel signal output line 117. In the memory area M, one memory unit 202 is designated by turning on one of the memory selection switches (SW) 203 using the control signal MSEL, and the pixel signal is held in the memory capacitor (CAM) 204 within that memory unit 202. The order in which the pixel signals output from the pixels P are held in the 256 memory units 202 is predetermined, and accordingly, the control / processing unit 4 sends control signals to turn on these switches.

[0023] Figure 4 shows the part of the control and processing unit 4 of the solid-state image sensor 1 that performs processing characteristic of this embodiment. The control and processing unit 4 includes a storage unit 41, a reference clock generation unit 42, an external signal input receiving unit 43, an image capture execution unit 44, a storage operation control unit 45, and a signal reading unit 46. The image capture execution unit 44 includes a delay processing unit 441 and an image capture control signal generation unit 442.

[0024] The memory unit 41 stores information such as the delay time when the delay processing unit 441 delays the shooting instruction signal to generate a shooting control signal, and information on the order in which the pixel signals are stored in the memory units 202 within the memory area M associated with each pixel P. The information regarding the delay time can be determined, for example, based on the results of a preliminary shooting operation in which only one cycle of shooting is performed beforehand.

[0025] The reference clock generation unit 42 repeatedly generates an internal clock signal at a predetermined period (for example, 100 MHz).

[0026] The external signal input receiving unit 43 receives an imaging instruction signal from the external control device 7 and an external trigger signal. The external control device 7 is a device that generates signals that control the timing at which the phenomenon to be photographed occurs in the object T by the solid-state image sensor 1. For example, when synchrotron radiation emitted at a predetermined period is irradiated onto a sample to cause a change (luminescence, reaction, etc.) in the sample, and the change that occurs in the sample is photographed by the solid-state image sensor 1, the signal that controls the timing of the emission of synchrotron radiation corresponds to the imaging instruction signal, and the sample corresponds to the object T. The trigger signal is a signal that instructs the end of the imaging of the object T by the solid-state image sensor 1. The trigger signal may be generated by the external control device 7, may be generated by an external device other than the external control device 7, or may be input by a person. The trigger signal may also include a signal that instructs the start of imaging of the object T by the solid-state image sensor 1.

[0027] The delay processing unit 441 outputs a signal that has been delayed by a predetermined time stored in the memory unit 41 in response to the shooting instruction signal input to the external signal input reception unit 43. The shooting control signal generation unit 442 outputs the signal input from the delay processing unit 441 as a shooting control signal to each part of the pixel P. In addition, when a trigger signal is input, the shooting execution unit 44 generates a shooting control signal according to a predetermined number of shooting instruction signals, and then stops the output of the shooting control signal from the shooting control signal generation unit 442 to the pixel P, thereby ending the shooting operation.

[0028] For example, if the predetermined number is 100, then 156 of the 256 memory units 202 will hold signals generated at pixel P before the trigger signal is input, and 100 of the memory units 202 will hold signals generated at pixel P after the trigger signal is input. Note that the predetermined number may be 0, or it may be the same number as the memory units 202. In the former case, only signals before the trigger signal is input are held, and in the latter case, only signals after the trigger signal is input are held.

[0029] Once the series of shooting operations is complete, the signal reading unit 46 reads the signals held in the 256 memory units 202, which are provided for each pixel P, to an external device in a predetermined order.

[0030] Figure 5 shows the configuration of the delay processing unit 411. The delay processing unit 441 in this embodiment includes a signal detection unit 4411, a first switch 4412, a first delay circuit 4413, a second delay circuit 4414, and a second switch 4415. The signal detection unit 4411 detects the input of a signal from the external signal input receiving unit 43. The first switch 4412 switches the output destination of the signal detected by the signal detection unit 4411 between the first delay circuit 4413 and the second delay circuit 4414, and switches the output destination of the signal to the second delay circuit 4414 when delay processing of the signal is being performed in the first delay circuit 4413. The second switch 4415 receives the input of the signal that has undergone delay processing in the first delay circuit 4413 and the second delay circuit 4414, and outputs it to the subsequent shooting control signal generation unit 442.

[0031] Examples of delay circuits include shift register logic circuits (circuits capable of delaying a signal by the number of D-flip flops), LCR analog delay circuits (circuits capable of delaying a signal by the filter time constant of an analog circuit), and count logic circuits (circuits that detect changes in the signal and delay the signal by the number of counters). However, if one attempts to accommodate an arbitrary frame rate (the period for repeating one cycle of imaging) and delay time in the range of ns to ms using a shift register circuit, it is necessary to configure a signal delay device by coupling multiple shift register circuits in stages, which increases the circuit size and is not practical in terms of cost. Furthermore, LCR analog delay circuits have large variations in accuracy and are unsuitable for solid-state image sensors 1 that capture phenomena that occur at high speed, as in this embodiment. Therefore, it is preferable to configure the first delay circuit 4413 and the second delay circuit 4414 using count logic circuits, as in this embodiment.

[0032] Next, referring to Figure 6, the relationship between the shooting operation in the pixel circuit section 100 and the pixel transfer pulse (ΦT) and pixel reset pulse (ΦR) will be explained. Note that the shooting operation described here is for the case where shooting is repeated at a constant period (frame rate).

[0033] During one cycle of shooting, the charge of the photodetector 102 is reset to a specified reset voltage by turning on both the pixel transfer pulse (ΦT) and the pixel reset pulse (ΦR). Subsequently, when the pixel transfer pulse (ΦT) is turned off while the pixel reset pulse (ΦR) remains ON, exposure to the photodetector 102 begins, and charge accumulates in the photodetector 102. Furthermore, when the pixel reset pulse (ΦR) is turned OFF and the pixel transfer pulse (ΦT) is turned ON, the charge signal accumulated in the photodetector 102 is read out and transferred to the memory area M provided corresponding to the pixel P. Exposure to the photodetector 102 continues during this time, and exposure to the photodetector 102 ends when the pixel transfer pulse (ΦT) is turned OFF. In this way, one cycle of shooting operation for each pixel P is completed.

[0034] In this embodiment, the solid-state image sensor 1 performs burst shooting. In burst shooting, each time a predetermined signal instructing the execution of shooting is input, the above-mentioned shooting operation is executed for one cycle, and the pixel signal generated by each pixel P in each cycle is repeatedly transferred and stored in 256 storage units 202 in the memory area M corresponding to the pixel P. After that, when a predetermined signal (trigger signal) instructing the end of shooting is input, a predetermined number of shooting cycles are executed, and the series of shooting is completed. During this time, if the number of shooting cycles executed exceeds the number of storage units 202 associated with one pixel (256 in this embodiment), the signals held in the storage units 202 are overwritten sequentially in chronological order. After the series of shooting operations is completed, the signals held in the 256 storage units 202 are read to an external device.

[0035] Here, we will explain the challenges of conventional solid-state image sensors.

[0036] When performing burst imaging with a solid-state image sensor, it is necessary to perform a reset operation of the photodetector and an operation to transfer and retain the signal generated by the photodetector to a memory unit within one cycle. During the reset operation and signal transfer (or at least for a portion of the time during signal transfer), the photodetector cannot be exposed, i.e., the object cannot be photographed. In general, phenomena occurring in objects photographed by a solid-state image sensor occur in accordance with control signals generated by an external control device, as described above, and the timing is independent of the reference clock of the solid-state image sensor. Therefore, in conventional solid-state image sensors, if a phenomenon to be photographed occurs during the time when the solid-state image sensor is reading charge from the photodetector or performing a reset operation of the photodetector, some or all of that phenomenon will not be photographed.

[0037] In the solid-state image sensor 1 of this embodiment, a control signal that governs the phenomenon to be photographed occurring on the object T is input as a shooting instruction signal from the external control device 7 to the external signal input receiving unit 43, and a predetermined delay processing is performed in the delay processing unit 441 to generate the shooting control signal generation unit 442. As described above, the delay time is set appropriately in advance by preliminary shooting, etc., so that the phenomenon to be photographed occurring on the object T can be photographed at the desired timing. Note that the desired timing referred to here is not limited to the timing at which the phenomenon to be photographed occurs on the object T, but may also be the timing after a predetermined time has elapsed since the phenomenon to be photographed occurred.

[0038] The imaging operation of the solid-state image sensor 1 of this embodiment will be described with reference to Figures 7 and 8. The imaging operation described here is for capturing a phenomenon that occurs periodically on an object T at two predetermined different timings (for example, the timing at which the phenomenon to be photographed occurs and a predetermined time after that timing).

[0039] In the solid-state image sensor 1 of this embodiment, when the user instructs the start of the shooting operation by a predetermined input operation (or when the start of shooting is instructed by a trigger signal), the shooting execution unit 44 keeps ΦR and ΦT in the ON state. This puts the system into a shooting standby state in which the voltage of the light-receiving element 102 is reset (Step 1). This shooting standby state is maintained until a shooting instruction signal is input from the external control device 7 to the external signal input receiving unit 43 (NO in Step 2).

[0040] When a shooting instruction signal is input from the external control device 7 to the external signal input receiving unit 43 (t1, t2, t3; YES in step 2), a shooting control signal is generated in the shooting execution unit by a predetermined delay process (+Δt). Upon receiving this shooting control signal, ΦT is turned OFF, and exposure to the light-receiving element 102 begins (step 3). Thereafter, the operation of one cycle described with reference to Figure 6 is executed in order, and when ΦR is OFF and ΦT is ON, the memory operation control unit 45 transmits predetermined control signals to the pixels P and each part within the memory unit, and transfers the signals generated by each pixel P to a predetermined memory unit 202 in the memory area M corresponding to that pixel P (step 4).

[0041] Until a trigger signal instructing the end of shooting is input to the external signal input receiving unit 43 from outside the solid-state image sensor 1 (including when it is the external control device 7) (NO in step 5), the shooting operations in steps 1 to 4 above (shooting operations before the trigger signal) are repeatedly performed.

[0042] When a trigger signal is input from the outside of the solid-state imaging device 1 (including the case of the external control device 7) to the external signal input receiving unit 43 (YES in step 5), in steps 6 to 9, in the same manner as in steps 1 to 4, upon receiving the input of the shooting start signal (t4, t5. YES in step 7), exposure of the light receiving element 102 (step 8) and transfer of the signal generated by the pixel P to the storage unit 202 (step 9) are performed. After the trigger signal is input, until a shooting operation for a predetermined number of cycles is performed (NO in step 10), the shooting operations in steps 6 to 9 (shooting operations after the trigger signal) are repeatedly executed. When a shooting operation for a predetermined number of cycles is performed after the trigger signal is input (YES in step 10), the shooting execution unit 44 ends the shooting operation. When the shooting operation ends, the signal reading unit 46 reads out the signals stored in the 256 storage units 202 in the storage area M provided for each pixel P to an external device (step 11).

[0043] In the solid-state imaging device 1 of the present embodiment, as described above, the imaging standby state in which the voltage of the light receiving element 102 is reset is maintained, and upon receiving the input of the imaging instruction signal, a shooting control signal obtained by delaying it for a predetermined time is generated to execute a one-cycle shooting operation. At this time, since the time to be delayed can be set to an appropriate time based on the result of the preliminary shooting, the phenomenon occurring in the object T under the control signal generated by the external control device 7 independent of the solid-state imaging device 1 can be photographed at a desired timing.

[0044] When performing shooting as described above, depending on the timing when the shooting instruction signal is input and the length of the delay time (for example, t2, t4), while the signal delay processing is being performed in the delay circuit, the next shooting instruction signal is input (t3, t5). In the solid-state imaging device 1 of the present embodiment, since the first switching device 4412 and the second switching device 4415 can operate a plurality of delay circuits, namely the first delay circuit 4413 and the second delay circuit 4414, simultaneously, even in a shooting operation in which the next shooting instruction signal is input during the delay processing, the delay processing for the two signals can be performed in parallel without problems.

[0045] In the above example of shooting, the photodetector 102 was reset to a shooting standby state (the last state during the period when both ΦR and ΦT are ON; standby state 1 in Figure 6). However, the state after exposure to the photodetector 102 has ended (the last state during the period when ΦR is ON and ΦT is OFF; standby state 2 in Figure 6) may be used as the shooting standby state, and the system may perform one cycle of shooting operations from that state after receiving the input of the shooting control signal.

[0046] Alternatively, both standby state 1 and standby state 2 described above may be used. In that case, a delay processing unit 541 as shown in Figure 9 may be used. This delay processing unit 541 includes a third delay circuit 5411 and a fourth delay circuit 5412. The third delay circuit 5411 and the fourth delay circuit 5412 simultaneously receive the shooting instruction signal input to the external signal input receiving unit 43. Upon receiving the shooting instruction signal, the third delay circuit 5411 generates a shooting control signal to release the shooting standby state (standby state 1) in which the voltage of the photodetector 102 has been reset. On the other hand, the fourth delay circuit 5412 generates a shooting control signal to release the shooting standby state (standby state 2) in which exposure to the photodetector 102 has been completed. The same shooting operation as described above can also be performed by using such a delay processing unit 541. In the case of shooting in which the next shooting instruction signal is input during the delay processing, as in the example described above, a configuration in which multiple delay processing units 541 are switched using a switch may be adopted.

[0047] Next, a synchronized imaging system 2, used for synchronized imaging with multiple solid-state image sensors, will be described with reference to Figure 10. This synchronized imaging system 2 is used, for example, when photographing an object T from different directions at the same time. The same parts as those of the pixels P, memory area M, and control / processing unit 4 of the solid-state image sensor 1 already described will be omitted from the illustration and description as appropriate, and the focus will be on the configuration necessary for synchronized imaging.

[0048] When performing synchronous shooting using a plurality of solid-state imaging devices, one of them is set as the main (Master) solid-state imaging device 1a, and the other solid-state imaging devices are set as slave (Slave) solid-state imaging devices 1b. The configuration of the pixels P and the memory unit of the main solid-state imaging device 1a and the slave solid-state imaging device 1b is the same as that of the solid-state imaging device 1 in the above embodiment, and the configuration of the control / processing unit is different from that of the solid-state imaging device 1.

[0049] The control / processing unit 5 of the main solid-state imaging device 1a is obtained by adding a signal output unit 47 to the control / processing unit 4 of the above embodiment. This signal output unit 47 outputs the reference clock generated by the reference clock generation unit 42 of the solid-state imaging device and the imaging control signal generated by the imaging control signal generation unit 442 to the control / processing unit 6 of the slave solid-state imaging device.

[0050] A solid-state imaging device usually has a reference clock generation unit. However, in the control / processing unit 6 of the slave solid-state imaging device 1b, the reference clock generation unit it has is not used, and the reference clock of the main solid-state imaging device 1a input from the signal output unit 47 of the control / processing unit 5 is used. In the control / processing unit 6 of the slave solid-state imaging device 1b, based on the imaging control signal generated by the imaging execution unit 44 of the control / processing unit 5 of the main solid-state imaging device 1a, the imaging execution unit 64 performs a series of imaging operations.

[0051] In this synchronous shooting system 2, in order to perform the shooting operation based on the imaging control signal generated by the control / processing unit 5 of the main solid-state imaging device 1a so as to shoot the phenomenon occurring in the object T at a desired timing under the control signal from the external control device 7, the slave solid-state imaging device 1b can also shoot the phenomenon occurring in the object T at a desired timing.

[0052] The synchronous shooting system is not limited to the configuration shown in FIG. 10, and another configuration can also be adopted. FIG. 11 shows the configuration of another synchronous shooting system 3.

[0053] The control and processing unit 50 for the main solid-state image sensor 1c in this synchronized imaging system 3 is also the control and processing unit 4 of the above embodiment with the addition of a signal output unit 57. However, unlike the signal output unit 47 of the main solid-state image sensor 1c in the synchronized imaging system 3, this signal output unit 57 outputs only the reference clock and trigger signal generated by the reference clock generation unit 42 of the main solid-state image sensor 1c to the control and processing unit 6 of the secondary solid-state image sensor 1d.

[0054] In this synchronized imaging system 3, the imaging instruction signal from the external control device 7 is input to the control and processing unit 50 of the main solid-state image sensor 1c and the control and processing unit 60 of the secondary solid-state image sensor 1d, respectively. Then, in the control and processing unit 50 of the main solid-state image sensor 1c and the control and processing unit 60 of the secondary solid-state image sensor 1d, a delay processing unit 441 performs delay processing, the imaging control signal generation unit 442 generates an imaging control signal, and the imaging execution unit 65 performs a series of imaging operations. This synchronized imaging system 3 differs from the synchronized imaging system 2 described above in that the delay processing and the generation of the imaging control signal are performed in the solid-state image sensors 1c and 1d respectively, but because the imaging operation is performed using the same imaging instruction signal and the same reference clock (having the main solid-state image sensor 1c), phenomena occurring on the target object T can be captured at the desired timing.

[0055] Furthermore, in this synchronized imaging system 3, different timings of imaging instruction signals can be input from the external control device 7 to the main solid-state image sensor 1c and the secondary solid-state image sensor 1d, allowing each solid-state image sensor 1c and 1d to perform independent imaging operations.

[0056] In addition, a synchronous imaging system can be configured by using multiple solid-state image sensors 1 as described in the above embodiment and individually supplying imaging instruction signals and trigger signals from an external control device 7 to each solid-state image sensor 1.

[0057] The above embodiments are all examples and can be modified as appropriate in accordance with the spirit of the present invention.

[0058] The specific numerical values, such as the configuration of pixels and memory units and the number of pixels and memory units, described in the above embodiment are all examples and can be changed as appropriate.

[0059] In the above embodiment, we described a case where a phenomenon occurring periodically on the object T is photographed at multiple different timings, but the same configuration can also be used when the same phenomenon is photographed at a single timing.

[0060] In the above embodiment, the delay processing unit 441 is provided with two delay circuits, but a configuration with three or more delay circuits can also be adopted. Furthermore, if it is not necessary to perform delay processing simultaneously, a delay processing unit with only one delay circuit may be used.

[0061] Furthermore, although the above describes a synchronous imaging system composed of two solid-state image sensors, a synchronous imaging system may be composed of three or more solid-state image sensors. For example, a synchronous imaging system can be composed of three or more solid-state image sensors by using one main solid-state image sensor and multiple secondary solid-state image sensors. In addition, although the above-described synchronous imaging systems 2 and 3 use multiple solid-state image sensors with the same number of pixels and memory units, a synchronous imaging system can also be composed of multiple solid-state image sensors with different numbers of pixels and / or memory units.

[0062] [Embodiments] It will be apparent to those skilled in the art that the exemplary embodiments described above are specific examples of the following embodiments.

[0063] (Section 1) A solid-state image sensor according to one aspect of the present invention comprises: n light-receiving elements (where n is an integer of 2 or more); a storage unit associated with each of the n light-receiving elements, each having m memory elements (where m is an integer of 2 or more); an external signal input receiving unit that receives input of a shooting instruction signal that indicates the timing of each shooting in a series of shootings and a shooting end signal that indicates the end of the series of shootings; a delay processing unit that generates a shooting control signal by delaying the shooting instruction signal by a predetermined time, and uses the shooting control signal to execute a one-cycle shooting sequence for all light-receiving elements, including the accumulation of charge in each light-receiving element, the transfer of the charge generated by the light-receiving element to the storage unit, and the reset processing of the light-receiving element, and maintains a shooting standby state until the next shooting control signal is generated; and a storage operation control unit that, after the completion of the one-cycle shooting sequence, stores the output from each of the n light-receiving elements in a predetermined order in the m memory elements of the storage unit corresponding to the light-receiving element. The system includes a signal readout unit that, upon receiving the aforementioned shooting completion signal, reads out the signals held in the m memory elements to the outside.

[0064] In the solid-state image sensor according to paragraph 1, a signal governing the phenomenon to be photographed occurring on the object is input to the external signal input receiving unit as a shooting instruction signal. When the shooting instruction signal is input, the shooting execution unit generates a shooting control signal by delaying the shooting instruction signal by a predetermined time using a delay processing unit, and executes a 1-cycle shooting sequence for all n pixels. After each cycle of the shooting sequence is executed, the memory operation control unit stores the output from the light-receiving element corresponding to each pixel in a predetermined order in m memory elements of the memory unit corresponding to the light-receiving element. The shooting execution unit maintains a shooting standby state until the next control instruction signal is generated. Then, when the shooting completion signal is input, the signal reading unit reads out the signals held in the m memory elements of the memory unit corresponding to each light-receiving element to the outside. In the solid-state image sensor according to paragraph 1, by setting the predetermined time (delay time when generating the shooting control signal from the shooting instruction signal) based on the results of prior preliminary measurements, phenomena occurring on the object can be photographed at a desired timing independently of the solid-state image sensor.

[0065] (Paragraph 2) The solid-state image sensor according to Paragraph 2 is the solid-state image sensor according to Paragraph 1, wherein the delay processing unit comprises a plurality of delay circuits.

[0066] (Clause 3) The solid-state image sensor according to Clause 3 is the solid-state image sensor according to Clause 2, wherein the delay processing unit further has a switch that selectively selects the plurality of delay circuits and inputs the shooting instruction signal.

[0067] In the solid-state image sensor described in paragraph 2, even if the next shooting instruction signal is input while delay processing is being performed by one delay circuit, delay processing can be performed using another delay circuit. In this case, as described in paragraph 3, a switch that selectively selects from multiple delay circuits to perform delay processing can be suitably used. Alternatively, delay processing can be performed in each of the multiple delay circuits to delay one shooting instruction signal by a different time.

[0068] (Clause 4) The solid-state image sensor according to paragraph 4 is a solid-state image sensor according to any of paragraphs 1 to 3, wherein the shooting execution unit holds a shooting control signal that is generated at a predetermined time included in the shooting sequence of one cycle in the shooting standby state.

[0069] (Clause 5) The solid-state image sensor relating to paragraph 5 is the solid-state image sensor relating to paragraph 4, wherein the predetermined time is the time when the reset process of the light-receiving element is completed and / or the time when the accumulation of charge on the light-receiving element is completed.

[0070] In the solid-state image sensor according to paragraph 4, even when the shooting instruction signal is input intermittently rather than continuously, shooting can be performed at a desired timing corresponding to the input. As the shooting control signal held by the shooting execution unit, for example, the one described in paragraph 5 can be suitably used.

[0071] (Clause 6) The synchronized imaging system according to paragraph 6 further comprises: a first solid-state image sensor, which is a solid-state image sensor according to any one of paragraphs 1 to 5, further comprising: a reference clock generation unit and a signal output unit that outputs a reference clock generated by the reference clock generation unit and the imaging control signal; na (where na is an integer of 2 or more) photodetectors; a storage unit associated with each of the na photodetectors, each having ma (where ma is an integer of 2 or more) memory elements; and an imaging execution unit that, based on the imaging control signal input from the signal output unit, executes a one-cycle imaging sequence for all photodetectors, including the accumulation of charge in each photodetector, the transfer of the charge generated by the photodetectors to the storage unit, and the reset process of the photodetectors, and maintains an imaging standby state until the next imaging control signal is generated. The second solid-state image sensor includes a memory operation control unit that, after the completion of the aforementioned one-cycle shooting sequence, stores the outputs from each of the na photodetectors in a predetermined order in the ma memory elements of the memory unit corresponding to the photodetector, and a signal readout unit that receives the shooting completion signal input to the first solid-state image sensor and reads out the signals held in the ma memory elements to the outside.

[0072] In the synchronized imaging system described in paragraph 6, the first solid-state image sensor is designated as the master and the second solid-state image sensor as the slave. By executing the imaging operation in the second solid-state image sensor using the imaging control signal generated by the first solid-state image sensor, phenomena occurring on an object can be captured synchronously by multiple solid-state image sensors at desired timings.

[0073] (Section 7) The synchronous imaging system according to Section 7 further comprises: a first solid-state image sensor, which is a solid-state image sensor according to any one of Sections 1 to 5, and further comprises: a reference clock generation unit and a signal output unit that outputs a reference clock generated by the reference clock generation unit and the imaging control signal; na (where na is an integer of 2 or more) photodetectors; a storage unit associated with each of the na photodetectors, each having ma (where ma is an integer of 2 or more) memory elements; an external signal input receiving unit that receives input of an imaging instruction signal that indicates the timing of each imaging in a series of imaging; a delay processing unit that generates an imaging control signal delayed by a predetermined time based on the reference clock, and uses the imaging control signal to execute a one-cycle imaging sequence for all photodetectors, including the accumulation of charge in each photodetector, the transfer of the charge generated in the photodetectors to the storage unit, and the reset processing of the photodetectors, and maintains an imaging standby state until the next imaging control signal is generated; The second solid-state image sensor includes a memory operation control unit that, after the completion of the aforementioned one-cycle shooting sequence, stores the outputs from each of the na photodetectors in a predetermined order in the ma memory elements of the memory unit corresponding to the photodetector, and a signal readout unit that receives the shooting completion signal input to the main solid-state image sensor and reads the signals held in the ma memory elements to the outside.

[0074] In the synchronized imaging system described in paragraph 7, the first solid-state image sensor is designated as the Master and the second solid-state image sensor as the Slave. The reference clock generated by the first solid-state image sensor is shared with the second solid-state image sensor. An imaging start signal is input to both the first and second solid-state image sensors. A delay processing is performed on the imaging start signal to generate an imaging control signal. The imaging control signal is used to execute the imaging operation on the second solid-state image sensor. This allows for synchronized imaging of phenomena occurring on an object using multiple solid-state image sensors at desired timings.

[0075] 1…Solid-state image sensor 2, 3…Synchronized shooting system 10…Main unit 100…Pixel circuit section 102…Photodetector 117…Pixel signal output line 202…Memory unit 205…Pixel signal transfer line 208…Memory selection line 4, 5, 6, 50, 60…Control and processing section 41…Memory section 411…Delay processing section 42…Reference clock generation section 43…External signal input reception section 44, 64, 65…Shooting execution section 441, 541…Delay processing section 4411…Signal detection section 4412…First switch 4413…First delay circuit 4414…Second delay circuit 4415…Second switch 5411…Third delay circuit 5412…Fourth delay circuit 442…Shooting control signal generation section 45…Memory operation control section 46…Signal readout section 47, 57…Signal output section 7…External control device P...Pixel M...Storage area T...Object

Claims

1. A photographic execution unit comprising: n (where n is an integer of 2 or more) photodetectors; a storage unit associated with each of the n photodetectors, each having m (where m is an integer of 2 or more) memory elements; an external signal input receiving unit that receives input of a shooting instruction signal that indicates the timing of each shot in a series of shots and a shooting end signal that indicates the end of the series of shots; a delay processing unit that generates a shooting control signal by delaying the shooting instruction signal by a predetermined time, and uses the shooting control signal to execute a one-cycle shooting sequence for all photodetectors, including the accumulation of charge in each photodetector, the transfer of the charge generated by the photodetectors to the storage unit, and the reset processing of the photodetectors, and maintains a shooting standby state until the next shooting control signal is generated; and a storage operation control unit that, after the completion of the one-cycle shooting sequence, stores the output from each of the n photodetectors in a predetermined order in the m memory elements of the storage unit corresponding to the photodetector. A solid-state image sensor comprising a signal readout unit that receives the aforementioned shooting completion signal and reads out the signals held in the m memory elements to the outside.

2. The solid-state image sensor according to claim 1, wherein the delay processing unit comprises a plurality of delay circuits.

3. The solid-state image sensor according to claim 2, wherein the delay processing unit further includes a switch that selectively selects the plurality of delay circuits and inputs the shooting instruction signal.

4. The solid-state image sensor according to claim 1, wherein the shooting execution unit holds a shooting control signal that is generated at a predetermined time included in the shooting sequence of one cycle in the shooting standby state.

5. The solid-state image sensor according to claim 4, wherein the predetermined time is the time when the reset process of the photodetector is completed and / or the time when the accumulation of charge on the photodetector is completed.

6. A first solid-state image sensor according to claim 1, further comprising a reference clock generation unit and a signal output unit that outputs a reference clock generated by the reference clock generation unit and the shooting control signal; na (where na is an integer of 2 or more) photodetectors; a storage unit associated with each of the na photodetectors, each having ma (where ma is an integer of 2 or more) memory elements; and a shooting execution unit that, based on the shooting control signal input from the signal output unit, executes a one-cycle shooting sequence for all photodetectors, including the accumulation of charge in each photodetector, the transfer of the charge generated by the photodetectors to the storage unit, and a reset process for the photodetectors, and maintains a shooting standby state until the next shooting control signal is generated. A synchronized imaging system comprising a second solid-state image sensor, which, after the completion of the aforementioned one-cycle imaging sequence, stores the outputs from each of the na photodetectors in a predetermined order in the ma memory elements of the memory unit corresponding to the photodetector, and which receives the input of the imaging completion signal to the first solid-state image sensor and reads out the signals held in the ma memory elements to the outside.

7. A first solid-state image sensor according to claim 1, further comprising a reference clock generation unit and a signal output unit that outputs a reference clock generated by the reference clock generation unit and the shooting control signal; na (where na is an integer of 2 or more) photodetectors; a storage unit associated with each of the na photodetectors, each having ma (where ma is an integer of 2 or more) memory elements; an external signal input receiving unit that receives input of a shooting instruction signal that indicates the timing of each shooting in a series of shootings; and a delay processing unit that generates a shooting control signal delayed by a predetermined time based on the reference clock, and uses the shooting control signal to execute a one-cycle shooting sequence for all photodetectors, including the accumulation of charge in each photodetector, the transfer of the charge generated in the photodetectors to the storage unit, and the reset processing of the photodetectors, and maintains a shooting standby state until the next shooting control signal is generated. A synchronized imaging system comprising a second solid-state image sensor, which after the completion of the aforementioned one-cycle imaging sequence, stores the outputs from each of the na photodetectors in a predetermined order in the ma memory elements of the memory unit corresponding to the photodetector, and which receives the input of the imaging completion signal to the main solid-state image sensor and reads out the signals held in the ma memory elements to the outside.

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