A digital interface chip configured to split a received set of radio signals into a first and a second subset, and method, computer program product, and non-transitory computer-readable storage medium therefor

Abstract

A digital interface chip, DIC, comprisable in a wireless device, WD, is connectable to two or more transceivers, to a first chip via a first digital interface, and to a second chip via a second digital interface. The DIC is configurable to be in a receiving mode or a transmitting mode. In receiving mode, the DIC receives a set of radio signals, splits the set into disjoint subsets, sends a first signal comprising to the first chip via, and sends a second signal comprising to the second chip. In transmitting mode, the DIC receives BB signals, pre- processes them to obtain transmit signals, and sends to the transceivers for transmission to TNodes.

Description

[0001] P4810WO00 / / lnvO38PCT

[0002] A digital interface chip configured to split a received set of radio signals into a first and a second subset, and method, computer program product, and non-transitory computer-readable storage medium therefor

[0003] Technical field

[0004] The present disclosure relates to a digital interface chip configured to split a received set of radio signals into a first and a second subset, and to a method, a computer program product, and a non-transitory computer-readable storage medium therefor.

[0005] More specifically, the disclosure relates to a digital interface chip configured to split a received set of radio signals into a first and a second subset, and to a method, a computer program product, and a non-transitory computer-readable storage medium as defined in the introductory parts of the independent claims.

[0006] Background art

[0007] US 2024 / 0195448 Al discloses a digital pre-processing chip. The digital pre-processing chip comprises an analog interface for transmitting and receiving analog signals to and from a plurality of analog Radio Frequency (RF) chips, and a digital interface for transmitting and receiving digital signals to and from a baseband chip.

[0008] WO 2020 / 052880 Al discloses that the transceiver arrangement comprises a plurality (e.g., two or more) of transceiver elements, and a further signal processing element such as a baseband chip (BB). The plurality of transceiver elements and the further signal processing elements are connected in series for transfer of received signals, wherein an output circuitry of each of the transceiver elements is connected to input circuitry of either of another one of the transceiver elements and the further signal processing element. The plurality of transceiver elements and the further signal processing element may typically also be connected in series for transfer of signals to be transmitted, wherein an additional input circuitry of each of the transceiver elements is connected to an additional output circuitry of either of another one of the transceiver elements and the further signal processing element. However, it is desirable to reduce the die area. The die area can be reduced by reducing the number of connector pins for each element.

[0009] Furthermore, EP 2640028 Al discloses a method, device, and system for communication signal transmission, which relate to the field of communications, so as to improve reception performance of the network, whereas US 2022 / 0216980 Al discloses a wirelessP4810WC00 / / lnvO38PCT

[0010] transceiver apparatus.

[0011] Thus, it would be useful to reduce the number of connector pins. Accordingly, the present invention provides integration designs that reduce the number of connector pins.

[0012] Summary

[0013] An object of the present disclosure is to mitigate, alleviate or eliminate one or more of the above-identified deficiencies and disadvantages in the prior art and / or solve at least the above-mentioned problem or other problems.

[0014] According to a first aspect there is provided a digital interface chip (DIC), comprisable in a wireless device (WD), connectable to two or more transceivers, connectable to a first chip via a first digital interface, and connectable to a second chip via a second digital interface, the DIC is configurable to be in a receiving mode or in a transmitting mode, and the DIC is configured, while in a receiving mode, to: receive a set of radio signals, the set of radio signals comprising one radio signal from each of the two or more transceivers; postprocess the received set of radio signals, post-processing the received set of radio signals comprises splitting the received set of radio signals into a first and a second subset, and the first and second subsets are disjoint; send a first signal comprising the first subset to the first chip via the first digital interface; and send a second signal comprising the second subset to the second chip via the second digital interface; and the DIC is configured, while in a transmitting mode, to: receive a first baseband (BB) signal from the first chip via the first digital interface; receive a second BB signal from the second chip via the second digital interface; pre-process the first and second BB signals to obtain a set of transmit signals; and send the set of transmit signals to the two or more transceivers for transmission to one or two or more remote transceiver nodes (TNodes).

[0015] According to some embodiments, the digital interface chip (DIC) is further configured, while in the receiving mode, to: receive a third signal from the first chip via the first digital interface; combine the third signal with the second subset, the second signal comprises the third signal.

[0016] According to some embodiments, each radio signal comprises an in-phase component and / or a quadrature component.

[0017] According to some embodiments, the DIC is further configured, while in the receiving mode, to: receive a fourth signal from the second chip via the second digital interface; and combine the fourth signal with the first subset, the first signal comprising the fourth signal.P4810WC00 / / lnvO38PCT

[0018] According to some embodiments, the DIC is further configured, while in a transmitting mode, to: apply a first function to the first BB signal to obtain a first resulting signal; and transmit the first resulting signal to the second chip via the second digital interface.

[0019] According to some embodiments, the DIC is further configured, while in a transmitting mode, to: apply a second function to the second BB signal to obtain a second resulting signal; and transmit the second resulting signal at to the first chip via the first digital interface.

[0020] According to a second aspect there is provided a digital interface chip (DIC), comprisable in a wireless device (WD), connectable to two or more transceivers, connectable to a first chip via a first digital interface, and connectable to a second chip via a second digital interface, the DIC is configured, while in a receiving mode, to: receive a set of radio signals, the set of radio signals comprising one radio signal from each of the two or more transceivers (each radio signal comprising an in-phase component and / or a quadrature component); post-process the received set of radio signals, post-processing the received set of radio signals comprises splitting the received set of radio signals into a first subset and a second subset, the first and second subsets are disjoint; send a first signal comprising the first subset to the first chip via the first digital interface; and send a second signal comprising the second subset to the second chip via the second interface.

[0021] According to a third aspect there is provided a digital interface chip (DIC), comprisable in a wireless device (WD), connectable to two or more transceivers, connectable to a first chip via a first digital interface, and connectable to a second chip via a second digital interface, the DIC is configured, while in a transmitting mode, to: receive a first baseband (BB) signal from the first chip via the first digital interface; receive a second BB signal from the second chip via the second interface; pre-process the first and second BB signals to obtain a set of transmit signals; and send the set of transmit signals to the two or more transceivers for transmission to one or more transceiver nodes (TNodes).

[0022] According to a fourth aspect there is provided a method of a digital interface chip (DIC) comprisable in a wireless device (WD), connectable to two or more transceivers, connectable to a first chip via a first digital interface, and connectable to a second chip via a second digital interface, the DIC is configurable to be in a receiving mode or in a transmitting mode, the method comprises: while the DIC is in a receiving mode: receiving, by the DIC, a set of radio signals, the set of radio signals comprising one radio signal from each of the two or more transceivers; post-processing, by the DIC, the received set of radio signals, post-processing the received set of radio signals comprises splitting the re-ceived set of radio signals into a first subset and a second subset, the first and secondP4810WO00 / / lnvO38PCT

[0023] subsets are disjoint; sending, by the DIC, a first signal comprising the first subset to the first chip via the first digital interface; and sending, by the DIC a second signal comprising the second subset to the second chip via the second digital interface; and / or while the DIC is in a transmitting mode: receiving, by the DIC, a first baseband (BB) signal from the first chip via the first digital interface; receiving, by the DIC, a second BB signal from the second chip; pre-processing, by the DIC, the first and second BB signals to obtain a set of transmit signals; and sending, by the DIC, the set of transmit signals to the two or more transceivers for transmission to one or two or more remote transceiver nodes (TNodes). According to a fifth aspect there is provided a computer program product comprising in-structions, which, when executed on at least one processor of a processing device, cause the processing device to carry out the method according to the fourth aspect or any of the embodiments mentioned herein.

[0024] According to a sixth aspect there is provided a non-transitory computer-readable storage medium storing one or more programs configured to be executed by one or more pro-cessors of a processing device, the one or more programs comprising instructions which, when executed by the processing device, causes the processing device to carry out the method according to the fourth aspect or any of the embodiments mentioned herein. According to a seventh aspect there is provided a chip comprising the DIC of any of the first, second, and third aspects.

[0025] Effects and features of the second, third, fourth, fifth, sixth, and seventh aspects are fully or to a substantial extent analogous to those described above in connection with the first aspect and vice versa.

[0026] Embodiments mentioned in relation to the first aspect are fully or largely compatible with the second, third, fourth, fifth, sixth, and seventh aspects and vice versa.

[0027] An advantage of some embodiments is that the number of connector pins for each digital interface chip is reduced.

[0028] Another advantage of some embodiments is that the die area is reduced (e.g., since the number of connector pins is reduced and / or since the number of digital interface components, such as the number of SerDes, the number of SerDes blocks and / or the number of semiconductor intellectual property cores, is reduced).

[0029] A further advantage of some embodiments is that faster processing is achieved.

[0030] Yet a further advantage of some embodiments is that the capacity (e.g., the transmissionP4810WO00 / / lnvO38PCT

[0031] rate) is increased.

[0032] Yet another further advantage of some embodiments is that delay / latency in transferring data to the BB chip / processor is reduced.

[0033] Yet a further another advantage of some embodiments is that life expectancy of the com-ponents (e.g., the digital interface chips) is increased.

[0034] Yet another advantage of some embodiments is that resolution / accuracy is increased. Other advantages are that complexity is reduced, an improved, more robust and / or more accurate beamforming may be provided and / or that the signal quality is increased.

[0035] The present disclosure will become apparent from the detailed description given below. The detailed description and specific examples disclose preferred embodiments of the disclosure byway of illustration only. Those skilled in the art understand from guidance in the detailed description that changes, and modifications may be made within the scope of the disclosure.

[0036] Hence, it is to be understood that the herein disclosed disclosure is not limited to the par-ticular component parts of the device described or steps of the methods described since such apparatus and method may vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. It should be noted that, as used in the specification and the appended claims, the articles "a", "an", "the", and "said" are intended to mean that there are one or more of the elements unless the context explicitly dictates otherwise. Thus, for example, reference to "a unit" or "the unit" may include several devices, and the like. Furthermore, the words "comprising", "including", "containing" and similar wordings do not exclude other elements or steps. Herein “comprising” can be replaced by “including” if it is not otherwise specified. Moreover, the term “configured” or “adapted” is intended to mean that a unit or similar is shaped, sized, connected, connectable or otherwise adjusted for a purpose. Brief descriptions of the drawings

[0037] The above objects, as well as additional objects, features, and advantages of the present disclosure, will be more fully appreciated by reference to the following illustrative and non-limiting detailed description of example embodiments of the present disclosure, when taken in conjunction with the accompanying drawings.

[0038] Figure 1A is a schematic drawing illustrating a wireless device according to some embodiments;P4810WO00 / / lnvO38PCT

[0039] Figure IB is a schematic drawing illustrating a wireless device according to some embodiments;

[0040] Figure 1C is a schematic drawing illustrating a wireless device according to some embodiments;

[0041] Figure ID is a schematic drawing illustrating a wireless device according to some embodiments;

[0042] Figure IE is a flowchart illustrating some method steps according to some embodiments; Figure 2 is a flowchart illustrating actions / method steps implemented in a wireless device, a Multi-Antenna Transmitter and Receiver Arrangement (MATARA) and / or in a digital in-terface chip (DIC) according to some embodiments;

[0043] Figure 3 is a schematic drawing illustrating a system comprising one or more wireless devices and one or more transceiver nodes according to some embodiments;

[0044] Figure 4 is a schematic drawing illustrating a computer readable (storage) medium according to some embodiments;

[0045] Figure 5A is a schematic drawing illustrating a prior art signal processing element / digital interface chip;

[0046] Figure 5B is a schematic drawing illustrating a digital interface chip according to some embodiments;

[0047] Figure 5C is a schematic drawing illustrating a digital interface chip according to some embodiments; and

[0048] Figure 5D is a schematic drawing illustrating a prior art signal processing element / digital interface chip.

[0049] Detailed description

[0050] The present disclosure will now be described with reference to the accompanying draw-ings, in which preferred example embodiments of the disclosure are shown. The disclosure may, however, be embodied in other forms and should not be construed as limited to the herein disclosed embodiments. The disclosed embodiments are provided to fully convey the scope of the disclosure to the skilled person.

[0051] Terminology

[0052] Herein is referred to a semiconductor intellectual property core. A semiconductor intellec-P4810WG00 / / lnvO38PCT

[0053] tual property core may also be called SIP core, IP core or IP block. A SIP core is a reusable unit of logic, cell, or integrated circuit layout design that is the intellectual property of one party.

[0054] Herein is referred to a processor / processing unit. The processor may be a digital proces-sor. Alternatively, the processor may be a microprocessor, a microcontroller, a central processing unit, a co-processor, a graphics processing unit (GPU), a digital signal processor (DSP), an image signal processor, a quantum processing unit, or an analog signal processor. The processing unit may comprise one or more processors and optionally other units, such as a control unit. Thus, the processor may be implemented as a single-processor, a dual-processor system, or a multiprocessor system. Furthermore, the invention can also be practiced in distributed computing environments where certain tasks are performed by remote processing devices that are linked through a communications network, e.g., 5G, to one or more local processors. In a distributed computing environment, program modules can be located in both local and remote memory storage devices. Moreover, some processing (e.g., for the data plane) may be moved to a centralized node, such as a centralized transceiver node (TNode). For example, baseband processing and / or higher layer processing, such as processing at layers above the physical layer, may be moved to a cloud, such as an mmW RAN cloud (wherein processing is performed by cloud processors). Such a (mmW) cloud deployment may bring significant cost savings to the operator due to centralized processing, collaborative radio processing, and availability of cheap commodity hardware.

[0055] Herein is referred to a baseband (BB) processor / processing unit. A BB processor is a processor specifically adapted for processing baseband signals / data.

[0056] Herein is referred to millimetre Wave (mmW) utilization, mmW communication, mmW com-munication capability and mmW frequency range. The mmW frequency range is from 24.25 Gigahertz (GHz) to 71 GHz or more generally from 24 to 300 GHz. The mmW frequency range may also be referred to as Frequency Range 2 (FR2).

[0057] Herein is referred to centimetre Wave (emW) utilization, emW communication, emW communication capability and emW frequency range. The emW frequency range is from 10 Gigahertz (GHz) to 30 GHz.

[0058] Herein is referred to a chip. A chip is an integrated circuit (chip) or a monolithic integrated circuit (chip) and may also be referred to as an IC, or a microchip.

[0059] Herein is referred to a wireless device (WD). A wireless device is any device capable of transmitting or receiving signals wirelessly. Some examples of wireless devices are userP4810WO00 / / lnvO38PCT

[0060] equipment (UE), mobile phones, cell phones, smart phones, Internet of Things (loT) devices, vehicle-to-everything (V2X) devices, vehicle-to-infrastructure (V2I) devices, vehicle-to-network (V2N) devices, vehicle-to-vehicle (V2V) devices, vehicle-to-pedestrian (V2P) devices, vehicle-to-device (V2D) devices, vehicle-to-grid (V2G) devices, fixed wireless access (FWA) points, and tablets.

[0061] Herein is referred to a “transceiver node” (TNode). ATNode may be a radio unit (RU), a remote radio unit (RRU), a repeater, a wireless node, or a base station (BS), such as a radio base station (RBS), a Node B, an Evolved Node B (eNB) or a gNodeB (gNB). Thus, a TNode may be a network (NW) node. Furthermore, a TNode may be a BS for a neigh-bouring cell, a BS for a handover (HO) candidate cell, a radio unit (RRU), a distributed unit (DU), another WD (e.g., a remote WD) or a base station (BS) for a (active / deacti-vated) secondary cell (SCell) or for a serving / primary cell (PCell, e.g., associated with an active TCI state), a laptop, a wireless station, a relay, a repeater device, a reconfigurable intelligent surface, or a large intelligent surface.

[0062] Herein is referred to an antenna unit. An antenna unit may be one single antenna. However, an antenna unit may also be a dual antenna, such as a dual patch antenna with a first (e.g., horizontal) and a second (e.g., vertical) polarization, thus functioning as two separate antennas or an antenna unit having two ports. Moreover, an antenna unit may be an antenna array, e.g., if analog beamforming is performed.

[0063] The polarization of an antenna refers to the orientation of the electric field of the radio wave transmitted by it and is determined by the physical structure of the antenna and its orientation. E.g., an antenna composed of a linear conductor (such as a dipole or whip antenna) oriented vertically will result in vertical polarization; if turned on its side the same antenna's polarization will be horizontal.

[0064] Basic concept

[0065] In WO 2020 / 052880 Al signal processing elements 160a, 160b, .... 160n are connected in series for transfer of received signals and at the same time connected in series for transfer of signals to be transmitted (as shown in figure 5D). However, as can be seen in figure 5A depicting one signal processing element (SPE, corresponding to a digital inter-face chip (DIC) 320 in the present invention) of WO 2020 / 052880 Al (e.g., 160b ), four standard receiver / transmitter (RX / TX) units (or interfaces, each comprising a receiver and a transmitter) 560, 570, 580, 590 and therefore four input pins and four output pins (or four sets of input pins and four sets of output pins if differential or IQ transmission is performed, e.g., one pin for quadrature and another for in-phase, thus two pins per set), areP4810WC00 / / lnvO38PCT

[0066] needed for each SPE / DIC 160a, 160b, .... 160n, 320 for serially interconnecting first and second SPEs / DICs (or a first SPE / DIC and a baseband, BB, chip) transferring received signals from a first SPE / DIC to a second SPE / DIC (or to the BB chip) and simultaneously serially interconnecting the first and second SPEs / DICs (or the first SPE / DIC and the BB chip) simultaneously transferring signals to be transmitted from the second SPE / DIC (or from the BB chip) to the first SPE / DIC. Thus, eight (I / O) pins (or sets of pins) are needed for each SPE / DIC. However, it is desirable to reduce the size of the chip (comprising a SPE / DIC), e.g., in order to reduce the size of a wireless device comprising the chip. One way of reducing the size of the chip is by reducing the die area. Furthermore, one way of reducing the die area is by reducing the number of (I / O) pins. Another way of reducing the die area is by reducing the number of digital interface components (e.g., the number of SerDes blocks, the number of SerDes, and / or the number of semiconductor intellectual property cores). Furthermore, in of WO 2020 / 052880 Al all data received from all of the SPEs 160a, 160b, .... 160n is fed to the BB processor 195 (for further BB processing of the signal, such as channel estimation and / or decoding) via the only SPE 160n connected directly to the BB processor 195. Thus, the only SPE 160n directly connected to the BB processor 195 has to transfer more data than any other SPE 160a, 160b. Thus, the performance or capacity (e.g., transmission rate) of the entire system (i.e. , the chain of SPEs 160a, 160b, .... 160n) is severely limited by a single component, namely the only SPE 160n directly connected to the BB processor 195. A basic concept of this invention is to connect a first DIC to a BB chip and to a second DIC (different from the first DIC, the second DIC is optionally connected to yet further DICs in series) and to connect the second DIC (or the last one of the further DICs) back to the BB chip for transferring received signals and for transferring signals to be transmitted (as explained herein), i.e., the data from each DIC is routed two different ways to the BB chip. Thus, the capacity (e.g., transmission rate) is doubled compared to prior art. Alternatively, or additionally, the delay / latency in transferring data to the BB chip / processor is cut in half. As another alternative, or additionally, the utilization of the DICs is more evenly distributed, i.e., load balancing is achieved. Thus, life expectancy of the DICs is increased. Furthermore, each DIC only needs two standard RX / TX units (or interfaces) 560, 570 and therefore only four (I / O) pins (or four sets of pins) as depicted in figure 5B (although the BB chip / processor still need eight pins eight set of pins), and hence the number of pins have been reduced by 50% (thereby enabling a reduction of the die area, and consequently the size of the chip and the size of a wireless device comprising the chip is reduced. Furthermore, the number of digital interface components (e.g., SerDes, SerDes blocks or SIP cores) has also been reduced by 50%. In some embodiments, the received signals, received by transceivers connected / connectable to the DIC, are split up and transferred to different chips (e.g., oneP4810WC00 / / lnvO38PCT

[0067] set of received signals is transferred to a different DIC (and further to the BB chip, e.g., directly or via further DICs) and another set of received signals is transferred directly to the BB chip. Furthermore, in some embodiments, a BB signal from the BB chip / processor is split up into a first and a second BB signal, and the first BB signal is sent to the DIC via one or more other DICs, whereas the second BB signal is sent to the DIC directly from the BB chip / processor. The DIC processes (or pre-processes, e.g., combines) the received BB signals to obtain a set of transmit signals. The set of transmit signals is sent to the transceivers (connected / connectable to the DIC) for transmission to one or more transceiver nodes. Thus, complexity is reduced.

[0068] Embodiments

[0069] In the following, embodiments will be described where figures 1A-1D illustrate a wireless device according to some embodiments and figure IE illustrates some method steps according to some embodiments. Figure 1A depicts a wireless device (WD) 302. In some embodiments, the WD 302 comprises a Multi-Antenna Transmitter and Receiver Arrange-ment (MATARA) 400. The WD 302 and / or the MATARA400 comprises two or more (i.e., a set of) receivers / transceivers 500, .... 505, 506, .... 510, 511, .... 515 (515 (shown in figure 1C). Furthermore, the WD 302 and / or the MATARA 400 comprises two or more (i.e., a set of) antenna units / ports 700, .... 705, 706, .... 710, 711, .... 715 (715 (shown in figure 1C). The two or more receivers / transceivers 500, .... 505, 506, .... 510, 511, .... 515 are515 are configured to receive a set of analog radio signals via the one or more antenna units / ports 700, .... 705, 706, .... 710, 711, .... 715. In some embodiments, the WD 322 and / or the MATARA 400 comprises one or more converter units 900, .... 905, 906, .... 910, 911, ....

[0070] 915 (915 (shown in figure 1C). Each converter unit 900, .... 905, 906, .... 910, 911, .... 915 is connected or connectable to a corresponding transceiver 500, .... 505, 506, .... 510, 511, .... 515. Each converter unit comprises an analog to digital converter (ADC) and / or a digital to analog converter (DAC). Alternatively, each converter unit 900, .... 905, 906, ....

[0071] 910, 911, .... 915 comprises one ADC / DAC pair (comprising one DAC and one ADC) for each quadrature (Q) component and one ADC / DAC pair (comprising one DAC and one ADC) for each in-phase (I) component of the transceiver(s) it is connected / connectable to. The converter units 900, .... 905, 906, .... 910, 911, .... 915 are configured to convert the one or more analog radio signals into one or more (corresponding) digital signals, and / or configured to convert one or more digital signals (e.g., digital transmit / radio signals) into one or more (corresponding) analog radio signals.

[0072] Furthermore, the WD 302 and / or the MATARA 400 comprises two or more digital interface chips (DICs) 318, 320, 322. Each converter unit 900, .... 905, 906, .... 910, 911, .... 915P4810WC00 / / lnvO38PCT

[0073] is connected or connectable to one of the DICs 318, 320, 322 (as shown in figure 1C). Alternatively, each of the DICs 318, 320, 322 comprises the converter units 900, .... 905, 906, .... 910, 911, .... 915 (and optionally the one or more receivers / transceivers 500, ....

[0074] 505, 506, .... 510, 511, .... 515 and / or the one or more antenna units / ports 700, .... 705, 706, .... 710, 711, .... 715 ). Moreover, the WD 302 and / or the MATARA 400 comprises a baseband (BB) chip 600. The BB chip 600 comprises a BB processor (e.g., the BB processor 195) or a BB processing unit. The BB chip / processor 600 is connected / con-nectable to two (or more) of the DICs 318, 320, 322. As shown in figure lAthe DIC 320 is connected / connectable to another DIC 318 via a first digital interface 342. Furthermore, the DIC 320 is connected / connectable to the BB chip / processor 600 via a second digital interface 352. In some embodiments, the DIC 320 comprises the first and the second digital interfaces 342, 352. Furthermore, in some embodiments, the first and / or second digital interfaces 342, 352 are or comprises a universal serial bus (USB). Alternatively (or additionally), the first and / or second digital interfaces 342, 352 are or comprises one (or two) serializer / deserializer (SerDes). By utilizing SerDes for the first and / or second digital interfaces, the number of I / O pins is reduced (e.g., compared to utilizing a parallel interface). The DIC 320 is comprisable in a wireless device (WD) 302. Furthermore, the DIC 320 is connected / connectable to two or more transceivers 506, .... 510. Moreover, the DIC 320 is connected / connectable to a first chip (i.e. , another DIC having the same structure as the DIC 320 or another DIC identical to the DIC 320) 318 via the first digital interface 342. The DIC 320 is connected / connectable to a second chip (i.e., the BB chip) 600 via the second digital interface 352. Furthermore, the DIC 320 is configurable / config-ured to be in either of a receiving mode and a transmitting mode. As an example, the DIC 320 (and all other DICs 318, 322) is configured to be in a receiving mode during a first pre-determined time interval and configured to be in a transmitting mode during a second pre-determined time interval (different / non-overlapping from / with the first pre-determined time interval). Alternatively, the DIC 320 (and all other DICs 318, 322 and the WD 302) is configured to be in the receiving mode or the transmitting mode based on / in dependence of an indication received from a remote TNode 396, 397, 398, 399. As another alternative, a processing unit, such as the BB processor comprised by the BB chip 600, determines whether the DIC 320 (and all other DICs 318, 322) is to be in the receiving mode or the transmitting mode, and the processing unit sets / configures the DIC 320 (and all other DICs 318, 322) to be in the receiving mode or the transmitting mode once the mode has been determined. The DIC 320 is configured, while in a receiving mode, to receive a set of radio signals. The set of radio signals comprises one radio signal from each of the two or more transceivers 506, .... 510 (received by the two or more transceivers 506 .... 510 from one or more remote TNodes via antenna units 706, ... 710). In some embodiments, each radioP4810WO00 / / lnvO38PCT

[0075] signal comprises an in-phase component and / or a quadrature component. Thus, in some embodiments, each radio signal comprises an in-phase component and a quadrature component. Moreover, the DIC 320 is configured, while in a receiving mode, to post-process the received set of radio signals. Post-processing the received set of radio signals com-prises splitting the received set of radio signals into a first subset r21 (of radio signals) and a second subset r22 (of radio signals). The first and second subsets r21, r22 are disjoint. Thus, the first subset r21 comprises / consists of e.g., one or more of the received radio signals and the second subset r22 comprises / consists of e.g., the remaining radio signals (i.e. , all other received radio signals, or the received radio signals not comprised in the first subset r21). Furthermore, in some embodiments, the first subset r21 and the second subset r22 are non-empty. The DIC 320 is configured, while in a receiving mode, to send a first signal SI comprising the first subset r21 to the first chip (e.g., a second DIC 318) via the first digital interface 342. Furthermore, the DIC 320 is configured, while in a receiving mode, to send a second signal S2 comprising the second subset r22 to the second chip (e.g., the BB chip 600 or a third DIC 322) via the second interface 352. The DIC 320 is configured, while in a transmitting mode, to receive a first baseband (BB) signal tl from the first chip 318 via the first digital interface 342. In some embodiments, the first chip 318 has received the first BB signal tl (or parts thereof) from the BB chip 600. Furthermore, the DIC 320 is configured, while in a transmitting mode to receive a second BB signal t2 from the second chip 600, 322 via the second interface 352. The DIC 320 is configured to pre-process the first and second BB signals tl, t2 to obtain a set of transmit signals TS6, .... TS10. In some embodiments, the DIC 320 comprises a pre-processor 350 (shown in figure ID). The pre-processor 350 is, in these embodiments configured to pre-process the first and second BB signals tl, t2 to obtain a set of transmit signals TS6, .... TS10. Furthermore, in some embodiments, pre-processing the first and second BB signals tl, t2 to obtain a set of transmit signals TS6, .... TS10 comprises receiving, by the pre-processor 350, the first and second BB signals tl, t2, the first BB signal comprising BB information for one or more transmit signals TS6, TS7, and the second BB signal comprising BB information for one or more other transmit signals TS8, TS9, TS10; and converting each of the BB information to corresponding (digital) transmit signals TS6, .... TS10. Moreover, in some embodiments, the pre-processor 350 comprises the converters 906, .... 910. In these embodiments, pre-processing the first and second BB signals tl, t2 to obtain a set of transmit signals TS6, .... TS10 comprises converting the digital transmit signals TS6, .... TS10 to corresponding analog transmit / radio signals. Furthermore, the DIC 320 is configured to send the set of analog transmit / radio signals TS6, .... TS10 to the two or more transceivers 506, 507, .... 510 for transmission to one or more remote transceiver nodes (TNodes) 397, 398, 399 (shown in figure 3). Thus, the transceiversP4810WC00 / / lnvO38PCT

[0076] 506, 507, .... 510 are configured to transmit the transmit / radio signals TS6, .... TS10 to one or more remote TNodes 397, 398, 399 via the corresponding antenna units 706, 707, .... 710. In some embodiments, the DIC 320 is configured, while in the receiving mode, to receive a third signal rl2 or a function / scaled version (al2*rl2) from the first chip 318 via the first digital interface 342. Furthermore, in these embodiments, the DIC 320 is configured, while in the receiving mode (e.g., prior to sending a second signal S2 to the second chip), to (e.g., phase coherently) combine the third signal rl2 (or the function / scaled / com-plex value scaled / complex number scaled version thereof) with the second subset r22. The second signal S2 comprises the third signal rl2 (or the combined full or scaled third signal rl2 and the second subset r22, i.e. , the second signal S2 comprises the third signal rl2 and the second subset r22 or scaled versions thereof). Combining comprises, in some embodiments, summing the third signal rl2 and the second subset r22 or scaled versions thereof (e.g., by a summer). Alternatively, combining comprises multiplying the third signal rl2 with the second subset r22 (or scaled versions thereof), e.g., by a multi-plier. As another alternative, combining comprises concatenating the third signal rl2 and the second subset r22 (or scaled versions thereof). As yet another alternative, combining comprises combining (e.g., multiplying or summing) a first portion of the third signal rl2 with a first portion of the second subset r22 and concatenating a second portion of the third signal rl2 and a second portion of the second subset r22 (i.e., applying combining by multiplication or addition or summing for some part of the signal and concatenation for another part of the signal). Moreover, in some embodiments, each radio signal comprises an in-phase component and / or a quadrature component. In some embodiments, the DIC 320 is configured, while in the receiving mode, to receive a fourth signal r31 (or a scaled version thereof or a function thereof) from the second chip 322 via the second digital in-terface 352. Furthermore, the DIC 320 is configured, while in the receiving mode (e.g., prior to sending the first signal to the first chip), to (e.g., phase coherently) combine the fourth signal r31 (or a scaled version thereof or a function thereof) with the first subset r21 (or a scaled version thereof or a function thereof). The first signal SI comprises the fourth signal r31 (or a scaled version thereof or a function thereof). Combining comprises, in some embodiments, summing the fourth signal r31 and the first subset r21 (or scaled versions thereof or functions thereof), e.g., by a summer. Alternatively, combining comprises multiplying the fourth signal r31 (or a scaled version thereof or a function thereof) with the first subset r21 (or a scaled version thereof or a function thereof), e.g., by a multiplier. As another alternative, combining comprises concatenating the fourth signal r31 and the first subset r21. As yet another alternative, combining comprises combining (e.g., multiplying or summing) a first portion of the fourth signal r31 with a first portion of the first subset r21 and concatenating a second portion of the fourth signal r31 and a second portion ofP4810WC00 / / lnvO38PCT

[0077] the first subset r21 (i.e. , applying combining by multiplication or addition or summing for some part of the signal and concatenation for another part of the signal). In some embodiments, the DIC 320 is configured, while in a transmitting mode, to apply a first function fl (e.g., scale by a constant al) to the first BB signal tl to obtain a first resulting signal (altl). In some embodiments, the first function fl comprises multiplying the first BB signal tl with a factor al. In some embodiments, the factor is non-zero. Furthermore, in some embodiments, the factor is a complex number. Alternatively, or additionally, the function comprises a filter. As another alternative, or additionally, the function is a quadratic function. Furthermore, in some embodiments, the function F is a polynomial, such as a linear polynomial, a quadratic polynomial, a cubic polynomial, a quartic polynomial (of degree four) or a quintic polynomial (of degree five). Furthermore, in some embodiments, the DIC 320 is configured, while in a transmitting mode, to transmit the first resulting signal (altl) to the second chip 600, 322 via the second digital interface 352. Moreover, in some embodiments, the DIC 320 is configured, while in a transmitting mode, to apply a second function f2 to the second BB signal t2 to obtain a second resulting signal (a2t2). In some embodiments, the second function f2 comprises multiplying the first BB signal t2 with a factor (a2). In some embodiments, the factor is non-zero. In some embodiments, the DIC 320 is configured, while in a transmitting mode, to transmit the second resulting signal a2t2 to the first chip 318 via the first digital interface 342.

[0078] A method 100 of a digital interface chip (DIC) 320 is depicted in figure IE. The DIC 320 is comprisable or comprised in a wireless device (WD) 302. Furthermore, the DIC 320 is connectable or connected to two or more transceivers 506, .... 510. Moreover, the DIC 320 is connectable or connected to a first chip 318 via a first digital interface 342. The DIC 320 is connectable or connected to a second chip 600, 322 via a second digital interface 352. The DIC 320 is configurable or configured to be in a receiving mode or in a transmitting mode. Determination of which mode the DIC 320 is in (or set to) is as described above. The method 100 comprises, while the DIC 320 is in a receiving mode, receiving 105, by the DIC 320, a set of radio signals. The set of radio signals comprises one radio signal from each of the two or more transceivers 500, .... 505, 506, .... 510, 511, .... 515 .515. Each radio signal comprises in some embodiments, an in-phase component and / or a quadrature component. Furthermore, the method 100 comprises, while the DIC 320 is in a receiving mode, post-processing 110 (by the DIC 320) the received set of radio signals. Post-processing 110 the received set of radio signals comprises splitting 116 the received set of radio signals into a first subset r21 and a second subset r22. The first and sec-ond subsets r21, r22 are disjoint. In some embodiments, post-processing 110 comprises first spatio-temporal filtering 114 (with a spatio-temporal filter unit comprised by the DICP4810WC00 / / lnvO38PCT

[0079] 320) the received set of radio signals (thereby reducing the number of signals), and) and thereafter splitting 114 the (reduced number of) spatio-temporal filtered signals into the first and the second subsets r21, r22. Furthermore, in some embodiments (the embodiments in which the DIC 320 comprises the converters 906, .... 910), post-processing 110 comprises (before spatio-temporal filtering 114) converting 112 (or A / D converting) the received set of analog radio signals into digital radio signals. The spatio-temporal filter unit (of the DIC 320) has one or more output signals. In some embodiments, the one or more output signals of the spatio-temporal filter unit (comprised by the DIC 320) are fewer than the number of (receiving) antenna units connected to / comprised by the DIC 320. Thus, the number of antenna streams to be feed, by the DIC 320 to the BB chip / processor 600 is reduced (i.e., the number of virtual antenna streams to be feed, by the DIC 320 to the BB chip / processor 600, is smaller than the number of actual antenna units / streams utilized for receiving the one or more radio signals). Thus, complexity is reduced. Moreover, the method 100 comprises, while the DIC 320 is in a receiving mode, sending 120 (by the DIC 320) a first signal SI comprising the first subset r21 to the first chip 318 via the first digital interface 342. The method 100 comprises, while the DIC 320 is in a receiving mode, sending 130 (by the DIC 320) a second signal S2 comprising the second subset r22 to the second chip 600, 322 via the second digital interface 352. Additionally, or alternatively, the method 100 comprises, while the DIC 320 is in a transmitting mode, receiving 140 (by the DIC 320), a first baseband (BB) signal tl from the first chip 318 via the first digital interface 342. Furthermore, in this alternative (step 140 is performed), or additionally, the method 100 comprises receiving 150 (by the DIC 320) a second BB signal t2 from the second chip 600, 322. Moreover, in this alternative (steps 140 and 150 are performed), or additionally, the method 100 comprises pre-processing 160 (by the DIC 320) the first and second BB signals tl, t2 to obtain a set of transmit signals TS6, .... TS10. In this alternative (steps 140, 150, and 160 are performed), or additionally, the method 100 comprises sending 170 (by the DIC 320) the set of transmit signals TS6, .... TS10 to the two or more transceivers 506, .... 510 for transmission to one or two or more remote transceiver nodes (TNodes) 397, 398, 399. The transceivers 506, .... 510 are, in this alternative (steps 140, 150, 160, and 170 are performed), or additionally, configured to transmit the set of transmit signals TS6, .... TS10 to the one or two or more remote TNodes 397, 398, 399 via the antenna units 706, .... 710. In some embodiments, the method 100 comprises configuring / setting the DIC 320 to be in a receiving mode or in a transmitting mode. In these embodiments, the method 100 comprises determining 180 whether the DIC 320 is to be in a receiving mode or in a transmitting mode, and setting 185 the DIC 320 to be in a receiving mode or in a transmitting mode. In some embodiments, determining 180, and setting 185 are performed before receiving 105.P4810WC00 / / lnvO38PCT

[0080] Furthermore, in some embodiments, the method 100 comprises repeating 190 one or more of the steps of receiving 105, post-processing 110, sending 120, sending 130, receiving 140, receiving 150, pre-processing 160, sending 170 and optionally one or more other steps described herein, such as determining 180, and setting 185, every time pe-riod. The time period is, in some embodiments, from 10 - 100000 milliseconds (ms), such as 10ms, 20m, 50ms, 100ms, 200ms, 400ms, 800ms, Is, 10s, or 50s. Alternatively, the method 100 comprises repeating 190 one or more of the steps of receiving 105, postprocessing 110, sending 120, sending 130, receiving 140, receiving 150, pre-processing 160, sending 170, and optionally one or more other steps described herein (e.g., determin-ing 180, and setting 185), based on an event. An example of such an event is that / when / if it has been determined that the mode of the DIC 320 is to be switched from receiving mode to transmitting mode. Another example of such an event is that / when / if it has been determined that the mode of the DIC 320 is to be switched from transmitting mode to receiving mode. Yet another example of such an event is when a new (time) slot starts, each slot comprising a receiving interval (with a first number of data symbols to receive) and a transmission interval (with a second number of data symbols to transmit, wherein the second number is equal to, or different, from the first number). A further example of such an event is that it has been determined that there are one or more data symbols to be received and thus switching to receiving mode is performed. Another further example of such an event is that it has been determined that there are one or more data symbols to be transmitted and thus switching to transmitting mode is performed.

[0081] Figure 2 illustrating actions / method steps (of the method 100 described above in connection with figure IE) implemented in a wireless device (WD) 302 (or a processing unit thereof), a Multi-Antenna Transmitter and Receiver Arrangement (MATARA) 400 and / or in a digital interface chip (DIC) 320 according to some embodiments. In some embodiments, the actions / method steps are caused by the WD 302, a processing unit thereof, the MATARA 400 (or a processing unit thereof) or by the DIC 320. Furthermore, in some embodiments, the DIC 320 is configured to be in a receiving mode or in a transmitting mode. Moreover, the DIC 320 (or the WD 302, a processing unit thereof, the MATARA 400, or a processing unit thereof) is configured to cause, while the DIC 320 is in a receiving mode, reception 205 of a set of radio signals, the set of radio signals comprising one radio signal from each of the two or more transceivers 500, ..., 505, 506, ..., 510, 511, ....

[0082] 515 . To this end, the DIC 320 (or the WD 302, a processing unit thereof, the MATARA 400, or a processing unit thereof) may be associated with (e.g., operatively connectable, or connected, to) a first reception unit (e.g., first receiving circuitry, a first receiver or the set of transceivers 506, 507, .... 510 with the set of antenna units 706, 707, .... 710). TheP4810WC00 / / lnvO38PCT

[0083] DIC 320 (or the WD 302, a processing unit thereof, the MATARA 400, or a processing unit thereof) is configured to cause, while the DIC 320 is in a receiving mode, post-processing 210 of the received set of radio signals, wherein post-processing the received set of radio signals comprises splitting 216 the received set of radio signals into a first and a second subset r21, r22, wherein the first and second subsets r21, r22 are disjoint. To this end, the DIC 320 (or the WD 302, a processing unit thereof, the MATARA 400, or a processing unit thereof) may be associated with (e.g., operatively connectable, or connected, to) a first post-processing unit (e.g., first post-processing circuitry, a first post-processor, a multiplexer, or a first splitter / splitting unit). In some embodiments, the post-processing 210 comprises conversion 212 and / or filtering 214 as described in connection with figure IE (for converting 112 and filtering 114). Furthermore, the DIC 320 (or the WD 302, a processing unit thereof, the MATARA 400, or a processing unit thereof) is configured to cause, while the DIC 320 is in a receiving mode, sending 220 of a first signal SI comprising the first subset r21 to the first chip 318 via the first digital interface 342. To this end, the DIC 320 (or the WD 302, a processing unit thereof, the MATARA 400, or a processing unit thereof) may be associated with (e.g., operatively connectable, or connected, to) a first sending unit (e.g., first sending circuitry, a first sender, a first interface, or a first RX / TX unit 560). Moreover, the DIC 320 (orthe WD 302, a processing unit thereof, the MATARA 400, or a processing unit thereof) is configured to cause, while the DIC 320 is in a receiving mode, sending 230 of a second signal S2 comprising the second subset r22 to the second chip 600, 322 via the second digital interface 352. To this end, the DIC 320 (or the WD 302, a processing unit thereof, the MATARA 400, or a processing unit thereof) may be associated with (e.g., operatively connectable, or connected, to) a second sending unit (e.g., second sending circuitry, a second sender, a second interface, or a second RX / TX unit 570). The DIC 320 (or the WD 302, a processing unit thereof, the MATARA 400, or a processing unit thereof) is configured to cause, while the DIC 320 is in a transmitting mode, reception 240 of a first baseband (BB) signal tl from the first chip 318 via the first digital interface 342. To this end, the DIC 320 (or the WD 302, a processing unit thereof, the MATARA 400, or a processing unit thereof) may be associated with (e.g., operatively connectable, or connected, to) a second reception unit (e.g., second receiving circuitry, a second receiver, a first digital interface, or the first RX / TX unit 560). Furthermore, the DIC 320 (or the WD 302, a processing unit thereof, the MATARA 400, or a processing unit thereof) is configured to cause, while the DIC 320 is in a transmitting mode, reception 250 of a second BB signal t2 from the second chip 600, 322 via the second digital interface 352. To this end, the DIC 320 (or the WD 302, a processing unit thereof, the MATARA 400, or a processing unit thereof) may be associated with (e.g., operatively connectable, or connected, to) a second reception unit (e.g., second receiving circuitry, a second re-P4810WG00 / / lnvO38PCT

[0084] ceiver, a second digital interface, or the second RX / TX unit 570). Moreover, the DIC 320 (or the WD 302, a processing unit thereof, the MATARA400, or a processing unit thereof) is configured to cause, while the DIC 320 is in a transmitting mode, pre-processing 260 of the first and second BB signals tl, t2 to obtain a set of transmit signals TSO, .... TS15. To this end, the DIC 320 (or the WD 302, a processing unit thereof, the MATARA400, or a processing unit thereof) may be associated with (e.g., operatively connectable, or connected, to) a first pre-processing unit (e.g., first pre-processing circuitry, the pre-processor 350 or a first combiner / concatenator). The DIC 320 (or the WD 302, a processing unit thereof, the MATARA400, or a processing unit thereof) is configured to cause, while the DIC 320 is in a transmitting mode, sending 270 of the set of transmit signals TSO, .... TS15 to the two or more transceivers 500, .... 505, 506, .... 510, 511, .... 515 for transmission to one or two or more remote transceiver nodes, TNodes 397, 398, 399. To this end, the DIC 320 (or the WD 302, a processing unit thereof, the MATARA400, or a processing unit thereof) may be associated with (e.g., operatively connectable, or connected, to) a third sending unit (e.g., third sending circuitry, a third sender or an analog interface).

[0085] In some embodiments, the DIC 320 (or the WD 302, a processing unit thereof, the MATARA400, or a processing unit thereof) is configured to cause setting of the DIC 320 to be in a receiving mode or in a transmitting mode. In these embodiments, the DIC 320 (or the WD 302, a processing unit thereof, the MATARA400, or a processing unit thereof) is configured to cause determination 280 of whether the DIC 320 is to be in a receiving mode or in a transmitting mode, and setting 285 of the DIC 320 to a receiving mode or a transmitting mode. In some embodiments, the method comprises repetition of one or more or all of the actions described above. The repetition 290 is, in some embodiments, as described above in connection with figure IE for repeating 190.

[0086] Figure 3 illustrates a system 999. The system 999 may be a wireless / cellular communication system, acellular network, a mobile network, a telecommunications network, acellular radio system, a digital cellular network, a mobile phone network, a mobile phone cellular network, such as 1G, 2G (e.g., GSM, GPRS, or EDGE), 3G (e.g., UMTS or CDMA2000), 4G (e.g., LTE, WiMAX, or MBWA), 5G (e.g., 5G NR or 5G-Advanced), 6G, or an ad hoc / mesh NW, such as Bluetooth or Wi-Fi. Furthermore, the system 999 comprises one or more wireless devices (WD) 302, 303, .... 308. Moreover, the system 999 comprises one or more transceiver nodes (TNodes) 396, 397, 398, 399, i.e. , the system 999 comprises a set 395 of one or more TNodes 396, 397, 398, 399. The one or more TNodes 396, 397, 398, 399 may be base stations (gNBs, eNBs, RBS), remote radio units (RRUs), NTN units or remote wireless nodes. The WD 302 (as well as the WDs 303, .... 308) is, in some embodiments, configured to communicate with (e.g., send / transmit and / or receiveP4810WO00 / / lnvO38PCT

[0087] signals, such as radio frequency or wireless signals, e.g., comprising baseband / informa-tion signals, to / from) one or more of the remote TNodes 396, 397, 398, 399. In some embodiments, some, or all of the communication between the WD 302 (as well as the WDs 303, .... 308) and the remote TNodes 396, 397, 398, 399 is performed with radio signals in the mmW frequency range. Alternatively, or additionally, the communication between the WD 302 (as well as the WDs 303, .... 308) and the remote TNodes 396, 397, 398, 399 is performed with radio signals in the emW frequency range. As another alternative, or additionally (to mmWand emW), (some of) the communication between the WD 302 (as well as the WDs 303, .... 308) and the remote TNodes 396, 397, 398, 399 is performed with radio signals in the FR1 frequency range. Each Tnode 396, 397, 398, 399 is, in some embodiments, connected to a central computing device via a backhaul, such as a fibre-based backhaul, a wireless point-to-point backhaul, a copper-based wireline, satellite communications and / or point-to-multipoint wireless technologies.

[0088] According to some embodiments, a computer program product comprising a non-transitory computer readable medium 405, such as a punch card, a compact disc (CD-) ROM, a read only memory (ROM), a digital versatile disc (DVD), an embedded drive, a plug-in card, or a universal serial bus (USB; e.g., USB 1.x, USB 2.0, USB 3.x, or USB4) memory, is provided. Figure 4 illustrates an example computer readable medium in the form of a compact disc (CD-) ROM 405. The computer readable medium has stored thereon a computer program comprising program instructions. The computer program is loadable into a data processor (PROC) 420, which may, for example, be comprised in a computer or a computing device, a processing unit 410 comprised by, or associated with, the WD 302, 303, comprised by, or associated with, the MATARA 400, or comprised by, or associated with, the TNode 396, 397, 398, 399. Thus, in some embodiments, the WD 302, 303 and / or the MATARA 400 comprises the processing unit 410. Moreover, in some embodiments, the TNode 396, 397, 398, 399 comprises the processing unit 410. Furthermore, in some embodiments, the processing unit 410 is the BB processor 195. When loaded into the data processor 420, the computer program may be stored in a memory (MEM) 430 associated with or comprised in the data processor 420. According to some embodiments, the computer program may, when loaded into and run by the data processor 420, cause execution of method steps according to, for example, the method illustrated in figure IE described herein. Furthermore, in some embodiments, there is provided a computer program product comprising instructions, which, when executed on at least one processor (e.g., the processing unit 410 or the BB processor 195) of a processing de-vice (e.g., the WD 302, 303, the MATARA 400, or the TNode 396, 397, 398, 399), cause the processing device to carry out the method illustrated in figure IE described herein.P4810WG00 / / lnvO38PCT

[0089] Moreover, in some embodiments, there is provided a non-transitory computer-readable storage medium storing one or more programs configured to be executed by one or more processors (e.g., the processing unit 410 or the BB processor 195) of a processing device (e.g., the WD 302, 303, the MATARA400, or the TNode 396, 397, 398, 399), the one or more programs comprising instructions which, when executed by the processing device, causes the processing device to carry out the method illustrated in figure IE described herein.

[0090] In addition, or alternatively, the program instructions are executed by at least one processor comprised in any other suitable processing device, such as a baseband chip 600, a computer or other computing device, a network node and / or transceiver node, TNode, 396, 397, 398, 399, and / or a centralized or cloud processing device. In such embodiments, the processor is configured to control and / or coordinate operation of the DIC 320 and to thereby cause performance of one or more steps of the method described herein by the DIC 320 and / or by the WD 302 (e.g., by providing configuration information, schedul-ing information, control commands and / or processing parameters to the DIC 320 and / or the WD 302). Accordingly, the method steps described herein may be performed locally in the WD 302 and / or DIC 320 and / or may be performed in a distributed manner across local and remote processing devices.

[0091] Figure 5C illustrates a digital interface chip (DIC) 320 according to some embodiments. As shown in figure 5C, the DIC 320 comprises a first and a second digital interface 342, 352 (as described above). Each of the first and second digital interfaces 342, 352 comprises a transmitter and a receiver. Furthermore, in some embodiments, each of the first and second digital interfaces 342, 352 operates in Time-division duplexing (TDD). TDD is the application of time-division multiplexing to separate transmission from reception in time, i.e. , transmit at a first time instant and receive at a second (different from the first) time instant. In some embodiments, each of the first and second digital interfaces 342, 352 is / comprises a SerDes.

[0092] Generally, all terms used herein are to be interpreted according to their ordinary meaning in the relevant technical field, unless a different meaning is clearly given and / or is implied from the context in which it is used. Reference has been made herein to various embodiments. However, a person skilled in the art would recognize numerous variations to the described embodiments that would still fall within the scope of the claims. For example, the method embodiments described herein discloses example methods through steps being performed in a certain order. However, it is recognized that these sequences of events may take place in another order without departing from the scope of the claims. Furthermore,P4810WG00 / / lnvO38PCT

[0093] some actions / method steps may be performed in parallel even though they have been described as being performed in sequence. Thus, the steps of any methods disclosed herein do not have to be performed in the exact order disclosed, unless a step is explicitly described as following or preceding another step and / or where it is implicit that a step must follow or precede another step. In the same manner, it should be noted that in the description of embodiments, the partition of functional blocks into particular units is by no means intended as limiting. Contrarily, these partitions are merely examples. Functional blocks described herein as one unit may be split into two or more units. Furthermore, functional blocks described herein as being implemented as two or more units may be merged into fewer e.g., a single) unit. Any feature of any of the embodiments / aspects disclosed herein may be applied to any other embodiment / aspect, wherever suitable. Likewise, any advantage of any of the embodiments may apply to any other embodiments, and vice versa. Hence, it should be understood that the details of the described embodiments are merely examples brought forward for illustrative purposes, and that all variations that fall within the scope of the claims are intended to be embraced therein.

[0094] List of some acronyms and abbreviations that may appear in the description

[0095] 3GPP - 3rd Generation Partnership Project

[0096] 5G - fifth generation

[0097] 5G - NR (5G - New Radio) is a new RAT developed by 3GPP for the 5G mobile network ADC - analog-to-digital converter

[0098] AGC - automatic gain controller

[0099] BB - baseband

[0100] BF - beamforming

[0101] BW - bandwidth

[0102] BWP - bandwidth part

[0103] emW - centimetre Wave

[0104] CSI-RS - channel state information reference signal

[0105] CU - control unit

[0106] DAC - digital-to-analog converterP4810WO00 / / lnvO38PCT

[0107] DCI - downlink control information

[0108] DIC - Digital Interface Chip

[0109] DL-PRS - downlink positioning reference signal

[0110] DM-RS - demodulation reference signal

[0111] DS - down-sampling

[0112] FDM - frequency-division multiplexing

[0113] FFT - Fast Fourier Transform

[0114] FR1 - Frequency Range 1

[0115] FR1.5 - Frequency Range 1.5

[0116] FR2 - Frequency Range 2

[0117] Fe - Front end

[0118] FWA - Fixed Wireless Access

[0119] GNSS - Global navigation satellite system

[0120] GPS - Global Positioning System

[0121] IF - intermediate frequency

[0122] IFFT- Inverse Fast Fourier Transform

[0123] I / O - input / output

[0124] LI - Layer 1

[0125] LNA- Low Noise Amplifier

[0126] LO - Local Oscillator

[0127] LoS - Line of Sight

[0128] LTE - Long-Term Evolution

[0129] MAC - Medium Access Control

[0130] MATARA- multi-antenna transmitter and receiver arrangement MIMO - multiple input, multiple outputP4810WO00 / / lnvO38PCT

[0131] MMSE - Minimum Mean Squared Error

[0132] mmW - millimetre wave

[0133] MRC - maximum ratio combining

[0134] NAS - Non-access Stratum

[0135] nLoS - non-Line of Sight

[0136] NRX - Number of received signals

[0137] NS - Number of Streams

[0138] NTX - Number of transmitting ports

[0139] OFDM - orthogonal frequency-division multiplexing PA - power amplifier

[0140] PBCH - Physical Broadcast Channel

[0141] PCB - printed circuit board

[0142] PCell - primary cell

[0143] PDCCH - physical downlink control channel PDP - Power delay profile

[0144] PDSCH - physical downlink shared channel PHY - Physical Layer

[0145] PLL - phase locked loop

[0146] PSCell - primary secondary cell

[0147] PSS - primary synchronization signal

[0148] PT-RS - Phase Tracking Reference signal PUCCH - physical uplink control channel PUSCH - physical uplink shared channel

[0149] QCL - quasi co-located

[0150] QoS - quality of serviceP4810WC00 / / lnvO38PCT

[0151] RAT - radio access technology

[0152] RRC - radio resource control

[0153] RSRP - Reference Signal Received Power RSRQ - Reference Signal Received Quality RSSI - Received Signal Strength Indicator SCell - Secondary Cell

[0154] SNR - Signal-to-noise ratio

[0155] SSB - Synchronization Signal Block

[0156] SRS - sounding reference signal

[0157] SSS - secondary synchronization signal STEF - spatio-temporal filter

[0158] STF - spatial transmission filter

[0159] TCI - Transmission Configuration Indicator TNode - transceiver node

[0160] VGA - variable gain amplifier

[0161] WD - wireless device

Claims

P4810WC00 / / lnvO38PCT1. A digital interface chip, DIC, (320), comprisable in a wireless device, WD, (302), connectable to two or more transceivers (506, .... 510), connectable to a first chip (318) via a first digital interface (342), and connectable to a second chip (600, 322) via a second digital interface (352), wherein the DIC (320) is configurable to be in a receiving mode or in a transmitting mode, and wherein the DIC (320) is configured, while in a receiving mode, to:receive a set of radio signals, the set of radio signals comprising one radio signal from each of the two or more transceivers (506, .... 510);post-process the received set of radio signals, wherein post-processing the received set of radio signals comprises splitting the received set of radio signals into a first and a second subset (r21, r22), wherein the first and second subsets (r21, r22) are disjoint;send a first signal (SI) comprising the first subset (r21) to the first chip (318) via the first digital interface (342); andsend a second signal (S2) comprising the second subset (r22) to the second chip (600, 322) via the second digital interface (352);and wherein the DIC (320) is configured, while in a transmitting mode, to: receive a first baseband, BB, signal (tl) from the first chip (318) via the first digital interface (342);receive a second BB signal (t2) from the second chip (600, 322) via the second digital interface (352);pre-process the first and second BB signals (tl, t2) to obtain a set of transmit signals (TSO, .... TS15); andsend the set of transmit signals (TSO, .... TS15) to the two or more transceivers (506, .... 510) for transmission to one or two or more remote transceiver nodes, TNodes (397, 398, 399).

2. The digital interface chip, DIC, (320) of claim 1, wherein the DIC (320) is further configured, while in the receiving mode, to:receive a third signal (rl2) from the first chip (318) via the first digital interface (342); combine the third signal (rl2) with the second subset (r22), andwherein the second signal (S2) comprises the third signal (rl2).

3. The digital interface chip, DIC, (320) of claim 1 or claim 2, wherein the DIC (320) is further configured, while in the receiving mode, to:receive a fourth signal (r31) from the second chip (322) via the second digital interface (352);combine the fourth signal (r31) with the first subset (r21), andP4810WC00 / / lnvO38PCTwherein the first signal (SI) comprises the fourth signal (r31).

4. The digital interface chip, DIC, (320) of any one of claims 1-3, wherein the DIC (320) is further configured, while in a transmitting mode, to:apply a first function (fl) to the first BB signal (tl) to obtain a first resulting signal (altl); andtransmit the first resulting signal (altl) to the second chip (600, 322) via the second digital interface (352).

5. The digital interface chip, DIC, (320) of any one of claims 1-4, wherein the DIC (320) is further configured, while in a transmitting mode, to:apply a second function (f2) to the second BB signal (t2) to obtain a second resulting signal (a2t2); andtransmit the second resulting signal (a2t2) to the first chip (318) via the first digital interface (342).

6. The digital interface chip, DIC, (320) of any one of claims 1-5, wherein each radio signal comprises an in-phase component and / or a quadrature component.

7. A digital interface chip, DIC, (320), comprisable in a wireless device, WD, (302), connectable to two or more transceivers (506, .... 510), connectable to a first chip (318) via a first digital interface (342), and connectable to a second chip (600, 322) via a second digital interface (352), wherein the DIC (320) is configured, while in a receiving mode, to:receive a set of radio signals, the set of radio signals comprising one radio signal from each of the two or more transceivers (506, .... 510);post-process the received set of radio signals, wherein post-processing the received set of radio signals comprises splitting the received set of radio signals into a first subset (r21) and a second subset (r22), wherein the first and second subsets (r21, r22) are disjoint;send a first signal (SI) comprising the first subset (r21) to the first chip (318) via the first digital interface (342); andsend a second signal (S2) comprising the second subset (r22) to the second chip (600, 322) via the second interface (352).

8. A digital interface chip, DIC, (320), comprisable in a wireless device, WD, (302), connectable to two or more transceivers (506, .... 510), connectable to a first chip (318) via a first digital interface (342), connectable to a second chip (600, 322) via a second digital interface (352), and wherein the DIC (320) is configured, while in a transmittingP4810WC00 / / lnvO38PCTmode, to:receive a first baseband, BB, signal (tl) from the first chip (318) via the first digital interface (342);receive a second BB signal (t2) from the second chip (600, 322) via the second interface (352);pre-process the first and second BB signals (tl, t2) to obtain a set of transmit signals (TSO, .... TS15); andsend the set of transmit signals (TSO, .... TS15) to the two or more transceivers (500, 501, .... 515) for transmission to one or more transceiver nodes, TNodes (397, 398, 399).

9. A method (100) of a digital interface chip, DIC, (320, DBFA2), comprisable in a wireless device, WD, (302), connectable to two or more transceivers (506, .... 510), connectable to a first chip (318) via a first digital interface (342), and connectable to a second chip (600, 322) via a second digital interface (352), wherein the DIC (320) is configurable to be in a receiving mode or in a transmitting mode, the method (100) comprising:while the DIC (320) is in a receiving mode:receiving (105), by the DIC (320), a set of radio signals, the set of radio signals comprising one radio signal from each of the two or more transceivers (506, .... 510); post-processing (110), by the DIC (320), the received set of radio signals, wherein post-processing the received set of radio signals comprises splitting the received set of radio signals into a first subset (r21) and a second subset (r22), wherein the first and second subsets (r21, r22) are disjoint;sending (120), by the DIC (320), a first signal (SI) comprising the first subset (r21) to the first chip (318, DBFA1) via the first digital interface (342); andsending (130), by the DIC (320), a second signal (S2) comprising the second subset (r22) to the second chip (600, 322, DBFA3, BB proc) via the second digital interface (352); and / orwhile the DIC (320) is in a transmitting mode:receiving (140), by the DIC (320), a first baseband, BB, signal (tl) from the first chip (318, DBFA2) via the first digital interface (342);receiving (150), by the DIC (320), a second BB signal (t2) from the second chip (600, 322, DBFA3, BB proc);pre-processing (160), by the DIC (320), the first and second BB signals (tl, t2) to obtain a set of transmit signals (TSO, .... TS15); andsending (170), by the DIC (320), the set of transmit signals (TSO, .... TS15) to the twoP4810WO00 / / lnvO38PCTor more transceivers (506, .... 510) for transmission to one or two or more remote transceiver nodes, TNodes (397, 398, 399).

10. A computer program product comprising instructions, which, when executed on at least one processor of a processing device, cause the processing device to carry out the method of claim 9.

11. A non-transitory computer-readable storage medium storing one or more programs configured to be executed by one or more processors of a processing device, the one or more programs comprising instructions which, when executed by the processing device, causes the processing device to carry out the method according to claim 9.

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