Flashlight having optical wireless data communication

Abstract

A handheld light communication system and a device incorporating components of a handheld light communication system are provided. The handheld light communication system includes: a transmitter configured to transmit light; and a receiver configured to determine data encoded in the light transmitted by the transmitter. The receiver includes: a light sensor for sensing the light transmitted by the transmitter; analog circuitry configured to generate a conditioned analog signal based on a light signal that is output from the light sensor; and a digital signal processing device configured to recover a clock of the light transmitted by the transmitter by processing the conditioned analog signal and to decode the data encoded in the light using the clock.

Description

FLASHLIGHT HAVING OPTICAL WIRELESS DATA COMMUNICATIONTECHNICAL FIELD

[0001] This invention relates to flashlights and other handheld or personally-portable devices, and to systems, and methods for establishing and communicating across an ad hoc, light-based data network, and to a physical layer communication platform and protocol for the network.BACKGROUND

[0002] Flashlights developed out of the need for personal, local illumination in low light environments, such as outdoors at night or within buildings when electric sources of illumination available. Traditional flashlights utilized incandescent bulbs, but nowadays typically use LEDs that supply white light, albeit of differing color temperatures. Although the modulation of the light output for purposes of signaling is known, e.g., by switching the flashlight on and off to gain attention or to disaffect a possible attacker, there are no know uses of flashlights for automated peer to peer data communication between the flashlight and another electronic device.

[0003] In an entirely different field of technology, optical wireless communication systems, in which light is modulated to encode data or information for communication between light communication nodes, are known for various applications, such as for establishing ad hoc networks among peers; for example, in one vehicular application, a visible light communication (VLC) system may be used for vehicle-to-vehicle communications, as described in U. S. Patent No. 11,245,469 and U. S. Patent Application Publication Nos. US2023 / 0065439A1 and US2023 / 0308254A1.SUMMARY

[0004] In accordance with an aspect of the invention, there is provided a handheld light communication system. The handheld light communication system includes: an input interface device for receiving an input from a user of the handheld light communication device and / or sensor data captured by the handheld light communication device; a transmitter configured to transmit light according to the input received at the input interface device; and a receiver configured to determine data encoded in the light transmitted by the transmitter. The receiver includes: a light sensor for sensing the light transmitted by the transmitter; transimpedance op-amp circuitry having a transimpedance op-amp integrator circuit and a transimpedance op-amp differentiator circuit; a gain control circuit; and adigital signal processing device configured to recover a clock of the incoming light and to decode the data encoded in the light using the clock.

[0005] According to various embodiments, the light communication system of the first aspect of the invention may further include any one of the following features or any technically -feasible combination of some or all of these features:- the handheld light communication system includes a flashlight having the transmitter;- the transimpedance op-amp circuitry and the gain control circuit are a part of analog circuitry that generates a conditioned analog signal based on a light signal that is output from the light sensor;the transimpedance op-amp integrator circuit is configured to generate a transimpedance integrated output signal by amplification of the sensor signal; - the transimpedance op-amp differentiator circuit is configured to generate a bandpass-filtered signal based on bandpass filtering of the transimpedance integrated output signal;- the gain control circuitry is configured to generate an analog gain control signal adjusting gain of an analog signal output by the transimpedance op-amp integrator circuit;- the gain control circuitry includes a non-inverting automatic op-amp circuit having a non-inverting op-amp for generating the analog gain control signal; - the digital signal processing device is a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC);- the digital signal processing device includes an analog-to-digital converter (ADC) for converting an analog signal output by the gain control circuit into a digital signal;- the digital signal processing device includes an automatic gain control (AGC) module configured to generate a digital gain control signal based on sampled data sampled based on an analog signal output by the gain control circuit;- the digital signal processing device includes a clock data recovery (CDR) module for recovering a clock of the light transmitted by the transmitter and for decoding data encoded within the light using the clock;- the CDR module includes a clock recovery (CR) module and a data decoder module;- the CR module is configured to recovering the clock of the light transmitted by the transmitter;- the data decoder module is configured to decode the data encoded within the light using the clock;- the CDR module uses a finite-state machine (FSM) as a part of decoding the data encoded within the light using the clock;- the FSM is configured to implement an error correcting procedure using Reed- Soloman error correction or other error correction framework; and / or- the light sensor is a photodiode.

[0006] In accordance with a second aspect of the invention, there is provided a handheld light communication system. The handheld light communication system includes: an input interface device for receiving an input from a user of the handheld light communication device and / or sensor data captured by the handheld light communication device; a transmitter configured to transmit light; and a receiver configured to determine data encoded in the light transmitted by the transmitter. The receiver includes: a light sensor for sensing the light transmitted by the transmitter; analog circuitry configured to generate a conditioned analog signal based on a light signal that is output from the light sensor; and a digital signal processing device configured to recover a clock of the light transmitted by the transmitter by processing the conditioned analog signal and to decode the data encoded in the light using the clock.

[0007] According to various embodiments, the light communication system of the second aspect of the invention may further include any one or more of those features discussed above in connection with the first aspect of the invention and / or any of the following features or any technically-feasible combination of some or all of these features:- the conditioned analog signal is generated by conditioning the light signal through transimpedance amplification and / or bandpass filtering;a transimpedance op-amp differentiator circuit is used for performing the bandpass filtering through generating a bandpass-filtered signal based on a transimpedance integrated output signal output from a transimpedance op-amp integrator circuit; and / or- the handheld light communication system includes a flashlight having the transmitter.

[0008] In accordance with a third aspect of the invention, there is provided a handheld light communication device. The handheld light communication device includes: a flashlighthaving a flashlight circuit. The flashlight circuit includes a transmitter configured to transmit light that is to be received at a receiver. The receiver is configured to determine data encoded in the light transmitted by the transmitter. The receiver includes: a light sensor for sensing the light transmitted by the transmitter; analog circuitry configured to generate a conditioned analog signal based on a light signal that is output from the light sensor; and a digital signal processing device having an automatic gain control (AGC) module and a clock recovery module, wherein the AGC module is configured to generate a gain-controlled digital signal, wherein the clock recovery module is configured to recover a clock of the incoming light, and wherein the clock of the incoming signal is used to decode the data encoded in the light.

[0009] According to various embodiments, the handheld light communication device of the third aspect of the invention may further include any one or more of those features discussed above in connection with the first or the second aspect of the invention. According to an embodiment, the handheld light communication device of the third aspect of the invention is characterized by the flashlight includes a light source for transmitting the light and / or for providing illumination to an area at which the flashlight is operated.

[0010] According to various embodiments, the handheld light communication system of the first aspect of the invention may further include any one or more of those features discussed above in connection with the second or the third aspect of the invention. Also, according to various embodiments, the handheld light communication system of the second aspect of the invention may further include any one or more of those features discussed above in connection with the third aspect of the invention.BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Preferred exemplary embodiments will hereinafter be described in conjunction with the appended drawings, wherein like designations denote like elements, and wherein:

[0012] FIG. 1 is a block diagram depicting a light communication system having a flashlight used for light communications and a facility that has a receiver, according to one embodiment;

[0013] FIG. 2 is a block diagram depicting a flashlight circuit that includes a transmitter circuit and that is used for the flashlight of FIG. 1, according to one embodiment;

[0014] FIG. 3 is a block diagram depicting a receiver circuit that is located at the facility of FIG. 1 and that may be used for light communications with the flashlight of FIG. 1, according to one embodiment;

[0015] FIG. 4 depicts an exemplary LED array suitable for use the in the flashlight of FIG.1, according to one embodiment;

[0016] FIG. 5 depicts a store and forward (SAF) flashlight that includes a user interface and display for textual and audio input, according to one embodiment;

[0017] FIG. 6 is a block diagram depicting components of a transmitter that may be used in the flashlight of FIG. 1, according to one embodiment;

[0018] FIG. 7 illustrates circuitry used for a power supply circuit of the transmitter of FIG.6, according to one embodiment;

[0019] FIG. 8 illustrates circuitry used for a microcontroller decoupling circuit of the transmitter of FIG. 6, according to one embodiment;

[0020] FIG. 9 depicts an exemplary microcontroller that may be used for the transmitter of FIG. 6, according to one embodiment;

[0021] FIG. 10 illustrates circuitry used for microcontroller programming / debugging components that may be used with or for the transmitter of FIG. 6, according to one embodiment;

[0022] FIG. 11 illustrates circuitry used for a light source driver circuit of the transmitter of FIG. 6, according to one embodiment;

[0023] FIG. 12 is a block diagram depicting components of a receiver that may be used in the electronic device at the facility of FIG. 1, according to one embodiment;

[0024] FIG. 13 is a block diagram depicting components of a receiver (such as, for example, the receiver of FIG. 12) that may be used in the electronic device at the facility of FIG. 1, according to one embodiment;

[0025] FIG. 14 illustrates circuitry used for a power supply circuit of the receiver of FIG.12, according to one embodiment;

[0026] FIG. 15 illustrates various connections used in implementing a receiver (such as, for example, the receiver of FIG. 12) on a printed circuit board (PCB) as well as a set of LEDs operated by a field programmable gate array (FPGA) for monitoring / test, according to one embodiment

[0027] FIG. 16 illustrates circuits used for transimpedance op-amp circuitry of the receiver of FIG. 12, according to one embodiment;

[0028] FIG. 17 illustrates circuitry used for a gain control circuit of the receiver of FIG. 12, according to one embodiment;

[0029] FIG. 18 illustrates circuitry used for a voltage divider circuit of the receiver of FIG.12, according to one embodiment;

[0030] FIG. 19 illustrates circuitry used for a voltage follower circuit of the receiver of FIG.12, according to one embodiment;

[0031] FIG. 20 depicts a Bode diagram with two graphs illustrating a bandpass filter with the frequency response of the transimpedance op-amp circuitry of FIG. 16, according to one embodiment;

[0032] FIG. 21 illustrates aspects of a transmission encoding scheme (protocol) used by the transmitter and receiver, including a packet level diagram for Table 1, along with the Reed- Solomon bytes at the end of the packet, according to one embodiment;

[0033] FIG. 22 illustrates aspects of a transmission encoding scheme (protocol) used by the transmitter and receiver, including an exemplary structure of a single data byte, according to one embodiment;

[0034] FIG. 23 depicts a CMOD A7-35T development board for a programmed FPGA used to carry out the ADC and digital functions, according to one embodiment;

[0035] FIG. 24 depicts graphs showing sample waveforms from an automatic gain control (AGC) state machine, according to one embodiment;

[0036] FIG. 25 is a block diagram of a clock recovery (CR) module of the digital signal processing device of the receiver of FIG. 12, according to one embodiment;

[0037] FIG. 26 is a block diagram of a quadrature signal conditioning module and a signal multiplier of the CR module of FIG. 25, according to one embodiment;

[0038] FIG. 27 is a graph illustrating frequency response magnitude of a frequency error signal resulting from the quadrature signal conditioning module and the signal multiplier of FIGS. 25-26, according to one embodiment;

[0039] FIG. 28 is a block diagram of a proportional integral (PI) controller of the CR module of FIG. 25, according to one embodiment;

[0040] FIG. 29 is a block diagram of a portion of the CR module of FIG. 25 including a roll-over accumulator (sawtooth generator), according to one embodiment;

[0041] FIG. 30 is a unit circle and graph illustrating aspects of a direct digital synthesizer (DDS) used as a part of the CR module of FIG. 25, according to one embodiment;

[0042] FIG. 31 is a block diagram of a VHDL (Very High-Speed Integrated Circuit (VHSIC) Hardware Description Language) component used as a part of a Reed-Soloman State Machine for a clock data recovery (CDR) module of the receiver of FIG. 12, according to one embodiment;

[0043] FIG. 32 is an exemplary prototype implementation of a receiver and transmitter that may be used in the light communications systems described herein, according to one embodiment;

[0044] FIG. 33 is another exemplary prototype implementation of a receiver and transmitter that may be used in the light communications systems described herein, according to one embodiment;

[0045] FIG. 34 illustrates various commercially-available vehicle exterior lamp modules modified to include a transmitter that may be used in the light communications systems of described herein, according to one embodiment;

[0046] FIG. 35 is a block diagram depicting a light communication system including a transmitter and a receiver, including an interface input device in communication with the transmitter and a HMI output device in communication with the receiver, according to one embodiment;

[0047] FIG. 36 is a block diagram depicting a light communication system including a pair of transceivers, and including an interface device in communication with each transceiver, according to one embodiment; and

[0048] FIG. 37 is a block diagram depicting a microphone-input light communication system, which may be used for the light communication systems of FIGS. 35 and 36, according to one embodiment.DETAILED DESCRIPTION

[0049] Referring to FIG. 1 there is shown a flashlight 40 constructed in accordance with an embodiment of the invention. The flashlight includes LED or an array of LEDs to provide visible illumination suitable for the intended use. The flashlight further includes a circuit 42 shown diagrammatically that powers the LED(s). Circuit 42 will be described in greater detail below, but in general includes a transmitter circuit (also referred to herein simply as a transmitter) that is able to modulate current to the LED(s) so as to encode a data communication within the modulated LED light. This can be useful for various purposes, including emergency signaling or “store and forward” (SAF) communication to an electronic device at a facility 50 when no wireless communication network is available for remote connection.

[0050] FIG. 2 is a block diagram of the flashlight circuit 42. It includes a transmitter circuit 44 connected to the LED(s) of the flashlight to send modulated current through the LED(s) to produce the encoded light-based data transfer. The circuit 42 further includes an inputdevice 46 that enables entry of the data to be encoded and sent. Input device 46 can be, for example, a microphone with suitable circuitry that receives and provides audio data to be digitized and encoded for transmission by the transmitter 44. Alternatively, the input device can be one that reads data from a data storage medium such as an SD card. Any other desired type of input device suitable for a particular application can be used. The flashlight circuit 42 includes a battery 48, which may be, for example, a 12 Volt battery.

[0051] FIG. 3 depicts a receiver circuit 51 that can be located at the facility 50 or otherwise incorporated into a physical device 58. The receiver circuit includes a receiver 52 for reception of the modulated light, an input / output (I / O) circuit 54, and a presenter 56, such as a display for text or a speaker for audio output.

[0052] FIG. 4 shows an LED array suitable for use the in the flashlight 40. It can include visible as well as infrared and / or UV LEDs. This enables various implementations of the data communication independently of the use of the same or different LEDs in the array for regular illumination as a flashlight. For example, IR or UV LEDs can be used for data communication with visible light LEDs in the array used for the normal flashlight function. Alternatively, the same LED(s) used for flashlight illumination can also be modulated with the data by combining the scene illumination power and modulated data power to the same LED(s).

[0053] FIG. 5 depicts a store and forward (SAF) flashlight that includes a user interface and display for textual and audio input. It includes a transmit and receive optical array at the top side. This device includes at least the circuitry of FIG. 2 for use in receiving and transmitting data optically. As discussed below, it can also include the receiver circuit of FIG. 3 to enable bi-directional communication.

[0054] The following description details the means by which the input device data at the flashlight is processed and optically transmitted, and how the transmitted modulated light is processed to decode the embedded data once received.

[0055] The technology discussed herein enables synchronization of communications between two electronic devices that are carried out using optical or light communications. This permits establishment of intrinsic synchronization in peer-to-peer ad hoc networks. Electronic devices having optical or light communication capabilities, such as line-of-sight optical communication capabilities, are each referred to herein as a light communication node and may include one or more transmitters for transmitting light in order to send data to another node and / or may include one or more receivers for receiving light in order to obtain data sent by another node. The “light” or “optical” communications discussed hereinmeans not only visible light (e.g., for VLC), but also light invisible to the human eye that has a wavelength suitable for use in line-of-sight or reflective communication, including at least portions of the infrared (IR), visible, and ultraviolet (UV) light spectrums. The transmitter encodes or modulates the data using light at or according to a transmitter clock rate and transmits such encoded data as a data input stream, which is then received at the receiver. At least in some embodiments, in order to properly decode and / or interpret the data input stream so as to obtain the data that is being communicated by the transmitter, the receiver synchronizes a clock that matches that used by transmitter to encode the data input stream. The synchronized clock is then used to decode the data input stream so as to obtain the data.

[0056] Transmitter 44 and receiver 52 have a design, construction, and operation that will be described below, but can include one or more of the features disclosed in the aforementioned U. S. Patent No. 11,245,469 and U. S. Patent Application Publication Nos. US2023 / 0065439A1 and US2023 / 0308254A1, the entire disclosures of which are hereby incorporated by reference.

[0057] Although flashlight 40 of FIG. 1 is depicted as including only a transmitter 44, it can also include a receiver such as receiver 52 so as to enable bi-directional (duplex) data transfer between the flashlight and another electronic device. This can be done by integrating transmitter 44 into a transceiver that also includes a receiver. Similarly with the receiver circuit 51 which can also be implemented using a transceiver. Such transceivers can include a transmitter 44 and receiver 52 separately in each transceiver, or can have them integrated together using a single circuit that provides all of the necessary analog and digital functions. Further, the transceivers in the flashlight and the other communicating device (e.g., at facility 50) can be identical transceivers or ones having different components or parameters, such as to utilize different clock rates or otherwise to permit rejection of unwanted received light modulations. As will become apparent to those skilled in the art, this use of different transmission attributes by different transmitters can be used by a receiver or transceiver to reject any received (e.g., reflected) light data transmissions originating from itself or from mixing of communications coming from multiple other devices.

[0058] As noted above, although the light used for communication can be inside or outside of the visible spectrum, many embodiments of the transmitter and receiver can use visible light, such as is used in visible light communication (VLC) systems. This allows for the use of existing device components such as the illumination-providing lights used for vehicleexterior illumination and other illuminating devices and applications. Except where otherwise described, the transmitters, receivers, and transceivers described utilize visible light to set up a VLC network, such that circuits 42 and 51 of FIGS. 2 and 3 can be referred to as VLC systems 42 and 51.

[0059] Turning now to FIGS. 6-11, the construction of the transmitter 44 will be described.The transmitter 44 includes a power supply circuit 102, a microcontroller decoupling circuit 104, microcontroller programming / debugging components 106, a microcontroller 108, a light source driver circuit 110, and a light source 112. In other embodiments, the transmitter 44 may include other components or may omit one or more components, such as, for example, one or more of components 102-106. In FIG. 6, in general, the double-line compounded arrows illustrate electric power and the single-line compounded arrows illustrate electronic signals.

[0060] In general, the transmitter 44 utilizes a 32-bit microcontroller, such as an STM32F103 available from STMicroelectronics, along with a metal-oxide-semiconductor field-effect transistor (MOSFET) connected to drive a dedicated or existing lamp (or light emitting diode (LED)) in the Device A (e.g., vehicle 610 or 618). This can be done using the microcontroller’s USART hardware to pulse the MOSFET for modulation of the light output. Components such as the 12V-to-5V DC voltage regulator, power MOSFET, pin headers, and 12V battery power cable connectors are through-hole. According to the present embodiment, the rest of the design utilizes surface-mount components.

[0061] The power supply circuit 102 is connected to a battery, such as, for example, a 12V battery. The power supply circuit 102 is used for stepping down the voltage of the battery to a suitable voltage for the microcontroller 108. In the present embodiment, power for the transmitter components is generated from 12V battery voltage by the circuitry of FIG. 7 to provide 5V and 3.3V (3V3) supplies. A pair of shrouded blade-style battery connectors supply 12 VDC nominal and Ground connections to the board. The 12V input power is stepped down to 5V by an L7805 through-hole low-dropout (LDO) regulator 114, and this 5V is in turn stepped down to 3.3V by an LP5907 LDO regulator 116. A small indicator LED D1 confirms that 12V input is connected and both LDO regulators 114,116 are active.

[0062] The microcontroller decoupling circuit 104 is configured to apply power supply smoothing to the power supplied by the battery via the power supply circuit 102. In the present embodiment, the microcontroller decoupling circuit 104 includes a bulk decoupling capacitor 118 to filter out noise from the power supply circuit 102, individual decoupling capacitors 120 deployed at each digital voltage pin, and a choke 122 configured to impedehigh-frequency signals. In the present embodiment, FIG. 8 depicts the microcontroller decoupling circuit 104 with the bulk decoupling capacitor 118 being 4.7 μF and configured to filter out noise from the LDO regulators 114,116. The individual decoupling capacitors 120 of the present embodiment of FIG. 8 are individual 100 nF decoupling capacitors and are deployed at each digital voltage input pin. Furthermore, additional smoothing required for the analog voltage input can be achieved using the choke 122, which is 27 nH in the present embodiment of FIG. 8 and which is placed in series with parallel 1 μF and 100 nF capacitors. This extra power supply smoothing may be superfluous in this application as the microcontroller’s analog hardware is not utilized and may be omitted in certain embodiments.

[0063] The microcontroller 108 is used for controlling the light source driver circuit 110 in order to cause the light source 112 to be driven according to data received at the microcontroller 108 from the Device A (or Device C or D). FIG. 9 depicts an embodiment of the microcontroller 108 in which the microcontroller 108 is a STM32F103 microcontroller. In embodiments, the microcontroller 108 has: timing pins [PD0, PD1] for connecting to a high-speed external crystal oscillator; Universal Synchronous / Asynchronous Receiver / Transmitter (USART) hardware; a light source driver pin for outputting signals driven by the USART hardware; and microcontroller programming / debugging pins for connecting to the programming / debugging components 106. According to the present embodiment, apart from power and ground connections, the only other pins required to be connected on the STM32F103 microcontroller in this application are:- PD0 and PD1, for the high-speed external crystal oscillator (Y1 in the diagram above)- PA2, for the USART hardware Tx output, which drives our light-modulating power MOSFET.- PA13 and PA14, for the Serial Wire Debug (SWD) Input / Output and Clock signals, respectively. SWD is used for both programming and debugging purposes.- NRST, BOOT0, and PB2 (BOOT1).

[0064] The microcontroller programming / debugging components 106 are used for programming and / or debugging the microcontroller 108. Referring to FIG. 10, Serial Wire Debug can be connected for programming and debugging the microcontroller through a set of five header pins (left figure), with 3.3 V and 5 V references provided over Universal SerialBus (USB) from a debugging tool. The microcontroller boot mode can be selected prior to power-on by toggling the boot pins (middle figure) according to the guidance contained in STMicro Application Note 2606. Finally, a jumper connected to the reset pin NRST (right figure) allows the pin to be toggled for microcontroller unit (MCU) reset. A 1 μF capacitor helps debounce the NRST input.

[0065] The light source driver circuit 110, also referred to as the lamp driver circuit, is shown in FIG. 11. In the present embodiment, the light source driver circuit 110 uses through-hole N-channel power MOSFET (Onsemi / F airchild FQP30N06L or equivalent) to on-off key the connected LED illumination source that provides the modulated light data used in communicating with the receiver 52. There is a pull-down resistor on the MCU USART Tx pin to ensure it does not float during MCU initialization. The USART Tx output acts on the MOSFET gate, switching the 12 V supply to the LED (the light source 112 of the present embodiment).

[0066] These physical components of FIGS. 6-11 make up the transmitter using the communications protocol described below following a discussion of the receiver analog circuitry. The associated programming of the microcontroller of transmitter 44 to carry out the communications according to the described protocol will be apparent to those skilled in the art.

[0067] FIGS. 12-31 depict the construction and operation of the receiver 52, including both its analog front end 202 and its signal processing carried out by a digital signal processing device 204 (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC)) that implements the digital processing to determine clocking and recover data from the modulated light signal received from the transmitter 44. FIGS. 12-19 depict the analog front end 202, with FIG. 13 being a block diagrammatic view of the analog circuitry that filters and pre-processes the received light signal prior to its conversion to digital and processing by the digital signal processing device 204.

[0068] The analog front end 202 of the receiver 52 includes a power supply circuitry 206 for conditioning power provided to the other components of the receiver 52, a light sensor 208 depicted as a photodiode in the present embodiment, and analog circuitry 210. The light sensor 208 is configured to sense incoming light, such as the light transmitted by the transmitter 44, and to generate a sensor signal, which is a photodiode signal generated by the photodiode (light sensor 208) in the present embodiment. In the present embodiment, the analog circuitry 210 is configured to generate a conditioned analog signal based on the sensor signal and a photodiode reverse bias signal from photodiode reverse bias circuit.

[0069] In the present embodiment, the analog front end 202 includes the light sensor (photodiode) 208, a two-stage capacitive-feedback transimpedance operational amplifier topology, a gain stage, a clipping circuit, and voltage leveling to bring the signal into the voltage into the ADC’s sampling threshold (0V to 3V3). Apart from that, there is a DC-DC railsplitter, which is fed +5V DC and outputs −5V DC to +5V DC, granting 10 Vpeak-to-peak for op-amp rails. This all culminates into the processed signal being fed into the ADC of a CMOD A7-35T breadboardable FPGA development board, which is also used to source power for the rest of the circuit via USB. This CMOD A7-35T utilizes the XC7A35T- 1CPG236C SoC FPGA.

[0070] According to the present embodiment, the photodiode part number is the SFH 203 P, manufactured by AMS OSRAM, and there are three dual-channel op-amps, providing six op-amps in total. These are part number OPA2810IDGKR. The system of the present embodiment operates on 5VDC input, which is sourced from the host computer’s USB port via a 5V DC and GND pin on the FPGA daughter board. This is fed into a IAB0105D05 isolated DC-DC Converter, which outputs an isolated -5V DC, +5V DC, and GND. These power supply circuits of the power supply circuitry 206 are shown in FIG. 14. FIG. 15 depicts various connections used in implementing the receiver on a printed circuit board (PCB) as well as a set of LEDs operated by the FPGA for monitoring / test.

[0071] The receiver 52 is implemented on a CMOD A7-35T, which is an FPGA Development board with many built in peripherals for speedy prototyping and development, namely a 1 MSPS ADC. The rest of the PCB design consists of passive discrete components, namely SMT resistors and capacitors of various values.

[0072] In the preset embodiment, the analog circuitry 210 includes: transimpedance op-amp circuitry 212, gain control circuitry 214, an analog-to-digital converter (ADC) voltage divider circuit 216, and a voltage follower circuit 218.

[0073] Referring to FIG. 16, the transimpedance op-amp circuitry 212 of the present embodiment is shown and includes: a transimpedance op-amp integrator circuit 220 for generating a transimpedance integrated output signal by amplification of the sensor signal and using the photodiode reverse bias signal; and a transimpedance op-amp differentiator circuit 222 for generating a bandpass-filtered signal based on bandpass filtering of the transimpedance integrated output signal.

[0074] In the present embodiment, the transimpedance op-amp circuitry 212 includes a filtered, voltage-divider reverse bias comparative voltage for the photodiode (Pd Rev Bias), as well as the integrator 220 with DC drain and the differentiator 222 witha single pole for stability. The photodiode 208 of the receiver 52 is shown connected to the inverting input of the first stage of the transimpedance op-amp circuitry 212. This transimpedance op-amp integrator circuit 220 is used to convert the current from the photodiode to a voltage signal, and is based a capacitive-feedback integrator with DC drain topology. This means that in lieu of a resistor (as is standard in transimpedance topologies) between the op-amp output and the inverting input pin of the op-amp, a capacitor is used for feedback. The DC-Drain component acts as a low-pass filter, which (at least in the present embodiment) is necessary for eliminating ambient light with low frequency change in intensity (e.g., sunlight, streetlights, etc.). The output of this transimpedance op-amp integrator circuit 220 is fed into a differentiator op-amp (of the transimpedance op-amp differentiator circuit 222), which extends the high frequency cut-off. The topology as a whole effectively acts as both a current-to-voltage converter, and a band-pass filter.

[0075] Given that this topology is composed of linear components (resistors, capacitors, and op-amps), and devoid of non-linear components (diodes and transistors), the system can be represented as a linear-time-invariant (LTI) system with a corresponding transfer function in the s-domain. For this circuit, the transfer function simplifies down to:Equation (1)RH(s) = R4 / R2CfWith the component values selected in the schematic, this gives us a bandpass filter with the frequency response shown in FIG. 20.

[0076] Referring back to FIG. 13, after processing by the transimpedance op-amp analog circuitry 212, the signal is fed into gain control circuitry 214, which includes a non-inverting op-amp circuit 224 and a diode clamp and power dissipation circuit 226. The non-inverting op-amp circuit 224 includes a non-inverting op-amp 228 that can be implemented with or without automatic gain control (AGC) and also includes a trim plot adjustable resistor 230 (implemented as a trim potentiometer). This is shown in FIG. 17 and can be done using an OPA2810 op-amp. Furthermore, in the present embodiment, the trim potentiometer 230 is used to set the desired amplification and maximum voltage range. The gain control circuitry 214 is configured for generating an analog gain control signal that is used for adjusting gain of the bandpass-filtered signal output by the transimpedance op-amp circuitry 212. This opamp output (or is fed into the diode clamp and power dissipation circuit 226 to keep thesignal between approximately -0.6 and 0.6 volts. This signal output by the diode clamp and power dissipation circuit 226 is referred to as a clamped analog gain control signal.

[0077] The clamped analog gain control signal is then buffered and summed with an ADC offset voltage generated using the voltage divider circuit 216 of FIG. 18. FIG. 19 depicts the voltage follower circuit 218, which is implemented using a voltage follower op-amp 232 that buffers the input signal, and it and the ADC offset are summed together at the noninverting input of a second OPA2810 op-amp 234 having feedback to its inverting input. That final analog output (also referred to as an analog circuit output signal) is then provided via a current limiting resistor to the FPGA ADC input.

[0078] The digital signal processing device 204 is a FPGA in the present embodiment;however, according to other embodiments, the digital signal processing device 204 is an ASIC or other processing device or electronic data processor. According to embodiments, any one or more of the processors discussed herein, including each of the at least one digital signal processing device 204, is an electronic processor that may be implemented as any suitable electronic hardware that is capable of processing computer instructions and may be selected based on the application in which it is to be used. Examples of types of processors that may be used include central processing units (CPUs), graphics processing units (GPUs), field-programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), microprocessors, microcontrollers, etc. Any one or more of the non-transitory, computer- readable memory discussed herein, including the memory of the digital signal processing device 204, may be implemented as any suitable type of memory that is capable of storing data or information in a non-volatile manner and in an electronic form so that the stored data or information is consumable by the processor. The memory discussed herein is computer- readable memory, may be any of a variety of different electronic memory types, and may be selected based on the application in which it is to be used. Examples of types of memory that may be used include magnetic or optical disc drives, ROM (read-only memory), solid- state drives (SSDs) (including other solid-state storage such as solid state hybrid drives (SSHDs)), other types of flash memory, hard disk drives (HDDs), non-volatile random access memory (NVRAM), etc.

[0079] With reference back to FIG. 12, the digital signal processing device 204 includes an ADC 236 for generating a sampled data signal based on the analog circuit output signal; an automatic gain control (AGC) module 238 for generating a digital gain control signal based on the sampled data signal and using a sequential propagation state machine; and a clock data recovery (CDR) module 240 having a clock recovery module 242 for generating arecovered clock output based on the digital gain control signal and also having a data decoder module 244 for decoding data within the sampled data signal based on the recovered clock output.

[0080] Turning to FIGS. 21 and 22, the transmission encoding scheme (protocol) used by the transmitter 44 and receiver 52 will now be described.

[0081] According to the present embodiment, each packet sent over the VLC network consists of 228 data bytes, 16 Reed-Solomon Error Correction bytes, and 11 “locator” bytes, for a total packet length of 255 bytes. This gives a Reed-Solomon notation RS(255,239). Locator bytes are static predetermined bytes situated throughout the packet that allows the receiver to know when a packet has been fully received. The locator bytes are positioned at the following indices with the values in Table 1:TABLE 1Locator Byte Index Locator Byte Value (Hexadecimal)2 0xF09 0x7012 0x0C25 0x3D42 0xE866 0x9074 0xF078 0xC783 0xB895 0xB2119 0xF7

[0082] FIG. 21 shows the packet level diagram for this table, along with the Reed-Solomon bytes at the end of the packet.

[0083] In the present embodiment, the data signal is Manchester Encoded and utilizes the dedicated Universal Asynchronous Receiver / Transmitter (UART) hardware of the STM32F103 microcontroller; therefore, the present encoding scheme must adhere to the constraints of UART protocol. In the present embodiment, the transmission scheme features a baud period for the start bit, 8 baud periods for the data, and a baud period for the stop bit, giving a frame a total of 10 baud periods.

[0084] Because, in the present embodiment, the data is Manchester Encoded, each data bit sent takes two baud periods to be transmitted. In this embodiment, therefore, in order to send a single byte of data, two UART bytes are required. FIG. 22 shows the structure of a single data byte.

[0085] The bit rate of the VLC system, in this case meaning the amount of data bits transmitted as a function of baud periods elapsed, can be calculated. For this calculation, the Reed-Solomon CRC bytes, locator bytes, and UART start / stop bits are not considered data bits, and are instead considered part of the packet overhead.

[0086] Each transmitted byte taking 20 baud periods (see FIG. 22), giving a bit rate of8 / 20 = 0.4. Of the 255 total bytes in the package, 11 are locator bytes and 16 are Reed-Solomon Error Correction bytes. This gives 255 - (11 + 16) = 228 transmitted data bytes per packet. In total, this gives a bit rate of 0.4(228 / 255) = 0.358. This means that if the baud rate is 57.6 kbps, the total data rate would be 57600 • 0.358 = 20600 data bits per second.

[0087] FIG. 23 shows the above-noted CMOD A7-35T development board for the programmed FPGA used to carry out the ADC and digital functions that will be described below. In the present embodiment, the FPGA includes the following modules:- XADC (Xilinx ADC IP) as the ADC 236;- AGC / CDR State Machine for the AGC module 238 and the CDR module 240; - UART Manchester Decoder;- Reed-Solomon State Machine; and- MicroBlaze Soft Processor.

[0088] The XADC is the Xilinx Vivado IP that allows sampling from the SoC’s integrated ADC. According to the present embodiment, in order to sample at the maximum sampling rate (1 MSPS), the XADC block must be fed a clock frequency that is a multiple of 26 MHz and between 104 and 250 MHz. For this reason, in the present embodiment, the clock frequency is ran at 156 MHz. In the present embodiment, to bypass timing constraint errors associated with clock-domain crossing (CDC), all custom programmable logic code is also clocked at 156 MHz.

[0089] In the present embodiment, the XADC IP Block is configured to sample a single unipolar (0V to 3 V3) channel in continuous mode at 1 MSPS. The analog signal is sampled through ADC channel 12. Some peripheral functionality is enabled, such as DC offset and gain calibration.

[0090] According to the present embodiment, the channel 12 positive and negative auxiliary ports of the IP Block (vauxp12 and, vauxn12 respectively) are pinned out to the top-level of the block diagram, and assigned to the corresponding pin in the physical constraints file of the project. Input and output data to the IP Block are fed via a Dynamic Reconfigure Port (DRP), a standard common to many Vivado IP along with AXI4-Lite. Through the DRP, the 7 -bit address for ADC channel 12 is specified (address = x" 1C"). The end-of-conversionoutput pin, eoc out, is fed back to the channel enable pin den_en. This restarts the ADC conversion process as soon as it ends. Furthermore, the eoc out port is connected to the input valid i port of the AGC / CDR state machine, meaning the state machine process begins each time a new sample is taken.

[0091] The AGC module 238 and the CDR module 240 process each new sample through a sequential state machine. The state machine waits for the end of conversion (EOC) output pin of the XADC block to go HIGH, signifying a new ADC sample, before beginning. Once a new sample is received, the state machine enables the AGC module 238 and waits for the AGC process to complete. The scaled and zero-centered waveform from the AGC module 238 is then passed to the CDR module 240, which is enabled to process the most recent sample. Once completed, the recovered clock and the most recent bit is output from the state machine. Sample waveforms from the AGC state machine according to the present embodiment are shown in FIG. 24.TABLE 2State Description Δt (Clock Periods) IDLE Waits for input valid signal to go high Variable WRITE AGC Writes most recent sample to the AGC 1 WAIT AGC Waits for valid output from AGC 37Single clock period delayINIT CDR VALS allowing input buff registers1 or CDR state machine to be written toWRITE CDR Initializes and starts CDR state machine 1Waits for CDR state machineWAIT CDR to produce valid output - Total: - -

[0092] The AGC module 238 includes: a signal centering module for generating the digital gain control signal based on the sampled data signal; and a gain control scaling module for generating a scaled digital gain control signal based on the digital gain control signal. The signal centering module generates a centered sampled waveform by filtering the sampled data signal with a moving average filter to get a DC average and subtracting the DV average from each sample to get a digital gain control signal also referred to as a (zero-) centered data signal. The gain control scaling module generates a scaled digital gain control signal based on the digital gain control signal output by the signal centering module. The gain control scaling module generates the scaled digital gain control signal by determining a sample peak value by detecting a peak of the centered data signal using a digital peakdetector circuit / module, detecting a scaling gain factor by dividing a peak reference value by the sampled peak value, and applying scaling according to the scaling gain factor to the centered data signal.

[0093] In the present embodiment, the AGC module 238 centers the sampled waveform on zero (using the signal centering module), then scales the data by a factor determined by a reference peak-to-peak value (using the gain control scaling module). The zero-centering is accomplished by filtering the waveform with a moving average filter to get the digital equivalent of the DC Average, then subtracting the DC average from each sample. Once the data is zero-centered, the peak of the waveform is detected with a digital approximation of a peak detector circuit. A peak reference value is then divided by the sampled peak value to get a scaling gain factor, which is multiplied by the zero-centered data.

[0094] The AGC process described above is accomplished with a sequential propagation state machine, which means that a state machine initializes each step, waits for valid output, and then moves onto the next process. Each state, its description, and the time to perform its corresponding action are outlined in Table 3.TABLE 3State Description Δt (Clock Periods)IDLE Waits for input_valid signal to go high VariableAGC_WAIT_ Waits for valid output from the3 MOVING AVERAGE moving average filterSubtracts the moving averagefrom incoming waveform.AGC ZERO Also, increments1 CENTER SUB TRACT peak detector count s, which isused in the peak detector’sdecay.Delay the subtract operation forAGC ZERO timing closure purposes, and for1 CENTER SUBTRACT D 1 unsigned tosigned type conversion.Delay the subtract operation forAGC ZERO timing closure purposes, and for1 CENTER SUBTRACT D2 unsigned tosigned type conversion.Determines whether peak sAGC_PEAK_ register needs to be updated, dueDETECTOR CALC to a new peak value being 1 CONDITIONALS detected or enough time elapsingto elicit decay.AGC_PEAK_Writes new peak value to DETECTOR_WRITE_ 1peak temp sTEMP PEAK AGC PEAK- Writes peak temp s1 DETECTOR WRITE PEAK to peak sAGC START- Start the Divider Generator1 DIV GEN Vivado IPAGC WAIT- Waits for Divider to26 DIV GEN finish its operationMultiplies the register holdingthe zero-centered data sample AGC_MULTIPLY_by the AGC gain value. Also, 1 GAINtoggles the output valid ooutput port.Total: - 37

[0095] Some real-time signal waveforms pertaining to the AGC system were captured with an Integrated Logic Analyser are shown below.- adc_data_s: 12 bit unsigned. The sampled incoming data from the XADC. Inthis example, the waveform has a crest at approximately 850 and a trough at approximately 810.- moving_ave_s: 12 bit unsigned. The moving average of adc_data_s.- centered_data_13_bit_s: see Table 4.TABLE 4Signal Radix DescriptionThe sampled incoming data from the XADC. In this example, the 12 bit unsigned waveform has a crest at adc data s approximately 850 and a trough at approximately 810.The moving average moving_ave_s 12 bit unsigned of adc data s.The waveform from adc data s centered around zero. Derived by subtracting centered_data_ 13 bit signedadc data s - moving ave s.13_bit_s Bit 13 is just for unsigned to signed conversion.The local maximum of centered data, this signal decays peak s 16 bit unsignedover time.The gain value that is multiplied with 24 bit unsigned fixed-point centered data s. Derived by dividing agc_gain_s with 12 integer bits and 12 target peak-to-peak reference (1000 fractional bits in this case) by peak_s.Output of AGC. Waveform has scaled centered da12 bit signed crest at approximately 1000 and ta_s trough at approximately -1000.

[0096] The CDR module 240 includes a clock recovery (CR) module 242 and a data decoder module 244. The CR module 242 is used for generating a recovered clock output based on the (scaled) digital gain control signal. The data decoder module 244 is used for determining the data encoded in the light signal received at the receiver 52 through use of the recovered clock output from the CR module 242.

[0097] FIG. 25 shows a block diagram of the CR module 242 of the FPGA (the digital signal processing device 204 of the present embodiment). According to embodiments, the CR module 242 includes: a quadrature signal conditioning module 246; a signal multiplier 248; a low-pass Finite Impulse Response (FIR) filter 250; a proportional integral (PI) controller(PI-controller) 252; a sawtooth generator (or arithmetic accumulator) 254; a direct digital synthesizer (DDS) 256; and an exclusive or (XOR) module 258. The quadrature signal conditioning module 246 is used for generating an in-phase (I) signal and a quadrature (Q) signal based on the (scaled) digital gain control signal and sinusoidal waveforms generated by the DDS 256. The signal multiplier 248 is used for generating a phase error signal based on the I signal and the Q signal. The low-pass FIR filter 250 is used for reducing / attenuating high-frequency signals within the phase error signal to generate a filtered phase error signal. The Pl-controller 252 is used for generating a timing control signal based on the (filtered) phase error signal. The sawtooth generator 254 is used for generating a phase accumulator output based on the timing control signal and an initial phase estimate. The DDS 256 is used for generating sinusoidal waveforms (a pair comprised of a sine waveform and a cosine waveform) based on the phase accumulator output. The XOR module 258 is used for generating a recovered clock output based on the sinusoidal waveforms.

[0098] The CDR state machine is based off a Costa’s Loop topology for binary phase shift keyed (BPSK) signals. Once the ADC output waveform is centered and scaled by the AGC state machine, the waveform is split and multiplied by two sinusoidal waveforms 90° out of phase with each other to produce in-phase (LChannel) and quadrature (Q- Channel) signals. The LChannel and Q-Channel are multiplied together at the signal multiplier 248 to produce a phase error signal, which is then filtered by the low-pass FIR filter 250 and fed into the Pl-controller 252. The Pl-controller output is added with an initial phase-step “estimate value,” which is summed with the arithmetic accumulator 254 to produce a roll-over sawtooth signal (also referred to as a phase accumulator output). The slope of this sawtooth signal is what is modulated by the Pl-controller 252, and corresponds to the recovered clock frequency. This sawtooth signal is fed into a Vivado Direct Digital Synthesizer (DDS) IP Core (the DDS 256), and the resulting sine and cosine waveforms generated are XOR-ed together (using the XOR module 258) to produce the recovered clock signal. The sine and cosine are also the two sinusoidal waveforms 90° out of phase with each other, which are mixed with the incoming data, closing the feedback loop.

[0099] According to the present embodiment, the purpose of the CR module 242 is to generate a sine and cosine wave with the same frequency (referred to as the ’’estimated frequency”) which is close in frequency to the incoming data, then determine the frequency error between the estimated frequency and frequency of the incoming data. According to embodiments, although the sampled incoming waveform is ideally a square wave, the clock can be recovered by regarding the waveform as a BPSK sinusoidal. Treating it as asinusoidal, the incoming waveform will have the formula sin(27r ’jnt), where finis the frequency of the incoming data. The waveforms generated with the estimated frequency have the equations sin(2πfestt) and cos(2πfestt) The frequency error is derived as explained below in connection with the channel mixing and the low-pass FIR filter 250.I-Channel Mixing Arithmetic

[0100] As the incoming data is multiplied by a cosine wave with the estimated frequency of fest, the following equation is derived and simplified.Equation (2)sin(2πfint) · cos(2πfestt)Substituting e = 2πfestt and i = 2πfintEquation (3)sin(i) • cos(e)1= - [sin(i + e) + sin(i — e)]Q-Channel Mixing Arithmetic

[0101] As the incoming data is multiplied by a sine wave with the estimated frequency of fest, the following equation is derived and simplified.Equation (4)sin(2πfint) · sin(2πfestt)Substituting e = 2πfestt and i = 2πfintEquation (5)sin(i) • sin(e)1= - [cos(i — e) — cos(i + e)]I-Channel and Q-Channel Mixing Arithmetic

[0102] When the I-Channel and Q-Channel are multiplied together, the following equation is derived and simplified:Equation (6)1— [(sin(i + e) + sin(i — e)) • (cos(i — e) — cos(i + e))]4Substituting i + e = a and i — e =? and expanding:Equation (7)1— [sin (a) cos( / ?) — sin(a) cos(cr) + sin( / ?) cos( / ?) — sin( / ?) cos(cr)]4It is important to note here that the main purpose is to isolate the frequency difference (a.k.a. P = i — e). For example, if the estimated frequency is fest= 100kHz but the incoming data signal is arriving at fin= 101kHz, then / ? = fin— fest= 101kHz — 100kHz = 1kHz. Using Angle-Sum Identity, sin(cr — / ?) = sin(a) cos( / ?) — cos(cr) sin( / ?):Equation (8)1= - [sin(cr — / ?) — sin(a) cos(cr) + sin( / ?) cos( / ?)]4Finally, with the Product Identity sin(cr) cos( / ?) = - [sin(cr + / ?) + sin(cr — / ?)], the equation simplifies to:Equation (9)I t 1 1 ]= — sin(cr — / ?) — — sin(2<z) + — sin(2 / ?)4 2 2The reduced equation can be separated into three terms: (1.) sin(cr — / ?); (2.)-sin(2<z); and (3.) |sin(2 / ?).

[0103] In the previous example described where fest= 100kHz and fin= 101kHz, a = 201kHz and β = 1kHz. The first term is a sinusoidal with frequency of 100kHz, the second term is a sinusoidal with frequency of 402 kHz, and the third term is a sinusoidal with frequency of 2 kHz. As we have isolated ft in the third term, the low-pass FIR filter 250 can be used to attenuate the first two terms. The isolated third term is a sinusoidal that represents the phase difference between the estimated frequency and the frequency of the actual data. This is fed into the Pl-controller 252, which controls the estimates’ frequency and drives the frequency error to zero.

[0104] Mixing the incoming data with two sinusoidal waveforms 90° out of phase with each other is achieved with three Vivado Multiplier IP blocks cascaded as shown in FIG. 26. The resulting signal freq err s is a signed 48-bit integer. Note that the delay blocks in the diagram below are for FPGA meta-stability purposes to close failing timing endpoints. The delays are handled by the wrapper state machine.

[0105] According to the present embodiment, in order to extract the phase difference from the freq err s signal in FIG. 27, a FIR low-pass filter (LPF) (which is the low-pass FIR filter 250 in the present embodiment). Vivado™ provides an FIR Compiler IP, which allows a user to specify the filter coefficients, and the IP will properly pipeline the filter and implement DSP blocks where necessary. This filter is designed as a 65-order filter with a - 3dB cut-off frequency of fc= 9.7kHz, and an output that is a 40 bit signed integer. It hasa sample latency of 33 cycles, after which it toggles the m axis data tvalid output. This filter is used by writing a single sample, enabling the filter, waiting for m axis data tvalid to go high, then disabling the filter until the next sample is ready to be processed.

[0106] The filtered phase difference signal pi controller err input s is then fed into the PI- controller 252 shown in FIG. 28. The Pl-controller 252 is accomplished in 3 clock cycles with 3 states in the state machine. The first state calculates the proportional branch by multiplying the error input by Kp, and adds the error input to an accumulator (a.k.a. integrator) for the integral branch. The second state multiplies the accumulator by Ktby the accumulator value to calculate the value of the integral branch. The final branch calculates the Pl-controller output by adding the values of the proportional and integral branches. In the present embodiment, the output is sliced into a 12 bit signed integer, which is necessary to eventually be fed into the DDS 256.

[0107] Referring to FIG. 29, in the present embodiment, the sawtooth phase generator 254 is used to control the frequency of the sine and cosine waveforms generated by the DDS 256. To achieve this, an initial frequency estimate is tuned to match the frequency of the incoming data waveform. For example, if the incoming data has a frequency of approximately 50 kHz and the sampling rate is 1 MSPS, each received bit will have 20 samples per bit as shown below:Equation (10)1,000,000= 20 samples per bitbits50,000secBecause the DDS 256 of the present embodiment has 65,536 positions around the unit circle, generating an initial frequency estimate of 50 kHz would require the initial_phase_offset_s signal to be (65536 / 20) = 3277. As the phase difference between the generated signal and the actual incoming data signal is fed into the Pl-controller 252, the phase difference is summed with the initial_phase_offset_s signal to get the phase of the corrected signal. This is then added to a 16 bit accumulator, designed to rollover past 65536 (meaning once per period of a received bit). The instantaneous value of the accumulator is the instantaneous phase of the recovered clock, and the rate of change of the accumulator (the number that is added to the accumulator each sample) is the frequency.

[0108] At least in the present embodiment, the DDS 256 is a lookup table capable of simultaneously generating sine and cosine wave- forms. Because the DDS 256 accepts a 16bit unsigned integer as a phase input, it is capable of generating 216= 65536 positions around the unit circle, as shown in FIG. 30.

[0109] The Reed-Solomon State Machine is based on the RS Codec Core. The main VHDL (Very High-Speed Integrated Circuit (VHSIC) Hardware Description Language) component of the core is found in the rs decoder.vhd file, with IO ports corresponding to the following diagram. The parameters of the Reed-Solomon system (which in this case are RS(255,239)) are set as generics in the VHDL file. FIG. 31 is a block diagram of the rs decoder.vhd.

[0110] The FPGA (the digital signal processing device 204 of the present embodiment) contains a MicroBlaze soft processor, which is mainly used to set parameter registers in the FPGA fabric and utilize the USB for printing received data to the host computer.

[0111] According to the present embodiment, when power bootup occurs, the first thing to execute in the MicroBlaze is writing values XGPIO ports, which allow for proper operation of the FPGA. A table describing the names and functions of each XGPIO are outlined in Table 5.XGPIO Name IO DescriptionSets the proportional gain constant for the PI write_kp 0controller in the CDRSets the integral gain write_ki_s 0constant for the PI controller in the CDR Prior version of the Receiver used level write detect threshold 0 binning to determine if a signal was begin received. No longer in use.Sets the initial frequency of recovery clock. It serves as an estimate close to the actual write_cdr_init_val 0clock of the received data, and is modified by the CDR block to match the frequency. The FPGA counts how many packets have read msg count I been received. This value is printed in debugging mode.The phase step of the sawtooth generator correlates to the frequency of the recovered read_dds_phase_step Iclock. This value is printed in debugging mode.The unsigned 12 bit integer that is received read adc data I directly from the ADC. Is printed in debugging mode.

[0112] When the FPGA state-machines detects and successfully decodes a packet, it writes the received string to memory mapped IO that the MicroBlaze soft-processor is able to access with the decoded_data_mem_map_ptr pointer. When this occurs, an interrupt is thrown, allowing the MicroBlaze to know when to copy the contents of the memory mapped IO. In the interrupt handler, the FormatDecodedData() function breaks the memory from 32-bit binary values to byte-sized ASCII chars for printing. The ASCII chars are then printed to the USB with the xil_printf() function. Finally, the interrupt flag is cleared and the interrupt handler is exited, allowing the interrupt to be repeated when the next packet is received.

[0113] In the present embodiment, when the FPGA state-machine detects and successfully decodes a packet, it writes the received string to memory mapped IO that the MicroBlaze soft-processor is able to access with the decoded_data_mem_map_ptr pointer. When this occurs, an interrupt is thrown, allowing the MicroBlaze to know when to copy the contents of the memory mapped IO. In the interrupt handler, the FormatDecodedData() function breaks the memory from 32-bit binary values to byte-sized ASCII chars for printing. The ASCII chars are then printed to the USB with the xil_printf() function. Finally, the interrupt flag is cleared and the interrupt handler is exited, allowing the interrupt to be repeated when the next packet is received.

[0114] FIGS. 32 and 33 show prototype implementations of the receiver 52 and transmitter 44, respectively. FIG. 34 shows various commercially available vehicle exterior lamp modules modified to include transmitter 44.

[0115] FIG. 35 depicts a light communication system 300 having a pair of electronic devices A and B that provide one way data communication from Device A to Device B. This simplex communication is accomplished using a transmitter 44 electronically coupled with Device A, and a receiver 52 electronically coupled to Device B. The Devices A and B are coupled to their respective transmitter 44 and receiver 52 via input / output (VO) circuits 43, 54, respectively. These I / O circuits enable the interfacing of various types of electronic devices to various types of light transmitters, receivers, and transceivers, in many cases allowing for the use of pre-existing electronic devices without the need for significant, if any, circuit modifications of those devices.

[0116] Device A, transmitter 44, and I / O 43 together comprise a light communication node and the electronics for each can be integrated together into a single physical device or be interconnectable, e.g., by wires. Similarly, this can be done for Device B, receiver 52, andI / O 54. Transmitter 44 and receiver 52 have a design, construction, and operation that will be described below, but can include one or more of the features disclosed in the aforementioned U. S. Patent No. 11,245,469 and U. S. Patent Application Publication Nos. US2023 / 0065439A1 and US2023 / 0308254A1, the entire disclosures of which are hereby incorporated by reference.

[0117] FIG. 36 discloses a light communication system 300' similar to the system 300 of FIG. 35, except that light communication system 300' utilizes a pair of transceivers (transmitter + receiver) 47 and 49 to enable bi-directional (duplex) data transfer between two electronic devices C and D. As in FIG. 35, the Devices C and D are electronically coupled to their respective transceivers 47, 49 by VO circuits 43 and 54, respectively. Transceivers 47 and 49 can be implemented by utilizing both a transmitter and a receiver, and this can be done either by providing a transmitter 44 and receiver 52 separately in each transceiver, or by integrating them together using a single circuit that provides all of the necessary analog and digital functions. Further, transceivers 47 and 49 can be identical transceivers or ones having different components or parameters, such as to utilize different clock rates or otherwise to permit rejection of unwanted received light modulations. As will become apparent to those skilled in the art, this use of different transmission attributes by different transmitters can be used by a receiver or transceiver to reject any received (e.g., reflected) light data transmissions originating from itself or from mixing of communications coming from multiple other devices.

[0118] Although the light used for communication can be inside or outside of the visible spectrum, many embodiments of the transmitter and receiver can use visible light, such as is used in visible light communication (VLC) systems. This allows for the use of existing device components such as the illumination-providing lights used for vehicle exterior illumination and other illuminating devices and applications. Except where otherwise described, the transmitters, receivers, and transceivers described utilize visible light to set up a VLC network, such that light communication systems 300 and 300' may also be referred to as VLC systems 300 and 300'.

[0119] In the light communication system 300, an input interface device 46 is included in a Device A and a human machine interface (HMI) output device 53 is used as the presenter 56 of a Device B. Device A includes the flashlight circuit 42 and Device B includes the receiver circuit 51.

[0120] The input interface device 46 is used for receiving inputs at the Device A, such as, for example, HMI inputs and / or sensor data captured by a sensor of the Device A.Accordingly, in embodiments, the input interface device is a sensor and / or a HMI input device. A HMI input device is a HMI device that is configured to receive information from a (human) user so that the information may be encoded and transmitted by the transmitter 44. The HMI input device may be, for example, a microphone, a pushbutton, a touch screen, a keyboard, a mouse, a joystick, a camera, or any other suitable device that allows a user to provide input into the Device A. In embodiments, the input interface device 46 is a sensor, such as, for example, a camera, microphone, radar sensor, lidar sensor, accelerometer, strain gauge, vibration sensor, temperature sensor, pressure sensor, etc. For example, in one embodiment, the input interface device 46 is a camera so that image data (representing images captured by the camera) can be used to communicate pictures via the light communication system 40'.

[0121] The HMI output device 53 corresponds to the presenter 56 of FIG. 3 and is a HMI device that is configured to present information to a (human) user so that the information may be interpreted by the user. The HMI output device 53 may be, for example, a display screen, a speaker, a printer, a projector, or any other suitable device that allows information to be presented to the human user in a way that can be interpreted by the user. For example, audio captured and transmitted by the transmitter 44 may be received at the receiver 52 and played by a speaker at Device B. In another example, image data captured by the input interface device 46 may be transmitted by the transmitter 44, received by the receiver 52, and presented on a display screen or projector of the Device B.

[0122] In the light communication system 300', an interface device 55 is illustrated as being a part of the Device C and an interface device 57 is illustrated as being a part of the Device D. Each of the HMI devices 55,57 may include one or both of the input interface device 46 and the HMI output device 53 discussed in connection with FIG. 35.

[0123] FIG. 37 depicts a transmitter portion of a light communication system 300", which is an example of the light communication system 300 of FIG. 35. The Device A includes a microphone 59 as the interface input device 46 used for receiving audio (sound) from the human user and also includes a speech-to-text module 61 for converting the audio signal from the microphone 59 to a suitable digital electronic format for use in encoding the audio for transmission by the transmitter 44. The speech-to-text module 61 may employ various algorithms and techniques, such as natural language processing (NLP) and machine learning models, to accurately transcribe spoken words into text (e.g., into American Standard Code for Information Interchange (ASCII) characters). For example, the module could utilize deep learning networks like recurrent neural networks (RNNs) or transformer models toenhance accuracy and context understanding. Additionally, the speech-to-text module 61 may support multiple languages and dialects, allowing for broader user interaction. Specific examples of the speech-to-text processing include applications such as voice-activated virtual assistants, automated transcription services for meetings or lectures, and voice- controlled smart home devices. These applications demonstrate the versatility and utility of integrating a speech-to-text module in Device A, providing seamless interaction and functionality for the user. According to embodiments, each or both of the interface devices 55,57 of the light communication system 300' include the microphone 59 and / or the speech- to-text module 61. In embodiments, the Device A of the light communication system 300" may omit the speech-to-text module 61 and instead encode the audio signal from the microphone 59 so that the audio itself may be presented by the HMI output device 53 for audio playback of the audio signal captured by the microphone (as opposed to, for example, presenting text or generating new audio based on the text output from the speech-to-text module 61).

[0124] According to embodiments, the light communication systems described herein (including one or more of the systems 300, 300', 300") may be used for: performing highly secure wireless software updates, of vehicles, machines, weapons, buildings, infrastructure; a variety of covert / special -military operations including for information drops; SOS transmission device including in urban / remote / underground / underwater / Bekow-Rubbell search and rescue situations; an entry / exit security applications (for authenticating / authorizing entry, exit, and / or access of a building or compartment); and / or financial transactions.

[0125] According to embodiments, the light communication systems described herein (including one or more of the systems 300, 300', 300") may include an adjustable lens in the front end, it can communicate to multiple receivers with a fan beam (short focal length lens) or it can communicate to a specific receiver with a narrow beam (long focal length lens).

[0126] It is to be understood that the foregoing description is of one or more embodiments of the invention. The invention is not limited to the particular embodiment(s) disclosed herein, but rather is defined solely by the claims below. Furthermore, the statements contained in the foregoing description relate to the disclosed embodiment(s) and are not to be construed as limitations on the scope of the invention or on the definition of terms used in the claims, except where a term or phrase is expressly defined above. Various other embodiments and various changes and modifications to the disclosed embodiment s) will become apparent to those skilled in the art.

[0127] As used in this specification and claims, the terms “e.g.,” “for example,” “for instance,” “such as,” and “like,” and the verbs “comprising,” “having,” “including,” and their other verb forms, when used in conjunction with a listing of one or more components or other items, are each to be construed as open-ended, meaning that the listing is not to be considered as excluding other, additional components or items. Other terms are to be construed using their broadest reasonable meaning unless they are used in a context that requires a different interpretation. In addition, the term “and / or” is to be construed as an inclusive OR. Therefore, for example, the phrase “A, B, and / or C” is to be interpreted as covering all of the following: “A”; “B”; “C”; “A and B”; “A and C”; “B and C”; and “A, B, and C.”

Claims

1. CLAIMS1. A handheld light communication system, comprising:an input interface device for receiving an input from a user of the handheld light communication device and / or sensor data captured by the handheld light communication device;a transmitter configured to transmit light according to the input received at the input interface device; anda receiver configured to determine data encoded in the light transmitted by the transmitter, wherein the receiver includes:a light sensor for sensing the light transmitted by the transmitter; transimpedance op-amp circuitry having a transimpedance op-amp integrator circuit and a transimpedance op-amp differentiator circuit;a gain control circuit; anda digital signal processing device configured to recover a clock of the incoming light and to decode the data encoded in the light using the clock.

2. The handheld light communication system of claim 1, wherein the handheld light communication system includes a flashlight having the transmitter.

3. The handheld light communication system of claim 1, wherein the transimpedance op-amp circuitry and the gain control circuit are a part of analog circuitry that generates a conditioned analog signal based on a light signal that is output from the light sensor.

4. The handheld light communication system of claim 1, wherein the transimpedance op-amp integrator circuit is configured to generate a transimpedance integrated output signal by amplification of the sensor signal, and wherein the transimpedance op-amp differentiator circuit is configured to generate a bandpass-filtered signal based on bandpass filtering of the transimpedance integrated output signal.

5. The handheld light communication system of claim 1, wherein the gain control circuitry is configured to generate an analog gain control signal adjusting gain of an analog signal output by the transimpedance op-amp integrator circuit.

6. The handheld light communication system of claim 5, wherein the gain control circuitry includes a non-inverting automatic op-amp circuit having a non-inverting op-amp for generating the analog gain control signal.

7. The handheld light communication system of claim 1, wherein the digital signal processing device is a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC).

8. The handheld light communication system of claim 1, wherein the digital signal processing device includes an analog-to-digital converter (ADC) for converting an analog signal output by the gain control circuit into a digital signal.

9. The handheld light communication system of claim 1, wherein the digital signal processing device includes an automatic gain control (AGC) module configured to generate a digital gain control signal based on sampled data sampled based on an analog signal output by the gain control circuit.

10. The handheld light communication system of claim 1, wherein the digital signal processing device includes a clock data recovery (CDR) module for recovering a clock of the light transmitted by the transmitter and for decoding data encoded within the light using the clock.

11. The handheld light communication system of claim 10, wherein the CDR module includes a clock recovery (CR) module and a data decoder module, wherein the CR module is configured to recovering the clock of the light transmitted by the transmitter, and wherein the data decoder module is configured to decode the data encoded within the light using the clock.

12. The handheld light communication system of claim 10, wherein the CDR module uses a finite-state machine (FSM) as a part of decoding the data encoded within the light using the clock.

13. The handheld light communication system of claim 12, wherein the FSM is configured to implement an error correcting procedure using Reed-Soloman error correction or other error correction framework.

14. The handheld light communication system of claim 1, wherein the light sensor is a photodiode.

15. A handheld light communication system, comprising:an input interface device for receiving an input from a user of the handheld light communication device and / or sensor data captured by the handheld light communication device;a transmitter configured to transmit light; anda receiver configured to determine data encoded in the light transmitted by the transmitter, wherein the receiver includes:a light sensor for sensing the light transmitted by the transmitter; analog circuitry configured to generate a conditioned analog signal based on a light signal that is output from the light sensor; and a digital signal processing device configured to recover a clock of the light transmitted by the transmitter by processing the conditioned analog signal and to decode the data encoded in the light using the clock.

16. The handheld light communication system of claim 15, wherein the conditioned analog signal is generated by conditioning the light signal through transimpedance amplification and / or bandpass filtering.

17. The handheld light communication system of claim 16, wherein a transimpedance op-amp differentiator circuit is used for performing the bandpass filtering through generating a bandpass-filtered signal based on a transimpedance integrated output signal output from a transimpedance op-amp integrator circuit.

18. The handheld light communication system of claim 15, wherein the handheld light communication system includes a flashlight having the transmitter.

19. A handheld light communication device, comprising:a flashlight having a flashlight circuit;wherein the flashlight circuit includes a transmitter configured to transmit light that is to be received at a receiver;wherein the receiver is configured to determine data encoded in the light transmitted by the transmitter, wherein the receiver includes:a light sensor for sensing the light transmitted by the transmitter; analog circuitry configured to generate a conditioned analog signal based on a light signal that is output from the light sensor; and a digital signal processing device having an automatic gain control (AGC) module and a clock recovery module, wherein the AGC module is configured to generate a gain-controlled digital signal, wherein the clock recovery module is configured to recover a clock of the incoming light, and wherein the clock of the incoming signal is used to decode the data encoded in the light.

20. The handheld light communication device of claim 19, wherein the flashlight includes a light source for transmitting the light and / or for providing illumination to an area at which the flashlight is operated.

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