Array substrate, display panel, display device, and external circuit
Patent Information
- Application Number
- PCT/CN2025/077925
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-02-18
- Publication Date
- 2026-08-27
Smart Images
Figure CN2025077925_27082026_PF_FP_ABST
Abstract
Description
Array substrate, display panel, display device and external circuitry Technical Field
[0001] This disclosure relates to the field of display technology, and in particular to an array substrate, display panel, display device and external circuit. Background Technology
[0002] Thin-film transistor liquid crystal displays (TFT-LCDs) are characterized by their small size, low power consumption, high image quality, no radiation, and portability. They have experienced rapid development in recent years and have gradually replaced traditional cathode ray tube (CRT) displays, dominating the current flat panel display market. Currently, TFT-LCDs are widely used in products of various sizes, covering almost all major electronic products in today's information society, such as LCD TVs, high-definition digital TVs, computers (desktops and laptops), mobile phones, tablets, navigation systems, in-vehicle displays, projection displays, cameras, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays. Summary of the Invention
[0003] The array substrate, display panel, display device, and external circuitry provided in this disclosure are specifically designed as follows:
[0004] On one hand, embodiments of this disclosure provide an array substrate, including:
[0005] A substrate, the substrate including a display area, a first non-display area and a second non-display area disposed opposite each other on both sides of the display area, and two third non-display areas connecting the first non-display area and the second non-display area, wherein the first non-display area is used to bond external circuits;
[0006] A sub-pixel, located in the display area, wherein the size of the sub-pixel along a first direction is greater than the size of the sub-pixel along a second direction;
[0007] A grid line extends along the first direction in the display area;
[0008] A gate driving circuit is located in the second non-display area, and the gate driving circuit is electrically connected to the gate line and the external circuit.
[0009] The data cable extends along the second direction in the display area;
[0010] A fan-out line extends from at least one of the third non-display areas to the first non-display area, and the fan-out line connects the data line to the external circuit.
[0011] In some embodiments, in the array substrate provided in the present disclosure, the fan-out line includes a first fan-out line and a second fan-out line, wherein the first fan-out line extends from one of the third non-display areas to the first non-display area, and the second fan-out line extends from another of the third non-display areas to the first non-display area.
[0012] In some embodiments, in the array substrate provided in the present disclosure, the data lines electrically connected to the first fan-out line and the data lines electrically connected to the second fan-out line are alternately arranged.
[0013] In some embodiments, in the array substrate provided in the present disclosure, the fan-out line includes a first portion and a second portion that are in different layers and electrically connected to each other, wherein the orthographic projection of the first portion on the substrate overlaps with the orthographic projection of the second portion on the substrate.
[0014] In some embodiments, in the array substrate provided in the present disclosure, one end of the same data line is electrically connected to the first fan-out line and the other end is electrically connected to the second fan-out line.
[0015] In some embodiments, in the array substrate provided in the present disclosure, the first fan-out line and the second fan-out line each include a first sub-fan-out line and a second sub-fan-out line that are insulated from each other and are not in the same layer. In the third non-display area, the orthographic projection of the first sub-fan-out line on the substrate and the orthographic projection of the second sub-fan-out line on the substrate overlap or alternate with each other.
[0016] In some embodiments, in the array substrate provided in the present disclosure, the gate driving circuit includes a plurality of cascaded shift registers, wherein the size of the shift register in the first direction is greater than the size of the shift register in the second direction.
[0017] In some embodiments, in the array substrate provided in the present disclosure, the shift register includes at least one gate signal output terminal, and different gate signal output terminals are electrically connected to different gate lines.
[0018] In some embodiments, the array substrate provided in this disclosure further includes a touch line extending along the first direction in the display area, the touch line being electrically connected to the external circuit.
[0019] In some embodiments, in the array substrate provided in the present disclosure, the touch line is disposed at at least a portion of the column gaps where the sub-pixels extend along the first direction.
[0020] In some embodiments, in the array substrate provided in the present disclosure, the orthogonal projection of the touch line on the substrate extends through at least a portion of the orthogonal projection of the sub-pixel on the substrate.
[0021] In some embodiments, in the array substrate provided in the present disclosure, the touch lines and the gate lines are disposed on the same layer.
[0022] In some embodiments, the array substrate provided in this disclosure further includes a connection line located in the first non-display area, the connection line being connected between the touch line and the external circuit.
[0023] In some embodiments, the array substrate provided in the present disclosure further includes a gate driving circuit signal line extending from the second non-display area through at least one of the third non-display areas to the first non-display area, the gate driving circuit signal line being connected between the gate driving circuit and the external circuit.
[0024] In some embodiments, in the array substrate provided in the present disclosure, the sub-pixels in different rows are electrically connected to different data lines, and the sub-pixels in different columns are electrically connected to different gate lines.
[0025] In some embodiments, in the array substrate provided in the present disclosure, the sub-pixels are divided into multiple pixels, each pair of adjacent pixels along the first direction constitutes a pixel period, in a pixel period, each pair of sub-pixels is connected on a data line, and each n sub-pixels is connected on a gate line, where n is the total number of sub-pixels in a single pixel.
[0026] In some embodiments, in the array substrate provided in the present disclosure, the pixel includes a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel;
[0027] The data lines include a first data line, a second data line, and a third data line; wherein,
[0028] The first data line is located on one side of the pixel period, and the first data line is electrically connected to two of its adjacent first color sub-pixel, second color sub-pixel, and third color sub-pixel;
[0029] The third data line is located on the other side of the pixel period, and the third data line is electrically connected to two of its adjacent first color sub-pixel, second color sub-pixel, and third color sub-pixel;
[0030] The second data line is located between two pixels in the pixel period, and the second data line is electrically connected to two sub-pixels in the pixel period that are not connected to the first data line and the third data line;
[0031] The gate lines include a first gate line and a second gate line; wherein...
[0032] The first gate line is located between the first color sub-pixel and the second color sub-pixel, and the first gate line is electrically connected to two first color sub-pixels and one second color sub-pixel in the pixel period;
[0033] The second gate line is located between the second color sub-pixel and the third color sub-pixel, and the second gate line is electrically connected to two of the third color sub-pixels and one of the second color sub-pixels in the pixel period.
[0034] In some embodiments, in the array substrate provided in the present disclosure, the first color sub-pixel is a red sub-pixel, the second color sub-pixel is a green sub-pixel, and the third color sub-pixel is a blue sub-pixel.
[0035] On the other hand, this disclosure provides an external circuit for bonding with the array substrate provided in this disclosure, wherein the external circuit includes a bonding terminal, the bonding terminal including a data signal terminal bonded to the fan-out line.
[0036] In some embodiments, in the external circuit provided in the present disclosure, the array substrate further includes a touch line and a connecting line connecting the touch line and the external circuit, and the bonding terminal further includes a touch signal terminal bonded to the connecting line.
[0037] In some embodiments, in the external circuit provided in the present disclosure, the fan-out line includes a first fan-out line and a second fan-out line, and the data signal terminal includes a first data signal terminal bound to the first fan-out line and a second data signal terminal bound to the second fan-out line;
[0038] In the second direction, the touch signal terminal is located between the first data signal terminal and the second data signal terminal.
[0039] In some embodiments, in the external circuit provided in the present disclosure, the array substrate further includes a gate drive circuit signal line connecting the gate drive circuit and the external circuit, and the bonding terminal further includes a gate drive signal terminal bonded to the gate drive circuit signal line.
[0040] In the second direction, the gate drive signal terminal is located on the side of the first data signal terminal and / or the second data signal terminal away from the touch signal terminal.
[0041] In some embodiments, in the external circuit provided in the present disclosure, the bonding terminals are arranged in multiple rows along the first direction in the middle area of their occupied area, and the bonding terminals in adjacent rows are at least partially staggered in the second direction.
[0042] In some embodiments, in the external circuit provided in the present disclosure, the bonding terminals are arranged in multiple rows along the first direction in the edge area of their occupied area, and the row of bonding terminals in the middle area substantially overlaps with the row of bonding terminals in the edge area.
[0043] In some embodiments, in the external circuit provided in the present disclosure, the bonding terminals are arranged in multiple rows at an angle away from the display area at the edge of their occupied area.
[0044] On the other hand, this disclosure provides a display panel including the array substrate provided in this disclosure and a counter substrate disposed opposite to the array substrate.
[0045] On the other hand, this disclosure provides a display device, including the display panel and external circuit provided in this disclosure. Attached Figure Description
[0046] Figure 1 is a schematic diagram of a display device provided in an embodiment of this disclosure;
[0047] Figure 2 is a magnified schematic diagram of a 3*12 sub-pixel region in Figure 1;
[0048] Figure 3 is a schematic diagram of an enlarged structure of region Z in Figure 1;
[0049] Figure 4 is a schematic diagram of the structure of simultaneous dual-sided data line driving provided in an embodiment of this disclosure;
[0050] Figure 5 is a schematic diagram of the shift register structure of a first-stage two-drive system;
[0051] Figure 6 is a schematic diagram of another enlarged structure of the 3*12 sub-pixel region in Figure 1;
[0052] Figure 7 is a schematic diagram of another enlarged structure of the 3*12 sub-pixel region in Figure 1;
[0053] Figure 8 is a schematic diagram of another enlarged structure of the 3*12 sub-pixel region in Figure 1;
[0054] Figure 9 is a magnified schematic diagram of a 2*6 sub-pixel region in Figure 1;
[0055] Figure 10 shows the layout of the 2*3 sub-pixel region in Figure 9;
[0056] Figure 11 is a magnified schematic diagram of a 2*3 sub-pixel region in Figure 1;
[0057] Figure 12 is a schematic diagram of another enlarged structure of the 2*3 sub-pixel region in Figure 1;
[0058] Figure 13 is a schematic diagram of another enlarged structure of the 2*3 sub-pixel region in Figure 1;
[0059] Figure 14 is a schematic diagram of another enlarged structure of the 2*3 sub-pixel region in Figure 1;
[0060] Figure 15 is a schematic diagram of another enlarged structure of the 2*3 sub-pixel region in Figure 1;
[0061] Figure 16 is a schematic diagram of another enlarged structure of the 2*3 sub-pixel region in Figure 1;
[0062] Figure 17 shows the polarity arrangement of the pixel architecture shown in Figure 9 under column flipping mode;
[0063] Figure 18 shows the polarity arrangement of the pixel architecture shown in Figure 11 under column flipping mode;
[0064] Figure 19 shows the polarity arrangement of the pixel architecture shown in Figure 12 under column flipping mode;
[0065] Figure 20 shows the polarity arrangement of the pixel architecture shown in Figure 13 under column flipping mode;
[0066] Figure 21 shows the polarity arrangement of the pixel architecture shown in Figure 14 under column flipping mode;
[0067] Figure 22 shows the polarity arrangement of the pixel architecture shown in Figure 15 under column flipping mode;
[0068] Figure 23 shows the polarity arrangement of the pixel architecture shown in Figure 16 under column flipping mode;
[0069] Figure 24 is a diagram showing an arrangement of bonding terminals in an external circuit provided in an embodiment of this disclosure.
[0070] Figure 25 is another arrangement diagram of the bonding terminals in the external circuit provided in the embodiments of this disclosure;
[0071] Figure 26 is a schematic diagram of the structure of the display panel provided in an embodiment of this disclosure;
[0072] Figure 27 is a schematic diagram of another structure of the display device provided in the embodiments of this disclosure. Detailed Implementation
[0073] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the following description will be made in conjunction with the accompanying drawings of the embodiments of this disclosure. For clarity, the thickness of layers, films, panels, regions, etc., is enlarged in the drawings. Exemplary embodiments are described in this disclosure with reference to cross-sectional views as schematic diagrams of idealized embodiments. Thus, deviations from the shapes in the drawings will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shapes of the regions shown in this disclosure, but rather include deviations in shape caused, for example, by manufacturing processes. For example, regions illustrated or described as flat may typically have rough and / or non-linear characteristics; sharp corners illustrated may be rounded, etc. Therefore, the regions shown in the drawings are schematic in nature, and their dimensions and shapes are not intended to illustrate the precise shapes of the regions or reflect true proportions, but are only intended to illustrate the content of this disclosure. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.
[0074] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.
[0075] In the following description, when an element or layer is referred to as "on" another element or layer or "connected" to another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as "located on one side of" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as "directly on" another element or layer" or "directly connected" to another element or layer, there are no intermediate elements or intermediate layers. The term "and / or" includes any and all combinations of one or more of the related listed items. The various embodiments of this disclosure may be combined and integrated with each other without conflict.
[0076] In the field of thin-film transistor liquid crystal displays (TFT-LCDs), while pursuing the lowest possible cost, major manufacturers are also placing increasingly higher demands on the bezels and display quality of the screens. To address this demand for extremely low display costs, panel manufacturers often adopt a triple-gate pixel architecture design, which uses a single data (source) line to charge three sub-pixels. Compared to the traditional single-gate pixel architecture, this reduces the number of data signal terminals in external circuitry (such as driver ICs) by two-thirds, significantly lowering product costs.
[0077] To improve the transmittance of the screen display area, the relevant three-gate pixel architecture design adopts a method of placing pixels horizontally, extending the gate lines horizontally, and extending the data lines vertically. In this design, the deflection of the pixel liquid crystal molecules is no longer affected by the upper and lower domain slits, but by the left and right domain slits. This leads to a larger area of magnetic field disturbance at the corner of the slit in the middle of the pixel, which in turn leads to a larger area of liquid crystal molecule deflection disturbance in the middle region. In other words, the dark area in the middle region of the pixel increases, and the contrast ratio (CR value) of the display area (AA) decreases, which cannot meet the requirements of automotive customers.
[0078] To further improve the contrast of the display area in automotive display products, a vertical screen with horizontal pixels is proposed. This involves vertically oriented pixels, horizontally extending data lines, and vertically extending gate lines. Correspondingly, the gate drive circuit (GOA) connecting the gate lines is placed on the top and bottom sides of the display area (i.e., the DP side and DPO side), while the external circuitry connecting the data lines (e.g., the driver chip IC) is located on the right side of the display area. This design significantly improves the low contrast problem caused by horizontal pixel designs. However, this design results in a narrow left bezel and a wide right bezel, and the right bezel cannot meet the narrow bezel (≤3.5mm) requirement of automotive products.
[0079] To address the aforementioned technical problems, this disclosure provides an array substrate. Figure 1 shows a schematic diagram of the array substrate provided in this disclosure after external circuitry is bonded, and Figure 2 is a structural schematic diagram of a 3*12 sub-pixel region in Figure 1. As shown in Figures 1 and 2, the array substrate of this disclosure may include:
[0080] The substrate 101 includes a display area AA, a first non-display area DP and a second non-display area DPO disposed opposite each other on both sides of the display area AA, and two third non-display areas LB & RB connecting the first non-display area DP and the second non-display area DPO. The first non-display area DP is used to bond an external circuit IC. In some embodiments, the substrate 101 is a substrate that allows visible light to pass through, such as glass, quartz, plastic and other materials.
[0081] Subpixels (including but not limited to red subpixel R, green subpixel G, and blue subpixel B) are located in the display area AA. The size of the subpixel along the first direction Y is larger than the size of the subpixel along the second direction X. In other words, the subpixels of this disclosure are arranged vertically. Optionally, the subpixel includes a slit electrode with upper and lower domains. Compared with the slit electrodes with left and right domains, the magnetic field disturbance area at the corner of the slit is smaller, and correspondingly, the liquid crystal molecule deflection disturbance area in the middle region is smaller. That is, the dark area in the middle region of the pixel is smaller, which is beneficial to improving the contrast of the display area AA.
[0082] Gate line 102 extends along the first direction Y in the display area AA; the material of gate line 102 may include metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni), and gate line 102 can be a single-layer structure or a multi-layer structure, for example, gate line 102 is a single-layer structure composed of a copper metal layer. Optionally, to reduce resistance, the thickness of the layer containing gate line 102 is [missing information]. For example wait
[0083] The gate driving circuit GOA is located in the second non-display area DPO. The gate driving circuit GOA is electrically connected to the gate line 102 and the external circuit IC. Optionally, the gate driving circuit GOA is electrically connected to the external circuit IC through a gate driving circuit signal line GL extending from the second non-display area DPO through at least one third non-display area LB&RB to the first non-display area DP. The gate drive circuit signal line GL may include, but is not limited to, one or more of the following: frame start signal lines STV1A and STV1B, total reset signal line STV0, clock signal lines CLK1 to CLK12 (specifically, the number of clock signal lines is not limited; this disclosure uses 12 as an example), noise reduction signal lines VDDO and VDDE, and low-level signal line VGL. The frame start signal line may be one or more, which is not limited here. This disclosure uses two frame start signal lines as an example. Frame start signal lines STV1A and STV1B are the trigger input signals for odd-numbered and even-numbered rows, respectively. Clock signal lines CLK1 to CLK12 are responsible for providing the output voltage of each row's gate. Noise reduction signal lines VDDO and VDDE provide input signals to the noise reduction unit of the gate drive circuit, with a 50% duty cycle and alternating high and low levels. The low-level signal line VGL provides an internal low-level voltage to the gate drive circuit.
[0084] This disclosure changes the gate drive circuit GOA in the vertical screen horizontal pixel horizontal application scheme from alternating DP&DPO bilateral driving to single-sided DPO driving. The space occupied by a single-stage shift register in the gate drive circuit GOA changes from two sub-pixels to one sub-pixel, and the horizontal space becomes half of the original. This necessitates increasing the vertical space to ensure the proper placement of each stage shift register. Taking the shift register of the automotive product 18T1C as an example, without changing the shift register structure, the DPO side bezel changes from 2.0mm to 3.2mm (<3.5mm), still meeting the bezel design requirements of automotive product customers.
[0085] Data cable 103 extends along the second direction X in the display area AA. The material of data cable 103 may include metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni). Data cable 103 can be a single-layer structure or a multi-layer structure; for example, data cable 103 can be a single-layer structure composed of a copper metal layer. Optionally, to reduce resistance, the thickness of the layer containing data cable 103 is [missing information]. For example wait.
[0086] A fan-out line FL extends from at least one of the two third non-display areas LB & RB to the first non-display area DP. The fan-out line FL is connected between the data line 103 and the external circuit IC. Optionally, the resistances of the different fan-out lines FL can be similar or even the same. In the vertical screen horizontal pixel horizontal application scheme, the fan-out line FL and the external circuit IC are both located in the right third non-display area RB, resulting in a wider right third non-display area RB. In the vertical screen horizontal pixel horizontal application scheme, the first non-display area DP is provided with a gate drive circuit GOA. In this disclosure, the first non-display area DP is not provided with a gate drive circuit GOA. Instead, the external circuit IC is located in the first non-display area DP, and the fan-out line FL is located in the left third non-display area LB and / or the right third non-display area RB. This ensures that the left third non-display area LB, the right third non-display area RB, and the first non-display area DP are all narrow, thereby effectively avoiding the problem of an excessively large bezel on one side.
[0087] In some embodiments, in the array substrate provided in the present disclosure, FIG3 shows an enlarged structure of the Z region in FIG1, and FIG4 shows a schematic diagram of bilateral driving of the data line 103 in FIG1. As can be seen from FIG1, FIG3, and FIG4, the fan-out line FL may include a first fan-out line FL1 and a second fan-out line FL2. The first fan-out line FL1 extends from a third non-display area (e.g., the left third non-display area LB) to the first non-display area DP, and the second fan-out line FL2 extends from another third non-display area (e.g., the right third non-display area RB) to the first non-display area DP. Optionally, the data lines 103 electrically connected to the first fan-out line FL1 and the data lines 103 electrically connected to the second fan-out line FL2 in FIG3 can be alternately arranged. For example, the first fan-out line FL1 is electrically connected to the odd-numbered rows of data lines 103 (e.g., the 1st, 3rd, 5th, etc.), and the second fan-out line FL2 is electrically connected to the even-numbered rows of data lines 103 (e.g., the 2nd, 4th, 6th, etc.) to ensure that the widths of the left and right bezels are similar, while simultaneously enabling alternating bilateral driving of the data lines 103. In Figure 4, one end of the same data line 103 is electrically connected to the first fan-out line FL1, and the other end is electrically connected to the second fan-out line FL2, enabling simultaneous dual-side driving. Compared to the embodiment shown in Figure 3, the load on the data line 103 in the embodiment shown in Figure 4 is halved, resulting in a more significant improvement in charging rate.
[0088] The width of the third non-display area (LB&RB) on both sides is mainly affected by the number and pitch of the fan-out line (FL). The size of the FL affects the load on the fan-out line, which in turn affects the pixel charging rate within the display area (AA). To ensure normal display, the grayscale difference between adjacent rows of pixels is typically ≤2 grayscale levels (pixel charging voltage ≤20mV). In Figure 3, a dual-sided alternating drive scheme is used for the data line 103 via the fan-out line FL, with adjacent rows of display pixels representing the near and far ends of the charging process. To ensure a small difference in pixel charging between rows, while meeting the design requirements for the third non-display area (LB&RB) (≤3.5mm) and the first non-display area (≤7.0mm) bezels, the largest possible trace width can be used to reduce trace resistance. Alternatively, each fan-out line FL can be designed with a double-layer parallel design of gate metal layer and source / drain metal layer to reduce resistance. This is equivalent to the fan-out line FL of this disclosure using double-thick copper (e.g., copper thickness of...). The design minimizes fan-out line (FL) load and improves charging differences between adjacent rows of pixels.
[0089] Based on this, as shown in Figure 3, the fan-out line FL of this disclosure may include a first portion P1 and a second portion P2 that are on different layers and electrically connected to each other. Optionally, the first portion P1 is disposed on the same layer and with the same material as the gate line 102 (i.e., located in the gate metal layer), and the second portion P2 is disposed on the same layer and with the same material as the data line 103 (i.e., located in the gate metal layer). In some embodiments, the orthographic projection of the first portion P1 on the substrate 101 may overlap with the orthographic projection of the second portion P2 on the substrate 101. For example, the orthographic projection of the first portion P1 on the substrate 101 and the orthographic projection of the second portion P2 on the substrate 101 are approximately coincident. Compared to the first portion P1 on the substrate 101 and the second portion P2 on the substrate 101 being partially or completely offset, the approximately coincident orthographic projections of the two can maximize the protection that the overall area occupied by the fan-out line FL is not too large, which is beneficial for achieving a narrow bezel effect.
[0090] It should be noted that in the embodiments provided in this disclosure, due to limitations of process conditions or the influence of other factors such as measurement, "approximately coincident" may coincide exactly or may have some deviation. Therefore, as long as the relationship of "approximately coincident" between related features meets the allowable error, it is within the protection scope of this disclosure.
[0091] In the case where a single data line 103 as shown in Figure 4 is driven by one first fan-out line FL1 and one second fan-out line FL2, both the first fan-out line FL1 and the second fan-out line FL2 can include a first sub-fan-out line FL' and a second sub-fan-out line FL'” that are in different layers and mutually insulated. For example, the first sub-fan-out line FL' is located in the gate metal layer and can be electrically connected to the data line 103 through a hole. The second sub-fan-out line FL'” is located in the source and drain metal layers and the data line 103 can extend to the third non-display area LB&RB and bend towards the first non-display area DP as the second sub-fan-out line. Optionally, within the third non-display area LB&RB on one side, the second sub-fan-out line FL" can be electrically connected to half of the data line 103 from the DPO side to the middle position of the display area AA, and the first sub-fan-out line FL' can be electrically connected to the other half of the data line 103 from the middle position of the display area AA to the DP side. The hole connection position of the first sub-fan-out line FL' and the corresponding data line 103 can be set close to the display area AA, so that the hole position is far from the outer edge of the third non-display area LB&RB, avoiding external moisture from entering through the hole and corroding the data line 103. Because there is an insulating layer between the gate metal layer and the source / drain metal layer, the first sub-fan-out line FL' and the second sub-fan-out line FL” can be insulated from each other through this insulating layer. Therefore, in the third non-display area LB&RB, the orthographic projection of the first sub-fan-out line FL' on the substrate 101 and the orthographic projection of the second sub-fan-out line FL” on the substrate 101 can overlap with each other. For example, in the third non-display area LB&RB, the orthographic projection of the first sub-fan-out line FL' on the substrate 101 and the orthographic projection of the second sub-fan-out line FL” on the substrate 101 can roughly coincide, so as to realize the narrow bezel design of the third non-display area LB&RB.
[0092] In some embodiments, within the third non-display area LB&RB, the orthographic projection of the first sub-fan-out line FL' onto the substrate 101 and the orthographic projection of the second sub-fan-out line FL” onto the substrate 101 can be alternately set, which is equivalent to setting the second sub-fan-out line FL” between the first sub-fan-out line FL' in FIG4. Since there is an insulating layer between the gate metal layer where the first sub-fan-out line FL' is located and the source / drain metal layer where the second sub-fan-out line FL” is located, even if the first sub-fan-out line FL' and the second sub-fan-out line FL” are alternately routed, it can be ensured that they are mutually insulated, and the width of the area where they are located can be comparable to the width of the area where they are located as shown in FIG4, thereby achieving a narrow bezel effect.
[0093] In some embodiments, in the array substrate provided in the present disclosure, the gate drive circuit GOA may include multiple shift registers cascaded together. The size of the shift register in the first direction Y may be larger than the size of the shift register in the second direction X, that is, the shift registers of the present disclosure are arranged vertically. In this way, by increasing the vertical space, the normal placement of each level of shift register can be guaranteed. In some embodiments, the shift register may include at least one gate signal output terminal, and different gate signal output terminals are electrically connected to different gate lines 102, thereby realizing a one-level shift register driving one gate line 103 in a one-level single-drive scheme or a one-level shift register sequentially driving multiple gate lines 103 in a one-level multi-drive scheme. Figure 5 shows the shift register of 18T1C+9T1C. Each stage of the shift register in this disclosure can adopt the shift register shown in Figure 5. Referring again to Figure 5, the shift register includes two gate signal output terminals OUT_1 and OUT_2. OUT_1 can be electrically connected to the 2m-1th gate line 103, and OUT_2 can be electrically connected to the 2mth gate line 103, thereby realizing a one-stage two-drive scheme where each stage of the shift register sequentially drives two adjacent gate lines 102. When the 18T1C one-stage one-drive scheme in this disclosure is changed to an 18T1C+9T1C one-stage two-drive scheme (as shown in Figure 5), the product bezel on the DPO side can be further reduced (2.9mm). Similarly, if a one-stage three-drive or even more-drive design is adopted, the bezel on the DPO side can be further reduced, even achieving an extremely narrow bezel of 2.0mm.
[0094] In some embodiments, as shown in FIG2, the array substrate provided in this disclosure may further include a touch line 104 extending along the first direction Y in the display area AA. Optionally, the touch line 104 and the gate line 102 are on the same layer and made of the same material. The touch line 104 can be electrically connected to an external circuit IC through the connection line CL of the first display area DP. Optionally, the common electrode (com) of the array substrate of this disclosure can be divided into multiple block electrodes according to the required touch accuracy. These block electrodes are electrically connected to the touch line 104 so that the common electrode is reused as a touch electrode and can realize touch function and display function in a time-division manner. In some embodiments, within the first non-display area DP, the connecting line CL can be located between the first fan-out line FL1 and the second fan-out line FL2, with each pair of adjacent connecting lines CL forming a group. In each group, one connecting line CL can be on the same layer and made of the same material as the gate line 102, and the other connecting line CL can be on the same layer and made of the same material as the data line 103. Furthermore, in multiple groups of connecting lines CL near the first fan-out line FL1 and the second fan-out line FL2, the orthographic projections of the two connecting lines CL in each group can partially overlap or alternate along the second direction X. The touch line 104 of this disclosure adopts a vertical routing design, and it is electrically connected to the external circuit IC through the connecting line CL of the first non-display area DP. Therefore, it is unnecessary to set up routing lines connecting the touch line 104 to the external circuit IC within the two third non-display areas LB&RB on the left and right sides, ensuring that the left and right bezels are not affected. In addition, since the load of the touch line 104 does not affect the charging rate of the pixels within the display area AA, its size does not need to be considered; a design scheme that meets the limits of the equipment's manufacturing capabilities is sufficient.
[0095] Referring again to Figure 2, the touch line 104 of this disclosure can be disposed at at least a portion of the column gaps of the sub-pixels (including but not limited to red sub-pixel R, green sub-pixel G, and blue sub-pixel B) extending along the first direction Y. That is, in this disclosure, the touch line 104 can be disposed adjacent to at least a portion of the gate lines 102. In some embodiments, Figures 6 to 8 respectively show another structural schematic diagram of the 3*12 sub-pixel region in Figure 1. As shown in Figures 6 to 8, in this disclosure, the orthogonal projection of the touch line 104 on the substrate 101 passes through the orthogonal projection of at least a portion of the sub-pixels on the substrate 101. For example, in FIG. 6, the orthogonal projection of the touch line 104 on the substrate 101 passes through the orthogonal projection of the red sub-pixel R on the substrate 101; in FIG. 7, the orthogonal projection of the touch line 104 on the substrate 101 passes through the orthogonal projections of the red sub-pixel R and the green sub-pixel G on the substrate 101; and in FIG. 8, the orthogonal projection of the touch line 104 on the substrate 101 passes through the orthogonal projections of the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B on the substrate 101. Thus, it can be seen that the touch line 104 of this disclosure can be adjacent to the gate line 102 as shown in FIG. 2, or it can be arranged in the manner shown in FIG. 6 to FIG. 8, passing through the sub-pixel (i.e., Tx in dot). In FIG. 6 and FIG. 8, only the gate line 102 is provided at the column gap of the sub-pixel, which allows for a narrower column gap, thereby improving the aperture ratio. Furthermore, because the screen is used in both landscape and portrait orientations in this disclosure, the vertical screen size is reduced, resulting in fewer vertical touch electrodes (touch sensors). Consequently, the required density of touch lines 104 is reduced, and the corresponding touch signal terminals on the external circuit IC are reduced, which helps to lower costs.
[0096] In some embodiments, in the array substrate provided in the present disclosure, as shown in FIG2, FIG6 to FIG8, sub-pixels in different rows can be electrically connected to different data lines 103, and sub-pixels in different columns are electrically connected to different gate lines 102. In other words, the gate lines 102 of the present disclosure are electrically connected to sub-pixel columns one-to-one, and the data lines 103 are electrically connected to sub-pixel rows one-to-one, thereby realizing a three-gate pixel architecture and reducing costs.
[0097] In some embodiments, in the array substrate provided in the present disclosure, FIG9 shows a pixel structure of a 2*6 sub-pixel region in FIG1 of the present disclosure, FIG10 is a layout of 2*3 sub-pixels in the pixel architecture shown in FIG9, and FIGS11 to 16 respectively show a pixel structure of a 2*3 sub-pixel region in FIG1 of the present disclosure. As shown in FIGS9 to 16, the present disclosure can also be applied to a dual-gate pixel architecture. Optionally, the sub-pixel is divided into multiple pixels PX. Every two adjacent pixels PX along the first direction Y constitute a pixel period PT. In a pixel period PT, every two sub-pixels are connected on a data line 103, and every n sub-pixels are connected on a gate line 102, where n is the total number of sub-pixels in a single pixel PX. For example, in the present disclosure, a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B constitute a pixel PX, then n is 3.
[0098] In some embodiments, in the array substrate provided in the present disclosure, as shown in Figures 9 to 16, a pixel PX may include a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel. Optionally, the present disclosure uses a red sub-pixel R as the first color sub-pixel, a green sub-pixel G as the second color sub-pixel, and a blue sub-pixel B as the third color sub-pixel for illustration and description. Data line 103 includes a first data line SL1, a second data line SL2, and a third data line SL3. The first data line SL1 is located on one side of the pixel period PT and is electrically connected to two of its adjacent red sub-pixels R, G, and B. The third data line SL3 is located on the other side of the pixel period PT and is electrically connected to two of its adjacent red sub-pixels R, G, and B. The second data line SL2 is located between two pixels PX in the pixel period PT and is electrically connected to two sub-pixels in the pixel period PT that are not connected to the first data line SL1 or the third data line SL3. The gate line 102 may include a first gate line GL1 and a second gate line GL2; wherein, the first gate line GL1 is located between the red sub-pixel R and the green sub-pixel G, and the first gate line GL1 is electrically connected to two red sub-pixels R and one green sub-pixel G in the pixel period PT; the second gate line GL2 is located between the green sub-pixel G and the blue sub-pixel B, and the second gate line GL2 is electrically connected to two blue sub-pixels B and another green sub-pixel G in the pixel period PT.
[0099] For example, in Figures 9 and 10, the first data line SL1 is electrically connected to the adjacent red sub-pixel R and blue sub-pixel B in the pixel period PT, the third data line SL3 is electrically connected to the adjacent red sub-pixel R and blue sub-pixel B in the pixel period PT, and the second data line SL2 is electrically connected to the two green sub-pixels G in the pixel period PT. In the relevant dual-gate high-transmittance pixel architecture, a connection method of two sub-pixels per period is adopted. Each data line 103 has red sub-pixel R / green sub-pixel G, red sub-pixel R / blue sub-pixel B, and green sub-pixel G / blue sub-pixel B mixed color connections, resulting in pre-fill differences in monochrome / mixed color images. This disclosure adopts the data line 103 connection method of Figures 9 and 10, avoiding the mixed color connection of RGB sub-pixels by data line 103, thus eliminating the pre-fill differences in mixed color connections.
[0100] Referring to Figures 9 and 10, the first gate line GL1 is electrically connected to the two red sub-pixels R in the pixel period PT, and the green sub-pixel G located between the first data line SL1 and the second data line SL2. The second gate line GL2 is electrically connected to the two blue sub-pixels B in the pixel period PT, and the green sub-pixel G located between the second data line SL2 and the third data line SL3. This gate connection method avoids cross-sub-pixel connections of the transistor TFT and has a high aperture ratio.
[0101] Figure 17 shows the polarity arrangement of the pixel architecture shown in Figure 9 under column flipping mode. In related dual-gate high-transmittance pixel structures, the data signal needs to be flipped 2 dots per frame, such as alternating positive and negative polarity signals (++--) to output signals in all rows, resulting in high power consumption and high IC output capability requirements. Using the dual-gate pixel architecture disclosed in this invention, as shown in Figures 9 and 10, column flipping can be achieved, meaning the data signal polarity is not flipped in each frame, while still achieving a 2-dot / 4-dot alternating positive and negative image polarity distribution, as shown in Figure 17. The alternating positive and negative polarity arrangement in each row and column helps reduce power consumption and lowers the risk of head-shaking patterns. Furthermore, compared to the three-gate pixel structure, it can increase the charging margin by 1 hour.
[0102] Figures 11 to 16 show the 6-pixel architecture obtained by adjusting the connection order of the source and drain based on the basic gate rules in Figure 9.
[0103] Specifically, in Figure 11, the first data line SL1 is electrically connected to the adjacent red sub-pixel R and green sub-pixel B in the pixel period PT; the third data line SL3 is electrically connected to the adjacent red sub-pixel R and blue sub-pixel B in the pixel period PT; the second data line SL2 is electrically connected to the blue sub-pixel B adjacent to the first data line SL1 and the green sub-pixel G adjacent to the third data line SL3 in the pixel period PT. The first gate line GL1 is electrically connected to the two red sub-pixels R in the pixel period PT and the green sub-pixel G located between the second data line SL2 and the third data line SL3; the second gate line GL2 is electrically connected to the two blue sub-pixels B in the pixel period PT and the green sub-pixel G located between the first data line SL1 and the second data line SL2.
[0104] In Figure 12, the first data line SL1 is electrically connected to the adjacent red sub-pixel R and blue sub-pixel B in the pixel period PT. The third data line SL3 is electrically connected to the adjacent red sub-pixel R and green sub-pixel G in the pixel period PT. The second data line SL2 is electrically connected to the green sub-pixel G adjacent to the first data line SL1 and the blue sub-pixel B adjacent to the third data line SL3 in the pixel period PT. The first gate line GL1 is electrically connected to the two red sub-pixels R in the pixel period PT and the green sub-pixel G located between the first data line SL1 and the second data line SL2. The second gate line GL2 is electrically connected to the two blue sub-pixels B in the pixel period PT and the green sub-pixel G located between the second data line SL2 and the third data line SL3.
[0105] In Figure 13, the first data line SL1 is electrically connected to the adjacent green sub-pixel G and blue sub-pixel B in the pixel period PT. The third data line SL3 is electrically connected to the adjacent red sub-pixel R and green sub-pixel G in the pixel period PT. The second data line SL2 is electrically connected to the adjacent red sub-pixel R of the first data line SL1 and the adjacent blue sub-pixel B of the third data line SL3 in the pixel period PT. The first gate line GL1 is electrically connected to the two red sub-pixels R in the pixel period PT and the green sub-pixel G located between the first data line SL1 and the second data line SL2. The second gate line GL2 is electrically connected to the two blue sub-pixels B in the pixel period PT and the green sub-pixel G located between the second data line SL2 and the third data line SL3.
[0106] In Figure 14, the first data line SL1 is electrically connected to the adjacent green sub-pixel G and blue sub-pixel B in the pixel period PT. The third data line SL3 is electrically connected to the adjacent red sub-pixel R and blue sub-pixel B in the pixel period PT. The second data line SL2 is electrically connected to the red sub-pixel R adjacent to the first data line SL1 and the green sub-pixel G adjacent to the third data line SL3 in the pixel period PT. The first gate line GL1 is electrically connected to the two red sub-pixels R in the pixel period PT and the green sub-pixel G located between the first data line SL1 and the second data line SL2. The second gate line GL2 is electrically connected to the two blue sub-pixels B in the pixel period PT and the green sub-pixel G located between the second data line SL2 and the third data line SL3.
[0107] In Figure 15, the first data line SL1 is electrically connected to the adjacent red sub-pixel R and green sub-pixel G in the pixel period PT. The third data line SL3 is electrically connected to the adjacent green sub-pixel G and blue sub-pixel B in the pixel period PT. The second data line SL2 is electrically connected to the blue sub-pixel B adjacent to the first data line SL1 and the red sub-pixel R adjacent to the third data line SL3 in the pixel period PT. The first gate line GL1 is electrically connected to the two red sub-pixels R in the pixel period PT and the green sub-pixel G located between the second data line SL2 and the third data line SL3. The second gate line GL2 is electrically connected to the two blue sub-pixels B in the pixel period PT and the green sub-pixel G located between the first data line SL1 and the second data line SL2.
[0108] In Figure 16, the first data line SL1 is electrically connected to the adjacent red sub-pixel R and blue sub-pixel B in the pixel period PT. The third data line SL3 is electrically connected to the adjacent green sub-pixel G and blue sub-pixel B in the pixel period PT. The second data line SL2 is electrically connected to the green sub-pixel G adjacent to the first data line SL1 and the red sub-pixel R adjacent to the third data line SL3 in the pixel period PT. The first gate line GL1 is electrically connected to the two red sub-pixels R in the pixel period PT and the green sub-pixel G located between the second data line SL2 and the third data line SL3. The second gate line GL2 is electrically connected to the two blue sub-pixels B in the pixel period PT and the green sub-pixel G located between the first data line SL1 and the second data line SL2.
[0109] Figures 18 to 23 show the polarity arrangement of the pixel architecture shown in Figures 11 to 16 under column flipping mode. As shown in Figures 18 to 23, the polarity distribution of the data signal column flipping mode is an in-plane 2-dot / 4-dot diagonally alternating arrangement of positive and negative polarities. Since the same data line 103 connects sub-pixels of different colors, such as green-blue (GB) images, the data signal can be input from both sides simultaneously or alternately, or from one side. Taking input from the right as an example, in the pixel architecture shown in Figure 18, the first row of green sub-pixels G has no pre-fill, while the second row of green sub-pixels G has pre-fill. The first row of blue sub-pixels B has no pre-fill, while the second row of blue sub-pixels B has pre-fill. Therefore, the brightness of the green sub-pixels G and blue sub-pixels B in adjacent rows differs, which poses a risk of horizontal stripes. The five-pixel architecture in Figures 19 to 23 also poses a risk of horizontal stripes due to color mixing pre-fill. Therefore, in Figure 9, connecting the green sub-pixels G, which are more sensitive to human vision and have higher brightness, to the same data line 103 (i.e., the second data line SL2) can avoid the difference in color mixing pre-fill, which is the preferred design.
[0110] In some embodiments, the dual-gate pixel architecture provided in this disclosure may include touch lines 104, and the touch lines 104 may be disposed at the column gaps between pixels PX, which is equivalent to the touch lines 104 being evenly distributed on the left and right sides of the pixels PX, as shown in Figures 9 to 16. A conventional FHD 1920*720 product requires 48*18 = 864 touch lines 104. The dual-gate pixel architecture of this disclosure uses the touch line 104 arrangement shown in Figures 9 to 16, which eliminates the need to add additional touch lines 104 to meet the product's touch block (40*40) requirements, ensuring high transmittance. In the dual-gate high-transmittance pixel architecture with the largest aperture ratio, each pixel PX has two horizontal gate lines 102, and each of the two sub-pixels has one vertical data line 103 and one vertical touch line 104 (which can be time-division multiplexed as a common electrode line). This is equivalent to each pixel PX having two gate lines 102, 1.5 data lines 103, and 1.5 touch lines 104. In Figures 9 to 16, each pixel PX has two gate lines 102, 1.5 data lines 103, and one touch line 104. Therefore, the horizontal screen vertical pixel ratio under the dual-gate architecture of this disclosure reduces the number of touch lines 104 by 0.5 compared to the dual-gate high-transmittance architecture, and the pixel aperture ratio can be increased by approximately 2% @ PPI = 167. The impact of the pixel aperture ratio is greater at higher PPI.
[0111] In some embodiments, the array substrate of this disclosure can be fabricated using a 6-mask patterning process, sequentially consisting of Metal1-GI-Metal2-1ITO-PVX-2ITO. The Metal1 layer is a gate metal layer, which may include gate lines 102 and touch lines 104; the Metal2 layer is a source / drain metal layer, which may include data lines 103; the GI layer is a gate insulating layer, which may include vias connecting the data lines 103 and the first sub-fan-out line FL' (which may be located in the gate metal layer) in the third non-display area LB&GB, or include a first portion P1 (which may be located in the gate metal layer) connecting the fan-out line FL in the third non-display area LB&GB. The 1ITO layer is a first electrode layer, which may include a pixel electrode 105; the 2ITO layer is a second electrode layer, which may include a common electrode 106, which may be divided into multiple block electrodes, and the block electrodes are time-division multiplexed as touch electrodes; optionally, in a single sub-pixel area, one of the pixel electrode and the common electrode may be a slit electrode and the other may be a planar electrode; the PVX layer is an interlayer dielectric layer, which may include a via connecting the block electrodes and the touch line 104 in the display area AA, and the via also penetrates the gate insulating layer GI. If a process of 6 mask or more is used to add other metal layers, the touch line 104 can be changed from the gate metal layer to other metal layers to improve transmittance, or the traces of other metal layers can be designed in parallel with the gate line 102 or the data line 103 to reduce resistance.
[0112] It should be noted that, in the embodiments of this disclosure, the patterning processes involved in forming each layer structure may include not only some or all of the processes such as deposition, photoresist coating, masking, exposure, development, etching, and photoresist stripping, but may also include other processes, depending on the actual pattern to be formed during the manufacturing process, and are not limited here. For example, a post-baking process may be included after development and before etching. The deposition process may be chemical vapor deposition, plasma-enhanced chemical vapor deposition, or physical vapor deposition, and is not limited here; the mask used in the masking process may be a half-tone mask, a single-slit mask, or a gray-tone mask, and is not limited here; the etching may be dry etching or wet etching, and is not limited here.
[0113] On the other hand, this disclosure provides an external circuit IC for bonding with the array substrate provided in this disclosure. Optionally, the external circuit IC includes bonding terminals PD. Figure 24 is a bonding terminal arrangement diagram of the external circuit IC of this disclosure. As shown in Figure 24, the bonding terminal PD includes data signal terminals SP that are bonded to the fan-out line FL. Taking 1920*720 as an example, where 1920 represents the number of columns of pixel PX and 720 represents the number of pixel rows, the dual-gate pixel architecture of this disclosure requires 720*1.5=1080 data signal terminals SP to provide signals, while the three-gate pixel architecture requires 720 data signal terminals SP to provide signals. Thus, the three-gate pixel architecture of this disclosure can share the external circuit IC of the dual-gate pixel architecture, and in practical applications, the extra data signal terminals SP in the external circuit IC corresponding to the dual-gate pixel architecture compared to the three-gate pixel architecture can be used as dummy terminals. In addition, in the related horizontal pixel three-gate scheme, for a 1920*720 product, the number of data signal terminals SP is 1920. The comparison shows that the number of data signal terminals SP in the three-gate pixel structure and the two-gate pixel structure of this disclosure is reduced by 1920-720=1200 and 1920-1080=840 respectively, which can greatly reduce the product cost.
[0114] When the panel has touch functionality, the bonding terminal PD may further include a touch signal terminal TP bonded to the connecting line CL (connected to the touch control line 104). In some embodiments, the data signal terminal SP may include a first data signal terminal SP1 bonded to the first fan-out line FL1 and a second data signal terminal SP2 bonded to the second fan-out line FL2; in the second direction X, the touch signal terminal TP may be located between the first data signal terminal SP1 and the second data signal terminal SP2 to facilitate bonding connection.
[0115] In some embodiments, to save costs, this disclosure may use a single chip to drive the gate drive circuit GOA (equivalent to the drive gate line 102), the data line 103, and the touch line 104. Based on this, the bonding terminal PD may further include a gate drive signal terminal (not shown in the figure) bonded to the gate drive circuit signal line GL. For ease of connection, this disclosure may be configured in the second direction X, with the gate drive signal terminal located on the side of the first data signal terminal SP1 and / or the second data signal terminal SP2 away from the touch signal terminal TP. That is, this disclosure may sequentially provide the touch signal terminal TP, the data signal terminal SP, and the gate drive signal terminal from the middle to the left and right sides.
[0116] In some embodiments, FIG25 shows another arrangement of bonding terminals of the external circuit IC of this disclosure. Referring to FIG24 and FIG25, the bonding terminals PD of this disclosure are arranged in multiple rows along the first direction Y in the middle area of their occupied region. To avoid short circuits and fully utilize chip space, the bonding terminals PD of adjacent rows can be at least partially staggered in the second direction X. For example, the bonding terminals PD of adjacent rows are exactly staggered in the second direction X, which is equivalent to the spacing between adjacent bonding terminals PD in the same row being approximately the same as the lateral width of the bonding terminals PD. It should be noted that in the embodiments provided in this disclosure, due to limitations in process conditions or the influence of other factors such as measurement, "approximately the same" may coincide exactly or may have some deviation. Therefore, the "approximately the same" relationship between related features, as long as the error is permissible, falls within the protection scope of this disclosure.
[0117] Referring to Figures 24 and 25, the bonding terminals PD can be arranged in multiple rows along the first direction Y in the edge area of their occupied area, as shown in Figure 24, and the row of bonding terminals PD in the middle area roughly overlaps with the row of bonding terminals PD in the edge area; or the bonding terminals PD can also be arranged in multiple rows at an angle away from the display area AA in the edge area of their occupied area, as shown in Figure 25, that is, a sunken arrangement method is adopted. Specifically, the bonding terminals PD are set to be arranged diagonally downward at both ends, which can leave more space in the upper left and upper right corners, which is convenient for panel wiring, thereby narrowing the bottom bezel, achieving a "narrow bezel" effect, and further reducing the DP side bezel.
[0118] In some embodiments, as shown in Figures 24 and 25, the bonding terminal PD may further include an input terminal IP, which may be arranged in a row in the second direction X. The input terminal IP may be bonded to a printed circuit board XPCB, a timing control board Tcon, a system board SOC, etc. Other essential components in the external circuit IC are known to those skilled in the art and will not be described in detail here, nor should they be construed as limiting the present disclosure.
[0119] Based on the same inventive concept, this disclosure provides a display panel, as shown in FIG26, including an array substrate 001 and a counter substrate 002 placed opposite each other, wherein the array substrate 001 is the array substrate 001 provided in this disclosure embodiment. Since the principle of this display panel in solving the problem is similar to that of the array substrate in solving the problem, the implementation of this display panel can refer to the embodiment of the array substrate described above, and repeated details will not be described again.
[0120] In some embodiments, as shown in FIG26, the display panel provided in this disclosure may further include a liquid crystal layer 003 between an array substrate and a counter substrate, a first polarizer 004 on the side of the array substrate 001 away from the counter substrate 002, and a second polarizer 005 on the side of the counter substrate 002 away from the array substrate 001, wherein the polarization direction of the first polarizer 004 and the polarization direction of the second polarizer 005 are perpendicular to each other. Other essential components of the display panel are those which should be understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure.
[0121] Based on the same inventive concept, this disclosure provides a display device, as shown in FIG1, including the display panel PNL and the external circuit IC provided in this disclosure. Optionally, as shown in FIG27, the display device of this disclosure may further include a backlight module BLU located on the light-incident side of the display panel PNL. The backlight module BLU may be a direct-lit backlight module or an edge-lit backlight module. Optionally, the edge-lit backlight module may include LED strips, stacked reflective sheets, light guide plates, diffusers, prism groups, etc., with the LED strips located on one side of the thickness direction of the light guide plate. The direct-lit backlight module may include a matrix light source, a reflective sheet, a diffuser plate, and a brightness enhancement film stacked on the light-emitting side of the matrix light source, with the reflective sheet including openings directly opposite the positions of the LEDs in the matrix light source. The LEDs in the LED strips and the LEDs in the matrix light source may be light-emitting diodes (LEDs), such as miniature light-emitting diodes (Mini LEDs, Micro LEDs, etc.).
[0122] Micro-LEDs, at the sub-millimeter or even micrometer scale, are self-emissive devices, just like organic light-emitting diodes (OLEDs). Like OLEDs, they offer a range of advantages, including high brightness, ultra-low latency, and ultra-wide viewing angles. Furthermore, because inorganic LEDs emit light based on more stable and lower-resistance metal semiconductors, they offer advantages over organic LEDs, such as lower power consumption, better resistance to high and low temperatures, and longer lifespan. When used as backlights, micro-LEDs can achieve more precise dynamic backlighting effects, effectively improving screen brightness and contrast while eliminating glare caused by traditional dynamic backlighting between bright and dark areas, thus optimizing the visual experience.
[0123] In some embodiments, the display device provided in this disclosure can be any product or component with display function, such as an in-vehicle display, projector, 3D printer, virtual reality device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, smartwatch, fitness wristband, personal digital assistant, etc. Optionally, the display device provided in this disclosure includes, but is not limited to, components such as: radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, and control chip. Optionally, the control chip is a central processing unit, digital signal processor, system-on-a-chip (SoC), etc. For example, the control chip may also include memory, power module, etc., and achieve power supply and signal input / output functions through separately provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer-executable code, etc. The hardware circuit may include conventional very large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips, transistors, etc.; the hardware circuit may also include field-programmable gate arrays, programmable array logic, programmable logic devices, etc. Furthermore, those skilled in the art will understand that the above structure does not constitute a limitation on the display device provided in the embodiments of this disclosure. In other words, the display device provided in the embodiments of this disclosure may include more or fewer of the above components, or combine certain components, or have different component arrangements.
[0124] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.
[0125] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.
Claims
1. An array substrate, wherein, include: A substrate, the substrate including a display area, a first non-display area and a second non-display area disposed opposite each other on both sides of the display area, and two third non-display areas connecting the first non-display area and the second non-display area, wherein the first non-display area is used to bond external circuits; A sub-pixel, located in the display area, wherein the size of the sub-pixel along a first direction is greater than the size of the sub-pixel along a second direction; A grid line extends along the first direction in the display area; A gate driving circuit is located in the second non-display area, and the gate driving circuit is electrically connected to the gate line and the external circuit. The data cable extends along the second direction in the display area; A fan-out line extends from at least one of the third non-display areas to the first non-display area, and the fan-out line connects the data line to the external circuit.
2. The array substrate as claimed in claim 1, wherein, The fan-out line includes a first fan-out line and a second fan-out line. The first fan-out line extends from one of the third non-display areas to the first non-display area, and the second fan-out line extends from another of the third non-display areas to the first non-display area.
3. The array substrate as described in claim 2, wherein, The data lines electrically connected to the first fan-out line and the data lines electrically connected to the second fan-out line are alternately arranged.
4. The array substrate as claimed in claim 3, wherein, The fan-out line includes a first part and a second part that are different layers and electrically connected to each other, wherein the orthographic projection of the first part on the substrate overlaps with the orthographic projection of the second part on the substrate.
5. The array substrate as claimed in claim 2, wherein, One end of the same data line is electrically connected to the first fan-out line, and the other end is electrically connected to the second fan-out line.
6. The array substrate as claimed in claim 5, wherein, Both the first fan-out line and the second fan-out line include a first sub-fan-out line and a second sub-fan-out line that are insulated from each other and are not in the same layer. In the third non-display area, the orthographic projection of the first sub-fan-out line on the substrate and the orthographic projection of the second sub-fan-out line on the substrate overlap or alternate with each other.
7. The array substrate according to any one of claims 1 to 6, wherein, The gate drive circuit includes a plurality of cascaded shift registers, wherein the size of the shift register in the first direction is larger than the size of the shift register in the second direction.
8. The array substrate as claimed in claim 7, wherein, The shift register includes at least one gate signal output terminal, and different gate signal output terminals are electrically connected to different gate lines.
9. The array substrate according to any one of claims 1 to 8, wherein, It also includes a touch line extending along the first direction in the display area, the touch line being electrically connected to the external circuit.
10. The array substrate as claimed in claim 9, wherein, The touch line is located at at least a portion of the column gaps where the sub-pixels extend along the first direction.
11. The array substrate as claimed in claim 9, wherein, The orthogonal projection of the touch line on the substrate extends through at least a portion of the orthogonal projection of the sub-pixel on the substrate.
12. The array substrate according to any one of claims 9 to 11, wherein, The touch line is disposed on the same layer as the gate line.
13. The array substrate according to any one of claims 9 to 12, wherein, It also includes a connection line located in the first non-display area, the connection line being connected between the touch line and the external circuit.
14. The array substrate according to any one of claims 1 to 13, wherein, It also includes a gate drive circuit signal line extending from the second non-display area through at least one of the third non-display areas to the first non-display area, the gate drive circuit signal line being connected between the gate drive circuit and the external circuit.
15. The array substrate according to any one of claims 1 to 14, wherein, The sub-pixels in different rows are electrically connected to different data lines, and the sub-pixels in different columns are electrically connected to different gate lines.
16. The array substrate according to any one of claims 1 to 14, wherein, The sub-pixel is divided into multiple pixels. Each pair of adjacent pixels along the first direction constitutes a pixel period. In a pixel period, every two sub-pixels are connected on a data line, and every n sub-pixels are connected on a gate line, where n is the total number of sub-pixels in a single pixel.
17. The array substrate as claimed in claim 16, wherein, The pixel includes a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel; The data lines include a first data line, a second data line, and a third data line; wherein, The first data line is located on one side of the pixel period, and the first data line is electrically connected to two of its adjacent first color sub-pixel, second color sub-pixel, and third color sub-pixel; The third data line is located on the other side of the pixel period, and the third data line is electrically connected to two of its adjacent first color sub-pixel, second color sub-pixel, and third color sub-pixel; The second data line is located between two pixels in the pixel period, and the second data line is electrically connected to two sub-pixels in the pixel period that are not connected to the first data line and the third data line; The gate lines include a first gate line and a second gate line; wherein... The first gate line is located between the first color sub-pixel and the second color sub-pixel, and the first gate line is electrically connected to two first color sub-pixels and one second color sub-pixel in the pixel period; The second gate line is located between the second color sub-pixel and the third color sub-pixel, and the second gate line is electrically connected to two of the third color sub-pixels and one of the second color sub-pixels in the pixel period.
18. The array substrate as claimed in claim 17, wherein, The first color sub-pixel is a red sub-pixel, the second color sub-pixel is a green sub-pixel, and the third color sub-pixel is a blue sub-pixel.
19. An external circuit for bonding to an array substrate as claimed in any one of claims 1 to 18, wherein, The external circuit includes a bonding terminal, which includes a data signal terminal that is bonded to the fan-out line.
20. An external circuit as claimed in claim 19, wherein, The array substrate also includes a touch line and a connecting line connecting the touch line to the external circuit, and the bonding terminal also includes a touch signal terminal bonded to the connecting line.
21. An external circuit as claimed in claim 20, wherein, The fan-out line includes a first fan-out line and a second fan-out line, and the data signal terminal includes a first data signal terminal bound to the first fan-out line and a second data signal terminal bound to the second fan-out line; In the second direction, the touch signal terminal is located between the first data signal terminal and the second data signal terminal.
22. The external circuit as claimed in claim 21, wherein, The array substrate further includes a gate drive circuit signal line connecting the gate drive circuit and the external circuit, and the bonding terminal further includes a gate drive signal terminal bonded to the gate drive circuit signal line. In the second direction, the gate drive signal terminal is located on the side of the first data signal terminal and / or the second data signal terminal away from the touch signal terminal.
23. An external circuit as claimed in any of claims 19 to 22, wherein, The bonding terminals are arranged in multiple rows along the first direction in the middle area of their occupied area, and the bonding terminals in adjacent rows are at least partially staggered in the second direction.
24. An external circuit as claimed in claim 23, wherein, The bonding terminals are arranged in multiple rows along the first direction in the edge area of their occupied area, and the row of bonding terminals in the middle area generally overlaps with the row of bonding terminals in the edge area.
25. An external circuit as claimed in claim 23, wherein, The bonding terminals are arranged in multiple rows at an angle along the edge of their occupied area, away from the display area.
26. A display panel, wherein, It includes an array substrate as described in any one of claims 1 to 18, and a counter substrate positioned opposite to the array substrate.
27. A display device, wherein, It includes the display panel as described in claim 26, and the external circuitry as described in any one of claims 19 to 25.