Display device and driving method therefor
Patent Information
- Application Number
- PCT/CN2025/077931
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-02-18
- Publication Date
- 2026-08-27
Smart Images
Figure CN2025077931_27082026_PF_FP_ABST
Abstract
Description
Display device and its driving method Technical Field
[0001] This disclosure relates to the field of display technology, and in particular to a display device and its driving method. Background Technology
[0002] With the continuous development of display technology, display devices (such as mobile phones, televisions, and computers) have been widely used. Common display devices include liquid crystal displays (LCDs) and organic light-emitting diode displays (OLEDs). Among them, liquid crystal displays have significant advantages in terms of manufacturing cost and manufacturing difficulty, and thanks to their simpler pixel circuit structure, liquid crystal displays have broad application prospects. Summary of the Invention
[0003] On one hand, a driving method for a display device is provided. The display device includes a backlight module and a display panel, the display panel including a gate driving circuit and a data writing transistor, the gate driving circuit being configured to transmit a scan signal to the data writing transistor. The driving method includes: when the display device displays at different refresh rates, the voltage value of the scan signal output by the gate driving circuit is different, and / or, the average luminous brightness of the backlight module is different.
[0004] In some embodiments, when the display device displays at the first refresh rate, the voltage value of the scan signal output by the gate driving circuit is a first voltage. When the display device displays at the second refresh rate, the voltage value of the scan signal output by the gate driving circuit is a second voltage. The first refresh rate is less than the second refresh rate, and the absolute value of the first voltage is greater than the absolute value of the second voltage.
[0005] In some embodiments, when the display device displays at the first refresh rate, during the display phase of one frame, the voltage value of the scan signal output by the gate driving circuit is a first non-operating voltage. When the display device displays at the second refresh rate, during the display phase of one frame, the voltage value of the scan signal output by the gate driving circuit is a second non-operating voltage. Both the first non-operating voltage and the second non-operating voltage are negative, and the first non-operating voltage is less than the second non-operating voltage.
[0006] In some embodiments, when the display device displays at the first refresh rate, during the data writing phase of a frame, the voltage value of the scan signal output by the gate driving circuit is a first operating voltage. When the display device displays at the second refresh rate, during the data writing phase of a frame, the voltage value of the scan signal output by the gate driving circuit is a second operating voltage. Both the first operating voltage and the second operating voltage are positive values, and the first operating voltage is greater than the second operating voltage.
[0007] In some embodiments, when the display device displays at a first refresh rate, the average luminous brightness of the backlight module is a first brightness. When the display device displays at a second refresh rate, the average luminous brightness of the backlight module is a second brightness. Wherein, the first refresh rate is less than the second refresh rate, and the first brightness is greater than the second brightness.
[0008] In some embodiments, the backlight module includes a plurality of light-emitting chips, the brightness of which increases with the increase of the driving current of the light-emitting chips. When the display device displays at a first refresh rate, the driving current of the light-emitting chips is a first current. When the display device displays at a second refresh rate, the driving current of the light-emitting chips is a second current. The second current is less than the first current.
[0009] In some embodiments, the backlight module includes a plurality of light-emitting chips. When the display device displays at a first refresh rate, the duty cycle of the light-emitting chips is X1. When the display device displays at a second refresh rate, the duty cycle of the light-emitting chips is X2. Wherein, X2 is less than X1.
[0010] On the other hand, a display device is provided. The display device includes a backlight module, a display panel, a timing manager, a power management chip, and a gate driver chip. The backlight module includes multiple light-emitting chips. The display panel is disposed on the light-emitting side of the backlight module and includes a gate driver circuit and a data writing transistor. The gate driver circuit is configured to transmit a data signal to the data writing transistor, and the data writing transistor is an oxide thin-film transistor. The timing manager is configured to transmit a corresponding control signal to the power management chip according to the refresh frequency of the display device. The power management chip is configured to transmit a power signal to the gate driver chip according to the control signal. The gate driver chip is configured to transmit the power signal to the backlight module and / or the display panel. Wherein, when the display device displays at different refresh frequencies, the timing manager controls the power management chip to transmit different power signals to the backlight module and / or the display panel.
[0011] In some embodiments, when the display device displays at a first refresh rate, the timing manager controls the power management chip to transmit a first power signal to the display panel. When the display device displays at a second refresh rate, the timing manager controls the power management chip to transmit a second power signal to the display panel. The first power signal includes a first gate high voltage and a first gate low voltage, and the second power signal includes a second gate high voltage and a second gate low voltage. Wherein, the first refresh rate is less than the second refresh rate, the voltage value of the first gate high voltage is greater than the voltage value of the second gate high voltage, and the voltage value of the first gate low voltage is less than or equal to the voltage value of the second gate low voltage; or, the voltage value of the first gate high voltage is greater than or equal to the voltage value of the second gate high voltage, and the voltage value of the first gate low voltage is less than the voltage value of the second gate low voltage.
[0012] In some embodiments, when the display device displays at a first refresh rate, the timing manager controls the power management chip to transmit a third power signal to the backlight module; when the display device displays at the first refresh rate, the timing manager controls the power management chip to transmit a fourth power signal to the backlight module. The light-emitting chip generates a first current under the drive of the third power signal; the light-emitting chip generates a second current under the drive of the fourth power signal. Wherein, the first refresh rate is less than the second refresh rate, and the first current is greater than the second current.
[0013] In some embodiments, when the display device is displaying at a first refresh rate, the timing manager controls the power management chip to transmit a fifth power signal to the backlight module. When the display device is displaying at the first refresh rate, the timing manager controls the power management chip to transmit a sixth power signal to the backlight module. The first refresh rate is less than the second refresh rate, and the duty cycle of the fifth power signal is greater than the duty cycle of the sixth power signal. Attached Figure Description
[0014] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.
[0015] Figure 1 is a structural diagram of a display device according to some embodiments;
[0016] Figure 2 is a structural block diagram of a display device according to some embodiments;
[0017] Figure 3 is a structural diagram of a display panel according to some embodiments;
[0018] Figure 4 shows the IV curves of different types of thin-film transistors according to some embodiments;
[0019] Figure 5 is a graph showing the change in voltage retention rate according to some embodiments;
[0020] Figure 6 shows the brightness of a display device at different frequencies over time in related technologies.
[0021] Figure 7 shows the brightness variation of a display device when switching between different frequencies in the related art.
[0022] Figure 8 is a diagram showing the position of the non-operating voltage of a thin-film transistor in the IV curve according to some embodiments;
[0023] Figure 9 is a diagram showing the position of the operating voltage of a thin-film transistor in the IV curve according to some embodiments;
[0024] Figure 10 shows the current relationship of the light-emitting chip at different frequencies according to some embodiments;
[0025] Figure 11 shows the duty cycle relationship of the light-emitting chip at different frequencies according to some embodiments. Detailed Implementation
[0026] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.
[0027] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.
[0028] In this disclosure, terms such as “down,” “below,” “above,” and “up” are used to explain the relationships between components shown in the accompanying drawings. The terms may be relative concepts and described based on the directions shown in the drawings, or based on the sequence of process steps, but are not limited thereto.
[0029] The term "relative" means that the first element can be directly or indirectly relative to the second element. In the case where the third element is between the first and second elements, although they are still relative to each other, the first and second elements can be understood as being indirectly relative to each other.
[0030] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.
[0031] In describing some embodiments, the term "connection" and its derived expressions are used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium.
[0032] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.
[0033] The use of “configured as” in this article implies an open and inclusive language that does not exclude the applicability to or configuration of devices to perform additional tasks or steps.
[0034] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values may in practice be based on additional conditions or values beyond those stated.
[0035] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).
[0036] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.
[0037] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.
[0038] Embodiments of this disclosure provide a display device, which is a product with image display functionality. Exemplarily, the display device can be any device that displays either moving (e.g., video) or stationary (e.g., still image) content, and whether it is text or an image.
[0039] For example, the display device can be any product or component with display function, such as electronic paper, television, laptop, tablet, personal digital assistant (PDA), mobile phone, watch, clock, calculator, GPS receiver / navigator, camera, display of camera view (e.g., display of a rearview camera in a vehicle), wearable device, augmented reality (AR) device, virtual reality (VR) device, mixed reality (MR) device, in-vehicle display, flying display, etc.
[0040] In some embodiments, the above-mentioned display device may be a liquid crystal display (LCD). Referring to FIG1, the liquid crystal display device 1000 may include a display panel 100, a backlight module 200, and a driving circuit board 300. The display panel 100 is disposed on the light-emitting side of the backlight module 200. The driving circuit board 300 may be electrically connected to the backlight module 200 and the display panel 100 respectively. The driving circuit board 300 may be used to transmit control signals to the backlight module 200 and the display panel 100 to control the backlight module 200 to emit light and to control the display panel 100 to adjust the grayscale of each sub-pixel. In addition, the display device 1000 may also include, but is not limited to, a touch structure, an under-display camera, and an under-display fingerprint recognition sensor, so that the display device 1000 can realize various functions such as touch, photography, video recording, or fingerprint recognition, which will not be listed here.
[0041] The backlight module 200 can be a direct-lit backlight module 200 or an edge-lit backlight module 200, wherein the backlight module 200 is used to emit light and provide a light source for the display panel 100. Exemplarily, the driving circuit board 300 can control the brightness of the backlight module 200. For example, the backlight module 200 can include multiple light-emitting chips, which can be light-emitting diodes, such as mini-LEDs or micro-LEDs. Mini-LEDs have a size of approximately 100μm to 300μm, while micro-LEDs have a size of approximately less than 100μm. Of course, the type of light-emitting chip is not limited to these, and any other suitable light-emitting chip can be used.
[0042] Referring to Figure 2, the driver circuit board 300 may include, for example, a timing controller (TCON) 301, a power management chip (DC / DC) 302, a gate driver chip 303, and an adjustable resistor voltage divider circuit (generating Vcom). Of course, the driver circuit board 300 may also include other circuit structures, which will not be listed here. For example, the timing controller 301 is configured to send a corresponding control signal to the power management chip 302 according to the refresh frequency of the display device. The power management chip 302 is configured to transmit the corresponding power signals (including but not limited to Vgh and Vgl) to the gate driver chip 303 based on the control signals. The gate driver chip 303 then transmits the power signals to the display panel 100 and the backlight module 200.
[0043] Referring again to Figure 1, the display panel 100 may include an array substrate 110 and a color filter substrate 120 disposed opposite to each other, and a liquid crystal layer 130 located between the array substrate 110 and the color filter substrate 120. Of course, the structure of the display panel 100 is not limited to this; it may also include other structures, as long as the same technical concept is adopted. For example, the display panel 100 may also include a first alignment film (not shown in the figure) disposed on the side of the array substrate 110 near the liquid crystal layer 130, and a second alignment film (not shown in the figure) disposed on the side of the color filter substrate 120 near the liquid crystal layer 130, etc.
[0044] Referring to Figure 3, the display panel 100 includes a display area AA and a peripheral area BB surrounding the display area AA. The display area AA refers to the area in the display panel 100 used for displaying images. The display area AA includes multiple sub-pixels P. Each sub-pixel P may include a pixel circuit, a pixel electrode 101, and a common electrode 102. The multiple sub-pixels P are arranged in rows along a first direction X, and the display panel 100 includes multiple rows of sub-pixels P. The multiple sub-pixels P are also arranged in rows along a second direction Y, and the display panel 100 includes multiple columns of sub-pixels P. The first direction Y intersects the second direction X; for example, the first direction Y and the second direction X are perpendicular to each other.
[0045] A pixel circuit may include at least one thin-film transistor (TFT) and a capacitor Cst. For example, the pixel circuit may be a "1T1C" circuit or a "3T1C" circuit, etc. Here, "T" refers to a thin-film transistor, and the number before "T" indicates the number of thin-film transistors; "C" refers to a capacitor, and the number before "C" indicates the number of capacitors. For instance, the pixel circuit may include a data writing transistor T1, and the pixel electrode 101 and the common electrode 102 may form a capacitor Cst.
[0046] As shown in Figure 3, the peripheral area BB can be used to set signal traces (such as power signal lines, clock signal lines, etc.), driving circuits (such as gate driving circuits), and bonding parts, etc. Of course, the structure and function of the peripheral area BB are not limited to this, and will not be listed here. For example, the display panel 100 may include a gate driving circuit (Gate Driver On Array; abbreviated as GOA) 103 disposed in the peripheral area BB.
[0047] The display panel may also include multiple scan signal lines GL and multiple data signal lines DL. Each scan signal line GL is electrically connected to the pixel circuit of a row of sub-pixels P. For example, the scan signal line GL is electrically connected to the data writing transistor T1 of a row of pixel circuits. Each scan signal line is also electrically connected to a gate drive circuit. Each data signal line DL is electrically connected to the data writing transistor T1 of a column of sub-pixels P. The data writing transistor T1 is configured to be turned on or off (disconnected) under the control of the scan signal of the scan signal line GL. When the data writing transistor T1 is on, it transmits the data signal from the data signal line DL to the pixel electrode 101. When the data writing transistor T1 is off, the voltage of the pixel electrode 101 remains constant under the action of the capacitor, and an electric field can be formed between the pixel electrode 101 and the common electrode 102. This electric field can drive the liquid crystal molecules in the liquid crystal layer to deflect, thereby adjusting the grayscale transmittance of the sub-pixel.
[0048] In some embodiments, the display device 1000 can display multiple refresh rates, meaning the refresh rate of the display device 1000 can be adjusted. For example, the refresh rate of the display device 1000 can be as low as 1 Hz and as high as 165 Hz or 240 Hz, etc. Furthermore, the display device 1000 can also display video at various frequencies such as 30 Hz, 48 Hz, 60 Hz, and 120 Hz; these will not be listed individually in the embodiments disclosed herein.
[0049] Referring to Figure 4, compared to a-Si thin-film transistors and low-temperature polycrystalline silicon (LTPS) thin-film transistors, oxide thin-film transistors have a higher on-state current (Io). on This allows for applications in display devices with higher refresh rates. Furthermore, oxide thin-film transistors (TFTs) exhibit lower off-state current (Io). off Oxide thin-film transistors (OSTs) exhibit good performance even at low refresh rates. Therefore, they are widely used in display devices with multiple refresh rates. For example, the data writing transistor T1 described above can be an OST, such as an N-type OST. In this case, the operating voltage of the data writing transistor T1 is positive, and its non-operating voltage is negative.
[0050] Voltage Holding Ratio (VHR) is a crucial parameter in liquid crystal display (LCD) devices. VHR = (1 - voltage decay V') / V0. Due to impurities or other contaminants in the liquid crystal molecules and within the liquid crystal cell, as shown in Figure 5, the VHR decreases continuously over a single frame during operation. Since LCDs achieve grayscale adjustment by driving liquid crystal deflection with voltage, a decrease in the refresh rate of the display panel leads to a corresponding increase in frame length, resulting in a decrease in VHR and average brightness within a frame. In the embodiments of this disclosure, "average brightness" refers to the average brightness during the light-emitting phase of a single frame.
[0051] For example, referring to Figure 6, the voltage retention rate of the liquid crystal molecules is higher when the refresh rate of the display device is higher (f2), and lower when the refresh rate of the display device is lower (f1). This results in the display device displaying the same grayscale at a lower refresh rate (f1) with less brightness than at a higher refresh rate (f2). Consequently, flickering (inconsistent brightness) may occur when the display device switches between different refresh rates and displays the same brightness. For example, referring to Figure 7, when the display device displays 127 gray levels and switches between 48Hz and 165Hz respectively, the brightness of the display device will fluctuate. For instance, when the display device displays at 48Hz, the average brightness of the display device is about 73.1 to 73.15 nits, and when the display device displays at 165Hz, the average brightness of the display device is about 73.2 to 73.25 nits. During the switching between different refresh rates, there is a brightness difference of about 0.1 nits between the display brightness of the same gray level, which causes the display device to flicker.
[0052] To address the aforementioned technical problems, embodiments of this disclosure provide a driving method for a display device. The driving method includes: when the display device displays at different refresh frequencies, the voltage value of the scan signal output by the gate driving circuit 103 is different, and / or the average luminous brightness of the backlight module 200 is different.
[0053] The voltage value of the scan signal output by the gate drive circuit 103 can be approximately equal to the voltage applied to the gate of the data writing transistor T1 (without considering factors such as voltage drop on the scan signal line). When the display device displays at different refresh frequencies, the voltage value of the scan signal output by the gate drive circuit 103 is different, that is, the voltage value applied to the data writing transistor T1 is different. This can cause the conduction / cutoff degree of the data writing transistor T1 to be inconsistent. For example, the operating voltage (the voltage that enables the data writing transistor T1 to conduct) applied to the data writing transistor T1 may be different, so that the conduction degree (on-state current) of the data writing transistor T1 is inconsistent, thereby causing the data signal written by the pixel electrode to be different when displaying the same grayscale at different refresh frequencies; or the non-operating voltage (the voltage that enables the data writing transistor T1 to cut off) applied to the data writing transistor T1 may be different, so that the cutoff degree (off-state current) of the data writing transistor T1 is inconsistent, thereby causing the voltage holding capability of the pixel electrode to be different within a frame. Therefore, when the display device displays the same grayscale at different frequencies, the average voltage of the pixel electrodes varies. This balances the different voltage retention rates of the liquid crystal layer at different refresh rates, reducing brightness differences when switching between frequencies. Similarly, when the display device displays at different refresh rates, the average luminous intensity of the backlight module 200 varies. This also balances the different voltage retention rates of the liquid crystal layer at different refresh rates, reducing brightness differences and lowering the risk of flickering when switching frequencies.
[0054] In some embodiments, when the display device displays at a first refresh rate f1, the voltage value of the scan signal output by the gate drive circuit 103 is a first voltage V1. When the display device displays at a second refresh rate f2, the voltage value of the scan signal output by the gate drive circuit 103 is a second voltage V2.
[0055] The first refresh frequency f1 is less than the second refresh frequency f2, meaning the first refresh frequency f1 is a low frequency and the second refresh frequency f2 is a high frequency. In this case, the absolute value of the first voltage V1 is greater than the absolute value of the second voltage V2. Thus, when the display device is displaying at a low frequency, a smaller voltage can be applied to the gate of the data writing transistor T1, allowing T1 to have a larger on-state current or a smaller off-state current. Based on this, a data signal with a larger voltage value can be written to the pixel electrode through the data writing transistor T1 during the data writing phase, and / or, the voltage retention capability of the pixel electrode during the light-emitting phase can be strengthened (the average voltage on the pixel electrode is higher), which is beneficial for increasing the display brightness of the display device. Correspondingly, when the display device displays at a high frequency, the data writing transistor T1 can have a smaller on-state current or a larger off-state current. Based on this, a data signal with a smaller voltage value can be written to the pixel electrode through the data writing transistor T1 during the data writing stage, and / or the voltage holding capability of the pixel electrode during the light emission stage can be made weaker (the average voltage on the pixel electrode is lower). This is beneficial to reduce the display brightness of the display device, balance the different voltage holding rates of the liquid crystal layer of the display device at different refresh frequencies, reduce the brightness difference when the display device switches between different refresh frequencies, and reduce or even eliminate the risk of flickering in the display device.
[0056] In some embodiments, when the display device displays at a first refresh rate f1, during the display phase of one frame, the voltage value of the scan signal output by the gate driving circuit 103 is a first non-operating voltage V11. When the display device displays at a second refresh rate f2, during the display phase of one frame (also referred to as the light-emitting phase), the voltage value of the scan signal output by the gate driving circuit 103 is a second non-operating voltage V21. Referring to FIG8, both the first non-operating voltage V11 and the second non-operating voltage V21 are negative, and the first non-operating voltage V11 is less than the second non-operating voltage V21. At this time, the absolute value of the first non-operating voltage V11 is greater than the absolute value of the second non-operating voltage V21.
[0057] Thus, when the display device displays at a low frequency (f1), the data writing transistor T1 experiences a leakage current I in the off-state during the display phase. off Smaller pixel size results in stronger voltage retention on the pixel electrodes, less voltage decay, and a higher average voltage on the pixel electrodes during the display phase. This is beneficial for improving the brightness of the display device at low frequencies (f1) and reducing the problem of low brightness during low-frequency display. Conversely, when the display device displays at high frequencies (f2), the off-state leakage current I of the data writing transistor T1 during the display phase... offThe larger the pixel electrode, the worse the voltage retention capability, and the greater the voltage decay. The lower the average voltage on the pixel electrode during the display phase, the better to reduce the brightness of the display device when displaying at high frequency (f2), thus reducing the problem of high brightness when displaying at high frequency.
[0058] In some embodiments, when the display device displays at a first refresh rate f1, during the data writing phase of one frame, the voltage value of the scan signal output by the gate drive circuit 103 is the first operating voltage V12. When the display device displays at a second refresh rate f2, during the data writing phase of one frame, the voltage value of the scan signal output by the gate drive circuit 103 is the second operating voltage V22. Referring to FIG9, both the first operating voltage V12 and the second operating voltage V22 are positive values, and the first operating voltage V12 is greater than the second operating voltage V22. At this time, the absolute value of the first operating voltage V12 is also greater than the absolute value of the second operating voltage V22. Thus, when the display device displays at a low frequency (f1), the on-state current I of the data writing transistor T1 during the data writing phase... on A larger voltage (higher charging rate) results in a higher voltage applied to the pixel electrode, leading to a higher average voltage at the pixel electrode during the display phase. This is beneficial for improving the brightness of the display device at low frequencies (f1) and mitigating the problem of low brightness during low-frequency display. Conversely, when the display device displays at high frequencies (f2), the on-state current I of the data writing transistor T1 during the data writing phase... on Smaller size and lower voltage (lower charging rate) of data signals written to the pixel electrodes result in a lower average voltage of the pixel electrodes during the display phase. This helps to reduce the brightness of the display device when it displays at a high frequency (f2) and reduces the problem of different brightness when the display device displays at different frequencies.
[0059] In some embodiments, when the first non-operating voltage V11 output by the gate driving circuit 103 when the display device displays at a low frequency is less than the second non-operating voltage V21 output by the gate driving circuit 103 when the display device displays at a high frequency, the first operating voltage V12 output by the gate driving circuit 103 when the display device displays at a low frequency can be equal to the second operating voltage V22 output by the gate driving circuit 103 when the display device displays at a high frequency. That is, when V11 is less than V21, V12 can be equal to V22. Thus, when the display device displays at different refresh rates, only the non-operating voltage output by the gate driving circuit 103 needs to be adjusted to reduce the brightness difference of the display device at different refresh rates, which helps to simplify the control difficulty of the display device.
[0060] In some embodiments, when the first non-operating voltage V11 output by the gate drive circuit 103 when the display device displays at a low frequency is less than the second non-operating voltage V21 output by the gate drive circuit 103 when the display device displays at a high frequency, the first operating voltage V12 output by the gate drive circuit 103 when the display device displays at a low frequency can also be greater than the second operating voltage V22 output by the gate drive circuit 103 when the display device displays at a high frequency. That is, when V11 is less than V21, V12 can also be greater than V22. In this way, the on-state current I of the data writing transistor T1 can be adjusted simultaneously. on and off-state leakage current I off This improves the brightness adjustment accuracy of the display device.
[0061] In other embodiments, when the first operating voltage V12 output by the gate driving circuit 103 when the display device displays at a low frequency is greater than the second operating voltage V22 output by the gate driving circuit 103 when the display device displays at a high frequency, the first non-operating voltage V11 output by the gate driving circuit 103 when the display device displays at a low frequency can also be equal to the second non-operating voltage V21 output by the gate driving circuit 103 when the display device displays at a high frequency. That is, when V12 is greater than V22, V11 can also be equal to V21. In this way, when the display device displays at different refresh rates, only the operating voltage output by the gate driving circuit 103 needs to be adjusted to reduce the brightness difference of the display device at different refresh rates, which helps to simplify the control difficulty of the display device.
[0062] In some embodiments, when the display device displays at a first refresh rate f1, the average luminous brightness of the backlight module 200 is a first brightness; when the display device displays at a second refresh rate, the average luminous brightness of the backlight module is a second brightness. The first refresh rate f1 is less than the second refresh rate f2, i.e., the first refresh rate f1 is a low frequency, and the second refresh rate f2 is a high frequency. The first brightness is greater than the second brightness, which helps to reduce the problem of the brightness being lower when the display device displays at low frequencies than when it displays at high frequencies, reduces the brightness difference when the display device switches between different refresh rates, and reduces or even eliminates the risk of flickering in the display device.
[0063] In some embodiments, the backlight module 200 includes multiple light-emitting chips (such as LED light-emitting chips). The types of light-emitting chips are described above and will not be repeated here. The luminous intensity L of the light-emitting chip varies with the driving current I of the light-emitting chip. ledThe brightness of the light-emitting chip increases with the increase in refresh rate. Based on this, when the display device is displaying at a first refresh rate f1, the driving current of the light-emitting chip is a first current I1. When the display device is displaying at a second refresh rate f2, the driving current of the light-emitting chip is a second current I2. Referring to Figure 10, the second current I2 is less than the first current I1, so that the first brightness of the light-emitting chip when the display device is displaying at the first refresh rate f1 can be greater than the second brightness of the light-emitting chip when the display device is displaying at the second refresh rate f2. This reduces the problem that the brightness of the display device at low frequency display is less than that at high frequency display, reduces the brightness difference of the display device at different refresh rates, and reduces or even eliminates the risk of flickering when the display device switches between different refresh rates.
[0064] In some embodiments, the backlight module includes multiple light-emitting chips. When the display device displays at a first refresh rate f1, the duty cycle of the light-emitting chip's illumination duration is X1. When the display device displays at a second refresh rate f2, the duty cycle of the light-emitting chip's illumination duration is X2. Referring to Figure 11, where X2 is less than X1, under the condition that the illumination brightness of the light-emitting chips is the same, the first brightness of the light-emitting chip when the display device displays at the first refresh rate f1 is greater than the second brightness of the light-emitting chip when the display device displays at the second refresh rate f2. This reduces the problem that the brightness of the display device at low frequency display is less than that at high frequency display, reduces the brightness difference of the display device at different refresh rates, and reduces or even eliminates the risk of flickering when the display device switches between different refresh rates.
[0065] The above-described embodiments of this disclosure can be implemented individually or in combination. For example, when the display device displays at different refresh rates, the difference between the brightness of the display device at low frequencies and high frequencies can be reduced by adjusting only the voltage of the scan signal output by the gate driving circuit, or by adjusting only the average luminous brightness of the backlight module. Alternatively, both the voltage of the scan signal output by the gate driving circuit and the average luminous brightness of the backlight module can be adjusted simultaneously. The embodiments of this disclosure do not list all combinations of the above-described embodiments.
[0066] On the other hand, embodiments of this disclosure also provide a display device. Referring to Figures 1 and 2, the display device includes a backlight module 200, a display panel 100, and a driving circuit board 300. The structures of the backlight module 200 and the display panel 100 are described above and will not be repeated here. The driving circuit board 300 includes a timing controller (TCON) 301, a power management chip (DC / DC) 302, and a gate driver chip 303.
[0067] The timing manager 301 is configured to transmit corresponding control signals to the power management chip 302 according to the refresh frequency of the display device. The power management chip 302 is configured to transmit power signals to the gate driver chip 303 according to the control signals. The gate driver chip 303 is configured to transmit power signals to the backlight module and / or the display panel. Specifically, when the display device displays at different refresh frequencies, the timing manager 301 controls the power management chip 302 to transmit different power signals to the backlight module 200 and / or the display panel 100 through the gate driver chip 303. The timing manager 301 controls the power management chip 302 to transmit different power signals to the display panel 100 through the gate driver chip 303, which can make the gate driver circuit 103 of the display panel output scanning signals with different voltage values. The timing manager 301 controls the power management chip 302 to transmit different power signals to the backlight module 200 through the gate driver chip 303, which can make the average luminous brightness of the backlight module 200 different, thereby reducing the brightness difference of the display device when displaying at different refresh rates, and reducing or even eliminating the risk of flickering when the display device switches between different refresh rates.
[0068] In some embodiments, when the display device 1000 displays at a first refresh rate f1, the timing manager 301 controls the power management chip 302 to transmit a first power signal to the display panel 100. The first power signal includes a first gate high voltage VGH1 and a first gate low voltage VGL1. When the display device displays at a second refresh rate f2, the timing manager 301 controls the power management chip 302 to transmit a second power signal to the display panel 100. The second power signal includes a second gate high voltage VGH2 and a second gate low voltage VGL2.
[0069] The aforementioned gate high voltage (including the first gate high voltage VGH1 and the second gate high voltage VGH2) and gate low voltage (including the first gate low voltage VGL1 and the second gate low voltage VGL2) are used to provide power supply voltage to the gate driving circuit 103 of the display panel. The gate driving circuit 103 can generate a scan signal (operating voltage) from the gate high voltage and transmit it to the scan signal line, and generate a scan signal (non-operating voltage) from the gate low voltage and transmit it to the scan signal line. That is, the gate high voltage is used to generate the operating voltage of the data writing transistor, and the gate low voltage is used to generate the non-operating voltage of the data writing transistor. Specifically, the first gate high voltage VGH1 is used to generate the first operating voltage V12, the second gate high voltage VGH2 is used to generate the second operating voltage V22, the first gate low voltage VGL1 is used to generate the first non-operating voltage V11, and the second gate low voltage VGL2 is used to generate the second non-operating voltage V21.
[0070] In this configuration, the first refresh frequency f1 is less than the second refresh frequency f2, the first gate high voltage VGH1 is greater than the second gate high voltage VGH2, and the first gate low voltage VGL1 is less than or equal to the second gate low voltage VGL2. That is, when V11 is less than V21, V12 is greater than V22. Alternatively, the first gate high voltage VGH1 is equal to the second gate high voltage VGH2, and the first gate low voltage VGL1 is less than the second gate low voltage VGL2. That is, when V11 is less than V21, V12 is equal to V22. Thus, when the display device is displaying at a low frequency, a smaller voltage is applied to the gate of the data writing transistor T1, allowing T1 to have a larger on-state current or a smaller off-state current; when the display device is displaying at a high frequency, T1 can have a smaller on-state current or a larger off-state current. This reduces the brightness difference of the display device when displaying at different refresh frequencies and reduces the risk of flickering when switching between different refresh frequencies.
[0071] In some embodiments, when the display device is displaying at a first refresh rate f1, the timing manager 301 controls the power management chip 302 to transmit a third power signal to the backlight module. When the display device is displaying at the first refresh rate, the timing manager controls the power management chip to transmit a fourth power signal to the backlight module. The light-emitting chip generates a first current I1 under the drive of the third power signal, and generates a second current I2 under the drive of the fourth power signal.
[0072] In this design, the first refresh rate f1 is less than the second refresh rate f2, and the first current I1 is greater than the second current I2. Thus, when the display device displays at the first refresh rate f1, the first brightness of the light-emitting chip can be greater than the second brightness of the light-emitting chip when the display device displays at the second refresh rate f2. This addresses the problem of the display device's brightness being lower at low frequencies than at high frequencies, reduces the brightness difference between different refresh rates, and minimizes or even eliminates the risk of flickering when switching between different refresh rates.
[0073] In some embodiments, when the display device displays at a first refresh rate f1, the timing manager 301 controls the power management chip 302 to transmit a fifth power signal to the backlight module 200. When the display device displays at a first refresh rate f2, the timing manager 301 controls the power management chip 302 to transmit a sixth power signal to the backlight module 200. The first refresh rate is lower than the second refresh rate, and the duty cycle X1 of the fifth power signal is greater than the duty cycle X2 of the sixth power signal. This reduces the difference in brightness between low-frequency and high-frequency displays while maintaining the same brightness of the light-emitting chip, thereby reducing brightness fluctuations when switching between different refresh rates and minimizing or even eliminating the risk of flickering in the display device.
[0074] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. A driving method for a display device, the display device comprising a backlight module and a display panel, the display panel comprising a gate driving circuit and a data writing transistor, the gate driving circuit being configured to transmit a scan signal to the data writing transistor; the driving method comprising: When the display device displays at different refresh rates, the voltage value of the scan signal output by the gate drive circuit is different, and / or the average luminous brightness of the backlight module is different.
2. The driving method for the display device according to claim 1, wherein, When the display device displays at a first refresh rate, the voltage value of the scan signal output by the gate drive circuit is a first voltage; When the display device displays at a second refresh rate, the voltage value of the scan signal output by the gate drive circuit is the second voltage; The first refresh frequency is less than the second refresh frequency, and the absolute value of the first voltage is greater than the absolute value of the second voltage.
3. The driving method for the display device according to claim 2, wherein, When the display device displays at the first refresh rate, during the display phase of one frame, the voltage value of the scan signal output by the gate drive circuit is a first non-operating voltage. When the display device displays at the second refresh rate, during the display phase of one frame, the voltage value of the scan signal output by the gate drive circuit is the second non-operating voltage; Both the first non-working voltage and the second non-working voltage are negative, and the first non-working voltage is less than the second non-working voltage.
4. The driving method for the display device according to claim 2 or 3, wherein, When the display device displays at the first refresh rate, during the data writing phase of a frame, the voltage value of the scan signal output by the gate drive circuit is the first operating voltage; When the display device displays at the second refresh rate, during the data writing phase of a frame, the voltage value of the scan signal output by the gate drive circuit is the second operating voltage; Both the first operating voltage and the second operating voltage are positive, and the first operating voltage is greater than the second operating voltage.
5. The driving method for the display device according to any one of claims 1 to 4, wherein, When the display device displays at a first refresh rate, the average luminous brightness of the backlight module is a first brightness; When the display device displays at a second refresh rate, the average luminous brightness of the backlight module is the second brightness; Wherein, the first refresh rate is less than the second refresh rate, and the first brightness is greater than the second brightness.
6. The driving method for the display device according to claim 5, wherein, The backlight module includes multiple light-emitting chips, and the brightness of the light-emitting chips increases with the increase of the driving current of the light-emitting chips; When the display device displays at a first refresh rate, the driving current of the light-emitting chip is a first current; When the display device displays at a second refresh rate, the driving current of the light-emitting chip is a second current; the second current is less than the first current.
7. The driving method for the display device according to claim 5 or 6, wherein, The backlight module includes multiple light-emitting chips; When the display device displays at a first refresh rate, the duty cycle of the light-emitting chip is X1. When the display device displays at the second refresh rate, the duty cycle of the light-emitting chip is X2; wherein X2 is less than X1.
8. A display device, comprising: The backlight module includes multiple light-emitting chips; A display panel is disposed on the light-emitting side of the backlight module, and includes a gate driving circuit and a data writing transistor. The gate driving circuit is configured to transmit a data signal to the data writing transistor, and the data writing transistor is an oxide thin film transistor. The timing manager is configured to transmit corresponding control signals to the power management chip according to the refresh frequency of the display device; A power management chip is configured to transmit a power signal to the gate driver chip according to the control signal; A gate driver chip is configured to transmit the power signal to the backlight module and / or the display panel; When the display device displays at different refresh rates, the timing manager controls the power management chip to transmit different power signals to the backlight module and / or the display panel.
9. The display device according to claim 8, wherein, When the display device displays at a first refresh rate, the timing manager controls the power management chip to transmit a first power signal to the display panel; the first power signal includes a first gate high voltage and a first gate low voltage. When the display device displays at a second refresh rate, the timing manager controls the power management chip to transmit a second power signal to the display panel; the second power signal includes a second gate high voltage and a second gate low voltage. Wherein, the first refresh frequency is less than the second refresh frequency, the voltage value of the first gate high voltage is greater than the voltage value of the second gate high voltage, and the voltage value of the first gate low voltage is less than or equal to the voltage value of the second gate low voltage; or, the voltage value of the first gate high voltage is greater than or equal to the voltage value of the second gate high voltage, and the voltage value of the first gate low voltage is less than the voltage value of the second gate low voltage.
10. The display device according to claim 8 or 9, wherein, When the display device displays at a first refresh rate, the timing manager controls the power management chip to transmit a third power signal to the backlight module; the light-emitting chip generates a first current under the drive of the third power signal. When the display device displays at a first refresh rate, the timing manager controls the power management chip to transmit a fourth power signal to the backlight module; the light-emitting chip generates a second current under the drive of the fourth power signal. Wherein, the first refresh frequency is less than the second refresh frequency, and the first current is greater than the second current.
11. The display device according to any one of claims 8 to 10, wherein, When the display device displays at a first refresh rate, the timing manager controls the power management chip to transmit a fifth power signal to the backlight module; When the display device displays at a first refresh rate, the timing manager controls the power management chip to transmit a sixth power signal to the backlight module. Wherein, the first refresh frequency is less than the second refresh frequency, and the duty cycle of the fifth power signal is greater than the duty cycle of the sixth power signal.