Gain-dependent fast mixed direct-current offset calibration circuit and method, and zero intermediate frequency receiver

Abstract

The present application discloses a gain-dependent fast mixed direct-current offset calibration circuit, comprising: a direct-current offset calibration controller, a mixed direct-current offset calibrator, and a digital domain direct-current offset calibrator. The direct-current offset calibration controller is used for outputting a first control signal enable_mix on the basis of state information rx_state sent by a state controller of a zero intermediate frequency receiver, to start the mixed direct-current offset calibrator; the mixed direct-current offset calibrator is used for, when the first control signal enable_mix signal is a first value, running a mixed direct-current offset calibration algorithm to perform mixed direct-current offset calibration, so as to obtain a calibration codeword; and the digital domain direct-current offset calibrator is used for, when the first control signal enable_mix signal is a second value, running a digital domain direct-current offset calibration algorithm, and performing digital domain direct-current offset calibration on the basis of the calibration codeword. Compared with conventional direct-current offset calibration methods, the method provided by the present application has the characteristics of fast calibration, high calibration accuracy, and insensitivity of the calibration accuracy and calibration speed to receiver gain changes.

Description

Gain dependent fast hybrid DC offset correction circuit, method and zero intermediate frequency receiver TECHNICAL FIELD

[0001] The present application relates to the field of radio frequency transceiver integrated SoC monolithic integrated circuit technology, in particular to a gain dependent fast hybrid DC offset correction circuit, method and zero intermediate frequency receiver. BACKGROUND

[0002] Zero intermediate frequency receiver has gradually become a research hotspot with the rapid development of integrated circuits due to its once frequency conversion, integration and other advantages. The on-chip zero intermediate frequency receiver is composed of a mixer, a low-pass filter, a digital-to-analog converter, a digital signal processing path and other units. When implementing the above receiver signal link using a semiconductor process, due to the non-ideal factors such as signal path from the local oscillator end to the radio frequency end of the mixer during physical implementation, a certain amount of DC signal exists in the received signal. The existence of the DC signal reduces the effective input range of the ADC input end and affects the performance of the receiver. When the DC signal is too large, it even affects the normal operation of the signal receiving channel.

[0003] In order to overcome the performance degradation problem caused by DC offset, different documents propose different offset correction circuits. Generally, the DC offset correction circuit can be divided into foreground correction and background correction. The foreground correction circuit is started before the zero intermediate frequency receiver works to correct the circuit; and the background correction circuit corrects the DC offset when the zero intermediate frequency receiver works normally. The foreground correction and the background correction each have advantages and disadvantages. The foreground correction works before the circuit works normally, and cannot change with the change of PVT parameters of the zero intermediate frequency receiver; the background correction can change with the change of parameters, but the correction time is long and affects the normal working state of the circuit. Neither the foreground correction nor the background correction considers the gain change of the receiver. However, with the change of wireless signals, the gain of the receiving channel usually changes with the change of signal amplitude. SUMMARY

[0004] In view of the above-mentioned shortcomings of the prior art, the present application provides a gain dependent fast hybrid DC offset correction circuit, method and zero intermediate frequency receiver for solving at least one defect in the prior art.

[0005] To achieve the above object and other objects, the present application provides a gain dependent DC offset correction circuit applied to a zero intermediate frequency receiver, the correction circuit comprising: a DC correction controller, a hybrid DC offset corrector, a digital domain DC offset corrector.

[0006] A direct current (DC) offset correction controller is configured to output a first control signal enable_mix to enable a hybrid DC offset correction based on a state information rx_state outputted by a state controller of the zero intermediate frequency (ZIF) receiver;

[0007] A hybrid DC offset correction circuit is configured to perform a hybrid DC offset correction to obtain a corrected code word based on a hybrid DC offset correction algorithm when the first control signal enable_mix is at a first value.

[0008] A digital domain DC offset correction circuit is configured to perform a digital domain DC offset correction based on a digital domain DC offset correction algorithm and the corrected code word when the first control signal enable_mix is at a second value.

[0009] In an embodiment of the present application, the DC offset correction circuit further comprises a DC offset correction DAC.

[0010] The hybrid DC offset correction circuit is configured to output a code word mix_code when the first control signal enable_mix is at the first value, and send the code word mix_code to the DC offset correction DAC.

[0011] The DC offset correction DAC is configured to convert the code word mix_code from a digital code word to an analog current, and the analog current outputted by the DC offset correction DAC is added to an output current of the mixer, and then the added current is filtered by a low pass filter, an ADC and a digital filter to obtain a digital code word.

[0012] The hybrid DC offset correction circuit is configured to detect a DC value based on the digital code word, and generate a corresponding correction code word.

[0013] In an embodiment of the present application, the correction circuit further comprises:

[0014] A memory is configured to store the correction code word and a link sequence gain_index[i] configured by a gain controller of the ZIF receiver as an association.

[0015] In an embodiment of the present application, the hybrid DC offset correction circuit outputs a second control signal lock_mix to indicate whether the hybrid DC offset correction is completed during the hybrid DC offset correction.

[0016] When the second control signal lock_mix is at a first value, it indicates that the hybrid DC offset correction is completed.

[0017] When the second control signal lock_mix is at a second value, it indicates that the hybrid DC offset correction is not completed.

[0018] In an embodiment of the present application, the hybrid DC offset corrector comprises a first stage accumulation unit, a gain unit, and a second stage accumulation unit.

[0019] The accumulation points of the first stage accumulation unit are N A , and the output signal A i of the gain unit is:

[0020] wherein k att is the gain of the gain unit, and x i [n] represents the i-th accumulation interval of the signal x[n] outputted by the digital filter, and the DC offset value of the signal does not change in the accumulation interval, and the signal x[n] is represented as: x[n] = a sin(2πfn) + d (2)

[0021] wherein a represents the signal amplitude, f represents the signal frequency, and d represents the DC component of the signal.

[0022] In the i-th accumulation interval, the signal x i [n] is x i [n] = a i sin(2πfn) + d - k conv d comp,i = a i sin(2πfn) + d i (3)

[0023] wherein a i represents the signal amplitude, d comp,i represents the correction code word, and k conv is the gain coefficient.

[0024] The output value A i of the gain unit is the current DC offset value of the signal,

[0025] The second stage accumulation unit receives the output value A i of the gain unit, and obtains the next update value d comp,i+1 : d comp,i+1 = d comp,i + k att d i N A (5)

[0026] Substituting d i = d - k conv × d comp,i into the above formula, we obtain:

[0027] wherein:

[0028] After multiple iterations of formula (7), the DC offset value in the signal is reduced or eliminated.

[0029] To achieve the above object and other objects, the present application provides a gain-dependent DC offset correction method applied to a zero intermediate frequency receiver, which comprises a gain controller and a state controller; the correction method comprises:

[0030] The first control signal enable_mix is outputted by the DC offset correction controller according to the state information rx_state sent by the state controller of the zero intermediate frequency receiver to start the mixed DC offset corrector;

[0031] When the first control signal enable_mix is a first value, the mixed DC offset corrector runs the mixed DC offset correction algorithm to perform mixed DC offset correction to obtain a corrected code word;

[0032] When the first control signal enable_mix is a second value, the digital domain DC offset corrector runs the digital domain DC offset correction algorithm and performs digital domain DC correction according to the corrected code word.

[0033] In an embodiment of the present application, when the first control signal enable_mix is the first value, the mixed DC offset corrector runs the mixed DC offset correction algorithm to perform mixed DC offset correction to obtain a corrected code word, which comprises:

[0034] When the first control signal enable_mix is the first value, the mixed DC offset corrector outputs a code word mix_code and sends the code word mix_code to the DC offset correction DAC;

[0035] The DC offset correction DAC converts the code word mix_code from a digital code word to an analog current, adds the analog current to the output current of the mixer, and obtains a digital code word after passing through a low-pass filter, an ADC and a digital filter;

[0036] The mixed DC offset corrector detects the DC value according to the digital code word and generates a corresponding corrected code word.

[0037] In an embodiment of the present application, the correction method further comprises:

[0038] The corrected code word and the link sequence gain_index[i] configured by the gain controller of the zero intermediate frequency receiver are stored as an association relationship.

[0039] In an embodiment of the present application, the hybrid DC offset corrector comprises a first-stage accumulation unit, a gain unit, and a second-stage accumulation unit. The hybrid DC offset corrector detects a DC value according to the digital code word and generates a corresponding correction code word, comprising:

[0040] The accumulation point number of the first-stage accumulation unit is N A The output signal A i of the gain unit is:

[0041] wherein k att is the gain of the gain unit, and x i [n] represents the i-th accumulation interval of the signal x[n] output by the digital filter, and the DC offset value of the signal in the accumulation interval does not change. The signal x[n] is represented as: x[n] = a sin(2πfn) + d (2)

[0042] wherein a represents the signal amplitude, f represents the signal frequency, and d is the DC component of the signal.

[0043] In the i-th accumulation interval, the signal x i [n] is x i [n] = a i sin(2πfn) + d - k conv d comp,i = a i sin(2πfn) + d i (3)

[0044] wherein a i represents the signal amplitude, d comp,i represents the correction code word, and k conv is the gain coefficient.

[0045] The output value A i of the gain unit is the current DC offset value of the signal,

[0046] The second-stage accumulation unit receives the output value A i of the gain unit, and obtains the next update value d comp,i+1 : d comp,i+1 = d comp,i + k att d i N A (5)

[0047] d i = d - k conv × dcomp,i Substitute the above formula, we get:

[0048] Wherein:

[0049] After multiple iterations of formula (7), the DC offset value in the signal is reduced or eliminated.

[0050] To achieve the above object and other objects, the application provides a zero intermediate frequency receiver, comprising a mixer, a low-pass filter, an ADC, a digital filter, a gain controller and a state controller; the zero intermediate frequency receiver further comprises the DC offset correction circuit.

[0051] The application has the following beneficial effects:

[0052] The gain-dependent DC offset correction circuit of the application is applied to a zero intermediate frequency receiver, and the correction circuit comprises a DC correction controller, a mixed DC offset corrector and a digital domain DC offset corrector. The DC correction controller is used to output a first control signal enable_mix to start the mixed DC offset corrector according to the state information rx_state sent by the state controller of the zero intermediate frequency receiver. The mixed DC offset corrector is used to run a mixed DC offset correction algorithm to perform mixed DC offset correction and obtain a correction code word when the first control signal enable_mix signal is a first value. The digital domain DC offset corrector is used to run a digital domain DC offset correction algorithm and perform digital domain DC correction according to the correction code word when the first control signal enable_mix signal is a second value. The method of the application has the characteristics of fast correction speed, high correction accuracy and non-sensitivity of correction accuracy and correction speed to gain change of the receiver, compared with the traditional DC offset correction method.

[0053] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, and cannot limit the application. BRIEF DESCRIPTION OF DRAWINGS

[0054] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and serve to explain the principles of the application. It is apparent that the accompanying drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings. In the drawings:

[0055] Fig. 1 is a principle block diagram of a gain-dependent DC offset correction circuit according to an embodiment of the application;

[0056] Fig. 2 is a schematic storage structure of a correction code word and a link sequence according to an embodiment of the application;

[0057] Figure 3 is a circuit diagram of the accumulator according to an embodiment of this application;

[0058] Figure 4 is a flowchart of a gain-dependent DC offset correction method according to an embodiment of this application. Detailed Implementation

[0059] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0060] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0061] Although the terms “first,” “second,” “A,” and “B,” etc., may be used herein to describe various elements, these elements should not be limited by these terms and are used only to distinguish one element from another. For example, without departing from the scope of the art described below, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. The term “and / or” includes a combination of multiple related items or any one of multiple related items.

[0062] As used herein, unless the context otherwise indicates, the singular form is also intended to include the plural form, and it will be understood that the term “comprising” means the presence of the stated feature, quantity, step, operation, element, or combination thereof, but does not exclude the presence or addition of one or more other features, quantities, steps, operations, elements, components, or combinations thereof.

[0063] Before proceeding with the detailed description, it is intended to clarify that the division of components in this specification is based solely on the primary function of each component. That is, two or more components described below may be combined into one component, or may be divided into two or more components based on more detailed functions. In addition to the primary functions of each component, each component described below may also perform some or all of the functions of other components, and some of the primary functions of each component may be performed specifically by other components.

[0064] To address the issue of neglecting receiver gain variations when addressing DC offset through foreground and background calibration, this application provides a gain-dependent fast hybrid DC offset correction circuit. Figure 1 shows a block diagram of a zero-IF receiver and the proposed DC offset correction circuit. The portion within the dashed box represents the proposed DC offset correction circuit, while the area outside the dashed box is the main signal path of the zero-IF receiver. The main signal path of the zero-IF receiver and the DC offset circuit operate in unison under the coordination of the receiver state controller (RX ENSM). The calibration process is broadly divided into two stages: foreground calibration and background calibration. Foreground calibration provides the initial calibration point for background calibration.

[0065] This application provides a gain-dependent DC offset correction circuit applied to a zero-IF receiver. The zero-IF receiver includes a mixer, a low-pass filter (LPF), an ADC, a digital filter, a gain controller, and a status controller. During normal operation, the radio frequency (RF) signal passes through the antenna and mixer, transforming it into an analog baseband signal. Subsequently, after filtering by the analog LPF, it enters the ADC. The ADC quantizes the analog baseband signal into a digital baseband signal, which then enters the digital filter and undergoes online DC offset correction processing. The digital signal is then sent to a host computer. When the input wireless signal power changes, the link adjusts the signal gain under the control of the gain controller, thereby stabilizing the output signal amplitude within a set range. Referring to Figure 1, the correction circuit includes a DC-OC controller, a hybrid DC-OC algorithm, and a digital domain DC-OC algorithm.

[0066] The DC offset correction controller is used to output the first control signal enable_mix to start the hybrid DC offset corrector based on the state information rx_state sent by the state controller of the zero intermediate frequency receiver.

[0067] A hybrid DC offset corrector is used to run a hybrid DC offset correction algorithm to perform hybrid DC offset correction and obtain correction codewords when the first control signal enable_mix is ​​at the first value.

[0068] A digital domain DC offset corrector is used to run a digital domain DC offset correction algorithm when the first control signal enable_mix signal is a second value, and to perform digital domain DC correction according to the correction codeword.

[0069] Of course, when the chip powers on, the state controller sends instructions to the gain controller and the DC offset correction controller. The gain controller configures the channel gain in a certain order, which can be configured from largest to smallest, from smallest to largest, or in a tabular form according to other settings. At the same time, the gain controller sends the current gain information to the DC offset correction controller; the gain information includes: link gain A[i] and gain index gain_index[i]. If the gain configuration is not completed, the gain controller iterates through all gain combinations according to the set gain control method and sorts all these gains in a certain way, such as from largest to smallest or from smallest to largest. Let the link gain configured in the i-th time be A[i], and the corresponding sequence be gain_index[i]. After the gain configuration is completed, the gain controller sends the link gain A[i] and the corresponding gain index gain_index[i] to the DC offset correction controller. The DC offset correction controller receives the link gain A[i] and the gain index gain_index[i] and processes it in conjunction with the state information rx_state sent by the state controller. When rx_state is in offline calibration state, the DC offset correction controller starts and runs the hybrid DC offset correction algorithm.

[0070] It should be noted that for a hybrid DC offset corrector, the first value can be "1" and the second value can be "0".

[0071] In one embodiment, the DC offset correction circuit further includes a DC offset correction DAC; the hybrid DC offset corrector is used to output a codeword mix_code when the first control signal enable_mix is ​​a first value, and send the codeword mix_code into the DC offset correction DAC; the DC offset correction DAC is used to convert the codeword mix_code from a digital codeword to an analog current; the analog current output by the DC offset correction DAC is added to the output current of the mixer, and after passing through a low-pass filter, an ADC, and a digital filter, a digital codeword is obtained; the hybrid DC offset corrector performs DC value detection based on the digital codeword and generates a corresponding correction codeword.

[0072] Specifically, the DC correction controller outputs a first control signal, `enable_mix`. When `enable_mix` changes from 0 to 1, the hybrid DC offset correction algorithm is executed. The first control signal `enable_mix` also serves as the selection signal for a two-to-one switch. When `enable_mix` is 1, the two-to-one switch selects the hybrid DC offset corrector to output the codeword `mix_code`, and sends this codeword `mix_code` to the DC offset correction DAC (DCOC DAC) to achieve the conversion from digital codeword to analog current. At this time, the output current of the DC offset correction DAC is added to the mixer output, and after passing through a low-pass filter, ADC, and digital filter, it is sent back to the hybrid DC offset corrector, forming a complete digital-analog mixed-signal correction loop. The hybrid DC offset corrector runs the hybrid DC offset correction algorithm, performs DC value detection based on the received digital codeword, and generates the corresponding correction codeword `mix_code` to achieve DC correction.

[0073] In one embodiment, the hybrid DC offset corrector includes: a first-stage accumulation unit, a gain unit, and a second-stage accumulation unit;

[0074] The number of accumulation points in the first-level accumulation unit is N. A The output signal A of the gain unit i for:

[0075] Where, k att x is the gain of the gain unit. i [n] represents the i-th accumulation interval of the signal x[n] output by the digital filter. The DC offset value of the signal does not change within the accumulation interval. The signal x[n] is expressed as: x[n]=a sin(2πfn)+d (2)

[0076] Where: a represents the signal amplitude, f represents the signal frequency, and d is the DC component of the signal;

[0077] Within the accumulation interval of the i-th segment, the signal x i [n] is, x i [n] = a i sin(2πfn)+dk conv d comp,i =a i sin(2πfn)+d i (3)

[0078] Among them, a i Indicates signal amplitude, d comp,i Indicates the correction codeword, k convThis is the gain coefficient;

[0079] The output value A of the gain unit i This represents the current DC offset value of the signal.

[0080] The second-stage accumulator unit receives the output value A of the gain unit. i In the middle, we get the next updated value d. comp,i+1 d comp,i+1 =d comp,i +k att d i N A (5)

[0081] d i =dk conv ×d comp,i Substituting into the above equation, we get:

[0082] in:

[0083] Equation (7) reduces or eliminates the DC offset value in the signal after multiple iterations.

[0084] Specifically, the hybrid DC offset corrector includes the following steps during correction:

[0085] Let the signal output from the digital filter be x[n]. After entering the offset correction algorithm, the signal x[n] is first accumulated to estimate the DC value of the current signal. In implementation, the accumulator may include a first-stage accumulator unit composed of an adder and a delay unit, a gain unit, and a second-stage accumulator unit composed of an adder and a delay unit. Let the number of accumulated data points in the first-stage accumulator unit be N. A In implementation, the accumulated points N A It is typically programmable in-system.

[0086] To adjust the closed-loop control loop gain, a gain unit is introduced after the output of the first-stage accumulator unit, denoted as k. att The output signal A after passing through the gain unit i for:

[0087] Where x i [n] represents the i-th accumulation interval of signal x[n], assuming that the DC offset value of the signal does not change within this accumulation interval. Assume that signal x[n] can be expressed as: x[n]=a sin(2πfn)+d (2)

[0088] Where: a represents the signal amplitude, f represents the signal frequency, and d is the DC component of the signal. Since the compensated DC value changes during the DC offset compensation process, the DC value d also changes with time. Let the output value of the DC offset compensation algorithm be d during the i-th integration time interval. comp,i (d comp,i For the correction codeword mix_code in Figure 1, d is used for simplicity in the following formulas. comp,i (Instead), the conversion gain coefficient from the correction codeword through the DAC to the ADC input is set to k. conv The signal is x i If [n] is a given number, then: x i [n] = a i sin(2πfn)+dk conv d comp,i =a i sin(2πfn)+d i (3)

[0089] At this time, the output value A of the gain unit i The current DC offset value of the signal can be expressed as:

[0090] The DC offset value A is obtained. i Then, it is fed into the first-level accumulation unit to obtain the next updated value d. comp,i+1 d comp,i+1 =d comp,i +k att d i N A (5)

[0091] d i =dk conv ×d comp,i Substituting into the above equation, we get:

[0092] in:

[0093] Equation (7) can reduce or eliminate the DC offset value in the signal after multiple iterations. Typically, the number of iterations is programmable in software. When the number of iterations exceeds a preset value, the mixed-signal DC offset correction algorithm converges, changing the lock_mix signal from 0 to 1.

[0094] In one embodiment, during the hybrid DC correction process, the hybrid DC offset corrector outputs a second control signal lock_mix to indicate whether the hybrid DC correction is complete;

[0095] When the second control signal lock_mix is ​​the first value, it indicates that the hybrid DC correction is complete;

[0096] When the second control signal lock_mix is ​​at the second value, it indicates that the hybrid DC correction has not been completed.

[0097] It should be noted that for a hybrid DC offset corrector, the first value can be "1" and the second value can be "0".

[0098] As the algorithm iterates, the correction codeword mix_code tends to converge. During the correction process, the hybrid DC offset corrector outputs a second control signal lock_mix to indicate whether the algorithm has converged. When the hybrid DC offset correction is not complete, the second control signal lock_mix remains at 0; the entire process waits for the algorithm to converge. When the algorithm converges, the second control signal lock_mix changes from 0 to 1, indicating that the hybrid DC offset correction for the current gain configuration A[i] is complete, and the process proceeds to the next step.

[0099] In one embodiment, the correction circuit further includes:

[0100] The memory (MEM) is used to store the correction codeword and the link sequence gain_index[i] configured by the gain controller of the zero intermediate frequency receiver as an association.

[0101] Specifically, the correction codeword mix_code is sent to both the DC offset correction DAC and the gating circuit. The second control signal lock_mix also serves as the control signal for the gating circuit. When the second control signal lock_mix changes from 0 to 1, the gating circuit opens. The correction codeword mix_code obtained from the hybrid DC offset corrector is sent to the data input terminal of the memory, forming a storage table with the link sequence gain_index[i]. The link sequence gain_index[i] serves as the row number of the storage table, and the correction codeword mix_code serves as the storage content of the corresponding row. Figure 2 shows a schematic storage structure of the correction codeword and the link sequence. In implementation, those skilled in the art can design other memory structures, but this does not affect the scheme proposed in this application. For example, on-chip memory can be implemented in different ways, such as SRAM (Static Random-Access Memory), ROM (Read-Only Memory), OTP (One Time Programmable), FLASH (flash memory), etc.

[0102] After storing the correction codeword mix_code, the gain is configured, and then the correction is completed.

[0103] After iterating through all possible gain values, the gain controller sends an indication signal to the state controller, indicating that the DC offset has been calibrated offline under all gain conditions. Upon receiving the indication signal, the state controller changes the rx_state from the off_calibration state to the normal_work state.

[0104] After receiving the rx_state signal as being in the normal_work state, the DC offset correction controller switches the correction mode from offline correction mode to normal receiving mode. At this time, the DC offset correction controller pulls the first control signal enable_mix low from 1 to 0. When the first control signal enable_mix is ​​0, the hybrid DC offset corrector is turned off, and the digital domain DC offset corrector is turned on. During normal operation, the DC offset correction controller receives the current link gain A[i] and gain index gain_index[i] from the gain controller. The DC offset correction controller retrieves the corresponding correction codeword mix_code from memory based on the input gain index gain_index[i]. Under the control of the first control signal enable_mix, the 2-to-1 selector connected to the input of the DC offset correction DAC selects the correction codeword mix_code as the output and sends it into the DC offset correction DAC. The DC offset correction DAC then converts the correction codeword mix_code from a digital codeword to an analog current and adds the analog current to the output current of the mixer. After passing through a low-pass filter, an ADC, and a digital filter, a digital codeword is obtained. The digital domain DC offset corrector detects the DC value based on the digital codeword and generates the corresponding correction codeword to complete the DC correction.

[0105] The above process relies on a hybrid direct offset correction algorithm and a digital DC offset correction algorithm. Algorithmically, the hybrid DC offset correction algorithm and the digital domain DC offset correction algorithm are the same. Comparatively, the hybrid DC offset algorithm involves an additional conversion process: from digital to analog domain and then back to digital domain.

[0106] For the digital domain DC offset correction algorithm, k in equation (7) can be directly set... conv The value is 1, and the correction method is the same as the hybrid DC offset correction method.

[0107] In hybrid DC offset correction, the signal passes through mixers, low-pass filters, ADCs, digital filters, etc.; therefore, a set time can be provided before each accumulation to allow the analog RF circuit to stabilize. In digital domain DC offset correction algorithms, this stabilization time can be accurately set based on the system's implementation delay.

[0108] Compared with traditional DC offset correction circuits, the method proposed in this invention has the advantages of fast correction speed, high correction accuracy, and insensitivity of correction accuracy and speed to changes in receiver gain.

[0109] This application provides a zero-IF receiver, including a mixer, a low-pass filter, an ADC, a digital filter, a gain controller, and a status controller; the zero-IF receiver also includes the aforementioned DC offset correction circuit.

[0110] Referring to Figure 4, this application provides a gain-dependent DC offset correction method applied to a zero-IF receiver, which includes a gain controller and a state controller; the correction method includes:

[0111] Step S410: The DC offset correction controller outputs the first control signal enable_mix to start the hybrid DC offset corrector based on the state information rx_state sent by the state controller of the zero intermediate frequency receiver.

[0112] Step S420: When the first control signal enable_mix is ​​at the first value, the hybrid DC offset corrector runs the hybrid DC offset correction algorithm to perform hybrid DC offset correction and obtain the correction codeword.

[0113] In step S430, when the first control signal enable_mix is ​​at the second value, the digital domain DC offset corrector runs the digital domain DC offset correction algorithm and performs digital domain DC correction according to the correction codeword.

[0114] In one embodiment, the step of running a hybrid DC offset correction algorithm to perform hybrid DC offset correction and obtain correction codewords when the first control signal enable_mix is ​​a first value includes:

[0115] When the first control signal enable_mix is ​​at the first value, the mixed DC offset corrector outputs the codeword mix_code, and the codeword mix_code is sent to the DC offset correction DAC;

[0116] The DC offset correction DAC converts the codeword mix_code from a digital codeword to an analog current, adds the analog current to the output current of the mixer, and obtains the digital codeword after passing through a low-pass filter, ADC, and digital filter.

[0117] The hybrid DC offset corrector detects the DC value based on the digital codeword and generates the corresponding correction codeword.

[0118] In one embodiment, the correction method further includes:

[0119] The correction codeword is stored as an association with the link sequence gain_index[i] configured by the gain controller of the zero-IF receiver.

[0120] In one embodiment of this application, the hybrid DC offset corrector includes: a first-stage accumulation unit, a gain unit, and a second-stage accumulation unit; the hybrid DC offset corrector performs DC value detection based on the digital codeword and generates a corresponding correction codeword, including:

[0121] The number of accumulation points in the first-level accumulation unit is N. A The output signal A of the gain unit i for:

[0122] Where, k att x is the gain of the gain unit. i [n] represents the i-th accumulation interval of the signal x[n] output by the digital filter. The DC offset value of the signal does not change within the accumulation interval. The signal x[n] is expressed as: x[n]=a sin(2πfn)+d (2)

[0123] Where: a represents the signal amplitude, f represents the signal frequency, and d is the DC component of the signal;

[0124] Within the accumulation interval of the i-th segment, the signal x i [n] is, x i [n] = a i sin(2πfn)+dk conv d comp,i =a i sin(2πfn)+d i (3)

[0125] Among them, a i Indicates signal amplitude, d comp,i Indicates the correction codeword, k conv This is the gain coefficient;

[0126] The output value A of the gain unit i This represents the current DC offset value of the signal.

[0127] The second-stage accumulator unit receives the output value A of the gain unit. i In the middle, we get the next updated value d. comp,i+1 d comp,i+1 =d comp,i +k att d i N A(5)

[0128] d i =dk conv ×d comp,i Substituting into the above equation, we get:

[0129]

[0130] in:

[0131] Equation (7) reduces or eliminates the DC offset value in the signal after multiple iterations.

[0132] Specifically, the correction method in this application embodiment includes:

[0133] Step 1: When the chip powers on, the state controller sends commands to the gain controller and the DC offset correction controller. The gain controller configures the channel gain in a specific order, which can be from largest to smallest, from smallest to largest, or in a tabular format. Simultaneously, the gain controller sends the current gain information to the DC offset controller.

[0134] Step 2: Check if gain configuration is complete. If gain configuration is incomplete, the gain controller iterates through all gain combinations according to the set gain control method and sorts all gains in a certain way, such as from largest to smallest or smallest to largest. Let the link gain configured in the i-th time be A[i], and the corresponding sequence be gain_index[i]. After gain configuration is complete, the gain controller sends the link gain A[i] and the corresponding index gain_index[i] to the DC offset correction controller. The DC offset controller receives the link gain A[i] and the gain index gain_index[i], and processes it in conjunction with the status information rx_state sent by the status controller. When rx_state is in the offline calibration state, the DC offset correction controller starts the hybrid DC offset correction algorithm.

[0135] Step 3: Activate the hybrid DC offset correction algorithm. In this stage, the DC offset controller outputs the first control signal `enable_mix`, which changes from 0 to 1, activating the hybrid DC offset corrector and running the hybrid DC offset correction algorithm. The first control signal `enable_mix` also serves as the selection signal for a two-to-one switch. When the first control signal `enable_mix` is 1, the two-to-one switch selects the hybrid DC offset correction algorithm output codeword `mix_code`, and sends this codeword `mix_code` to the DC offset correction DAC (DCOC DAC) to achieve the conversion from digital codeword to analog current. At this time, the output current of the DC offset correction DAC is added to the mixer output, and after passing through a low-pass filter, ADC, and digital filter, it is sent to the hybrid DC offset corrector, forming a complete digital-analog hybrid correction loop. The hybrid DC offset corrector performs DC value detection based on the received digital codeword and generates the corresponding correction codeword `mix_code` to achieve DC correction.

[0136] As the algorithm iterates, the correction codeword `mix_code` tends to converge. During the correction process, the hybrid DC offset correction algorithm outputs a second control signal `lock_mix` to indicate whether the algorithm has converged. When the hybrid DC offset correction is not complete, the second control signal `lock_mix` remains at 0; the entire process waits for the algorithm to converge. When the algorithm converges, the second control signal `lock_mix` changes from 0 to 1, indicating that the hybrid DC offset correction for the current gain configuration A[i] is complete, and the process proceeds to the next step.

[0137] Step 4: Storing the correction value. The correction codeword `mix_code` is sent to both the DC offset correction DAC and the gating circuit. The second control signal `lock_mix` also serves as the control signal for the gating circuit. When the second control signal `lock_mix` changes from 0 to 1, the gating circuit opens. The correction codeword `mix_code` obtained from the hybrid DC offset corrector is then sent to the data input terminal of the memory, forming a storage table with the gain index `gain_index[i]`. The gain index `gain_index[i]` serves as the row number of the storage table, and the correction codeword `mix_code` is the stored content of the corresponding row.

[0138] After storing the correction codeword mix_code, return to step two.

[0139] Step 5: End hybrid DC offset correction and receive normal operation indication. After traversing all possible gain values, the gain controller sends an indication signal to the state controller, indicating that DC offset correction has been completed offline for all gain conditions. Upon receiving the indication signal, the state controller changes the state of rx_state from off_calibration to normal_work.

[0140] Step 6: After receiving the rx_state signal as being in the normal_work state, the DC offset correction controller switches the correction mode from offline correction mode to normal receiving mode. At this time, the DC offset correction controller pulls the first control signal enable_mix low from 1 to 0. When the first control signal enable_mix is ​​0, the hybrid DC offset corrector is turned off, and the digital domain DC offset corrector is turned on to run the digital domain DC offset correction algorithm. During normal operation, the DC offset correction controller receives the current gain information and corresponding gain index from the gain controller. Based on the input gain index, the DC offset correction controller retrieves the corresponding correction codeword mix_code stored in the memory. Under the control of the first control signal enable_mix, the 2-to-1 selector connected to the input of the DC offset correction DAC selects the correction codeword mix_code as the output and sends mix_code into the DC offset correction DAC.

[0141] The above process relies on a hybrid direct offset correction algorithm and a digital DC offset correction algorithm. Algorithmically, hybrid DC offset correction and digital DC offset correction are the same. Comparatively, the hybrid DC offset algorithm involves an additional conversion process: from digital to analog domain and then back to digital domain. Therefore, this paper uses the hybrid DC offset correction algorithm as an example to describe its working process.

[0142] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A gain-dependent DC offset correction circuit, applied to a zero-IF receiver, characterized in that, The correction circuit includes: a DC correction controller, a hybrid DC offset corrector, and a digital domain DC offset corrector; The DC offset correction controller is used to output the first control signal enable_mix to start the hybrid DC offset corrector based on the state information rx_state sent by the state controller of the zero intermediate frequency receiver. A hybrid DC offset corrector is used to run a hybrid DC offset correction algorithm to perform hybrid DC offset correction and obtain correction codewords when the first control signal enable_mix is ​​at the first value. A digital domain DC offset corrector is used to run a digital domain DC offset correction algorithm when the first control signal enable_mix signal is a second value, and to perform digital domain DC correction according to the correction codeword.

2. The gain-dependent DC offset correction circuit according to claim 1, characterized in that, The DC offset correction circuit also includes a DC offset correction DAC; The hybrid DC offset corrector is used to output codeword mix_code when the first control signal enable_mix is ​​a first value, and to send the codeword mix_code into the DC offset correction DAC; The DC offset correction DAC is used to convert the codeword mix_code from a digital codeword to an analog current; the analog current output by the DC offset correction DAC is added to the output current of the mixer, and after passing through a low-pass filter, an ADC, and a digital filter, a digital codeword is obtained. The hybrid DC offset corrector detects the DC value based on the digital codeword and generates the corresponding correction codeword.

3. The gain-dependent DC offset correction circuit according to claim 2, characterized in that, The correction circuit also includes: The memory is used to store the correction codeword and the link sequence gain_index[i] configured by the gain controller of the zero intermediate frequency receiver as an association.

4. The gain-dependent DC offset correction circuit according to claim 3, characterized in that, During the hybrid DC correction process, the hybrid DC offset corrector outputs a second control signal, lock_mix, to indicate whether the hybrid DC correction is complete. When the second control signal lock_mix is ​​the first value, it indicates that the hybrid DC correction is complete; When the second control signal lock_mix is ​​at the second value, it indicates that the hybrid DC correction has not been completed.

5. The gain-dependent DC offset correction circuit according to claim 2, characterized in that, The hybrid DC offset corrector includes: a first-stage accumulation unit, a gain unit, and a second-stage accumulation unit; The number of accumulation points in the first-level accumulation unit is N. A The output signal A of the gain unit i for: Where, k att x is the gain of the gain unit. i [n] represents the i-th accumulation interval of the signal x[n] output by the digital filter. Within the accumulation interval, the DC offset value of the signal does not change. The signal x[n] is represented as: x[n]=asin(2πfn)+d (2) Where: a represents the signal amplitude, f represents the signal frequency, and d is the DC component of the signal; Within the accumulation interval of the i-th segment, the signal x i [n] is, x i [n]=a i sin(2πfn)+d-k conv d comp,i =a i sin(2πfn)+d i (3) Among them, a i Indicates signal amplitude, d comp,i Indicates the correction codeword, k conv This is the gain coefficient; The output value A of the gain unit i This represents the current DC offset value of the signal. The second-stage accumulator unit receives the output value A of the gain unit. i In the middle, we get the next updated value d. comp,i+1 : d comp,i+1 =d comp,i +k att d i N A (5) d i =dk conv ×d comp,i Substituting into the above equation, we get: in: Equation (7) reduces or eliminates the DC offset value in the signal after multiple iterations.

6. A gain-dependent DC offset correction method applied to a zero-IF receiver, the zero-IF receiver comprising a gain controller and a state controller; characterized in that, The correction method includes: The DC offset correction controller outputs the first control signal enable_mix to start the hybrid DC offset corrector based on the state information rx_state sent by the state controller of the zero intermediate frequency receiver. When the first control signal enable_mix is ​​at its first value, the hybrid DC offset corrector runs the hybrid DC offset correction algorithm to perform hybrid DC offset correction and obtain the correction codeword. When the first control signal enable_mix is ​​at the second value, the digital domain DC offset corrector runs the digital domain DC offset correction algorithm and performs digital domain DC correction according to the correction codeword.

7. The gain-dependent DC offset correction method according to claim 6, characterized in that, When the first control signal enable_mix is ​​at a first value, the hybrid DC offset corrector runs a hybrid DC offset correction algorithm to perform hybrid DC offset correction and obtain correction codewords, including: When the first control signal enable_mix is ​​at the first value, the mixed DC offset corrector outputs the codeword mix_code, and the codeword mix_code is sent to the DC offset correction DAC; The DC offset correction DAC converts the codeword mix_code from a digital codeword to an analog current, adds the analog current to the output current of the mixer, and obtains the digital codeword after passing through a low-pass filter, ADC, and digital filter. The hybrid DC offset corrector detects the DC value based on the digital codeword and generates the corresponding correction codeword.

8. The gain-dependent DC offset correction method according to claim 7, characterized in that, The correction method further includes: The correction codeword is stored as an association with the link sequence gain_index[i] configured by the gain controller of the zero-IF receiver.

9. The gain-dependent DC offset correction method according to claim 7, characterized in that, The hybrid DC offset corrector includes: a first-stage accumulation unit, a gain unit, and a second-stage accumulation unit; the hybrid DC offset corrector performs DC value detection based on the digital codeword and generates a corresponding correction codeword, including: The number of accumulation points in the first-level accumulation unit is N. A The output signal A of the gain unit i for: Where, k att x is the gain of the gain unit. i [n] represents the i-th accumulation interval of the signal x[n] output by the digital filter. Within the accumulation interval, the DC offset value of the signal does not change. The signal x[n] is represented as: x[n]=asin(2πfn)+d (2) Where: a represents the signal amplitude, f represents the signal frequency, and d is the DC component of the signal; Within the accumulation interval of the i-th segment, the signal x i [n] is, x i [n]=a i sin(2πfn)+d-k conv d comp,i =a i sin(2πfn)+d i (3) Among them, a i Indicates signal amplitude, d comp,i Indicates the correction codeword, k conv This is the gain coefficient; The output value A of the gain unit i This represents the current DC offset value of the signal. The second-stage accumulator unit receives the output value A of the gain unit. i In the middle, we get the next updated value d. comp,i+1 : d comp,i+1 =d comp,i +k att d i N A (5) d i =dk conv ×d comp,i Substituting into the above equation, we get: in: Equation (7) reduces or eliminates the DC offset value in the signal after multiple iterations.

10. A zero-IF receiver, comprising a mixer, a low-pass filter, an ADC, a digital filter, a gain controller, and a state controller; characterized in that, The zero-IF receiver further includes a DC offset correction circuit as described in any one of claims 1-5.

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