Error correction decoding circuit, control circuit, storage medium, and error correction decoding method

Abstract

The present invention obtains an error correction decoding circuit (1) capable of performing chase decoding processing while suppressing an increase in circuit scale and an increase in delay. The error correction decoding circuit (1) comprises: a group division unit (30) that acquires pieces of reliability data indicating the reliability of data reproduced from a received signal by performing hard decision processing and the reliability obtained in soft decision processing, and divides the pieces of reliability data into a plurality of groups; and a sort processing unit (31) that performs, on pieces of reliability data included in each group, a first sort for extracting, in ascending order of the reliability, data positions indicating the positions of pieces of data in the received signal and corresponding to a second number of pieces of reliability data, the second number being equal to or less than a first number, and further extracts the first number of data positions by performing one or more sorts including a second sort from the data positions extracted from each group in the first sort until the data positions corresponding to the first number of pieces of the reliability data are extracted in ascending order of the reliability.

Description

Error correction decoding circuit, control circuit, storage medium, and error correction decoding method

[0001] This disclosure relates to an error correction decoding circuit, control circuit, storage medium, and error correction decoding method for performing error correction.

[0002] In high-speed transmission devices such as optical transmission systems, error correction codes are generally applied as an effective method for achieving high transmission capacity and long-distance transmission. Error correction codes are a technology used in wired communication systems, wireless communication systems, and memory devices. Error correction codes are a technology in which a transmitting device adds redundant bits to the data it transmits, allowing a receiving device to correct errors even if errors occur in the received data. One example of an error correction code is the BCH (Bose Chaudhuri Hocquenghem) code. Because BCH codes enable error correction with simple algebraic decoding, not only BCH codes themselves but also high-performance codes that use BCH codes as element codes are widely used. Regarding high-performance codes that use BCH codes as element codes, for example, Non-Patent Document 1 proposes OFEC (Open Forward Error Correction), a high-performance FEC (Forward Error Correction).

[0003] Generally, error correction codes are required to achieve good error correction performance with a high coding rate. To achieve high error correction performance, a soft-decision decoding process is used that expresses the likelihood of the data extracted from the received signal being "1" or "0" in numerical gradations. As a soft-decision decoding process for the aforementioned BCH code, for example, chase decoding is proposed in Non-Patent Document 2.

[0004] Open ROADM "Open ROADM MSA 6.0 W B400G Port Digital Specification (400G - 800G)", Open ROADM Rev1.0.1, December 7, 2023, www.OpenROADM.org DAVID CHASE "A Class of Algorithms for Decoding Block Codes With Channel Measurement Information", IEEE TRANSACTIONS ON INFORMATION THEORY, VOL. IT-18, NO.1, JANUARY 1972

[0005] Generally, in Chase decoding processing, first, as data positions with low reliability for the soft decision values of the received code sequence, search for a specified number of data positions. Regarding the number of data positions to be searched at this time, since it affects the error correction performance, a relatively large value is selected according to the system. For the search of data positions with low reliability, it is generally detected by sorting processing, but as the code length N of the BCH code increases, the processing of comparison and sorting increases. Also, as the number of data positions with low reliability to be searched increases, it becomes difficult to improve circuit efficiency. Thus, regarding the implementation of a circuit for performing Chase decoding processing, there is a problem that as the number of data positions with low reliability to be searched increases, the delay increases due to the increase in processing, and the circuit scale becomes large.

[0006] The present disclosure has been made in view of the above, and an object thereof is to obtain an error correction decoding circuit capable of performing Chase decoding processing while suppressing an increase in circuit scale and an increase in delay.

[0007] To solve the above-mentioned problems and achieve the objective, this disclosure provides an error correction decoding circuit that performs soft-decision error correction decoding using a chase decoding algorithm. The error correction decoding circuit is characterized by comprising: a group division unit that acquires confidence data indicating the confidence level of data reconstructed from a received signal by a hard-decision process and the confidence level obtained by a soft-decision process, and divides the confidence data into a plurality of groups; a sorting unit that performs a first sort in each group, targeting the confidence data included in each group, and extracts data positions indicating the data positions in the received signal corresponding to a second number of confidence data, starting from the lowest confidence level; and further performs one or more sorts, including a second sort, from the data positions extracted from each group in the first sort until data positions corresponding to a first number of confidence data, starting from the lowest confidence level, are extracted, thereby extracting the first number of data positions.

[0008] The error correction decoding circuit of this disclosure has the effect of enabling chase decoding processing while suppressing increases in circuit size and delay.

[0009] Figure 1 shows an example of the configuration of the error correction decoding circuit according to Embodiment 1. Figure 2 shows an example of the configuration of the data location search unit included in the error correction decoding circuit according to Embodiment 1. Figure 3 shows an example of the configuration of the data location search unit included in the error correction decoding circuit according to Embodiment 1. Figure 4 shows the difference in error correction performance for each search method in the data location search unit included in the error correction decoding circuit according to Embodiment 1. Figure 5 shows an example of the configuration of the processing circuit when the processing circuit that realizes the error correction decoding circuit according to Embodiment 1 is realized with a processor and memory. Figure 6 shows an example of the processing circuit when the processing circuit that realizes the error correction decoding circuit according to Embodiment 1 is configured with dedicated hardware. Figure 1 shows an example of the configuration of the data position search unit. Figure 2 shows an example of operation when the probability of error occurrence in the received signal is high in the data position search unit of the error correction decoding circuit according to Embodiment 2. Figure 3 shows an example of operation when the probability of error occurrence in the received signal is low in the data position search unit of the error correction decoding circuit according to Embodiment 2. Figure 4 shows an example of operation when the probability of error occurrence in the received signal is average in the data position search unit of the error correction decoding circuit according to Embodiment 2. Figure 5 shows an example of BCH codes that constitute the high-performance FEC targeted by the error correction decoding circuit according to Embodiment 3. Figure 6 shows an example of the configuration of the data position search unit of the error correction decoding circuit according to Embodiment 3. Figure 7 shows the content of the group division process by the group division unit of the data position search unit of the error correction decoding circuit according to Embodiment 3.

[0010] The error correction decoding circuit, control circuit, storage medium, and error correction decoding method according to embodiments of this disclosure will be described in detail below with reference to the drawings.

[0011] Embodiment 1. Figure 1 shows an example of the configuration of an error correction decoding circuit 1 according to Embodiment 1. The error correction decoding circuit 1 performs soft-decision error correction decoding using a chase decoding algorithm. The error correction decoding circuit 1 receives a code sequence signal encoded by a transmitting device (not shown) and transmitted from the transmitting device, performs chase decoding processing based on the chase decoding algorithm on the received signal which is the received code sequence signal, and outputs the decoding result. The error correction decoding circuit 1 comprises a soft-decision processing unit 2, a data position search unit 3, a hard-decision processing unit 4, a test pattern generation unit 5, a plurality of hard-decision decoding units 6, and a decoding result selection processing unit 7.

[0012] The error correction decoding circuit 1 first performs soft-decision processing and hard-decision processing on the received signal as part of chase decoding. Specifically, the hard-decision processing unit 4 reproduces "0" or "1" digital data from the received signal as part of hard-decision processing. The soft-decision processing unit 2 expresses the certainty, i.e., reliability, of the "0" or "1" digital data reproduced by the hard-decision processing unit 4 in a multi-level representation as part of soft-decision processing. For reliability, the absolute value of the likelihood, the absolute value of the log-likelihood ratio, etc., are used. In the following explanation, digital data may be simply referred to as data.

[0013] Next, the data location search unit 3 performs specific processing on the confidence levels of the multi-level representation processed by the soft determination processing unit 2 to search for, i.e., extract T1 data locations. As a general process, the data location search unit 3 searches for T1 data locations with low confidence levels. T1 data locations with low confidence levels indicate the data locations in the code sequence, which is the received signal. These are data locations corresponding to the T1 confidence levels extracted in order from the lowest confidence level when the confidence levels are sorted in confidence level. The data location search unit 3 may actually sort the confidence levels in confidence level, or it may not need to actually sort them in confidence level as long as it can extract data locations corresponding to T1 confidence levels starting from the lowest confidence level. The detailed configuration and operation of the data location search unit 3 will be described later.

[0014] The test pattern generation unit 5 generates test patterns using T1 low-confidence data locations searched by the data location search unit 3 and hard judgment values, which are the result of the hard judgment processing by the hard judgment processing unit 4, i.e., digital data of "0" or "1" reproduced by the hard judgment processing unit 4. The test pattern generation unit 5 generates multiple test patterns by inverting the hard judgment values ​​of the locations corresponding to the T1 low-confidence data locations. Inverting the hard judgment value means changing the hard judgment value from "0" to "1", and changing the hard judgment value from "1" to "0". For example, for each hard judgment value of the locations corresponding to the T1 low-confidence data locations, the test pattern generation unit 5 generates up to 2 to the power of T1 test patterns when considering all non-inversion to all inversion.

[0015] Each of the multiple hard-determination decoding units 6 performs hard-determination decoding processing on one test pattern and outputs the hard-determination decoding processing result. As described above, when the test pattern generation unit 5 generates 2 to the power of T1 test patterns, the error correction decoding circuit 1 is equipped with a maximum of 2 to the power of T1 hard-determination decoding units 6. However, the error correction decoding circuit 1 may have fewer than 2 to the power of T1 hard-determination decoding units 6 by having one hard-determination decoding unit 6 perform hard-determination decoding processing on multiple test patterns.

[0016] The decoding result selection processing unit 7 selects the most suitable hard-determination decoding result from among multiple hard-determination decoding results obtained from multiple hard-determination decoding units 6. The decoding result selection processing unit 7 outputs the selected hard-determination decoding result as the decoding result. As a result, the error correction decoding circuit 1 can achieve error correction performance that is superior to that of general hard-determination decoding.

[0017] Next, the detailed configuration and operation of the data location search unit 3 will be described. In Embodiment 1, when the code length of the code sequence is N, the data location search unit 3 divides the confidence data corresponding to the received signal of the code sequence of code length N, obtained from the soft decision processing unit 2, into multiple groups. Assuming that the number of confidence data points in each group is the same, the number of confidence data points in one group × the number of groups = N. The data location search unit 3 performs a sorting process on the divided groups and searches for T2 data locations with low confidence from each group. Note that T2 < T1. The T2 data locations with low confidence can be defined in the same way as the T1 data location with low confidence described above. In the second stage and beyond, the data location search unit 3 performs a sorting process combining the T2 data locations with low confidence to finally search for T1 data locations with low confidence.

[0018] Figure 2 is a first diagram showing an example of the configuration of the data position search unit 3 included in the error correction decoding circuit 1 according to Embodiment 1. In Figure 2, the configuration of the error correction decoding circuit 1 other than the data position search unit 3 is omitted from the description. The same applies to similar figures thereafter. The data position search unit 3 includes a group division unit 30 and a sorting processing unit 31. The sorting processing unit 31 includes a plurality of sorting units 32 and a sorting unit 33. Although the description is simplified in Figure 2, the seven sorting units below the sorting unit 32 shown in Figure 2 are also referred to as sorting units 32. That is, the sorting processing unit 31 includes eight sorting units 32 as a plurality of sorting units 32. In Figure 2, as an example, the case in which the data position search unit 3 searches for T1 = 8 data positions as the number of low-reliability data positions from the reliability data corresponding to the received signal of a code sequence with code length N = 256 is described. Note that in Figure 2, the reliability data corresponding to the received signal of a code sequence with code length N = 256 is represented by data 0 to 255. The same applies to subsequent figures.

[0019] In the data position search unit 3, the group division unit 30 obtains confidence data, which is a multi-level representation of confidence, from the soft determination processing unit 2. The group division unit 30 divides the confidence data corresponding to the received signal of a code sequence with code length N = 256 into eight groups of 32 data units, which are units of confidence data corresponding to the received signal of a code sequence with code length N = 32.

[0020] In the data location search unit 3, as the first stage of sorting by the sorting processing unit 31, eight sorting units 32 each perform sorting on one of the eight groups generated by the group division unit 30, with 32 inputs and the lowest four-value output. That is, each sorting unit 32 extracts the data locations of four confidence levels corresponding to the four lowest confidence levels when the 32 confidence level data are arranged in confidence order, and outputs them as the four lowest confidence level data locations. Next, in the data location search unit 3, as the second stage of sorting by the sorting processing unit 31, one sorting unit 33 performs sorting on the 4 × 8 = 32 data locations output by the eight sorting units 32, with 32 inputs and the lowest eight-value output. That is, the sorting unit 33 extracts eight data locations corresponding to the eight lowest confidence levels when the 32 data locations are arranged in confidence order, and outputs them as the eight lowest confidence level data locations. As a result, the data location search unit 3 significantly reduces the amount of confidence data through the small sorting process in the first stage, allowing for a smaller sorting process in the subsequent stages. This enables a smaller circuit size for the decoding circuit and a reduction in delay.

[0021] Figure 3 is a second diagram showing an example of the configuration of the data position search unit 3 included in the error correction decoding circuit 1 according to Embodiment 1. The data position search unit 3 includes a group division unit 34 and a sorting processing unit 35. The sorting processing unit 35 includes a plurality of sorting units 36, a plurality of sorting units 37, and a sorting unit 38. Although the description is simplified in Figure 3, the 15 sorting units below the sorting unit 36 ​​shown in Figure 3 are also referred to as sorting units 36. That is, the sorting processing unit 35 includes 16 sorting units 36 as a plurality of sorting units 36. In addition, in the example of Figure 3, the sorting processing unit 35 includes 2 sorting units 37 as a plurality of sorting units 37. As with the case in Figure 2, in Figure 3, as an example, we will explain the case in which T1 = 8 data positions are searched for as the number of low-reliability data positions from reliability data corresponding to a received signal of a code sequence with code length N = 256.

[0022] In the data location search unit 3, the group division unit 34 obtains confidence data, which is a multi-level representation of confidence, from the soft decision processing unit 2. The group division unit 34 divides the confidence data corresponding to the received signal of a code sequence with code length N = 256 into 16 groups of 16 data units, which correspond to the received signal of a code sequence with code length N = 16. In Figure 3, the data location search unit 3 subdivides the groups compared to the example in Figure 2.

[0023] In the data location search unit 3, as the first stage of sorting by the sorting processing unit 35, 16 sorting units 36 each perform sorting on one of the 16 groups generated by the group division unit 34, with 16 inputs and the smallest binary output with the lowest confidence level. That is, each sorting unit 36 ​​extracts the data locations of two confidence levels corresponding to the two lowest confidence levels when the 16 confidence level data are arranged in confidence order, and outputs them as the two lowest confidence level data locations. Next, in the data location search unit 3, as the second stage of sorting by the sorting processing unit 35, two sorting units 37 each perform sorting on 2 × 8 = 16 data locations output from the eight sorting units 36, with 16 inputs and the smallest octave output with the lowest confidence level. That is, each sorting unit 37 extracts eight data locations corresponding to the eight lowest confidence levels when the 16 data locations are arranged in confidence order, and outputs them as the eight lowest confidence level data locations. Next, in the data location search unit 3, as the third sorting process of the sorting processing unit 35, the sorting unit 38 performs a sorting process on the 8 × 2 = 16 data locations output from the two sorting units 37, with 16 inputs and the lowest 8 values ​​output. That is, the sorting unit 38 extracts 8 data locations corresponding to the 8 lowest confidence levels when the 16 data locations are arranged in confidence order, and outputs them as the 8 lowest confidence data locations. As a result, in the example of Figure 3 as in the example of Figure 2, the data location search unit 3 can significantly reduce the amount of confidence data through the small sorting process in the first stage, allowing for a smaller configuration of the subsequent sorting process, thus enabling a smaller circuit size for the decoding circuit and a reduction in delay.

[0024] Note that in the configurations shown in Figures 2 and 3, the data location search unit 3 does not guarantee that it will correctly search for the minimum eight values ​​when searching for data locations with low reliability. Therefore, in Figures 2 and 3, the output from the data location search unit 3 is set to the quasi-minimum eight values. Figure 4 is a diagram showing the differences in error correction performance for each search method in the data location search unit 3 of the error correction decoding circuit 1 according to Embodiment 1. Figure 4 compares the error correction performance when chase decoding is performed based on the minimum eight values ​​obtained by each search method in the cases where the data location search unit 3 of the error correction decoding circuit 1 correctly searches for the minimum eight values, when it searches for the minimum eight values ​​with the configuration of Figure 2, and when it searches for the minimum eight values ​​with the configuration of Figure 3, using an extended BCH (256, 239) with 17 parity bits added to 239 information bits as an example.

[0025] In this way, in the data position search unit 3, the group division units 30 and 34 acquire confidence data that represents the confidence level of the data regenerated from the received signal by the hard determination processing of the hard determination processing unit 4 and the confidence level obtained by the soft determination processing of the soft determination processing unit 2, and divide the confidence data into multiple groups. The sorting units 31 and 35 perform a first sort on the confidence data contained in each group, extracting data positions that indicate the data positions in the received signal corresponding to a second number of T2 confidence data, up to a first number of T1, starting from the lowest confidence level. Furthermore, they perform one or more sorts, including a second sort, from the data positions extracted from each group in the first sort until data positions corresponding to a first number of T1 confidence data, starting from the lowest confidence level, are extracted, thereby extracting a first number of T1 data positions.

[0026] In the first embodiment, the method described for reducing the data to T2 in the first sorting process after dividing the confidence data input to the data location search unit 3 into multiple groups was explained, but the method is not limited to this. Depending on the code length N of the code sequence, the number of data locations to search T1, etc., the data location search unit 3 may configure the second and subsequent sorting processes in multiple groups and further reduce the data by using T3 data locations with lower confidence levels. Note that T3 < T2 < T1. The T3 data locations with lower confidence levels can be defined in the same way as the T1 data locations with lower confidence levels described above.

[0027] Figure 5 is a flowchart showing the operation of the data location search unit 3 of the error correction decoding circuit 1 according to Embodiment 1. In the data location search unit 3, the group division unit 30 (or 34) divides the confidence data obtained from the soft judgment processing unit 2 into a plurality of groups, each containing a predetermined number of confidence data (step S1). Next, the sorting processing unit 31 (or 35) performs a first sort (step S2). Specifically, in the sorting processing unit 31 (or 35), each sorting unit 32 (or 36) in the first stage searches for and outputs T2 low-confidence data locations from a predetermined number of confidence data included in one group, which is less than the number T1 of low-confidence data locations ultimately output from the data location search unit 3. Next, the sorting processing unit 31 (or 35) performs one or more sorts, including a second sort (step S3). Specifically, the sorting processing unit 31 (or 35) further performs one or more sorts, including sorting by the second sorting unit 33 (or 37). The sorting processing unit 31 (or 35) searches for T1 low-confidence data locations through the processing in steps S2 and S3, and outputs T1 low-confidence data locations (step S4).

[0028] Next, the hardware configuration of the error correction decoding circuit 1 will be described. In the error correction decoding circuit 1, the soft judgment processing unit 2, the data position search unit 3, the hard judgment processing unit 4, the test pattern generation unit 5, the multiple hard judgment decoding units 6, and the decoding result selection processing unit 7 are implemented by a processing circuit. The processing circuit may be a processor and memory that execute a program stored in memory, or it may be dedicated hardware. The processing circuit is also called a control circuit.

[0029] Figure 6 shows an example of the configuration of a processing circuit 90 when the processing circuit that realizes the error correction decoding circuit 1 according to Embodiment 1 is realized by a processor 91 and a memory 92. The processing circuit 90 shown in Figure 6 is a control circuit and comprises a processor 91 and a memory 92. When the processing circuit 90 is composed of a processor 91 and a memory 92, each function of the processing circuit 90 is realized by software, firmware, or a combination of software and firmware. The software or firmware is written as a program and stored in the memory 92. In the processing circuit 90, each function is realized by the processor 91 reading and executing the program stored in the memory 92. That is, the processing circuit 90 includes a memory 92 for storing a program that will result in the processing of the error correction decoding circuit 1 being executed. This program can also be said to be a program that causes the error correction decoding circuit 1 to execute each function realized by the processing circuit 90. This program may be provided by a storage medium on which the program is stored, or by other means such as a communication medium.

[0030] The above program can also be described as a program to be executed by the error correction decoding circuit 1, which includes a group division step in which the group division unit 30 (or 34) acquires reliability data that indicates the reliability of the data regenerated from the received signal by the hard judgment process and the reliability obtained by the soft judgment process, and divides the reliability data into multiple groups; a sorting step in which the sorting processing unit 31 (or 35) performs a first sort in each group, targeting the reliability data contained in each group, and extracts data positions in the received signal that indicate the position of the data corresponding to a second number of reliability data, up to a first number, starting from the lowest reliability; and further performs one or more sorts, including a second sort, from the data positions extracted from each group in the first sort until data positions corresponding to a first number of reliability data, starting from the lowest reliability, are extracted, thereby extracting the first number of data positions.

[0031] Here, the processor 91 is, for example, a CPU (Central Processing Unit), processing unit, arithmetic unit, microprocessor, microcomputer, or DSP (Digital Signal Processor). The memory 92 is, for example, a non-volatile or volatile semiconductor memory such as RAM (Random Access Memory), ROM (Read Only Memory), flash memory, EPROM (Erasable Programmable ROM), EEPROM (Registered Trademark) (Electrically EPROM), magnetic disk, flexible disk, optical disk, compact disk, minidisc, or DVD (Digital Versatile Disc).

[0032] Figure 7 shows an example of a processing circuit 93 when the processing circuit realizing the error correction decoding circuit 1 according to Embodiment 1 is configured with dedicated hardware. The processing circuit 93 shown in Figure 7 may be, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or a combination thereof. The processing circuit may be partially realized with dedicated hardware and partially realized with software or firmware. In this way, the processing circuit can realize each of the above functions with dedicated hardware, software, firmware, or a combination thereof.

[0033] As described above, according to this embodiment, in the error correction decoding circuit 1, the data position search unit 3 divides the reliability data obtained by the soft judgment process into multiple groups, and as the first stage sorting process, searches for data positions with low reliability in each group to reduce the amount of reliability data, and then performs the second and subsequent sorting processes on the obtained data positions. As a result, the error correction decoding circuit 1 can perform chase decoding while suppressing an increase in circuit size and delay. The error correction decoding circuit 1 enables miniaturization of the decoding circuit and reduction of delay.

[0034] Embodiment 2. In Embodiment 1, the search process for low-reliability data locations in the chase decoding process of the error correction decoding circuit 1 was simplified without degrading error performance by reducing the amount of reliability data used in the sorting process. This was achieved because the noise applied in the transmission line followed a Gaussian distribution, resulting in a low frequency of low-reliability data occurrences, and also because, due to the system configuration, even if burst errors occur due to noise generated in the transmission line, the errors, i.e., the low-reliability data locations, are diffused by the interleavers that are generally inserted. Embodiment 2 describes a case where the frequency of low-reliability data occurrences is relatively high and they occur in bursts in the same group, that is, where there is a possibility that T2 or more low-reliability data occur in the same group.

[0035] Figure 8 shows an example of the configuration of the data position search unit 3 included in the error correction decoding circuit 1 according to Embodiment 2. Although not shown in the figure, in Embodiment 2, the configuration of the error correction decoding circuit 1 is the same as the configuration of the error correction decoding circuit 1 in Embodiment 1 shown in Figure 1. The data position search unit 3 includes a group division unit 40, a sort processing unit 41, a distribution evaluation unit 50, and a sort control unit 51. The sort processing unit 41 includes a plurality of sorting units 42, a synthesis unit 43, a sorting unit 44, a sorting unit 45, a synthesis unit 46, a sorting unit 47, and a synthesis unit 48. Although the description is simplified in Figure 8, the seven sorting units below the sorting unit 42 shown in Figure 8 are also considered sorting units 42. That is, the sort processing unit 41 includes eight sorting units 42 as a plurality of sorting units 42. In Figure 8, similar to Embodiment 1, the data position search unit 3 will explain, as an example, the case in which it searches for T1 = 8 data positions as the number of low-reliability data positions from the reliability data corresponding to the received signal of a code sequence with code length N = 256.

[0036] In the data location search unit 3, the group division unit 40 obtains confidence data, which is a multi-level representation of confidence, from the soft determination processing unit 2. The group division unit 40 divides the confidence data corresponding to the received signal of a code sequence with code length N = 256 into eight groups of 32 data units, which are units of confidence data corresponding to the received signal of a code sequence with code length N = 32.

[0037] At this time, in the data position search unit 3, the distribution evaluation unit 50 evaluates the distribution of confidence in the confidence data based on the confidence data acquired by the group division unit 40 from the soft judgment processing unit 2. The distribution evaluation unit 50 outputs the evaluation result of the confidence distribution of the confidence data to the sort control unit 51. The sort control unit 51 controls the operation of the sort processing unit 41 based on the evaluation result acquired from the distribution evaluation unit 50. That is, based on the evaluation result, the sort control unit 51 controls the input signals and stops processing for the synthesis unit 43, sort unit 44, sort unit 45, synthesis unit 46, sort unit 47, and synthesis unit 48 within the sort processing unit 41.

[0038] Specifically, the distribution evaluation unit 50 calculates the frequency of occurrence of low-confidence data in the received signal based on the confidence data. Based on the frequency of occurrence calculated, the distribution evaluation unit 50 evaluates the probability of error occurrence in the received signal. For example, consider a case where the confidence level is represented by 4 bits in 16 steps from 0 to 15. In the evaluation by the distribution evaluation unit 50, if the frequency of occurrence of 0 or low-confidence values ​​between 0 and 1 is higher than a defined first threshold, the probability of error occurrence in the received signal is high, and therefore, strictness is required in extracting the locations of low-confidence data. In this case, the sort control unit 51 controls the sort processing unit 41 so that the locations of low-confidence data are extracted strictly.

[0039] Figure 9 shows an example of the operation of the data position search unit 3 of the error correction decoding circuit 1 according to Embodiment 2 when the probability of error occurrence in the received signal is high. In the data position search unit 3, as the first stage of sorting processing of the sort processing unit 41, eight sorting units 42 each perform sorting processing of 32 inputs and the lowest 8 values ​​output for one of the eight groups generated by the group division unit 40. That is, each sorting unit 42 extracts the data positions of eight confidence data corresponding to the eight lowest confidence levels when the 32 confidence data are arranged in confidence order, and outputs them as eight data positions with the lowest confidence levels. Next, in the data position search unit 3, as the second stage of sorting processing of the sort processing unit 41, sorting unit 44 performs sorting processing of 32 inputs and the lowest 8 values ​​output for the 8 × 4 = 32 data positions output from the four sorting units 42. Furthermore, the sorting unit 45 performs a sorting process on the 8 × 4 = 32 data positions output from four sorting units 42 that are different from the sorting unit 42 targeted by the sorting unit 44, using 32 inputs and outputting the 8 lowest values ​​with the lowest confidence level. That is, the sorting units 44 and 45 extract the 8 data positions corresponding to the 8 lowest confidence levels when the 32 data positions are sorted in confidence order, and output them as the 8 lowest confidence data positions. Next, in the data position search unit 3, as the third sorting process of the sorting processing unit 41, the sorting unit 47 performs a sorting process on the 8 × 2 = 16 data positions output from the sorting units 44 and 45, using 16 inputs and outputting the 8 lowest values ​​with the lowest confidence level. That is, the sorting unit 47 extracts the 8 data positions corresponding to the 8 lowest confidence levels when the 16 data positions are sorted in confidence order, and output them as the 8 lowest confidence data positions.

[0040] As a result, the data location search unit 3 can extract the data location of the smallest 8 values ​​with the lowest reliability. At this time, the sort control unit 51 controls each part within the data location search unit 3 so that the above-described three-stage sorting can be performed. In addition, the sort processing unit 41 can simplify the processing in the second and third stages of sorting because the sorting in ascending order in units of 8 inputs was performed in the previous sorting stage.

[0041] Next, in the evaluation by the distribution evaluation unit 50, if the frequency of occurrence of 0 or low-confidence values ​​between 0 and 1 is extremely low and lower than the defined second threshold, the probability of error occurrence is low, and the possibility of consecutive low-confidence data positions is also small. Therefore, it is highly likely that there will be no problem in significantly reducing the data in the first sorting process. Note that the second threshold is less than the first threshold. In this case, the sort control unit 51 controls the sort processing unit 41 to significantly reduce the data in the first sorting process.

[0042] Figure 10 shows an example of operation in the data position search unit 3 of the error correction decoding circuit 1 according to Embodiment 2 when the probability of error occurrence in the received signal is low. In the data position search unit 3, as the first stage of sorting processing of the sort processing unit 41, eight sort units 42 each perform sorting processing of 32 inputs and the output of the 8 smallest values ​​with the lowest confidence for one of the eight groups generated by the group division unit 40. That is, each sort unit 42 extracts the data positions of the 8 confidence data corresponding to the 8 lowest confidence levels when the 32 confidence data are arranged in confidence order, and outputs them as the 8 data positions with the lowest confidence. Next, in the data position search unit 3, the synthesis unit 46 selects and outputs the minimum 2 values ​​from the 8 smallest values ​​with the lowest confidence output from each sort unit 42. That is, the synthesis unit 46 selects the minimum 2 values ​​from the 8 × 8 = 64 values ​​output from the 8 sort units 42, and outputs the 2 × 8 = 16 smallest values ​​with the lowest confidence. Next, in the data location search unit 3, as the second sorting process of the sorting processing unit 41, the sorting unit 47 performs a sorting process on the 2 × 8 = 16 data output from the synthesis unit 46, with 16 inputs and the lowest 8 values ​​to output. That is, the sorting unit 47 extracts 8 data locations corresponding to the 8 lowest confidence levels when the 16 data locations are arranged in confidence order, and outputs them as the 8 lowest confidence data locations.

[0043] As a result, the data position search unit 3 can extract a data position corresponding to the smallest 8 values with low reliability. At this time, the sort control unit 51 controls each unit in the data position search unit 3 so that the two-stage sort as described above can be performed. Since the sort processing unit 41 can greatly reduce the data before the second-stage sort processing, the processing can be simplified.

[0044] Next, in the evaluation by the distribution evaluation unit 50, when the occurrence frequency of 0 or the occurrence frequency of values with low reliability between 0 and 1 does not correspond to any of the above, that is, when the occurrence frequency of values with low reliability is greater than or equal to the second threshold and less than or equal to the first threshold, the error occurrence probability in the received signal is estimated to be an average error occurrence probability.

[0045] FIG. 11 is a diagram showing an example of the operation when the error occurrence probability in the received signal in the data position search unit 3 included in the error correction decoding circuit 1 according to Embodiment 2 is average. In the data position search unit 3, as the first-stage sort processing of the sort processing unit 41, eight sort units 42 each perform a 32-input and minimum 8-value output sort processing with low reliability on one of the eight groups generated by the group division unit 40. That is, each sort unit 42 extracts eight data positions corresponding to the eight lowest reliabilities when arranging 32 reliability data in ascending order of reliability, and outputs them as eight data positions with low reliability. Next, in the data position search unit 3, the synthesis unit 43 selects and outputs the minimum 4 values from the minimum 8 values with low reliability output from each sort unit 42. That is, the synthesis unit 43 selects the minimum 4 values for each of the eight sort units 42 from the 8×8 = 64 values output from the eight sort units 42, and outputs the minimum 4×8 = 32 values with low reliability. Next, in the data position search unit 3, as the second-stage sort processing of the sort processing unit 41, the sort unit 44 performs a 32-input and minimum 8-value output sort processing with low reliability on the 4×8 = 32 data output from the synthesis unit 43. That is, the sort unit 44 extracts eight data positions corresponding to the eight lowest reliabilities when arranging 32 data positions in ascending order of reliability, and outputs them as eight data positions with low reliability.

[0046] As a result, the data position search unit 3 can extract a data position corresponding to the smallest 8 values with low reliability. At this time, the sort control unit 51 controls each unit in the data position search unit 3 so that the two-stage sort as described above can be performed. The two-stage sort process of the sort processing unit 41 shown in FIG. 11 is substantially the same as the two-stage sort process of the sort processing unit 31 in the first embodiment shown in FIG. 2.

[0047] As described above, when there is an assumed bias in the reliability among the reliability data included in each group, the sort processing unit 41 performs each sort so that the data positions corresponding to the T1 reliability data, which is the first number from the lower reliability, are extracted based on the control of the sort control unit 51. Further, when there is no assumed bias in the reliability among the reliability data included in each group, the sort processing unit 41 performs a process of reducing the data amount of the target reliability data at any stage of the sort or between sorts based on the control of the sort control unit 51.

[0048] Although the distribution evaluation unit 50 evaluates the error occurrence probability in the received signal by comparing the occurrence frequency of 0 or the occurrence frequency of low values of reliability from 0 to 1 among the 16 levels from 0 to 15 represented by 4 bits of reliability, it is not limited to this. The distribution evaluation unit 50 may further evaluate the occurrence frequencies of two or more among the 16 levels of reliability and perform a composite evaluation. For example, the distribution evaluation unit 50 can also perform a composite evaluation using the occurrence frequency of low values of reliability from 0 to 1, the occurrence frequency of reliability from 2 to 3, the occurrence frequency of reliability from 4 to 5, and the like.

[0049] As described above, according to the present embodiment, in the error correction decoding circuit 1, the data position search unit 3 changes the number of times of repeating the sort, the number of data positions with low reliability searched in each sort, etc., according to the state of the reliability data acquired from the soft decision processing unit 2. As a result, the data position search unit 3 can perform processing corresponding to changes in the noise distribution.

[0050] Embodiment 3. As described above, in the configuration of the data location search unit 3 described in Embodiment 1, if there are T2 or more low-confidence data locations to be searched within the group sorted in the first stage due to burst errors, it may affect the error correction performance. On the other hand, in order to achieve high error correction performance that cannot be achieved with BCH codes alone, a high-performance FEC such as OFEC using BCH codes as element codes has been proposed in Non-Patent Literature 1. Embodiment 3 describes a case in which the burst error resistance in data location search by the data location search unit 3 described in Embodiment 1 is improved by using such a high-performance error correction code configured with BCH codes as element codes.

[0051] Figure 12 shows an example of a BCH code that constitutes a high-performance FEC targeted by the error correction decoding circuit 1 according to Embodiment 3. A BCH code consists of information bits and parity bits calculated based on the information bits. As shown in Figure 12, half of the BCH code uses data that has already been encoded with another code sequence. In Embodiment 3, the parity bits are calculated using information bits obtained by adding new data to this half of the BCH code data. The BCH code shown in Figure 12 will be generated by a transmitting device not shown. In the aforementioned OFEC, an extended BCH (256, 239) is used as the element code, but for a 111-bit input, 256 bits are used as a single BCH code by adding 128 bits that have already been encoded with another code sequence to make a total of 239 bits, and then calculating a 17-bit parity.

[0052] Figure 13 shows an example of the configuration of the data position search unit 3 included in the error correction decoding circuit 1 according to Embodiment 3. Although not shown in the figure, in Embodiment 3, the configuration of the error correction decoding circuit 1 is the same as the configuration of the error correction decoding circuit 1 in Embodiment 1 shown in Figure 1. The data position search unit 3 includes a group division unit 60 and a sorting processing unit 61. The sorting processing unit 61 includes a plurality of sorting units 62 and a sorting unit 63. Although the description is simplified in Figure 13, the seven sorting units below the sorting unit 62 shown in Figure 13 are also referred to as sorting units 62. That is, the sorting processing unit 61 includes eight sorting units 62 as a plurality of sorting units 62. In Figure 13, as with Embodiment 1, the case in which the data position search unit 3 searches for T1 = 8 data positions as the number of low-reliability data positions from reliability data corresponding to a received signal of a code sequence with code length N = 256 will be described as an example.

[0053] In Embodiment 3, the group division unit 60 obtains confidence data, which is a multi-level representation of confidence, from the soft judgment processing unit 2. The group division unit 60 divides the confidence data corresponding to the received signal of a code sequence with code length N = 256 into eight groups of 32 data units, which correspond to the confidence data corresponding to the received signal of a code sequence with code length N = 32, and outputs them to the subsequent sorting unit 62. The operation of the eight sorting units 62 and sorting unit 63 is the same as the operation of the eight sorting units 32 and sorting unit 33 in Embodiment 1 shown in Figure 2.

[0054] Figure 14 shows the details of the group division process performed by the group division unit 60 of the data position search unit 3 in the error correction decoding circuit 1 according to Embodiment 3. Although the description in Figure 14 is simplified, the group division unit 60 outputs confidence data to the eight connected sort units 62 using the same process.

[0055] When the group division unit 60 outputs 32 bits of confidence data to one sort unit 62 corresponding to one group, it selects half of the 16 bits of confidence data from the confidence data corresponding to the first half A region of the BCH code shown in Figure 12, and selects the remaining 16 bits of confidence data from the confidence data corresponding to the second half B region of the BCH code. The group division unit 60 selects and outputs confidence data in the same manner for eight sort units 62. When considering the decoding process, the BCH code that constitutes a high-performance FEC, due to its structure, undergoes decoding processing once for the first half A region compared to the second half B region. That is, the first half A region has a higher confidence level compared to the second half B region. Therefore, by selecting and combining confidence data corresponding to the first half A region and the second half B region of the BCH code to form a group for the first sorting stage, the group division unit 60 can reduce the possibility of low-confidence data locations being concentrated in one group and improve burst error tolerance.

[0056] In the data location search unit 3, the group division unit 60 selected the same number of data points from both the first half (A) region and the second half (B) region of the BCH code, but is not limited to this. The group division unit 60 may ultimately search the data location search unit 3 for T1 = 8 data points with low confidence levels, and the number of confidence points selected from the confidence data corresponding to the first half (A) region and the number of confidence points selected from the confidence data corresponding to the second half (B) region of the BCH code may differ depending on the group.

[0057] Thus, in Embodiment 3, the received signal is an encoded code sequence composed of information bits and parity bits calculated from the information bits, and half of the information bits corresponding to the code sequence are bits encoded with another code sequence. In this case, the group division unit 60 divides the confidence data into multiple groups such that each group includes confidence data corresponding to the bits encoded with the other code sequence, and confidence data corresponding to additional bits or parity bits that do not correspond to the bits encoded with the other code sequence among the information bits.

[0058] As described above, according to this embodiment, in the error correction decoding circuit 1, when a high-performance error correction code configured with BCH codes as element codes is used, the data position search unit 3 selects the reliability data from the acquired reliability data, from the portion corresponding to the region encoded with another code sequence (region A shown in Figure 12) and the portion corresponding to the newly added data or parity bit region (region B shown in Figure 12) that is not encoded with another code sequence, and divides the reliability data into groups. As a result, the error correction decoding circuit 1 can reduce the possibility of low-reliability data positions being clustered in one group and improve burst error tolerance.

[0059] Although the case of applying Embodiment 3 to Embodiment 1 has been described, the invention is not limited thereto. Embodiment 3 can also be applied to Embodiment 2. For example, the distribution evaluation unit 50 may evaluate the distribution of confidence levels in each group after the group division unit 60 has performed group division in the manner described in Embodiment 3. In this case, the sort control unit 51 performs the sort processing unit 41 control as described in Embodiment 2 based on the evaluation result of the distribution evaluation unit 50.

[0060] Embodiment 4. Embodiment 4 describes a case in which burst error tolerance is improved using a high-performance error correction code configured with BCH codes as element codes, similar to Embodiment 3, while maintaining the same data position search unit 3 configuration as in Embodiment 1. Embodiment 4 is applicable to Embodiments 1 to 3, but Embodiment 3 will be used as an example for explanation.

[0061] In high-performance error correction codes that use BCH codes as element codes, high error correction performance is generally achieved by repeatedly performing decoding and updating the reliability based on the obtained decoding results. As mentioned above, in the configuration of the data position search unit 3 of Embodiment 1, if there are T2 or more low-reliability data positions that should be searched in the group sorted to the first stage due to burst errors, the data positions that should be searched may not be searched, and the error correction performance may deteriorate.

[0062] Therefore, in Embodiment 4, the data position search unit 3 changes the components of the group sorted in the first stage with each iteration of the decoding process. This allows the error correction decoding circuit 1 to reduce the possibility of low-reliability data being aggregated and to improve burst error tolerance.

[0063] Thus, in Embodiment 4, the received signal is an encoded code sequence composed of information bits and parity bits calculated from the information bits, and half of the information bits corresponding to the code sequence are bits encoded with another code sequence. In this case, the group division unit 60 changes the combination of bits included in each group each time the error correction decoding process is performed repeatedly by the error correction decoding circuit 1. For example, in the example of Embodiment 3, the group division unit 60 can change the combination of bits included in each group by not changing the method of selecting bits from area A shown in Figure 12 for a predetermined number of times during the repeated decoding process, and changing the method of selecting bits from area B shown in Figure 12 each time.

[0064] Although Embodiments 1 to 4 have all been described using a binary BCH code as an example, other codes such as Reed-Solomon codes may be used as long as they employ chase decoding.

[0065] The configurations shown in the above embodiments are merely examples, and it is possible to combine them with other known technologies, combine different embodiments, and omit or modify parts of the configuration without departing from the gist of the invention.

[0066] 1 Error correction decoding circuit, 2 Soft judgment processing unit, 3 Data position search unit, 4 Hard judgment processing unit, 5 Test pattern generation unit, 6 Hard judgment decoding unit, 7 Decoding result selection processing unit, 30, 34, 40, 60 Group division unit, 31, 35, 41, 61 Sorting processing unit, 32, 33, 36, 37, 38, 42, 44, 45, 47, 62, 63 Sorting unit, 43, 46, 48 Synthesis unit, 50 Distribution evaluation unit, 51 Sorting control unit, 90, 93 Processing circuit, 91 Processor, 92 Memory.

Claims

1. An error correction decoding circuit that performs soft-decision error correction decoding using a chase decoding algorithm, comprising: a group division unit that acquires reliability data indicating the reliability of data reconstructed from a received signal by a hard-decision process and the reliability obtained in the soft-decision process, and divides the reliability data into a plurality of groups; a sorting unit that performs a first sort on the reliability data included in each group, extracting data positions indicating the position of the data in the received signal corresponding to a second number of reliability data, up to a first number, starting from the lowest reliability; and a sorting unit that performs one or more sorts, including a second sort, from the data positions extracted from each group in the first sort until the data positions corresponding to the first number of reliability data, starting from the lowest reliability, are extracted, thereby extracting the first number of data positions.

2. The error correction decoding circuit according to claim 1, wherein the received signal is an encoded code sequence composed of information bits and parity bits calculated from the information bits, and half of the information bits corresponding to the code sequence are bits encoded with another code sequence, and the group division unit divides the reliability data into a plurality of groups such that each group includes reliability data corresponding to the bits encoded with the other code sequence, and reliability data corresponding to additional bits that do not correspond to the bits encoded with the other code sequence or the parity bits among the information bits.

3. The error correction decoding circuit according to claim 1 or 2, characterized in that the received signal is an encoded code sequence composed of information bits and parity bits calculated from the information bits, and half of the information bits corresponding to the code sequence are bits encoded with another code sequence, and the group division unit changes the combination of bits included in each group each time the decoding process is performed repeatedly by the error correction decoding circuit.

4. An error correction decoding circuit according to any one of claims 1 to 3, comprising: a distribution evaluation unit that evaluates the distribution of confidence in the confidence data; and a sort control unit that controls the operation of the sort processing unit based on the evaluation result of the distribution evaluation unit, wherein the sort processing unit, based on the control of the sort control unit, performs sorting so that, if a bias in confidence is expected in the confidence data included in each group, the data positions corresponding to the first number of confidence data are extracted from the lowest confidence level; and if no bias in confidence is expected in the confidence data included in each group, performs processing to reduce the amount of data of the target confidence data at any sorting stage or between sorts.

5. A control circuit for controlling an error correction decoding circuit that performs soft-decision error correction decoding using a chase decoding algorithm, characterized in that the error correction decoding circuit is made to perform the following: acquire confidence data indicating the confidence of data regenerated from a received signal by a hard-decision process and the confidence obtained in the soft-decision process; divide the confidence data into a plurality of groups; perform a first sort on the confidence data contained in each group, extracting data positions indicating the position of the data in the received signal corresponding to a second number of confidence data, up to a first number, starting from the lowest confidence level; and further perform one or more sorts, including a second sort, from the data positions extracted from each group in the first sort until the data positions corresponding to the first number of confidence data, starting from the lowest confidence level, are extracted, thereby extracting the first number of data positions.

6. A storage medium storing a program for controlling an error correction decoding circuit that performs soft-decision error correction decoding using a chase decoding algorithm, wherein the program is characterized by causing the error correction decoding circuit to perform the following: acquire reliability data indicating the reliability of data regenerated from a received signal by a hard-decision process and the reliability obtained in the soft-decision process; divide the reliability data into a plurality of groups; perform a first sort on the reliability data contained in each group, extracting data positions indicating the position of the data in the received signal corresponding to a second number of reliability data, starting from the lowest reliability, up to a first number; and further perform one or more sorts, including a second sort, from the data positions extracted from each group in the first sort until the data positions corresponding to the first number of reliability data, starting from the lowest reliability, are extracted, thereby extracting the first number of data positions.

7. An error correction decoding method for an error correction decoding circuit that performs soft judgment error correction decoding using a chase decoding algorithm, comprising: a group division step in which a group division unit acquires confidence data indicating the confidence level of data regenerated from a received signal by a hard judgment process and obtained in a soft judgment process, and divides the confidence data into a plurality of groups; and a sorting processing step in which a sorting processing unit performs a first sort in each group, targeting the confidence data included in each group, and extracts data positions indicating the position of the data in the received signal corresponding to a second number of confidence data, starting from the lowest confidence level, starting from a first number; and further performs one or more sorts, including a second sort, from the data positions extracted from each group in the first sort until the data positions corresponding to the first number of confidence data, starting from the lowest confidence level, are extracted, thereby extracting the first number of data positions.

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