Symbol selection method, and data communication system using symbol selected using same

Abstract

This data communication system comprises: a link unit including a plurality of transmission lines; a first communication unit connected to one side of the link unit so as to transmit / receive a PAM signal; and a second communication unit connected to the other side of the link unit so as to transmit / receive a PAM signal, wherein the number of PAM signal levels for driving the transmission lines is greater than or equal to the number of transmission lines, the sum of the respective PAM values of the transmission lines is "0", and the PAM value of each transmission line driven at the same time is defined as a symbol according to a relationship determined by assigning signal pairs having different signal levels to the vertices and the line segments of an inference graph using graph coloring theory, and each of the first communication unit and the second communication unit encodes and transmits transmission data to correspond a corresponding symbol, and decodes and restores received data.

Description

Symbol selection method and data communication system using the selected symbol The present invention relates to a symbol selection method and a data communication system using the selected symbol. More specifically, it relates to a symbol selection method for selecting symbols that are pairs of Pulse Amplitude Modulation (PAM) signals to be represented as electrical signals on each transmission line by utilizing the principles of a graph coloring algorithm, and a data communication system using the selected symbol. The primary issue with high-speed wired communication is the parasitic capacitance existing between the transmission line and the ground signal, as well as the matching capacitance between the transmission lines. While the inductance and resistance components of the transmission line also have an impact, advancements in ultra-high-speed transmission line manufacturing technology have made these factors relatively negligible. Since signals are transmitted using voltage variations on high-speed transmission lines, the capacitance of the line increases the time constant and capacitive load, posing significant difficulties for high-speed data transmission or data communication over long distances. Generally, if Vpp is defined as the signal voltage containing pulse period or phase information, the capacitance of the transmission line is a factor that interferes with communication by causing effects such as signal distortion, attenuation, and phase delay. High-speed serial communication techniques over wires known to date (MIPI, LVDS, USB 2.0, USB 3.0, SATA, etc.) have increased their speed by reducing the amplitude of the signal voltage to reduce the influence of capacitive loads and enabling high-speed serial signal transmission. The current value (i) required for signal transmission can be defined by i = C × (dv / dt). That is, as the frequency component dv / dt (the amount of voltage variation over time) increases, the amount of current (i) required for signal transmission increases even though the value of C, which is the same capacitive load, is constant. In addition, the impedance on the signal transmission line also acts as a resistor, increasing the time constant and hindering high-speed signal transmission. Meanwhile, the volume of computing and transmitted data is increasing significantly due to the emergence of big data applications such as artificial intelligence (AI), virtual reality, and media streaming. The energy cost of DRAM access in computing systems is rising as system performance becomes more advanced. [Prior Art Literature] [Patent Literature] (Patent Document 0001) Republic of Korea Registered Patent No. 10-2543177 (Published June 14, 2023) (Title of Invention: High-bandwidth memory device and system device including the device) (Patent Document 0002) Republic of Korea Registered Patent No. 10-0817031 (Published on March 20, 2008) (Title of Invention: Single-wire Serial Communication Module) (Patent Document 0003) Republic of Korea Published Patent No. 2017-0024223 (Published on Mar. 07, 2017) (Title of Invention: Device including a single-wire interface and data processing system including the same) Accordingly, the technical problem of the present invention is based on this point, and the objective of the present invention is to provide a symbol selection method for selecting symbols, which are pairs of PAM signals to be represented as electrical signals on each transmission line, by utilizing the principle of a graph coloring algorithm in parallel data communication using Pulse Amplitude Modulation (PAM) signals. Another objective of the present invention is to provide a data communication system capable of ultra-high-speed parallel data transmission with stable data transmission / reception and a high data transmission rate using a symbol selected through the symbol selection method described above. To realize the objective of the present invention as described above, a symbol selection method according to one embodiment comprises the step of inputting a first condition, a second condition, a third condition, and a fourth condition to be verified in a program provided for selecting a symbol, wherein the first condition is a condition in which the sum of difference values ​​based on the common voltage of all transmission lines is 0V, the second condition is a condition in which adjacent transmission lines have different signal levels, the third condition is a condition in which elements have different differential signals converted into differential signals through signal level comparison between adjacent transmission lines, and the fourth condition is a condition in which elements have different differential signals converted into differential signals through signal level comparison between non-adjacent transmission lines; the step of inputting the number of transmission lines and the number of signal levels and determining the type of signal level; the step of initializing a candidate list and a result list; and the step of inputting all possible cases that may occur in the transmission lines into the candidate list, considering the input number of transmission lines, the number of signal levels, and the type of signal level. The method includes: a step of extracting one element from the above candidate list; a step of inputting the extracted element into a result list and feeding back to the step of extracting one element if the extracted element is checked to satisfy the above first condition; a step of inputting the extracted element into a result list and feeding back to the step of extracting one element if the extracted element is checked to satisfy the above second condition; a step of inputting the extracted element into a result list and feeding back to the step of extracting one element if the extracted element is checked to satisfy the above third condition; a step of inputting the extracted element into a result list and feeding back to the step of extracting one element if the extracted element is checked to satisfy the above fourth condition; and a step of outputting a result list if it is checked that there are no remaining elements in the above candidate list. In one embodiment, the element may refer to each of the cases according to the number of transmission lines and the number of signal levels. To realize another objective of the present invention as described above, a data communication system according to one embodiment comprises: a link unit including a plurality of transmission lines; a first communication unit connected to one side of the link unit and performing transmission and reception of a Pulse Amplitude Modulation (PAM) signal; and a second communication unit connected to the other side of the link unit and performing transmission and reception of a PAM signal, wherein the number of PAM signal levels driving the transmission lines is greater than or equal to the number of transmission lines, the sum of the PAM values ​​of each transmission line is "0", and signal pairs having different signal levels of PAM values ​​of each transmission line driven simultaneously are assigned to vertices and line segments of a graph shape for inference using graph coloring theory and defined as symbols according to a determined relationship, and each of the first communication unit and the second communication unit encodes the transmitted data to match the corresponding symbol and transmits it, and decodes the received data and restores it. In one embodiment, each of the first communication unit and the second communication unit may include one or more DRV blocks that convert a TX signal of a voltage level input from the outside into current and output it to a transmission line through an I / O pad, and one or more RCV blocks that receive a PAM signal transmitted through the link unit; a PHY unit that transmits / receives the PAM signal with one side connected to one side of the link unit; and an encoding / decoding unit that transmits / receives the PAM signal with one side connected to the other side of the PHY unit. In one embodiment, the DRV block may include: a first TX buffer that buffers a first TX signal; a first TX resistor, one end of which is connected to the output terminal of the first TX buffer and the other end of which is connected to an I / O pad; a second TX buffer that buffers a second TX signal; and a second TX resistor, one end of which is connected to the output terminal of the second TX buffer and the other end of which is connected to the I / O pad. In one embodiment, the DRV block may include: a PAM encoding unit that encodes a TX signal according to a TX enable signal; a first buffer comprising a front inverter that is enabled by the TX enable signal and inverts the TX signal, and a rear inverter connected to the rear end of the front inverter and enabled by the TX enable signal and inverts the signal inverted by the front inverter; and a voltage-to-current converter that converts the PAM signal buffered by the first buffer into a current. In one embodiment, the DRV block may include: a first TX buffer for buffering a first TX signal; a first TX resistor, one end of which is connected to the output terminal of the first TX buffer; a second TX buffer for buffering a second TX signal; a second TX resistor, one end of which is connected to the output terminal of the second TX buffer; and a current conveyor including an X-port connected to the common terminal of the first TX resistor and the second TX resistor, a Y-port to which a common mode voltage on a transmission line is applied, and a ZP-port connected to an I / O pad. In one embodiment, the DRV block may include: a first TX buffer for buffering a first TX signal; a first TX resistor, one end of which is connected to the output terminal of the first TX buffer; a second TX buffer for buffering a second TX signal; a second TX resistor, one end of which is connected to the output terminal of the second TX buffer; a current conveyor including an X-port connected to the common terminal of the first TX resistor and the second TX resistor, a Y-port to which a common mode voltage on a transmission line is applied, and a ZP-port connected to an I / O pad; and a pre-emphasis circuit that is enabled by a TX enable signal to buffer a pre-emphasis signal, a variable resistor, and a variable capacitor, and temporarily increases or decreases the strength of the TX signal of the TX signal applied to the X-port of the current conveyor. In one embodiment, the RCV block may include a voltage generation unit that includes a plurality of RC parallel circuits and converts the current of a PAM signal provided through the transmission line into a voltage; and a voltage comparator module that includes a plurality of differential voltage comparators and differentially compares the PAM signals converted into voltage by the voltage generation unit. In one embodiment, in each of the RC parallel circuits, the R value is the value of the intended circuit component between 10Ω and 300Ω, and the C value may be the value of an unintended parasitic capacitance component or an intended capacitance component. In one embodiment, each of the differential voltage comparators may include differential voltage comparators that receive a current bias and detect the difference in the input voltage of the gate. In one embodiment, the RCV block may include a voltage generation unit that converts the current of a PAM signal provided through the transmission line into a voltage, comprising a plurality of current conveyors and a plurality of RC parallel circuits disposed at the output end of the current conveyor; and a voltage comparator module that includes a plurality of differential voltage comparators and differentially compares the PAM signals converted into voltage by the voltage generation unit. In one embodiment, the voltage comparator module may include: a first differential voltage comparator that outputs a first differential voltage obtained by differentially comparing a first voltage and a second voltage provided from the voltage generation unit; a second differential voltage comparator that outputs a second differential voltage obtained by comparing the second voltage and a third voltage provided from the voltage generation unit; a third differential voltage comparator that outputs a third differential voltage obtained by comparing the third voltage and a fourth voltage provided from the voltage generation unit; a fourth differential voltage comparator that outputs a fourth differential voltage obtained by comparing the first voltage and the fourth voltage provided from the voltage generation unit; a fifth differential voltage comparator that outputs a fifth differential voltage obtained by comparing the first voltage and the third voltage provided from the voltage generation unit; and a sixth differential voltage comparator that outputs a sixth differential voltage obtained by comparing the second voltage and the fourth voltage provided from the voltage generation unit. In one embodiment, the first to sixth differential voltage comparators may operate in response to a clock. In one embodiment, each of the first to sixth differential voltage comparators may include a differential ARM (Analog Re-generative Memory) latch voltage comparator that detects a difference in the input voltage of a gate using a comparison clock. In one embodiment, the differential ARM (Analog Re-generative Memory) latch voltage comparator may include: a differential voltage comparator that determines an output signal by comparing two input signals, amplifying the difference between VIN(+) and VIN(-), and determining the output signal based on the amplified difference; and an SR-latch that stores the output state of the differential voltage comparator and maintains it for a certain period of time. In one embodiment, the RCV block may include a voltage generation unit that converts the current of a PAM signal provided through the transmission line into a voltage, comprising a plurality of current conveyors and a plurality of R circuits disposed at the output end of the current conveyor; and a voltage comparator module that includes a plurality of differential voltage comparators and differentially compares the PAM signals converted into voltage by the voltage generation unit. In one embodiment, the voltage generating unit may further include a variable resistor, one end of which is connected to the transmission line and the other end of which is connected to the current conveyor. In one embodiment, each of the first communication unit and the second communication unit may further include a pre-encoder, one side of which is connected to the other side of the encoding / decoding unit, and which receives data to be transmitted from a processor unit or memory device during signal transmission and performs pre-encoding processing. In one embodiment, each of the first communication unit and the second communication unit may further include a post decoder, one side of which is connected to the other side of the encoding / decoding unit, which processes post-decoding of the received data upon data reception. According to this symbol selection method and a data communication system utilizing the selected symbols, by utilizing the principles of a graph coloring algorithm in parallel data communication using Pulse Amplitude Modulation (PAM) signals to select symbols that are pairs of PAM signals to be represented as electrical signals on each transmission line, generating data to be transmitted on the transmission line using the selected symbols, and recovering the original data from the transmitted signal during data reception, it is possible to realize ultra-high-speed parallel data transmission with stable data transmission / reception and a high data transmission rate. FIG. 1 is a block diagram schematically illustrating a data communication system according to the present invention. Figure 2 is a diagram illustrating a graph shape for inference using graph coloring theory when there are three transmission lines constituting a link unit. Figure 3 is a diagram illustrating a graph shape for inference using graph coloring theory when there are 4 transmission lines constituting a link unit. Figure 4 is a diagram illustrating a graph shape for inference using graph coloring theory when there are 5 transmission lines constituting a link unit. Figure 5 is a diagram illustrating a graph shape for inference using graph coloring theory when there are 6 transmission lines constituting a link unit. Figure 6 is a diagram illustrating a graph shape for inference using graph coloring theory when there are 6 transmission lines constituting a link unit. FIGS. 7a and FIGS. 7b are flowcharts for explaining symbol selection according to the present invention. Figure 8 is an electrical equivalent modeling circuit for one transmission line shown in Figure 1. FIG. 9 is a circuit symbol for explaining a link unit composed of four transmission lines as illustrated in FIG. 8. FIG. 10 is a diagram illustrating the concept of n link units forming a link as illustrated in FIG. 9. FIG. 11 is a block diagram illustrating a data communication system according to an embodiment of the present invention. FIG. 12 is a drawing for explaining the first PHY unit, link unit, and second PHY unit illustrated in FIG. 11. FIG. 13 is a circuit diagram illustrating an example of the DRV block shown in FIG. 12. FIG. 14 is a circuit diagram illustrating another example of the DRV block shown in FIG. 12. FIG. 15 is a circuit diagram illustrating another example of the DRV block shown in FIG. 12. FIG. 16 is a circuit diagram illustrating an example of a current conveyor shown in FIG. 15. FIG. 17 is a circuit diagram illustrating an example of the RCV block shown in FIG. 12. FIG. 18 is a circuit diagram illustrating another example of the RCV block shown in FIG. 12. FIG. 19 is a circuit diagram for explaining an example of a voltage comparator shown in FIG. 17 or FIG. 18. FIG. 20 is a circuit diagram for explaining the first differential voltage comparator of the voltage comparator module shown in FIG. 19. FIG. 21 is a circuit diagram for explaining an example of a voltage comparator module shown in FIG. 17 or FIG. 18. FIG. 22 is a circuit diagram for explaining the first differential voltage comparator of the voltage comparator module shown in FIG. 21. FIG. 23 is a circuit diagram illustrating another example of the DRV block shown in FIG. 12. FIG. 24 is a circuit diagram illustrating another example of the current conveyor shown in FIG. 15. FIG. 25 is a circuit diagram illustrating an example of a voltage generation unit illustrated in FIG. 17. FIG. 26 is a circuit diagram illustrating another example of the voltage generation unit shown in FIG. 17. FIG. 27 is a circuit diagram illustrating another example of the RCV block shown in FIG. 12. FIG. 28 is a circuit diagram illustrating another example of the RCV block shown in FIG. 12. FIGS. 29a, FIGS. 29b, and FIGS. 29c are graphs showing the signal amplitude according to the output impedance of the X-port of the RCV block shown in FIG. 28. FIGS. 30a and FIGS. 30b are circuit diagrams for explaining other examples of the current comparator module shown in FIG. 17 or FIG. 18. FIG. 31 is a circuit diagram for explaining the first differential current comparator of the current comparator module shown in FIG. 27 or FIG. 30. FIG. 32 is a circuit diagram for explaining the first differential current comparator of the current comparator module shown in FIG. 27 or FIG. 30. FIG. 33 illustrates an eye-diagram of a PAM4 signal received from a PAM4 signal basic communication system according to a comparative example. FIG. 34 illustrates an eye-diagram of a PAM4 signal received from a PAM4 signal basic communication system according to the present invention. FIG. 35 is a block diagram illustrating the first encoding / decoding unit illustrated in FIG. 11. FIG. 36 is a diagram for explaining symbol restoration by the first communication unit or the second communication unit shown in FIG. 11. Hereinafter, the present invention will be described in more detail with reference to the attached drawings. Since the present invention is susceptible to various modifications and may take various forms, specific embodiments are illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed forms, and it should be understood that it includes all modifications, equivalents, and substitutions that fall within the spirit and scope of the present invention. In describing each drawing, similar reference numerals have been used for similar components. In the attached drawings, the dimensions of the structures are depicted enlarged compared to their actual size to ensure clarity of the invention. Terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. A singular expression includes a plural expression unless the context clearly indicates otherwise. In this application, terms such as "comprising" or "having" are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof. Furthermore, unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in this application. First, the terms described in this specification are defined as follows. A "Processor Unit" is an IC that performs logical operations for AI processors, GPUs, CPUs, SoCs, etc. A "processor module" is a board or assembly composed of HBM (High Bandwidth Memory) and processor units. "DDR RAM" includes DDR4, DDR5, DDR6, GDDR5, GDDR6, etc. "TSV-link" is a signal transmission wiring (transmission line) connected by Through Silicon Via (TSV) between DRAM dies and interface dies inside HBM. "T-Link" is a signal transmission wiring (transmission line) connected between the processor unit and HBM via a silicon interposer or PCB. The "Physical Layer (PHY)" is the layer that transmits and receives data in individual bit units as electrical signals, and is the layer that transmits and receives electrical signals to and from actual transmission lines. This invention relates to the configuration of a PHY unit and to encoders / decoders for transmitting and receiving data through the PHY unit. A "link unit" is defined by multiple transmission lines. A "communication link" is defined by multiple link units. A unit of a transmission line (e.g., a link unit, a T-link unit, a TSV-link unit) refers to a minimum communication unit composed of a PAM signal and consists of 3, 4, 5, etc. of transmission lines. The link units are expanded to form a number N to form a communication link. The communication link may be composed of a T-link, a TSV-link, a PCB pattern, a wire, etc., as a signal transmission medium. "Communication system" means a bidirectional communication system implemented with a first communication module (or first communication unit), a bundle of transmission lines (or link units), and a second communication module (or second communication unit). "Communication system module" means that it is configured to have at least two communication systems and has a number of transmission lines that are integer multiples of 4 (4 × N), such as 8, 16, 32, 64, 128, 256, 1024, 2048, etc., and the number of communication systems is matched accordingly. "Communication subject" refers to a semiconductor system that governs one side or the other in a communication system or communication system module composed of one or more, and acts as a host and device, or server and client, where data transmission (i.e., transmission and reception) takes place. In this embodiment, the communication subject may refer to the memory device and the processor unit in a structure where the memory device and the processor unit are connected. Alternatively, the communication subject may refer to the processor units on both sides in a structure where the processor units are connected. "NRZ (Non-Return-to-Zero) signal" refers to a signal modulation method in which data 1-bit is converted (mapped) into electrical signals of two different amplitudes corresponding to the meanings of "0" and "1". For example, if the NRZ signal value corresponding to the 1-bit value is 0V or 1V, it is a method of simply converting bit value 0 into 0V and bit value 1 into 1V signals. A "Pulse Amplitude Modulation (PAM) signal" refers to a method that applies encoding / decoding technology to convert two or more bits into electrical signals with at least three amplitudes corresponding to their meaning. For example, PAM4 utilizes four signal levels per transmission line; it represents 2-bit data (00, 01, 10, 11) by encoding it into relative voltages such as (-3, -1, +1, +3), thereby expressing the value over a single transmission line. Since PAM4 can transmit 2-bit data using a single transmission line, it can transmit twice the amount of data compared to the NRZ method based on the same transmission line. Generally, PAM has disadvantages compared to NRZ, such as higher power consumption, a lower Signal-to-Noise Ratio (SNR), and a higher Error Rate (BER). However, PAM is commonly used for high-speed data transmission through the application of sophisticated signal processing and error correction technologies. "PAM4" is a signal modulation technique that uses four different signal levels for high-speed signal transmission. A PAM4 signal has two more levels than a comparative example NRZ signal, which uses high and low signal levels to represent the 1 and 0 of a digital logic signal. An NRZ signal can only transmit 1 bit of information per symbol period of the signal. In contrast, since a PAM4 signal transmits the signal using four different signal levels, such as (00, 01, 10, 11), it can transmit 2 bits of logic information per symbol period of the signal. Therefore, compared to NRZ, PAM4 has the advantage of doubling the bit transmission rate for a given baud rate. The "Bit Error Ratio (BER)" is an indicator that can evaluate the extent to which a digital signal is affected by changes in analog characteristics, such as noise and distortion, occurring in digital communication, and typically refers to the ratio of the number of error bits to the total number of bits transmitted. A "symbol" is the basic unit of transmission used to transmit digital data in a communication system. A symbol is a unit of signal represented by a specific state, waveform, frequency, phase, amplitude, etc., of a transmission line. A symbol can represent the meaning of one bit or multiple bits at a time. For example, in the case of PAM2, 1 bit is transmitted using 2 symbols (0 and 1, respectively). In the case of PAM4, 2 bits are transmitted using 4 symbols (00, 01, 10, 11, respectively). In the case of PAM8, 3 bits are transmitted using 8 symbols (000, 001, 010, 011, 100, 101, 110, 111, respectively). "Encoding" is the process of converting data to be transmitted into specific signal symbols that have the physical meaning of electrical signals. "Decoding" is the process of recovering data from symbols that have the physical meaning of a received electrical signal. "Graph coloring theory" is a method in graph theory for assigning colors to vertices of a graph such that no two adjacent vertices have the same color. This can be used to define invariants of a graph. FIG. 1 is a block diagram schematically illustrating a data communication system according to the present invention. Referring to FIG. 1, a data communication system according to one embodiment of the present invention comprises a transmission line (10), a first process unit (21) disposed on one side of the transmission line (10), a first encoder / decoder (22) connected to the output terminal of the first process unit (21), a first transmit / receive buffer (23) connected to the output terminal of the first encoder / decoder (22) and one side of the transmission line (10), a second transmit / receive buffer (31) connected to the other side of the transmission line (10), a second encoder / decoder (32) connected to the output terminal of the second transmit / receive buffer (31), and a second process unit (33) connected to the output terminal of the second encoder / decoder (32). In this embodiment, the first process unit (21), the first encoder / decoder (22), and the first transmit / receive buffer (203) can define the first chiplet, and the second transmit / receive buffer (31), the second encoder / decoder (32), and the second process unit (33) can define the second chiplet. Here, the first chiplet and the second chiplet refer to a complete chip formed by combining modularized components in a semiconductor design. While traditional methods focused on designing a single large chip, chiplet technology is a method of combining multiple small chips (chiplets) to form a single system. Integration performance between chiplets can be improved by utilizing 2.5D and 3D packaging technologies. In other words, the chiplet system was developed to overcome the limitations of conventional monolithic chips; the dies within the package can be connected via a silicon interposer, and the chiplets within the chiplet system can communicate with each other according to die-to-die communication standards such as UCIe (Universal Chiplet Interconnect Express). The present invention can simplify the circuit configuration by encoding / decoding parallel data and transmitting / receiving using the determined symbol as the data transmission unit, without using a serializer / deserializer (hereinafter SerDes) and a PLL. In addition, the present invention can improve the BER value by determining the received value by comparing the difference values ​​between transmission lines, and also minimize the silicon area and the energy consumption required for data transmission by minimizing the number of comparators. In addition, since the present invention uses a method of immediately converting parallel data into symbols through a parallel transmission line without overhead or data conversion between parallel and serial, it does not use flip-flops for temporary data storage used in the data conversion process for separate SerDes, and there is no time latency associated with the SerDes process. Table 1 shows examples of some codes for 8B10B code conversion. [Table 1] Referring to Table 1, the technology for converting 8-bit parallel data into 10-bit serial data is used to implement reliable data transmission in high-speed data communication technologies such as USB 3.0, 1Gbit LAN, and PCI-Express (PCIe). USB 3.0 uses a serial data transmission method for high-speed data transmission. USB 3.0 can transmit data at SuperSpeed ​​(5Gbps) and safely transmits data using methods such as 8b / 10b encoding. 1Gbit LAN is a standard for transmitting data at high speed over a network, and it transmits data by placing it in Ethernet frames. PCIe is an interface that transfers data between various devices (e.g., graphics cards, network cards, etc.) within a computer. PCIe maximizes data transfer speed and efficiency by using a serial data transfer method. Data transfer is performed through 8b / 10b encoding on each channel. The present invention can solve various problems that occur in systems where the speed of parallel data generated by the system is faster than the signal transmission speed that can be implemented in transmission lines between systems (e.g., TSV-link, T-link) due to advancements in semiconductor manufacturing and design technologies. To this end, at least three transmission lines are combined into a single link unit, and the number of link units is expanded to match the size of the data that needs to be transmitted simultaneously, thereby operating in a form that configures a T-link or TSV-link. For example, if three transmission lines are bundled to form a link unit, the number of transmission lines required for the link is 3 × N, where N is an integer. As another example, if four transmission lines are bundled to form a link unit, the number of transmission lines required for the link is 4 × N. In this way, link units can be implemented by bundling five or more transmission lines as needed. If 64 transmission lines are assigned to a link, 16 link units consisting of four transmission lines each (i.e., 64 / 4 = 16) are used. The individual transmission lines constituting each link unit (i.e., a bundle of transmission lines) use PAM signals. Typically, signal levels (signal values) such as PAM3, PAM4, PAM5, PAM6, and PAM7 are configured. Since the interface voltage or current used in the transmission lines can be implemented in various forms depending on the application, PAM signal levels are defined as relative values ​​as shown in Table 2 below. [Table 2] Referring to Table 2, the PAM3 signal has three signal levels, such as (-1, 0, +1). The PAM4 signal has four signal levels, such as (-3, -1, +1, +3). The PAM5 signal has five signal levels, such as (-2, -1, 0, +1, +2). The PAM6 signal has six signal levels, such as (-5, -3, -1, +1, +3, +5). The PAM7 signal has seven signal levels, such as (-3, -2, -1, 0, +1, +2, +3). Using the number of transmission lines M constituting the link unit and the number of PAM signal levels N, the number of symbols, which are the types of signals that can be represented by a single link unit is. Here, M and N can be expanded to 3, 4, 5, 6, 7, etc., respectively, as needed. The number of PAM signal levels can be defined to be equal to or greater than the number of transmission lines. For example, if the number of PAM signal levels is 3, PAM3 is defined, and PAM3 has 3 signal levels such as (-1, 0, +1). If the number of PAM signal levels is 4, PAM4 is defined, and PAM4 has 4 signal levels such as (-3, -1, +1, +3). If the number of PAM signal levels is 5, PAM5 is defined, and PAM5 has 5 signal levels such as (-2, -1, 0, +1, +2). However, it is desirable that the optimal number for BER improvement is equal to the number of PAM signal levels and the number of transmission lines. The following describes the process of defining the number and form of symbols to be used in the present invention. The above Among the symbols with all possible combinations generated by the combination, a polygon with the same number of vertices as the number of transmission lines used in each link unit is constructed by applying Graph Coloring Theory. For example, if the number of transmission lines is 3, 4, 5, and 6, respectively, a triangle, a square, a pentagon, and a hexagon are constructed. Assign transmission lines to the vertices of the constructed polygon (e.g., triangles, quadrilaterals, etc.), and assign graph theory segment values ​​(or difference values) to the line segments connecting the vertices. The assigned segment values ​​do not overlap. When the total sum of the PAM values ​​expressed in the transmission lines constituting the link unit is "0" and all non-overlapping line segments connecting each vertex (transmission line) are connected, only the symbols corresponding to the case where the values ​​of the connected line segments and the connected ends (vertices) are all different are selected and defined as the final symbols. Since the selected final symbols have different values ​​at both ends of the vertices (transmission lines) of the line segments (transmission lines), a differential value (a non-zero value, where the result in the comparator circuit explicitly exists as 0 or 1) exists for all symbols during the process of transmitting and receiving symbols. Therefore, the transmission and reception of selected final symbols have the same effect as a communication method using a differential signal. In the field of communication for data transmission, this differential signal transmission method has excellent signal transmission characteristics even in the presence of noise on the transmission line, power noise, or low-grade transmission lines, so it is a method that can be expected to improve BER. In addition, by performing communication using only signals for which the sum of the PAM values ​​constituting the link unit's transmission line is "0", the energy consumption of the link required for signal transmission can be maintained constant regardless of the symbol, thereby facilitating power management and design of the communication system and reducing EMI radiation noise. This is explained in detail with examples as follows. Example 1) When three transmission lines (A, B, C) constituting the link unit are used and PAM3 signals are used, the number of symbols that can be represented by the link unit is There are a total of 27 (i.e., 3^3=27). Here, PAM4, PAM5, etc., which have a greater number of signal levels than PAM3, are also possible. However, PAM3 signals are used to improve BER and maximize the difference in signal levels between transmission lines. Figure 2 is a diagram illustrating a graph shape for inference using graph coloring theory when there are three transmission lines constituting a link unit. Referring to Figure 2, each transmission line A, B, and C is assigned to a vertex on a triangle as in the method used in graph coloring theory, and line segments connecting all vertices are defined without overlapping. Here, the defined line segments are RX[0], RX[1], and RX[2]. When the PAM3 values ​​of transmission lines A, B, and C are all added together, the sum of the transmission lines is 0 (A+B+C=0). If only the cases where the ends (vertices) of all line segments RX[0], RX[1], and RX[2] all have different values ​​are selected, only 6 symbols remain out of a total of 27 symbols. In this embodiment, 6 symbols are defined as the final symbols to be used for communication. As shown in Table 3 below, 6 symbols are defined as the final symbols. [Table 3] Referring to Table 3, there are three transmission lines (A, B, C) constituting the link unit, and the final symbol using the PAM3 signal is defined, showing the symbol and the PAM3 value assignment for each transmission line. It is defined to assign digital values ​​with six different cases (e.g., decimal 0 to 5) to these six symbols in a 1:1 ratio. According to the above definition, communication proceeds by encoding when transmitting data and decoding when receiving data. Example 2) If the link unit consists of 4 transmission lines (A, B, C, and D) and uses PAM4 signals, the number of symbols that can be represented by the link unit is There are a total of 256 by (i.e., 4^4=256). Figure 3 is a diagram illustrating a graph shape for inference using graph coloring theory when there are 4 transmission lines constituting a link unit. Referring to Figure 3, each transmission line A, B, C, and D is assigned to a vertex on a rectangle in the manner used in graph coloring theory, and line segments connecting all vertices are defined without overlapping. Here, the defined line segments are RX[0], RX[1], RX[2], RX[3], RX[4], and RX[5]. When the PAM4 values ​​of transmission lines A, B, C, and D are all added together, the sum of the transmission lines is 0 (A+B+C+D=0). If only the cases where the ends (vertices) of all line segments RX[0], RX[1], RX[2], RX[3], RX[4], and RX[5] all have different values ​​are selected, only 24 symbols remain out of a total of 256 symbols. In this embodiment, 24 symbols are defined as the final symbols to be used for communication. As shown in Table 4 below, 24 symbols are defined as the final symbols. [Table 4] Referring to Table 4, there are four transmission lines (A, B, C, and D) constituting the link unit, and the final symbol using the PAM4 signal is defined, showing the symbol and the PAM4 value assignment for each transmission line. It is defined to assign digital values ​​with 24 different cases (e.g., decimal numbers 0 to 23) to these 24 symbols in a 1:1 ratio. According to the above definition, communication is carried out by encoding when transmitting data and decoding when receiving data. Example 3) If the link unit consists of 5 transmission lines (A, B, C, D, and E) and uses PAM5 signals, the number of symbols that can be represented by the link unit is There are a total of 3125 by (i.e., 5^5=3125). Figure 4 is a diagram illustrating a graph shape for inference using graph coloring theory when there are 5 transmission lines constituting a link unit. Referring to Figure 4, each transmission line A, B, C, D, and E is assigned to a vertex on a pentagon in the manner used in graph coloring theory, and line segments connecting all vertices are defined without overlapping. Here, the defined line segments are RX[0], RX[1], RX[2], RX[3], RX[4], RX[5], RX[6], RX[7], RX[8], and RX[9]. The number of symbols inferred from the 10 comparators selected by PAM5's graph coloring theory is 120. A detailed description of the inference graph shape in Fig. 4 can be easily inferred from the content described in Figs. 2 and 3, so a detailed description is omitted. Example 4) Figure 5 is a diagram illustrating a graph shape for inference using graph coloring theory when there are 6 transmission lines constituting a link unit. Referring to FIG. 5, when a PAM6 signal is used and the link unit is implemented with 6 transmission lines, a case is illustrated in which the graph shape for inference using graph coloring theory for selecting symbols is composed of 12 line segments (comparators). A detailed description of the inference graph shape of Fig. 5 can be easily inferred from the content described in Figs. 2 and 3, so a detailed description is omitted. Example 5) Figure 6 is a diagram illustrating a graph shape for inference using graph coloring theory when there are 6 transmission lines constituting a link unit. Referring to FIG. 6, a graph shape for inference using graph coloring theory to select symbols when using PAM6 signals and a link unit implemented with 6 transmission lines is illustrated as being composed of 15 line segments (comparators). The number of symbols inferred from the 15 comparators selected by PAM6's graph coloring theory is 720. A detailed description of the graph in Fig. 6 can be easily inferred from the content described in Figs. 2 and 3, so a detailed description is omitted. In parallel data communication using the aforementioned PAM signals, symbols, which are pairs of PAM signals to be represented as electrical signals on each transmission line by utilizing the principles of a graph coloring algorithm, can be selected through a program. FIGS. 7a and FIGS. 7b are flowcharts for explaining symbol selection according to the present invention. Referring to FIGS. 7a and 7b, conditions to be verified in a program prepared for selecting a symbol, namely the first condition, the second condition, the third condition, and the fourth condition, are input (step S102). In this embodiment, the first to fourth conditions may be input as boolean data types. The first condition means that the sum of the difference values ​​based on the common voltage of all transmission lines is 0V. The second condition means that adjacent transmission lines have different signal levels. The third condition means that elements have different differential signals converted into differential signals through signal level comparison between adjacent transmission lines. The fourth condition means that elements have different differential signals converted into differential signals through signal level comparison between non-adjacent transmission lines. Next, the number of transmission lines and the number of signal levels are entered, and the type of signal level is determined (step S104). Here, the number of transmission lines is the number of transmission lines used for communication. The number of signal levels is determined by the number of signal levels supported by the transmission lines, for example, between 2 and 7. The type of signal level can be determined according to the correlation shown in Table 5 below based on the signal level. Although the types of signal levels in Table 5 are expressed using voltage as the unit, this is intended to intuitively explain relative signals and represents the symbolic relative value of non-signal. [Table 5] Next, the candidate list and the result list are initialized (step S106). Here, the candidate list and the result list are composed of Python list data types and are initialized as empty lists. Next, considering the number of received transmission lines, the number of signal levels, and the types of signal levels, all possible cases that may occur in the transmission lines are entered into the candidate list (step S108). For example, when the number of transmission lines is 2 and the number of signal levels is 2, as can be seen in Table 5, the types of signal levels are 0V and 1V. Therefore, all possible cases are that the levels of transmission line 1 and transmission line 2 are (0V,0V), (1V,0V), (0V,1V), and (1V,1V). Next, one element is extracted from the above candidate list (step S110). Here, the element refers to each case according to the number of transmission lines and signal levels described above, such as (0V, 0V). If there are elements remaining in the above candidate list, the first element is extracted using the pop method of the Python list. Next, it is checked whether the one element withdrawn in step S110 satisfies the first condition (step S112). If one element extracted in step S112 is checked as satisfying the first condition, the extracted element is entered into the result list (step S114) and then fed back to step S110. Through this process, elements satisfying the first condition, where the sum of the difference values ​​based on the common voltage of all transmission lines is 0V, can be extracted. For example, if the number of transmission lines is 4 and the number of signal levels is 4, (level of transmission line 1, level of transmission line 2, level of transmission line 3, level of transmission line 4) = (-3V, -1V, 1V, 3V) satisfies the first condition because the sum is 0V, and (-1V, -1V, 1V, 3V) does not satisfy the first condition because the sum is 2V. If it is checked that one element withdrawn in step S112 does not satisfy the first condition, it is checked whether the one element withdrawn satisfies the second condition (step S116). If one element extracted in step S116 is checked as satisfying the second condition, the extracted element is entered into the result list (step S118) and then fed back to step S110. Through this process, elements satisfying the second condition, in which adjacent transmission lines have different signal levels, can be extracted. For example, if the number of transmission lines is 4 and the number of signal levels is 4, (level of transmission line 1, level of transmission line 2, level of transmission line 3, level of transmission line 4) = (-3V, -1V, 1V, 3V) satisfies the first condition because all adjacent transmission lines have different signal levels, and (1V, 1V, 1V, -3V) does not satisfy the second condition because transmission line 1 and transmission line 2, and transmission line 2 and transmission line 3 are adjacent and have the same signal level. If it is checked that one element withdrawn in step S116 does not satisfy the second condition, it is checked whether one element withdrawn satisfies the third condition (step S120). If one element extracted in step S120 is checked to satisfy the third condition, the extracted element is entered into the result list (step S122) and then fed back to step S110. Through this process, each element is converted into a differential signal to verify the third condition, and for this purpose, a comparison of signal levels between adjacent transmission lines is performed. For example, when the number of transmission lines is 4 and the number of signal levels is 4, (level of transmission line 1, level of transmission line 2, level of transmission line 3, level of transmission line 4) = (-3V, 3V, -3V, 3V) is converted into a differential signal of [(level of transmission line 1 > level of transmission line 2), (level of transmission line 2 > level of transmission line 3), (level of transmission line 3 > level of transmission line 4), (level of transmission line 4 > level of transmission line 1)] = (0, 1, 0, 1). This process aims to find only the elements that have different differential signals when the signal levels of the transmission lines are converted into differential signals as above, and therefore the third condition checks whether there were previously elements that had the same differential signal when the signal levels of the transmission lines possessed by each element were converted into differential signals. For example, the signal (-3V, 3V, -3V, 3V) is converted into a differential signal of (0, 1, 0, 1), which has a differential signal such as (-3V, 3V, -1V, 1V), so only one of the two elements satisfies the third condition. If it is checked that one element withdrawn in step S118 does not satisfy the third condition, it is checked whether one element withdrawn satisfies the fourth condition (step S124). If one element extracted in step S124 is checked to satisfy the fourth condition, the extracted element is entered into the result list (step S126) and then fed back to step S110. Through this process, in the process of converting each element into a differential signal, not only is the signal level comparison between adjacent transmission lines performed, but the signal level comparison between non-adjacent transmission lines is also performed. For example, if the number of transmission lines is 4 and the number of signal levels is 4, the signal (level of transmission line 1, level of transmission line 2, level of transmission line 3, level of transmission line 4) = (1V, -3V, 3V, -1V) is converted into a differential signal [(level of transmission line 1 > level of transmission line 2), (level of transmission line 2 > level of transmission line 3), (level of transmission line 3 > level of transmission line 4), (level of transmission line 4 > level of transmission line 1), (level of transmission line 1 > level of transmission line 3), (level of transmission line 2 > level of transmission line 4)] = (1, 0, 1, 0, 0, 0). Similar to the process of the third condition, this process also aims to identify only the elements that have different differential signals when the signal levels of the transmission lines are converted into differential signals as described above. For example, the signal (1V, -3V, 3V, -1V) is converted into the differential signal (1, 0, 1, 0, 0, 0), which has the same differential signal as (1V, -1, 1V, -1V), so only one element among the elements satisfies the fourth condition. Here, during the process of converting to differential signals, signal comparisons between more pairs of transmission lines are performed as the number of transmission lines increases. If it is checked that one element withdrawn in step S124 does not satisfy the fourth condition, it is checked whether there is a remaining element in the candidate list (step S128). If it is checked that there is a remaining element in step S128, it is fed back to step S110. If it is checked in step S128 that there are no remaining elements in the candidate list, the result list is printed (step S130). Referring again to FIG. 1, the system that is a communication entity located at both ends of a transmission line and generates data to transmit / receive the generated data may be a structure in which two processor units are connected, or a structure in which a processor unit and a memory device such as HBM are placed on one side and a DRAM die and a base logic die of the HBM are placed on the other side. A link, which is a means of physical signal connection between communicating entities, includes a data link and a control link. The data link performs the transmission and reception of data. The control link includes communication enable / disable, direction control, data read / write, idle, start, stop, error check, built-in test, transmission line loop test, etc. In this specification, the data link is described primarily, and the control link is not described separately, under the premise that it is sufficiently controlled to satisfy the progress of communication. Hereinafter, the data link is referred to as a link. Although the present invention is based on the premise of supporting bidirectional communication, this specification primarily describes the transmission of data from one side and the reception of data from the other side. Since the transmission of data from the other side and the reception of data from the one side is the reverse process of the above-described process, a detailed explanation is omitted. Figure 8 is an electrical equivalent modeling circuit for one transmission line shown in Figure 1. Referring to Figure 8, L0 is an inductance component, RS is an impedance component (serial resistance), L1 is a reactance component, and CS0~CS2 are parasitic capacitance components, representing a transmission line model. The inductance component L0 and the impedance component RS are relatively very small values ​​and are factors that have relatively little effect on high-speed signal transmission. On the other hand, the parasitic capacitance components Cs0~Cs3 are relatively small values ​​but are factors that have the greatest effect on high-speed parallel signal transmission. When the above-described transmission line model is composed of multiple lines, cross-coupling capacitance between the transmission lines also exists, but this is not explained separately in the present invention. In some embodiments, transmission lines are utilized to couple adjacent chips. In one embodiment, transmission lines can increase the available periphery for chip-to-chip connectivity and full capacity. In another embodiment, transmission lines can be utilized for increased bandwidth of chip-to-chip communication with reduced latency. In some embodiments, the transmission line may be utilized as a transmission line between logic chips. The transmission line may be oriented toward communication, bandwidth satisfaction, power, latency, and cost targets. Logic chips, such as a System-on-Chip (SOC), may include a Central Processing Unit (CPU) or a Graphics Processing Unit (GPU). Additionally, the logic chip periphery may be formatted to enable memory integration and other inputs / outputs (I / O) to other devices. Transmission lines can support metal stacks and logic (e.g., transistor types) compatible with communication functions. Transmission lines can be packaged in various configurations, including chip-on-wafer (CoW) and 2.5D packaging techniques. The CoW can also be, for example, a 2.5D or 3D array. Here, individual chips are bonded together (i.e., chip-to-chip) or bonded to an interposer (i.e., chip-to-interposer-chip). Bonding techniques can be micro-bumps (high-density I / O), ACF, hybrid bonding supporting very high-density I / O (metal-to-metal), or even optical bonding. Instead of individual chips, wafer-to-wafer (W2W) bonding is also possible and can be used depending on the application. For example, CoW may involve a singulated area of ​​a support wafer or panel larger than the chip mounted on the support wafer, while W2W may involve the same areas of singulated wafers or panels. 2.5D packaging may utilize smaller, high-density interconnect connections between two chips. The chiplets used for 2.5D packaging may be shorter passive bridges or longer ones arranged as transmission lines. These transmission lines provide options for balancing bandwidth, power, complexity, thermal and power transfer, and other architectural requirements. Additionally, the transmission lines may be active silicon (or other device technologies such as GaAs). The transmission lines may also be encapsulated in a molding compound and optionally include multiple component connections via bridges. Thus, the transmission lines utilized for 2.5D packaging may also be individually formed and packaged using 2.5D packaging. Larger transmission lines may also have special requirements for assembly into substrates to manage mechanical stress and other assembly problems.Connections between the chip and the transmission line may be made using solder (micro-bumps), ACF, and hybrid bonds (metal-to-metal). In some exemplary implementations, CoW integration may be utilized for performance logic with high-density I / O using micro-bumps or even higher-density hybrid bonding. In some implementations, CoW integration may include hybrid bonding of an interposer and silicon chiplets. In some embodiments, CoW integration may include silicon chiplets connected to back-end-of-the-line (BEOL) interconnects in a chip-like manner. For example, the silicon chiplets may have partial BEOL build-up structures and interconnects, and a subsequent second-level BEOL build-up structure connects the silicon chiplets in a chip-like manner. The silicon chiplets may be embedded in an inorganic gap-filling material (e.g., oxide) on which the second-level BEOL build-up structure is formed. In some embodiments, 2.5D packaging can be utilized for chip set optical functions having intermediate bandwidth and latency requirements. In one embodiment, to couple a group of memory chips to a logic chip, a transmission line may be utilized as a memory bar. A group of memory chips may be laterally separated. Additionally, the laterally separated memory chips may each be packaged or may be part of a die stack having a plurality of dies or modules. Thus, the laterally separated chips according to the embodiments may be part of laterally separated packages, die stacks, or modules. In one embodiment, the transmission lines may enable the logic chips to communicate with various types of DRAM chips, including LPDDR-x, DDR, HBM, etc. According to the embodiments, the memory chips are not limited to DRAM or variations such as LPDDR-x, DDR, HBM, etc. Likewise, the logic chips may include various functions such as (but not limited to) an SOC, CPU, GPU, caches, signal processors, glue logic, etc., and may be based on silicon or other technologies (e.g., GaAs). Transmission lines may include physical interfaces (PHYs) compatible with memory (e.g., PHY analog and PHY digital controllers), as well as local controllers compatible with the memory type. In some implementations, memory bars are packaged in configurations such as 2.5D packages, multi-chip modules (MCMs), and MCM plus bridges. Additionally, memory bars may be packaged in various shapes for routing, such as L-shapes. FIG. 9 is a circuit symbol for explaining a link unit composed of four transmission lines as illustrated in FIG. 8. Referring to FIG. 9, four transmission lines are configured as a single bundle to define a link unit. Although FIG. 9 illustrates a link unit defined by four transmission lines, four transmission lines may also be configured to define a T-link, TSV-link, PCB pattern, physical connection line, etc. Link units can be further configured into 16 to 32 bundles each to expand into a link having 64 to 128 transmission lines. That is, multiple transmission lines define link units, and multiple link units define a link. If necessary, it can be expanded into a link having 256, 512, 1024, 2048, or more transmission lines. Communication units connected to both ends of the link are also each expanded to the same number as the bundle of link units defining the link to form a communication module. In this specification, a plurality of communication units are defined as a communication module. FIG. 10 is a diagram illustrating the concept of n link units forming a link as illustrated in FIG. 9. Referring to FIG. 10, n link units are configured as a single group to define a link. When the number of link units is expanded to two or more, a mapping module for data transmission and a remapping module for data reception may be added to each communication module. Specifically, for data transmission by the communication module, a mapping module is additionally used to convert binary (BIN) or hexadecimal (HEX) data used by the processor unit (or computing system) into a base number according to a numerical system to match the number of symbols of each communication unit, and to assign the converted base value as a symbol signal according to the definition specified for each communication unit. In the case of PAM4 using four transmission lines, 24 symbols can be transmitted per communication unit. For example, when converting 64-bit data (e.g., 64 sets of binary numbers or 16 sets of hexadecimal numbers) into 14 sets of base-24 numbers, a logic block is used to assign the values ​​of the converted base-24 numbers to the symbols of each communication unit. This logic block is composed of combinational logic, which is a logic circuit in which the result is determined according to the input value, and can be designed to enable base conversion at a speed of 1-clock (data transmission speed) without significant overhead using current advanced semiconductor manufacturing technology. In addition, for receiving data from the communication module, a remapping module is additionally used to convert the received data of each communication unit into symbols, and to restore the original data by converting the converted symbols into bases according to a defined definition that corresponds to the binary (BIN) or hexadecimal (HEX) used by each processor unit (or computing system). For example, a logic block is used that converts received data into symbols, converts the converted symbols into 14 sets of base 24 numbers, and then converts the bases into 64-bit data (e.g., 64 sets of base 2 numbers, 16 sets of base 16 numbers) and transmits it to a processor unit. This logic block is composed of combinational logic and can be designed to enable base conversion at a speed of 1 clock (data transfer speed) without significant overhead using current advanced semiconductor manufacturing technology. Hereinafter, an example in which link units are composed of m units is described, in which there is 1 link unit (m=1) and the number of transmission lines constituting the link unit is 4, and a PAM4 signal is used. The following example describes a link unit unit representing the number of transmission lines, and since implementing a link unit as a group of n (where n is an integer greater than 1) is an extended concept of a link unit, a detailed description is omitted. FIG. 11 is a block diagram illustrating a data communication system according to an embodiment of the present invention. Referring to FIG. 11, a first communication unit (200) and a second communication unit (300) are respectively disposed on one side and the other side of a link unit (100) composed of four transmission lines. In this embodiment, the first communication unit (200) can define a first chiplet module, and the second communication unit (300) can define a second chiplet module. A chiplet is a method of dividing a whole chip into a plurality of small modules. The first chiplet module and the second chiplet module are independent small chips capable of performing different functions, and a system is defined by combining multiple chips instead of one large chip. In this embodiment, when the first communication unit (200) transmits a signal, the second communication unit (300) receives the signal, and when the second communication unit (300) transmits a signal, the first communication unit (200) receives the signal. The first communication unit (200) includes a first PHY unit (210) connected to one side of the link unit (100) to perform transmission / reception of PAM signals, a first encoding / decoding unit (220) connected to the first PHY unit (210), a first pre-encoder (230) connected to the first encoding / decoding unit (220), and a first post-decoder (240) connected to the first encoding / decoding unit (220). The first PHY unit (210) includes one or more DRV blocks that convert a TX signal of a voltage level input from the outside into current and output it to a transmission line through an I / O pad, and one or more RCV blocks that receive a PAM signal transmitted through a link unit (100), and transmits / receives the PAM signal. The first encoding / decoding unit (220) receives transmission data (TXA_DATA[n:0]) provided by the first pre-encoder (230) upon signal transmission, forms a symbol based on the TX signal (TX[7:0]) and the TX enable signal (TX_EN[7:0]), and provides the formed symbol to the first PHY unit (210). Additionally, the first encoding / decoding unit (220) restores the symbol based on the RX signal (RX[5:0]) provided by the first PHY unit (210) upon signal reception and provides it to the first post-decoder (240). The first pre-encoder (230) receives data to be transmitted from a processor unit or memory device during signal transmission and performs pre-encoding processing. The first post decoder (240) performs post decoding of the received data when receiving data. The second communication unit (300) includes a second PHY unit (310) connected to the other side of the link unit (100) to perform signal transmission / reception, a second encoding / decoding unit (320) connected to the second PHY unit (310), a second pre-encoder (330) connected to the second encoding / decoding unit (320), and a second post-decoder (340) connected to the second encoding / decoding unit (320). The second PHY unit (310) includes one or more DRV blocks that convert a TX signal of a voltage level input from the outside into current and output it to a transmission line through an I / O pad, and one or more RCV blocks that receive a PAM signal transmitted through a link unit (100), and transmits / receives the PAM signal. The second encoding / decoding unit (320) restores a symbol based on the RX signal (RX[5:0]) provided from the second PHY unit (310) upon receiving a signal and provides it to the second post decoder (340). Additionally, the second encoding / decoding unit (320) receives transmission data (TXB_DATA[n:0]) provided from the second pre-encoder (330) upon transmitting a signal, forms a symbol based on the TX signal (TX[7:0]) and the TX enable signal (TX_EN[7:0]), and provides the formed symbol to the second PHY unit (310). The second pre-encoder (330) receives data to be transmitted from a processor unit or memory device during signal transmission and performs pre-encoding processing. The second post decoder (340) performs post decoding of the received data when receiving data. The comparator used in each of the first PHY unit (210) and the second PHY unit (310) may include a voltage comparator. If the comparator used in the first PHY unit (210) and the second PHY unit (310) uses a clock (RXA_CLK, or RXB_CLK), the voltage comparator may include an ARM (Analog Re-generative Memory) latch voltage comparator. In FIG. 11, the first PHY unit (210), link unit (100), and second PHY unit (310) can be represented as in FIG. 12. FIG. 12 is a drawing for explaining the first PHY unit (210), link unit (100), and second PHY unit (310) shown in FIG. 11. Referring to FIG. 12, a first PHY unit (210) is positioned on one side of the link unit (100), and a second PHY unit (310) is positioned on the other side of the link unit (100). The link unit (100) includes four transmission lines. In this embodiment, since there are four transmission lines, a PAM4 signal is used as a TX signal to drive each transmission line. Each of the first PHY unit (210) and the second PHY unit (310) includes four DRV blocks (400) and four RCV blocks (500). Each DRV block (400) is a circuit configured to drive a PAM4 signal on one transmission line. Each RCV block (500) uses four input circuits that receive a signal received from one transmission line. It has a circuit configuration that outputs the result of comparing these four input results with six comparators configured by graph coloring theory. In order to process the driving signal of the first transmission line, i.e., the TX signal, the TX_EN[1], TX_EN[0], TX[1], TX[0] and PAD of the first DRV block (400) are each connected to the TX_EN[1], TX_EN[0], TX[1], TX[0] and PAD[0] of the first PHY unit (210). In order to process the driving signal of the second transmission line, i.e., the TX signal, the TX_EN[1], TX_EN[0], TX[1], TX[0] and PAD of the second DRV block (400) are each connected to the TX_EN[3], TX_EN[2], TX[3], TX[2] and PAD[1] of the first PHY unit (210). To process the driving signal of the third transmission line, i.e., the TX signal, the TX_EN[1], TX_EN[0], TX[1], TX[0] and PAD of the third DRV block (400) are each connected to the TX_EN[5], TX_EN[4], TX[5], TX[4] and PAD[2] of the first PHY unit (210). In order to process the driving signal of the fourth transmission line, i.e., the TX signal, the TX_EN[1], TX_EN[0], TX[1], TX[0] and PAD of the fourth DRV block (400) are each connected to the TX_EN[7], TX_EN[6], TX[7], TX[6] and PAD[3] of the first PHY unit (210). The DRV blocks (400) applicable in this embodiment can be implemented with various circuits such as those shown in FIGS. 13, 14, and 15 below. FIG. 13 is a circuit diagram illustrating an example of the DRV block (400) shown in FIG. 12. In particular, a Voltage Mode Driver (DRV) circuit is shown. Referring to FIG. 13, a DRV block (400) according to one example includes a first TX buffer (ATX0), a first TX resistor (RTX0), a second TX buffer (ATX1), and a second TX resistor (RTX1), and converts a TX signal of a voltage level input from the outside into a current and outputs it to a transmission line of a link unit (100) through an I / O pad. In this embodiment, it is preferable that the first TX resistor (RTX0) and the second TX resistor (RTX1) have resistance values ​​between 300Ω and 10kΩ. Alternatively, the first TX resistor (RTX0) and the second TX resistor (RTX1) may be set to values ​​for using a current between 50µA and 300µA as a data transmission signal, depending on the voltage (VDD) of the output circuit. Conventional signal transmission driver (TX or DRV) circuits have modeled an ideal output buffer (when the output impedance or Ron is 0Ω) and the Ron (ON resistance value) of the PMOS and NMOS FETs constituting the output buffer stage as a virtual resistance (RT). The resistance (RT) is set to a value between approximately 10Ω and 300Ω to match the impedance of the transmission line. On the other hand, in the present invention, the output resistor, namely the first TX resistor (RTX0) (or the first TX resistor (RTX0) and the second TX resistor (RTX1)), serves to generate a transmission current by converting the voltage generated in the output buffer into a current. The above resistors are intended to generate a constant current regardless of the impedance of the transmission line, and generally have a resistance value in the range of 300Ω to 10kΩ, or are set to generate a current of 50µA to 300µA depending on the VDD and VCOM voltages. This is an important feature that distinguishes it from existing technology. For example, if VDD is 1.0V and VCOM is 0.5V, and the signal transmission current is set to -25µA, RTX0 (i.e., when only RTX0 is used) becomes 20kΩ according to [Equation 4] and [Equation 5]. If the current is set to 100µA, 150µA, 200µA, and 300µA, the resistance values ​​of RTX0 are calculated to be 5kΩ, 3.333kΩ, 2.5kΩ, and 1.667kΩ, respectively. The first TX buffer (ATX0) and the first TX resistor (RTX0), to which the first TX signal (TX[0]) and the first TX enable signal (TX_EN[0]) are applied, are connected in series and connected to an I / O pad, and the second TX buffer (ATX1) and the second TX resistor (RTX1), to which the second TX signal (TX[1]) and the second TX enable signal (TX_EN[1]) are applied, are connected in series and connected to an I / O pad. FIG. 13 describes configuring two TX buffers and two resistors in the DRV block (400) to represent four relative current values. In a similar manner, if three or more TX buffers and three or more resistors are configured in the DRV block (400), more relative current values ​​can be represented, but this is omitted in the specification. FIG. 14 is a circuit diagram illustrating another example of the DRV block shown in FIG. 12. In particular, a Current Mode Driver (DRV) circuit of the Current Source (reference) type is shown. Referring to FIG. 14, a DRV block (400) according to another example includes a PAM encoding unit (410), a first buffer (420), and a voltage-current conversion unit (430), and converts a TX signal of a voltage level input from the outside into a current and outputs it to a transmission line through an I / O pad. The PAM encoding unit (410) encodes the TX signal according to the TX_EN signal. In this embodiment, if the number of transmission lines is 3, the TX signal driving each transmission line uses the PAM3 signal, and if the number of transmission lines is 4, the TX signal driving each transmission line uses the PAM4 signal. The first buffer (420) includes a front inverter (BU1) that is enabled by a TX_EN signal and inverts a TX signal, and a rear inverter (BU2) that is connected to the rear of the front inverter (BU1) and is enabled by a TX_EN signal and inverts a signal inverted by the front inverter (BU1), thereby buffering a PAM4 signal of a voltage level encoded by the PAM encoding unit (410). The voltage-current converter (430) includes a pull-up current source (PUC), a pull-down current source (PDC), a pull-up switch (PUS), and a pull-down switch (PDS) to convert a PAM4 signal of a voltage level buffered by the first buffer (420) into a current. The pull-up current source (PUC) and the pull-down current source (PDC) generate a first current. The pull-up current source (PUC) and the pull-down current source (PDC) may include a current source or a current mirror. The pull-up switch (PUS) controls the output of the first current generated by the pull-up current source (PUC) in response to a signal output from the downstream inverter (BU2) of the first buffer (420). The pull-down switch (PDS) controls the output of the first current generated by the pull-down current source (PDC) in response to a signal output from the upstream inverter (BU1) of the buffer (310). Accordingly, a current corresponding to the transmission voltage signal, i.e., a first current, is applied to the transmission line connected through the I / O pad. That is, to convert the input voltage signal into a current, a current switch in which a pull-up switch (PUS) and a pull-down switch (PDS) are connected to a pull-up current source (PUC) and a pull-down current source (PDC) can be used. FIG. 15 is a circuit diagram illustrating another example of the DRV block shown in FIG. 12. In particular, a Current Mode Driver (DRV) circuit of the current conveyor type is shown. Referring to FIG. 15, a DRV block (400) according to another example includes a first TX buffer (ATX0), a first TX resistor (RTX0), a second TX buffer (ATX1), a second TX resistor (RTX1), and a current conveyor (CC), converting an input voltage signal into current and providing it to a transmission line through an I / O pad. The first TX buffer (ATX0) and the first TX resistor (RTX0), to which the first TX signal (TX[0]) and the first TX enable signal (TX_EN[0]) are applied, are connected in series and connected to the X-port of the current conveyor (CC), and the second TX buffer (ATX1) and the second TX resistor (RTX1), to which the second TX signal (TX[1]) and the second TX enable signal (TX_EN[1]) are applied, are connected in series and connected to the X-port of the current conveyor (CC). The current conveyor (CC) includes an X-port connected to the common terminal of the first TX resistor (RTX0) and the second TX resistor (RTX1), a Y-port to which a common mode voltage (VCOM) on the transmission line is applied, and a ZP-port connected to an I / O pad. The Y-port receives the common mode voltage (VCOM) on the transmission line, the X-port receives current, and the ZP-port mirrors the input current and outputs it through the I / O pad. The current conveyor (CC) may further include an EN-port (not shown) to which an EN signal is input to enable / disable the operating state of the current conveyor. The relationship between the input and output signals of the current conveyor (CC) can be defined by the following matrix. According to the matrix definition of the relationship between the symbol of the current conveyor (CC) shown in Fig. 15 and the signal input / output described above, the current conveyor (CC) has the following characteristics. - The Y-port is a high-impedance port that receives a voltage signal with an input current of "0". - The voltage of the X-port is the same as the voltage of the Y-port, and it is a low-impedance port that receives a current signal. - The ZP-port is a high-impedance port that mirrors the input (or output) current of the X-port 1:1 to have the same current output value as the X-port. FIG. 16 is a circuit diagram illustrating an example of the current conveyor (CC) illustrated in FIG. 15. In this embodiment, the current conveyor (CC) illustrates a Balanced Output Rail-to-rail Current Conveyor ±. Referring to FIG. 16, the current conveyor (CC) includes a core block (CORE) and a driving block (D2). The core block (CORE) includes an upper differential input terminal (1110), a lower differential input terminal (1120), an upper current mirror terminal (1130), a lower current mirror terminal (1140), a switching terminal (1150), a first capacitor (C1), and a second capacitor (C2), and receives VBP0, VBP1, and VBP2 as bias voltages for PMOS devices from a bias circuit block (not shown), and receives VBN0, VBN1, and VBN2 as bias voltages for NMOS devices. In the balanced output rail-to-rail second-generation current conveyor (CC) shown in FIG. 16, the illustration of the bias circuit block is omitted. The core block (CORE) implements rail-to-rail input / output through an upper differential input terminal (1110) and a lower differential input terminal (1120) commonly connected to the Y-port and X-port, and outputs a first driving voltage (P_DRV) and a second driving voltage (N_DRV) to the driving block (D2) by mirroring the current applied by the bias voltage based on the voltage of the Y-port and the voltage of the X-port. The upper differential input terminal (1110) is composed of p-MOSFET MP0 and p-MOSFET MP1 connected in series, and p-MOSFET MP2 and p-MOSFET MP3 connected in parallel. p-MOSFET MP0 has a source to which a first power supply voltage (VDD) is applied, a gate to which a bias voltage (VBP0) is applied, and a drain connected to the source of p-MOSFET MP1. p-MOSFET MP1 has a source connected to the drain of p-MOSFET MP0, a gate to which a bias voltage (VBP1) is applied, and a drain connected to the source of p-MOSFET MP2 and the source of p-MOSFET MP3. p-MOSFET MP2 has a source connected to the drain of p-MOSFET MP1, a gate connected to the Y-port, and a drain connected to the lower current mirror terminal (1140). p-MOSFET MP3 has a source connected to the drain of p-MOSFET MP1, a gate connected to the X-port, and a drain connected to the lower current mirror terminal (1140). p-MOSFET MP2 and p-MOSFET MP3 are responsible for the input and compare the voltage of the Y-port with the voltage of the X-port to flow a current (tail current) (Ip) applied by the bias voltage toward the gate where the lower voltage is input. Here, the range of the operable input signal voltage (Common mode voltage) is approximately 0.8V to 0V, assuming the first power supply voltage (VDD) is about 1.0V. The lower differential input terminal (1120) consists of n-MOSFET MN0 and n-MOSFET MN1 connected in series, and n-MOSFET MN2 and n-MOSFET MN3 connected in parallel. n-MOSFET MN0 has a drain connected to the source of n-MOSFET MN1, a gate to which a bias voltage (VBN0) is applied, and a source to which a second power supply voltage (VSS) is applied. n-MOSFET MN1 has a drain connected to the source of n-MOSFET MN2 and the source of n-MOSFET MN3, a gate to which a bias voltage (VBN1) is applied, and a source connected to the drain of n-MOSFET MN0. n-MOSFET MN2 has a drain connected to the upper current mirror terminal (1130), a gate connected to the Y-port, and a source connected to the drain of n-MOSFET MN1. n-MOSFET MN3 has a drain connected to the upper current mirror terminal (1130), a gate connected to the X-port, and a source connected to the drain of n-MOSFET MN1. n-MOSFET MN2 and n-MOSFET MN3 are responsible for the input and perform the role of comparing the voltage of the Y-port and the voltage of the X-port to flow a current (In) applied by the bias voltage toward the gate where the higher voltage is input. Here, the range of the operable input signal voltage (Common mode voltage) is approximately 0.2V to 1.0V, assuming the first power supply voltage (VDD) is about 1.0V. Since the upper differential input terminal (1110) and the lower differential input terminal (1120) are arranged as input stages of the current conveyor (CC), rail-to-rail input can be implemented. That is, when the power supply is 1.0V, a tail current (Ip, In) can be flowed so that the range of the input voltage (Common Mode Voltage) covers the entire range of the power supply voltage (first power supply voltage (VDD)). Rail-to-rail input covers the entire range of input signals from 0V to VDD, so it has the advantage of operating over a wider range of input voltages compared to conventional circuits that receive upper or lower inputs. The upper current mirror terminal (1130) is composed of p-MOSFET MP4, p-MOSFET MP5, p-MOSFET MP6, and p-MOSFET MP7 to define the current mirror. p-MOSFET MP4 has a source to which the first power supply voltage (VDD) is applied, a gate connected to the drain of p-MOSFET MP5 and the gate of p-MOSFET MP6, and a drain connected to the source of p-MOSFET MP5. Additionally, the drain of p-MOSFET MP4 is connected to the source of n-MOSFET MN3 of the lower differential input terminal (1120). p-MOSFET MP5 has a source connected to the drain of p-MOSFET MP4, a gate connected to the gate of p-MOSFET MP7, and a drain connected to the gate of p-MOSFET MP4. Additionally, the source of p-MOSFET MP5 is connected to the source of n-MOSFET MN3 of the lower differential input terminal (1120). p-MOSFET MP6 has a source to which the first power supply voltage (VDD) is applied, a gate connected to the drain of p-MOSFET MP5 and the gate of p-MOSFET MP4, and a drain connected to the source of p-MOSFET MP7. Additionally, the drain of p-MOSFET MP6 is connected to the source of n-MOSFET MN2 of the lower differential input terminal (1120). p-MOSFET MP7 has a source connected to the drain of p-MOSFET MP6, a gate connected to the gate of p-MOSFET MP5, and a drain connected to the driving block (D2) and the switching terminal (1150). Here, p-MOSFET MP5 and p-MOSFET MP7 are biased by a bias voltage (VBP1), and the bias voltages of p-MOSFET MP4 and p-MOSFET MP6 have the circuit characteristic of having the drain voltage of p-MOSFET MP5 applied. If the gate area of ​​p-MOSFET MP4 is equal to the gate area of ​​p-MOSFET MP6, and the gate area of ​​p-MOSFET MP5 is equal to the gate area of ​​p-MOSFET MP7, then the current flowing through p-MOSFET MP6 and p-MOSFET MP7 is equal to the current flowing through p-MOSFET MP4 and p-MOSFET MP5. In this case, the saturation voltage of p-MOSFET MP5 becomes higher than the threshold voltage (Vth) of p-MOSFET MP4, and consequently, current is supplied to the drain of p-MOSFET MP7. Therefore, it has the characteristic of having a wider operating voltage range than a current mirror of a conventional structure. At this time, when currents are applied to the drains of p-MOSFET MP4 and p-MOSFET MP6 with different values ​​due to the difference in input voltage of the lower differential input terminal (1120), the final output current (I(MP7)) flowing through p-MOSFET MP7 is determined as a current ± @IN of the bias current due to the bias voltage (VBP1). Here, @ is the ratio of the current (In) to the difference in input voltage obtained from the upper differential input terminal (1110) and the lower differential input terminal (1120), which are the input stages of the current conveyor (CC). The lower current mirror section (1140) is composed of n-MOSFET MN4, n-MOSFET MN5, n-MOSFET MN6, and n-MOSFET MN7 to define the current mirror. n-MOSFET MN4 has a drain connected to the source of n-MOSFET MN5, a gate connected to the gate of n-MOSFET MN6, and a source to which a second power supply voltage (VSS) is applied. Additionally, the drain of n-MOSFET MN4 is connected to the source of p-MOSFET MP3 of the upper differential input section (1110). n-MOSFET MN5 has a drain connected to the switching section (1150), a gate connected to the gate of n-MOSFET MN7, and a source connected to the drain of n-MOSFET MN4. Additionally, the source of n-MOSFET MN5 is connected to the source of p-MOSFET MP2 of the upper differential input section (1110). n-MOSFET MN6 has a drain connected to the source of n-MOSFET MN7, a gate connected to the gate of n-MOSFET MN4, and a source to which the second power supply voltage (VSS) is applied. n-MOSFET MN7 has a drain connected to the switching terminal (1150), a gate connected to the gate of n-MOSFET MN5, and a source connected to the drain of n-MOSFET MN6. Additionally, the drain of n-MOSFET MN7 is connected to the source of p-MOSFET MP2 of the upper differential input terminal (1110). Here, n-MOSFET MN5 and n-MOSFET MN7 are biased by a bias voltage (VBN1), and the bias voltages of n-MOSFET MN4 and n-MOSFET MN6 have the circuit characteristic of having the source voltage of n-MOSFET MN5 applied. If the gate area of ​​n-MOSFET MN4 is equal to the gate area of ​​n-MOSFET MN6, and the gate area of ​​n-MOSFET MN5 is equal to the gate area of ​​n-MOSFET MN7, then the current flowing through n-MOSFET MN6 and n-MOSFET MN7 is equal to the current flowing through n-MOSFET MN4 and n-MOSFET MN5. In this case, the saturation voltage of n-MOSFET MN5 becomes higher than the threshold voltage (Vth) of n-MOSFET MN4, and as a result, current is supplied to the source of n-MOSFET MN7. Therefore, it has the characteristic of having a wider operating voltage range than a current mirror of a general structure. At this time, when currents are applied to the sources of n-MOSFET MN4 and n-MOSFET MN6 with different values ​​due to the difference in input voltage of the upper differential input terminal (1110), the final output current (I(MN7)) flowing through n-MOSFET MN7 is determined as the current ± @IP of the bias current by VBN1. Here, @ is the ratio of the current (Ip) to the difference in input voltage obtained from the upper differential input terminal (1110) and the lower differential input terminal (1120), which are the input stages of the current conveyor (CC). In this embodiment, the upper current mirror section (1130) and the lower current mirror section (1140) employ a high-compliance current mirror. The driving block (D2) includes a first driver (1210) and a second driver (1220), and outputs a normal output current through the ZP-port in response to a first driving voltage (P_DRV) and a second driving voltage (N_DRV). The first driver (1210) consists of a series-connected p-MOSFET MP10 and an n-MOSFET MN10. The p-MOSFET MP10 has a source to which the first power supply voltage (VDD) is applied, a gate connected to the upper current mirror terminal (1130), and a drain connected to the X-port of the n-MOSFET MN10. The n-MOSFET MN10 has a source to which the second power supply voltage (VSS) is applied, a gate connected to the lower current mirror terminal (1140), and a drain connected to the X-port of the p-MOSFET MP10. The first driver (1210) performs the function of connecting the output to the X-port of the input stage to match the structure of the second-generation current conveyor. The second driver (1220) is composed of a series-connected p-MOSFET MP11 and an n-MOSFET MN11, identical in structure to the first driver (1210). The p-MOSFET MP11 has a source to which VDD is applied, a gate connected to the gate of the p-MOSFET MP10 of the first driver (1210), a drain of the n-MOSFET MN11, and a drain connected to the ZP-port. The n-MOSFET MN11 has a source to which VSS is applied, a lower current mirror terminal (1140), a gate connected to the gate of the n-MOSFET MN10, and a drain connected to the drain of the p-MOSFET MP11 and the ZP-port. Unlike the first driver (1210) being connected to the X-port of the differential input stage of the upper differential input terminal (1110) and the lower differential input terminal (1120), the second driver (1220) is connected to the ZP-port for output driving. Referring again to FIG. 15, the first TX buffer (ATX0) is enabled according to the first TX enable signal (TX_EN[0]) to provide the first TX signal (TX[0]) to the first TX resistor (RTX0), and the second TX buffer (ATX1) is enabled according to the second TX enable signal (TX_EN[1]) to provide the second TX signal (TX[1]) to the second TX resistor (RTX1). The operating voltage of the first TX buffer (ATX0) and the second TX buffer (ATX1) may be the first power supply voltage (VDD). The first TX resistor (RTX0) is placed between the first TX buffer (ATX0) and the X-port of the current conveyor (CC), so that the voltage of the logic signal TX[0] can be easily converted into two types of currents applied to the X-port of the current conveyor (CC). That is, for the logic signal voltage values ​​of 0 and 1, current values ​​of -1 and +1 of relative magnitude can be applied to the X-port of the current conveyor (CC). In addition, the second TX resistor (RTX1) is placed between the second TX buffer (ATX1) and the X-port of the current conveyor (CC), so that the voltage of the logic signal TX[0] can be easily converted into two types of currents applied to the X-port of the current conveyor (CC). That is, for the logic signal voltage values ​​of 0 and 1, current values ​​of -1 and +1 of relative magnitude can be applied to the X-port of the current conveyor (CC). In this embodiment, when the voltage of the power supply of the logic core generating the transmission signal and the voltage of the interface power supply for signal transmission are different, or when different voltages must be used for the quality of the communication signal, the first TX buffer (ATX0) may use a buffer including a voltage level shifter. The operating voltage of the voltage level shifter is the VDD power supply voltage. At this time, when the value of the first TX resistor (RTX0) is RTX, the voltage of the first TX buffer (ATX0) is the first power supply voltage (VDD), the common mode voltage (VCOM) is 1 / 2VDD, and the value of the first TX buffer (ATX0) is 1, the current applied to the X-port of the current conveyor (CC) is given by the following equation (1). [Formula 1] On the other hand, when the value of the first TX buffer (ATX0) is 0, the current applied to the X-port of the current conveyor (CC) is as shown in the following equation (2). [Equation 2] Since the common mode voltage (VCOM) is 1 / 2VDD, the above currents are (11 / 2VDD) / RTX and -(11 / 2VDD)RTX, respectively, and can be expressed as +1 and -1, respectively in relative magnitude. When the first TX buffer (ATX0) is disabled, the output of the first TX buffer (ATX0) is floating, and the value of the current applied to the X-port of the current conveyor (CC) is "0". Also, the value of the current mirrored to the ZP-port of the current conveyor (CC) is "0". When this signal state is applied to the transmission line, it has a relative magnitude of 0. In the above, an example was described in which the first TX signal (TX[0]) is applied to the X-port of the current conveyor (CC) via the first TX buffer (ATX0) and the first TX resistor (RTX0) and converted into current, but in the same way, the second TX signal (TX[1]) can be applied to the X-port of the current conveyor (CC) via the second TX buffer (ATX1) and the second TX resistor (RTX1) and converted into current. FIG. 15 illustrates the representation of four relative current values ​​by configuring two TX buffers and two resistors in the DRV block. In a similar manner, if three or more TX buffers and three or more resistors are configured in the DRV block, more relative current values ​​can be represented, but this is omitted in the present specification. Hereinafter, in this specification, the DRV block (400) is described based on the Current Mode Driver (DRV) circuit of the Current Conveyor type shown in FIG. 15. In FIG. 15, the RCV block (500) of the PHY unit may be composed of a voltage generator and a voltage comparator module for four transmission lines to receive a PAM4 signal transmitted through the link unit. FIG. 17 is a circuit diagram illustrating an example of the RCV block (500) shown in FIG. 12. In particular, a voltage mode comparator (or OPAMP) circuit is shown. Referring to FIG. 17, an RCV block (500) according to one example includes a voltage generating unit (510) that converts the current of a PAM4 signal provided through a transmission line into a voltage, and a voltage comparator module (530) that differentially compares the PAM4 signals converted into voltage by the voltage generating unit (510). The voltage generation unit (510) includes a plurality of RC parallel circuits positioned between the transmission line and the voltage comparator module (530). Each RC parallel circuit includes a resistor (RRX) and a capacitor (CRX), one end of which is connected to a PAD connected to the transmission line and the other end of which is connected to a common mode voltage (or common ground voltage). The resistor (RRX) converts the current of the PAM4 signal provided through the transmission line into a voltage, and the capacitor (CRX) improves signal quality by bypassing high-frequency components or adjusting the frequency response. The capacitor (CRX) can perform high-frequency noise removal and equalization functions together with the resistor (RRX). In FIG. 17, the voltage generation unit (510) is shown to include a plurality of RC parallel circuits, but the capacitor (CRX) connected between the PAD and the common mode voltage (or common ground voltage) may be used optionally. That is, the capacitor (CRX) may be omitted from the voltage generation unit (510). The voltage comparator module (530) includes six voltage comparators and differentially compares PAM4 signals converted into voltage by the voltage generator (510). The CLK input used in the voltage comparator module (530) can be selectively used as needed depending on the type of voltage comparator. Specifically, when the four transmission lines are named A, B, C, and D, and each transmission line is connected to the receiver's PAD[0], PAD[1], PAD[2], and PAD[3], the voltage comparator module (530) compares the PAD signals of RX[0]=(AB), RX[1]=(BC), RX[2]=(CD), RX[3]=(DA), RX[4]=(AC), and RX[5]=(BD), respectively, and outputs the values ​​of RX[0:5] as input values ​​to the decoder circuit. In FIG. 17, A represents PAD[0], B represents PAD[1], C represents PAD[2], and D represents PAD[3]. The voltage comparator module (530) illustrated in FIG. 17 may include analog comparators or clock-based latch comparators that compare the voltage of the differential input terminal through current bias. FIG. 18 is a circuit diagram illustrating another example of the RCV block (500) shown in FIG. 12. In particular, a circuit using the input of the X-port of the current conveyor (CC) and a comparator is shown. Referring to FIG. 18, an RCV block (500) according to another example includes a voltage generator (520) that converts the current of a PAM4 signal provided through a transmission line into a voltage, and a voltage comparator module (530) that differentially compares the PAM4 signals converted into voltage by the voltage generator (520). The voltage generation unit (520) includes a plurality of current conveyors (CC) connected to a transmission line and a plurality of RC parallel circuits arranged between the current conveyors (CC) and the voltage comparator module (530). Each of the current conveyors (CC) is connected to the four transmission lines of the link unit in a one-to-one manner. Each RC parallel circuit includes a resistor (RRX) and a capacitor (CRX), one end of which is connected to the ZP-port of the current conveyors (CC) and the other end of which is connected to the common mode voltage (or common ground voltage). The resistor (RRX) converts the current of the PAM4 signal provided through the ZP-port of the current conveyors (CC) into voltage, and the capacitor (CRX) improves signal quality by bypassing high-frequency components or adjusting the frequency response. The capacitor (CRX), together with the resistor (RRX), can perform high-frequency noise removal and equalization functions. Specifically, to generate the voltage value (RXA[3:0]) of the transmitted signal, a resistor (RRX) is placed between the ZP-port of the current conveyor (CC) and the common mode voltage (VCOM) to convert the current, which is the transmitted signal, into voltage. Additionally, a capacitor (CRX) is placed between the ZP-port of the current conveyor (CC) and the common mode voltage (VCOM) to cooperate with the resistor (RRX) in the process of converting the current, which is the transmitted signal, into voltage, and can operate as a passive filter for high-frequency noise removal or equalization. In FIG. 18, the voltage generation unit (520) is shown to include a plurality of RC parallel circuits, but the capacitor (CRX) connected between the PAD and the common mode voltage (or common ground voltage) may be used optionally. That is, the capacitor (CRX) may be omitted from the voltage generation unit (510). The voltage comparator module (530) includes a comparator (or OPAMP) having six differential inputs for distinguishing PAM4 signals from four RXA[3:0] outputs. When the four transmission lines are named A, B, C, and D, and each transmission line is connected to the receiver's PAD[0], PAD[1], PAD[2], and PAD[3], the voltage comparator module (530) compares the PAD signals of RX[0]=(AB), RX[1]=(BC), RX[2]=(CD), RX[3]=(DA), RX[4]=(AC), and RX[5]=(BD), respectively, and outputs the values ​​of RX[0:5] as input values ​​to the decoder circuit. In this embodiment, A represents RXA[0], B represents RXA[1], C represents RXA[2], and D represents RXA[3]. The CLK input used in the voltage comparator module (530) is used selectively as needed depending on the type of voltage comparator. The voltage comparator is a circuit that detects a differential signal, that is, the difference between the positive input voltage and the negative input voltage, and converts it into a digital signal [High (1) or Low (0)]. FIG. 19 is a circuit diagram for explaining an example of a voltage comparator module (530) shown in FIG. 17 or FIG. 18. Referring to FIG. 19, a voltage comparator module (530) according to one example includes a first differential voltage comparator (COP1), a second differential voltage comparator (COP1), a third differential voltage comparator (COP3), a fourth differential voltage comparator (COP4), a fifth differential voltage comparator (COP5), and a sixth differential voltage comparator (COP6), and differentially compares the voltage values ​​(RXA[3:0]) of a signal transmitted from a voltage generation unit (510, illustrated in FIG. 18) (520, illustrated in FIG. 21). The first to sixth comparators (COP1, COP2, COP3, COP4, COP5, COP6) include differential voltage comparators that receive a current bias and detect the difference in the input voltage of the gate. The first differential voltage comparator (COP1) outputs a first differential voltage (OUT[0]) obtained by differentially comparing the first voltage (IN[0]) and the second voltage (IN[1]) provided by the voltage generation unit (510:520), and the second differential voltage comparator (COP1) outputs a second differential voltage (OUT[1]) obtained by comparing the second voltage (IN[1]) and the third voltage (IN[2]) provided by the voltage generation unit (510:520). Additionally, the third differential voltage comparator (COP3) outputs a third differential voltage (OUT[2]) by comparing the third voltage (IN[2]) and the fourth voltage (IN[3]) provided by the voltage generation unit (510:520), and the fourth differential voltage comparator (COP4) outputs a fourth differential voltage (OUT[3]) by comparing the first voltage (IN[0]) and the fourth voltage (IN[3]) provided by the voltage generation unit (510:520). Additionally, the fifth differential voltage comparator (COP5) outputs a fifth differential voltage (OUT[4]) by comparing the first voltage (IN[0]) and the third voltage (IN[2]) provided by the voltage generation unit (510:520), and the sixth differential voltage comparator (COP6) outputs a sixth differential voltage (OUT[5]) by comparing the second voltage (IN[1]) and the fourth voltage (IN[3]) provided by the voltage generation unit (510:520). Data with specific bit values ​​designated by encoders and decoders connected to four transmission lines is transmitted and received as differential signals. Six differential voltage comparators are used to compare the signals input from each of the four transmission lines. Encoding logic (used during transmission) and decoding logic (used during reception) are required to select and transmit valid values ​​from the results of these differential voltage comparators that do not overlap. FIG. 20 is a circuit diagram for explaining the first differential voltage comparator of the voltage comparator module (530) illustrated in FIG. 19. Although the first differential voltage comparator is illustrated in FIG. 20, the second to sixth differential voltage comparators also have the same configuration. Referring to FIG. 20, the first differential voltage comparator (COP1) of the voltage comparator module (530) includes a first comparison circuit (VCC1), a second comparison circuit (VCC2), and a buffer driving circuit (BDC) to compare the voltage of the differential voltage input terminal through the current bias. The first comparison circuit (VCC1) is connected to a current bias circuit to supply the operating current of the FET to the lower part of the FET that receives the differential input. The second comparison circuit (VCC2) rapidly amplifies the signal of the first comparison circuit. The buffer driving circuit (BDC) is connected to the second comparison circuit, enhancing fast operation and driving characteristics even when a logic block with a large load is connected to the output terminal. The output of the differential amplifier configured in this way is affected by any input voltage applied to VIN(+) and VIN(-) because the transistors are connected to the common drain. In other words, since the drain current of the two transistors must always be constant as the sum of the current flowing through transistor T1 and the current flowing through transistor T2, the output voltages operate differentially such that if the voltage of one side increases, the voltage of the other side decreases. FIG. 21 is a circuit diagram for explaining an example of a voltage comparator module (530) shown in FIG. 17 or FIG. 18. Referring to FIG. 21, the voltage comparator module (530) includes a first differential voltage comparator (COP21), a second differential voltage comparator (COP21), a third differential voltage comparator (COP23), a fourth differential voltage comparator (COP24), a fifth differential voltage comparator (COP25), and a sixth differential voltage comparator (COP26) that operate in response to a clock (CLK), and differentially compares the voltage values ​​(RXA[3:0]) of the signal transmitted from the voltage generation unit (510, shown in FIG. 17) (520, shown in FIG. 18). The first to sixth voltage comparators (COP21, COP22, COP23, COP24, COP25, COP26) are differential ARM (Analog Re-generative Memory) latch voltage comparators that detect differences in input voltages of gates using a comparison clock. The first differential voltage comparator (COP21) outputs a first differential voltage (OUT[0]) by differentially comparing the first voltage (IN[0]) and the second voltage (IN[1]) provided by the voltage generation unit (510:520) in response to the clock (CLK), and the second differential voltage comparator (COP22) outputs a second differential voltage (OUT[1]) by comparing the second voltage (IN[1]) and the third voltage (IN[2]) provided by the voltage generation unit (510:520) in response to the clock (CLK). Additionally, the third differential voltage comparator (COP23) outputs a third differential voltage (OUT[2]) by comparing the third voltage (IN[2]) and the fourth voltage (IN[3]) provided by the voltage generation unit (510:520) in response to the clock (CLK), and the fourth differential voltage comparator (COP24) outputs a fourth differential voltage (OUT[3]) by comparing the first voltage (IN[0]) and the fourth voltage (IN[3]) provided by the voltage generation unit (510:520) in response to the clock (CLK). Additionally, the fifth differential voltage comparator (COP25) outputs a fifth differential voltage (OUT[4]) by comparing the first voltage (IN[0]) and the third voltage (IN[2]) provided by the voltage generation unit (510:520) in response to the clock (CLK), and the sixth differential voltage comparator (COP26) outputs a sixth differential voltage (OUT[5]) by comparing the second voltage (IN[1]) and the fourth voltage (IN[3]) provided by the voltage generation unit (510:520) in response to the clock (CLK). Data with specific bit values ​​designated by four transmission line encoders and decoders is transmitted and received as differential signals. Six differential voltage comparators, each comparing the input signals from the four transmission lines, are used for the received signals. Encoding logic (used during transmission) and decoding logic (used during reception) are required to select and transmit valid values ​​from the results of these differential voltage comparators that do not overlap. FIG. 22 is a circuit diagram for explaining the first differential voltage comparator of the voltage comparator module (530) shown in FIG. 21. Referring to FIG. 22, the first differential voltage comparator (COP21) is a circuit in which a differential voltage comparator (ALC) and an SR-latch (SRL) operate together, and detects the difference in input voltage of the gate using a comparison clock. The first differential voltage comparator (COP21) includes a differential ARM (Analog Re-generative Memory) latch voltage comparator. The differential voltage comparator (ALC) determines the output signal by comparing two input signals, amplifying the difference between VIN(+) and VIN(-), and determining the output signal based on the amplified difference. When the output of the differential voltage comparator (ALC) is determined, the SR-latch (SRL) stores it. The output of the SR-latch (SRL) remembers the output state of the differential voltage comparator (ALC) and maintains it for a certain period of time. Compared to the above-described bias application method comparator, it does not require a separate bias voltage (or current), making it highly advantageous in systems where power consumption is critical, such as in the present invention. Additionally, the time required to output the comparison result for the input signal is relatively short, making it highly advantageous for high-speed operation. Furthermore, the comparison result is quickly output by the comparison clock or trigger signal, thereby enabling accurate sampling timing control. It also features a memory function that maintains the output until the comparison clock or trigger signal changes. Additionally, a differential voltage comparator was configured and used by additionally connecting an SR-latch to both ends of the output of the ARM latch voltage comparator, so that the comparison value is generated and updated only at the rising edge (or falling edge) of the comparison clock or trigger signal each time. In the detailed embodiments of this specification, the RCV block is described based on a differential ARM latch voltage comparator that detects the difference in input voltage of the gate using a comparison clock among the circuits. In the present invention, when transmitting / receiving PAM4 signals through a link unit having four transmission lines, the maximum number of symbols used for communication is 24 (refer to the values ​​in Table 4 above). As previously mentioned, since the sum of the values ​​of the PAM4 signals applied to the four transmission lines is 0, the sum of the values ​​of the energy required to drive the corresponding symbol on the transmission line (i.e., calculating the energy consumed at VDD as a positive value and the energy consumed at GND as a negative value) is 0 regardless of which of the 24 symbols is transmitted. Therefore, since the signals applied to the four transmission lines are configured to have values ​​that are complementary (opposite polarity) to each other transmission line, the electromagnetic energy emitted from the transmission lines cancels each other out, so the radiation of EMI (Electromagnetic Interface) is very small even without separate GND shield wiring. In addition, since the signal transmitted through the four transmission lines (link units) is transmitted in a form that can be distinguished as a differential signal, the signal has a superior signal-to-noise ratio (SNR) compared to the single-ended method of the comparative example, which transmits signals independently for each transmission line, and has the characteristics of a signal with less jitter or skew. In addition, since the transmission line current consumption is the same for any of the 24 symbols, the difference between the average power consumption required during the data transmission process and the maximum peak-to-peak power consumption (maximum power consumption - minimum power consumption) can be minimized, thereby reducing the complexity of the power supply system and providing ease in designing the link (transmission line) by evenly controlling the total amount of energy cross-coupled per signal on the transmission line, and improving the overall BER. Since the present invention can express more symbols than the state symbols that can be expressed in data transmission by a link unit having the NRZ signal format of the comparative example, the number of link units used can be reduced by utilizing the number of extra symbols, or the amount of data transmission can be maximized by using all conventional link units, or some symbols can be designated and used as symbols to control communication (e.g., start, end, idle state of communication, etc.) or to check the transmission line (e.g., error correction signal, error judgment signal, transmission line quality check signal such as ECC, or control signal for quality improvement, etc.). As a method to improve the quality of the transmission line, a specific value is designated among predefined signal control methods or symbol display values. Using information regarding the value of the information transmitted from one PHY unit and the expected value of the signal received from the other PHY unit, calibration is performed on the driving value and the received value of the PHY unit, taking into account the load conditions of each transmission line. This calibration is carried out at both the signal transmission and data reception stages of the PHY unit, as described below. The DRV block of the PHY unit performing data transmission on one side optimizes driving characteristics to minimize signal jitter and maximize the area of ​​the eye pattern through pre-emphasis, and the RCV block of the PHY unit on the other side measures and adjusts the reception sensitivity and data timing of the received signal through adaptive equalization processing to perform a series of actions to improve the quality of communication. The pre-emphasis used in this invention emphasizes the high-frequency components of the signal at the transmitting end, thereby compensating for high-frequency attenuation (loss) occurring in the transmission channel. In particular, it is used to resolve the problem of signal attenuation caused by high data rates. Typically, during data transmission, it is used to compensate for the effect of signals attenuated by the transmission line by driving the signal strength to temporarily increase in data sequences with large signal variations and decrease the signal magnitude in data sequences with small signal variations. FIG. 23 is a circuit diagram illustrating another example of the DRV block shown in FIG. 12. In particular, a DRV block including a pre-emphasis circuit is shown in FIG. 15. Referring to FIG. 23, a DRV block (500) according to another example includes a first TX buffer (ATX0), a first TX resistor (RTX0), a second TX buffer (ATX1), a second TX resistor (RTX1), a pre-emphasis circuit (PEC), and a current conveyor (CC), which converts an input voltage signal into current and provides it to a transmission line through an I / O pad. The first TX resistor (RTX0) and the second TX resistor (RTX1) have resistance values ​​ranging from 300Ω to 10kΩ. Alternatively, the first TX resistor (RTX0) and the second TX resistor (RTX1) are set to resistance values ​​for generating a current between 50µA and 300µA as a data transmission signal, depending on the voltage (VDD) of the output circuit. The first TX buffer (ATX0), first TX resistor (RTX0), second TX buffer (ATX1), second TX resistor (RTX1) and current conveyor (CC) shown in FIG. 23 are given the same reference numerals as shown in FIG. 15, and their detailed description is omitted. The pre-emphasis circuit (PEC) is enabled by TX_EN[1:0] and includes a preamplifier buffer (PTX) that buffers the pre-emphasis (PEMP) signal, a variable resistor (RPH), and a variable capacitor (CPH) to temporarily increase or decrease the strength of the TX signal applied to the X-port of the current conveyor (CC). Here, the variable resistor (RPH) and the variable capacitor (CPH) apply artificial distortion to the TX signal to improve the signal characteristics of the receiving side. At least one of the variable resistor (RPH) and the variable capacitor (CPH) may be omitted. There may be one or more pre-emphasis circuits (PEC) per single transmission line. The degree of distortion caused by the pre-emphasis circuit (PEC) can be variably adjusted according to the characteristics of the transmission line. Here, the characteristics of the transmission line may include frequency response characteristics, the impedance of the transmission line, and cross-coupling characteristics for adjacent signals. FIG. 24 is a circuit diagram illustrating another example of the current conveyor shown in FIG. 15. Referring to FIG. 24, the current conveyor (CC) includes a core block (CORE) and a driving block (D2). The core block (CORE) is identical to the core block (CORE) shown in FIG. 16, so the same reference numeral is used and the detailed description is omitted. The driving block (D2) includes a first driver (1210) and a second driver (2220), and outputs a first normal output current and a second normal output current through a first ZP-port (IZPP) and a second ZP-port (IZPN) in response to a first driving voltage (P_DRV) and a second driving voltage (N_DRV). The first driver (1210) consists of a series-connected p-MOSFET MP10 and an n-MOSFET MN10. The p-MOSFET MP10 has a source to which the first power supply voltage (VDD) is applied, a gate connected to the upper current mirror terminal (1130), and a drain connected to the X-port of the n-MOSFET MN10. The n-MOSFET MN10 has a source to which the second power supply voltage (VSS) is applied, a gate connected to the lower current mirror terminal (1140), and a drain connected to the X-port of the p-MOSFET MP10. The first driver (1210) performs the function of connecting the output to the X-port of the input stage to match the structure of the second-generation current conveyor. The second driver (2220) is composed of p-MOSFET MP11 and n-MOSFET MN11 connected in series in the same structure as the first driver (1210), p-MOSFET MP12 and p-MOSFET MP13 connected to n-MOSFET MN11 to output a first normal output current through a first ZP-port (IZPP), and n-MOSFET MN12 and n-MOSFET MN13 connected to p-MOSFET MP11 to output a second normal output current through a second ZP-port (IZPN). p-MOSFET MP11 has a source to which VDD is applied, an upper current mirror terminal (1130), a gate commonly connected to the gate of p-MOSFET MP10, and a drain connected to the source of n-MOSFET MN12. n-MOSFET MN11 has a source to which VSS is applied, a lower current mirror terminal (1140), a gate commonly connected to the gate of n-MOSFET MN10, and a drain connected to the drain of p-MOSFET MP12. p-MOSFET MP12 has a source to which VDD is applied, a gate and a drain commonly connected to the source of n-MOSFET MN11. p-MOSFET MP13 has a source to which VDD is applied, a drain connected to the gate of p-MOSFET MP12, and a drain connected to the first ZP-port. p-MOSFET MP12 and p-MOSFET MP13 function as current mirrors that source current. n-MOSFET MN12 has a source connected to the drain of p-MOSFET MP11, a gate connected to the source and connected to the drain of p-MOSFET MP11, and a drain connected to VSS. n-MOSFET MN13 has a source connected to the second ZP-port, a gate connected to the gate of n-MOSFET MN12, and a drain connected to VSS. n-MOSFET MN12 and n-MOSFET MN13 function as current mirrors that sink the current. Unlike the first driver (1210) being connected to the X-port of the differential input stage of the upper differential input terminal (1110) and the lower differential input terminal (1120), the second driver (2220) is connected to the first ZP-port (IZPP) and the second ZP-port (IZPN) for output driving. Meanwhile, in FIG. 17, the voltage generating unit (510) that generates an output voltage based on the mirrored current of the ZP-port, which is the output of the current conveyor, is described as being composed of an RC parallel circuit, but the voltage generating unit (510) may also be composed of a resistor element alone. FIG. 25 is a circuit diagram illustrating an example of a voltage generation unit illustrated in FIG. 17. Referring to FIG. 25, the voltage generating unit (510) includes a source follower (512) composed of a first NMOS M1 and a first PMOS M2 with common gates, and a CMOS inverter (514) composed of a second PMOS M3 and a second NMOS M4 with common gates. The first NMOS M1 includes a drain connected to the power supply voltage, a gate connected to the gate of the first PMOS M1, and a source connected to the drain of the first PMOS M2. The first PMOS M2 includes a drain connected to the source of the first NMOS M1, a gate connected to the gate of the first NMOS M1, and a source connected to the ground power supply. The source of the first NMOS M1 and the drain of the first PMOS M2 are connected in common to apply an input current Iin. The gate of the first NMOS M1 and the gate of the first PMOS M2 are connected in common to output an output voltage Vout. The second PMOS M3 includes a drain connected to the power supply voltage, a gate connected to the gate of the second NMOS M4, and a source connected to the drain of the second PMOS M4. The second NMOS M4 includes a drain connected to the source of the second PMOS M3, a gate connected to the gate of the second PMOS M3, and a source connected to the ground power supply. The source of the second PMOS M3 and the drain of the second NMOS M4 are commonly connected to output an output voltage Vout. The input current Iin represents the difference in input currents, and the output voltage Vout is the result of the comparison, which is amplified by the subsequent CMOS inverters (M3 and M4) and output as a rail-to-rail signal. In this embodiment, the voltage generation unit (510) uses source followers (M1 and M2) as input stages and CMOS inverters (M3 and M4) as positive feedback, thereby lowering the input resistance and shortening the response time compared to a voltage generation unit based on a conventional current mirror. Meanwhile, in the dynamic response of a small input current, there exists a temporary deadband region where both input transistors (M1 and M2) are turned off, and the input resistance is high. Therefore, when the input current decreases, the dynamic response time of the voltage generation unit (510) increases rapidly. FIG. 26 is a circuit diagram illustrating another example of the voltage generation unit shown in FIG. 17. Referring to FIG. 26, the voltage generation unit (510) includes source followers (M1 and M2), diode operating transistors (MB1 and MB2), four current sources (IB1A, IB1B, IB2A, IB2B) for the bias circuit, and CMOS inverters (M3 and M4). In the voltage generation unit (510) illustrated in FIG. 26, the biasing method of the input stage is changed from Class B to Class AB operation, and two diode-operated transistors (MB1 and MB2) are added compared to the voltage generation unit (510) illustrated in FIG. 19. This reduces the deadband area and decreases the response time for small input currents. FIG. 27 is a circuit diagram illustrating another example of the RCV block shown in FIG. 12. In particular, a circuit diagram of an RCV block configured to include the current conveyor shown in FIG. 17 is shown. Referring to FIG. 27, the RCV block includes a first current conveyor (CC1), a second current conveyor (CC2), a third current conveyor (CC3), a fourth current conveyor (CC4), a first differential current comparator (COP1), a second differential current comparator (COP1), a third differential current comparator (COP3), a fourth differential current comparator (COP4), a fifth differential current comparator (COP5), and a sixth differential current comparator (COP6). The first current conveyor (CC1) includes an X-port connected to the first pad (PAD[0]) to which current is applied, a Y-port to which a common mode voltage (VCOM) on the transmission line is applied, a first ZP-port (IZP) that mirrors and outputs the first normal output current, and a second ZP-port (IZN) that mirrors and outputs the second normal output current. Here, the first ZP-port (IZP) and the second ZP-port (IZN) of the first current conveyor (CC1) are each connected to the first differential current comparator (COP1), the fourth differential current comparator (COP4), and the fifth differential current comparator (COP5) to output the mirrored current. The second current conveyor (CC2) includes an X-port connected to the second pad (PAD[1]) to which current is applied, a Y-port to which a common mode voltage (VCOM) on the transmission line is applied, a first ZP-port (IZP) that mirrors and outputs the first normal output current, and a second ZP-port (IZN) that mirrors and outputs the second normal output current. Here, the first ZP-port (IZP) and the second ZP-port (IZN) of the second current conveyor (CC2) are each connected to the first differential current comparator (COP1), the second differential current comparator (COP2), and the fifth differential current comparator (COP5) to output the mirrored current. The third current conveyor (CC3) includes an X-port connected to the third pad (PAD[2]) to which current is applied, a Y-port to which a common mode voltage (VCOM) on the transmission line is applied, a first ZP-port (IZP) that mirrors and outputs a first normal output current, and a second ZP-port (IZN) that mirrors and outputs a second normal output current. Here, the first ZP-port (IZP) and the second ZP-port (IZN) of the third current conveyor (CC3) are each connected to the second differential current comparator (COP2), the third differential current comparator (COP3), and the fifth differential current comparator (COP5) to output the mirrored current. The fourth current conveyor (CC4) includes an X-port connected to the fourth pad (PAD[3]) to which current is applied, a Y-port to which a common mode voltage (VCOM) on the transmission line is applied, a first ZP-port (IZP) that mirrors and outputs a first normal output current, and a second ZP-port (IZN) that mirrors and outputs a second normal output current. Here, the first ZP-port (IZP) and the second ZP-port (IZN) of the fourth current conveyor (CC4) are each connected to the third differential current comparator (COP3), the fourth differential current comparator (COP4), and the sixth differential current comparator (COP6) to output the mirrored current. The first differential current comparator (COP1) outputs a first differential current (OUT[0]) by differentially comparing the first and second normal output currents provided from the first current conveyor (CC1) and the first and second normal output currents provided from the second current conveyor (CC2) in response to a clock signal. The second differential current comparator (COP2) outputs a second differential current (OUT[1]) by differentially comparing the first and second normal output currents provided from the second current conveyor (CC2) and the first and second normal output currents provided from the third current conveyor (CC3) in response to a clock signal. The third differential current comparator (COP3) outputs a third differential current (OUT[2]) by differentially comparing the first and second normal output currents provided from the third current conveyor (CC3) and the first and second normal output currents provided from the fourth current conveyor (CC4) in response to a clock signal. The fourth differential current comparator (COP4) outputs a fourth differential current (OUT[3]) by differentially comparing the first and second normal output currents provided from the first current conveyor (CC1) with the first and second normal output currents provided from the fourth current conveyor (CC4) in response to a clock signal. The fifth differential current comparator (COP5) outputs a fifth differential current (OUT[4]) by differentially comparing the first and second normal output currents provided from the first current conveyor (CC1) and the first and second normal output currents provided from the third current conveyor (CC3) in response to a clock signal. The sixth differential current comparator (COP6) outputs a sixth differential current (OUT[5]) by differentially comparing the first and second normal output currents provided from the second current conveyor (CC2) and the first and second normal output currents provided from the fourth current conveyor (CC4) in response to a clock signal. FIG. 28 is a circuit diagram illustrating another example of the RCV block shown in FIG. 12. Referring to FIG. 28, an RCV block (500) according to another example includes a voltage generator (540) that converts the current of a PAM4 signal provided through a transmission line into a voltage, and a voltage comparator module (530) that differentially compares the PAM4 signals converted into voltage by the voltage generator (540). Since the voltage comparator module (530) shown in FIG. 28 is identical to the voltage comparator module (530) shown in FIG. 18, the same reference numerals are used and a detailed description is omitted. The voltage generation unit (540) includes a plurality of variable resistors (Rin) connected to a transmission line at one end, a plurality of current conveyors (CC) connected to the other end of the variable resistors (Rin), and a plurality of RC parallel circuits disposed between the current conveyors (CC) and the voltage comparator module (530). Since the current conveyors (CC) and RC parallel circuits shown in FIG. 28 are identical to the current conveyors (CC) and RC parallel circuits shown in FIG. 18, the same reference numerals are used and a detailed description is omitted. The RCV block (500) shown in FIG. 28 includes an additional variable resistor between the pad and the X-port of the current conveyor compared to the RCV block (500) shown in FIG. 18. The purpose of the variable resistor (Rin), specifically the reason why a variable resistor is required for impedance matching in the X-port, is explained as follows. In order to receive the current transmitted from the DRV block, the current conveyor of the RCV block drives the opposite current to the current transmitted to the X-port. At this time, if the impedance value of the transmission line matches the output impedance of the X-port, the received signal can guarantee optimal rising time and polling time without overshoot or undershoot, thereby improving communication quality. Transmission lines can vary in shape, length, and configuration conditions, such as PCBs, TSVs, and wires. Consequently, the impedance values ​​of the transmission lines may differ. Therefore, it is necessary to match (or make the impedances equal) the output impedance of the X-port of the RCV block, which is the receiving end, with the impedance of the transmission line. To achieve such impedance matching, the present invention inserts a series resistor capable of changing and adjusting its resistance value between the PAD of the RCV block, which is the receiving end, and the X-port of the current conveyor. FIGS. 29a, FIG. 29b, and FIG. 29c are graphs showing signal amplitudes according to the output impedance of the X-port of the RCV block shown in FIG. 28. In particular, FIG. 29a is a graph showing the waveform when the output impedance of the X-port of the RCV block shown in FIG. 28 is low, FIG. 29b is a graph showing the waveform when the output impedance of the RCV X-port of the RCV block shown in FIG. 28 is high, and FIG. 29c is a graph showing the waveform when the output impedance of the RCV X-port of the RCV block shown in FIG. 28 is moderate. Referring to FIG. 29a, when the output impedance of the X-port is smaller than the impedance of the transmission line, waveforms of overshoot and undershoot that interfere with communication are generated. In this case, by increasing the resistance value of Rin to control the output impedance of the X-port to match the impedance of the transmission line, it is possible to generate a signal waveform used for stable communication as shown in FIG. 29c. Referring to FIG. 29b, when the output impedance of the X-port is greater than the impedance of the transmission line, there is no overshoot or undershoot, but the rising time and falling time are significantly increased. In this case, by reducing the resistance value of Rin to control the output impedance of the X-port to match the impedance of the transmission line, it is possible to ensure optimal rising time and falling time as shown in FIG. 29c, thereby generating a signal waveform used for stable communication. FIGS. 30a and FIGS. 30b are circuit diagrams for explaining other examples of the current comparator module shown in FIG. 17 or FIG. 18. Referring to FIGS. 30a and 30b, the RCV block includes a first current conveyor (CC11), a second current conveyor (CC12), a third current conveyor (CC21), a fourth current conveyor (CC22), a fifth current conveyor (CC31), a sixth current conveyor (CC32), a seventh current conveyor (CC41), an eighth current conveyor (CC42), a ninth current conveyor (CC51), a tenth current conveyor (CC52), an eleventh current conveyor (CC61), a twelfth current conveyor (CC62), a first differential current comparator (COP1), a second differential current comparator (COP1), a third differential current comparator (COP3), a fourth differential current comparator (COP4), a fifth differential current comparator (COP5), and a sixth differential current comparator (COP6). The first current conveyor (CC11) includes an X-port connected to the first pad (IN[0]) to which current is applied, a Y-port to which a common mode voltage (VCOM) on the transmission line is applied, a first ZP-port (IZP) that mirrors the first normal output current and outputs it to the first differential current comparator (COP1), and a second ZP-port (IZN) that mirrors the second normal output current and outputs it to the first differential current comparator (COP1). The second current conveyor (CC12) includes an X-port connected to the second pad (IN[1]) to which current is applied, a Y-port to which a common mode voltage (VCOM) on the transmission line is applied, a first ZP-port (IZP) that mirrors the first normal output current and outputs it to the first differential current comparator (COP1), and a second ZP-port (IZN) that mirrors the second normal output current and outputs it to the first differential current comparator (COP1). The third current conveyor (CC21) includes an X-port connected to the second pad (IN[1]) to which current is applied, a Y-port to which a common mode voltage (VCOM) on the transmission line is applied, a first ZP-port (IZP) that mirrors the first normal output current and outputs it to the second differential current comparator (COP2), and a second ZP-port (IZN) that mirrors the second normal output current and outputs it to the second differential current comparator (COP2). The fourth current conveyor (CC22) includes an X-port connected to the third pad (IN[2]) to which current is applied, a Y-port to which a common mode voltage (VCOM) on the transmission line is applied, a first ZP-port (IZP) that mirrors the first normal output current and outputs it to the second differential current comparator (COP2), and a second ZP-port (IZN) that mirrors the second normal output current and outputs it to the second differential current comparator (COP2). The fifth current conveyor (CC31) includes an X-port connected to the third pad (IN[2]) to which current is applied, a Y-port to which a common mode voltage (VCOM) on the transmission line is applied, a first ZP-port (IZP) that mirrors the first normal output current and outputs it to the third differential current comparator (COP3), and a second ZP-port (IZN) that mirrors the second normal output current and outputs it to the third differential current comparator (COP3). The sixth current conveyor (CC32) includes an X-port connected to the fourth pad (IN[3]) to which current is applied, a Y-port to which a common mode voltage (VCOM) on the transmission line is applied, a first ZP-port (IZP) that mirrors the first normal output current and outputs it to the third differential current comparator (COP3), and a second ZP-port (IZN) that mirrors the second normal output current and outputs it to the third differential current comparator (COP3). The seventh current conveyor (CC41) includes an X-port connected to the third pad (IN[2]) to which current is applied, a Y-port to which a common mode voltage (VCOM) on the transmission line is applied, a first ZP-port (IZP) that mirrors the first normal output current and outputs it to the fourth differential current comparator (COP4), and a second ZP-port (IZN) that mirrors the second normal output current and outputs it to the fourth differential current comparator (COP4). The eighth current conveyor (CC42) includes an X-port connected to the first pad (IN[0]) to which current is applied, a Y-port to which a common mode voltage (VCOM) on the transmission line is applied, a first ZP-port (IZP) that mirrors the first normal output current and outputs it to the fourth differential current comparator (COP4), and a second ZP-port (IZN) that mirrors the second normal output current and outputs it to the fourth differential current comparator (COP4). The ninth current conveyor (CC51) includes an X-port connected to the first pad (IN[0]) to which current is applied, a Y-port to which a common mode voltage (VCOM) on the transmission line is applied, a first ZP-port (IZP) that mirrors the first normal output current and outputs it to the fifth differential current comparator (COP5), and a second ZP-port (IZN) that mirrors the second normal output current and outputs it to the fifth differential current comparator (COP5). The 10th current conveyor (CC52) includes an X-port connected to the 3rd pad (IN[2]) to which current is applied, a Y-port to which a common mode voltage (VCOM) on the transmission line is applied, a 1st ZP-port (IZP) that mirrors the 1st normal output current and outputs it to the 5th differential current comparator (COP5), and a 2nd ZP-port (IZN) that mirrors the 2nd normal output current and outputs it to the 5th differential current comparator (COP5). The 11th current conveyor (CC61) includes an X-port connected to the 2nd pad (IN[1]) to which current is applied, a Y-port to which a common mode voltage (VCOM) on the transmission line is applied, a 1st ZP-port (IZP) that mirrors the 1st normal output current and outputs it to the 6th differential current comparator (COP6), and a 2nd ZP-port (IZN) that mirrors the 2nd normal output current and outputs it to the 6th differential current comparator (COP6). The 12th current conveyor (CC62) includes an X-port connected to the 3rd pad (IN[2]) to which current is applied, a Y-port to which a common mode voltage (VCOM) on the transmission line is applied, a 1st ZP-port (IZP) that mirrors the 1st normal output current and outputs it to the 6th differential current comparator (COP6), and a 2nd ZP-port (IZN) that mirrors the 2nd normal output current and outputs it to the 6th differential current comparator (COP6). The first differential current comparator (COP1) outputs a first differential current (OUT[0]) by differentially comparing the first and second normal output currents provided from the first current conveyor (CC11) and the first and second normal output currents provided from the second current conveyor (CC12) in response to a clock signal. The second differential current comparator (COP2) outputs a second differential current (OUT[1]) by differentially comparing the first and second normal output currents provided from the third current conveyor (CC21) and the first and second normal output currents provided from the fourth current conveyor (CC22) in response to a clock signal. The third differential current comparator (COP3) outputs a third differential current (OUT[2]) by differentially comparing the first and second normal output currents provided from the fifth current conveyor (CC31) and the first and second normal output currents provided from the sixth current conveyor (CC32) in response to a clock signal. The fourth differential current comparator (COP4) outputs a fourth differential current (OUT[3]) by differentially comparing the first and second normal output currents provided from the seventh current conveyor (CC41) and the first and second normal output currents provided from the eighth current conveyor (CC42) in response to a clock signal. The fifth differential current comparator (COP5) outputs a fifth differential current (OUT[4]) by differentially comparing the first and second normal output currents provided from the ninth current conveyor (CC51) and the first and second normal output currents provided from the tenth current conveyor (CC52) in response to a clock signal. The sixth differential current comparator (COP6) outputs a sixth differential current (OUT[5]) by differentially comparing the first and second normal output currents provided from the first current conveyor (CC61) and the first and second normal output currents provided from the second current conveyor (CC62) in response to a clock signal. FIG. 31 is a circuit diagram for explaining the first differential current comparator of the current comparator module shown in FIG. 27 or FIG. 30. Referring to FIG. 31, the first differential current comparator (COP1) includes a dynamic latch comparator and generates an output signal based on the difference between two input currents. That is, the first differential current comparator (COP1) generates an output signal based on the difference between two input currents input through the first positive input port (IZPP) and the second positive input port (IZPN). Alternatively, the first differential current comparator (COP1) generates an output signal based on the difference between two input currents input through the first negative input port (IZNP) and the second negative input port (IZNN). The active latch comparator includes p-MOSFET MP0, p-MOSFET MP1, p-MOSFET MP2, p-MOSFET MP3, n-MOSFET MN0, n-MOSFET MN1, n-MOSFET MN2, n-MOSFET MN3, p-MOSFET MP4, and p-MOSFET MP5. p-MOSFET MP0 is connected to the first positive input port (IZPP) through its source, connected to the clock (CLK) through its gate, and connected to the power supply voltage (VDD) through its drain. p-MOSFET MP1 is connected to the first positive input port (IZPP) through its source, connected to the source of p-MOSFET MP2 through its gate, and connected to the power supply voltage (VDD) through its drain. p-MOSFET MP2 is connected to the second positive input port (IZPN) through its source, connected to the sources of p-MOSFET MP0 and p-MOSFET MP1 through its gate, and connected to the power supply voltage (VDD) through its drain. p-MOSFET MP3 is connected to the second positive input port (IZPN) through its source, connected to the clock (CLK) through its gate, and connected to the power supply voltage (VDD) through its drain. n-MOSFET MN0 is connected to ground through its source, connected to the gate of p-MOSFET MP1 through its gate, and connected to the first negative input port (IZNP) through its drain. n-MOSFET MN1 is connected to ground through its source, connected to the gate of p-MOSFET MP2 through its gate, and connected to the second negative input port (IZNN) through its drain. n-MOSFET MN2 is connected to the first positive input port (IZNP) through its source, connected to the clock (CLK) through its gate, and connected to the source of p-MOSFET MP1 through its drain. n-MOSFET MN3 is connected to the second positive input port (IZNN) through its source, connected to the clock (CLK) through its gate, and connected to the source of p-MOSFET MP2 through its drain. p-MOSFET MP4 is connected to the first positive input port (IZNP) through its source, connected to the gate of p-MOSFET MP5 through its gate, and connected to the source of p-MOSFET MP1 through its drain. p-MOSFET MP5 is connected to the second positive input port (IZNN) through its source, connected to the gate of p-MOSFET MP4 through its gate, and connected to the source of p-MOSFET MP2 through its drain. Although the first differential current comparator (COP1) has been described above, the second differential current comparator (COP2) through the sixth differential current comparator (COP6) are identical, so a detailed description thereof is omitted. FIG. 32 is a circuit diagram for explaining the first differential current comparator of the current comparator module shown in FIG. 27 or FIG. 30. Referring to FIG. 32, the first differential current comparator (COP1) includes a dynamic latch comparator and an SR-latch, and generates an output signal based on the difference between two input currents. That is, the first differential current comparator (COP1) generates an output signal based on the difference between two input currents input through the first positive input port (IZPP) and the second positive input port (IZPN). Alternatively, the first differential current comparator (COP1) generates an output signal based on the difference between two input currents input through the first negative input port (IZNP) and the second negative input port (IZNN). The active latch comparator includes p-MOSFET MP0, p-MOSFET MP1, p-MOSFET MP2, p-MOSFET MP3, n-MOSFET MN0, n-MOSFET MN1, n-MOSFET MN2, n-MOSFET MN3, p-MOSFET MP4, and p-MOSFET MP5, and as described in FIG. 31, a detailed description is omitted. The SR-latch includes a first inverter (INV1), a second inverter (INV2), a first NAND gate (NAND1), and a second NAND gate (NAND2). Specifically, the first inverter (INV1) is connected to a first negative input port (IZNP) through an input terminal, and the second inverter (INV2) is connected to a second negative input port (IZNN) through an input terminal. The first NAND gate (NAND1) is connected to the output terminal of the first inverter (INV1) through a first input terminal and to the output terminal of the second NAND gate (NAND2) through a second input terminal. The second NAND gate (NAND2) is connected to the output terminal of the first NAND gate (NAND1) through a first input terminal and to the output terminal of the second inverter (INV2) through a second input terminal. When operating, if the current of the first negative input port (IZNP) is high and the current of the second negative input port (IZNN) is high, it is in a data preservation state. If the current of the first negative input port (IZNP) is low and the current of the second negative input port (IZNN) is low, it is in a data extinction state. If the current of the first negative input port (IZNP) is low and the current of the second negative input port (IZNN) is high, it is in a data set state. If the current of the first negative input port (IZNP) is high and the current of the second negative input port (IZNN) is low, it is in a data reset state. Meanwhile, the equalization used in the present invention uses a method to improve the quality of the received signal by controlling the reception sensitivity of the RCV block, changing the bias current of the comparator, or controlling the data comparison timing to reduce the Inter-symbol Interference (ISI) occurring in the PAM4 signal. Figure 33, described below, illustrates an eye-diagram of a PAM4 signal with vulnerable characteristics, and Figure 34 illustrates an eye-diagram of a PAM4 signal with improved characteristics through a pre-emphasis circuit (PEC). FIG. 33 illustrates an eye-diagram of a PAM4 signal received from a PAM4 signal basic communication system according to a comparative example. Referring to Fig. 33, it can be seen that in the eye pattern, the area of ​​the eye region (the white part at the center) is not wide, and jitter occurs in which the period of the data clock is not constant. This narrow eye pattern area and increased jitter are attributed to the driving characteristics of the high-speed PHY unit and the signal transmission characteristics of the transmission line. The shape of such a narrow eye pattern and large jitter characteristics increase the possibility of errors in the transmission line and cause an increase in BER, and as a method to improve this, the use of a pre-emphasis function is required. FIG. 34 illustrates an eye-diagram of a PAM4 signal received from a PAM4 signal basic communication system according to the present invention. In particular, when pre-emphasis is performed at the DRV block side and equalization is performed at the RCV block side, the eye pattern of the received PAM4 signal is illustrated. Referring to Fig. 34, it can be seen that the area of ​​the eye region (the white part at the center) in the eye pattern is large, and the period of the data clock is relatively constant, so the signal waveform has reduced jitter. Since data transmission speed or BER can be improved by performing pre-emphasis by identifying the signal transmission characteristics of a high-speed transmission line, high-speed communication systems generally include pre-emphasis and equalization circuits, and in the example of the present invention, they were applied according to the characteristics of the circuit and the transmission line. Hereinafter, an embodiment of the present invention is described in which a PAM4 signal is transmitted and received through a link unit having four transmission lines, and a current conveyor is used in a DRV block and an RCV block. An embodiment of the present invention is a system that transmits and receives data as is and decodes it through encoding that matches 24 symbols 1:1 with the data to be transmitted as is. An embodiment of the present invention is a method for transmitting the largest number of symbols compared to existing methods, without the need to control the DC level of the link unit (transmission line) as in the parallel transmission method of the comparative example. Table 6 is a table to explain the number of transmission bits per transmission line according to the parallel transmission method of the comparative example (NRZ method) and the transmission method of the present invention (PAM4 method), respectively. [Table 6] Referring to Table 6, when four transmission lines are expressed as the basic unit for data transmission, the number of symbols in a transmission line using the parallel transmission method (i.e., NRZ method) of the comparative example is 2^4, so a total of 16 symbols can be transmitted at once. This means that 4 bits of data can be transmitted per four transmission lines at once. In contrast, the present invention transmits and receives data using symbols composed of 24 differential PAM4 signals selected from 256 symbols that can be implemented in four transmission lines. This allows 24 different symbols to be transmitted per link unit having four transmission lines. This means that 4.585 bits of data can be transmitted per four transmission lines at once. Meanwhile, when 16 link units are used (i.e., when the link is configured with 64 transmission lines), the number of symbols that can be transmitted at once in the NRZ method of the comparative example is 1.84467E+19 (2^64 or 16^16). In contrast, the number of symbols that can be transmitted at once in the PAM4 method of the present invention is 1.21166E+22 (24^16). Therefore, the PAM4 method of the present invention can transmit approximately 656.8 times more symbols than the NRZ method of the comparative example on the same link. In addition, to transmit 64-bit data at once, the NRZ method of the comparative example requires a communication link with 64 transmission lines. However, the PAM4 method of the present invention can be implemented with a link having 56 transmission lines. Therefore, the PAM4 method of the present invention can reduce the number of transmission lines compared to the NRZ method of the comparative example. In the case of the NRZ method of the comparative example, the number of symbols that can be transmitted at once in a link with 64 (link unit x 16) transmission lines, that is, the number of symbols in a link with 64 transmission lines, is 16^16(2^64)=18,446,744,073,709,551,616. In contrast, in the case of the PAM4 method of the present invention, the number of symbols that can be transmitted at once in a link having 56 (link unit of the present invention × 14) transmission lines, that is, the number of symbols in a link having 56 transmission lines is 24^14 = 21,035,720,123,168,587,776. In summary, according to the PAM4 method of the present invention, the number of symbols of a link having 64 transmission lines of the NRZ method of the comparative example can be transmitted with the number of symbols of a link having 56 transmission lines. FIG. 35 is a block diagram illustrating the first encoding / decoding unit illustrated in FIG. 11. Referring to FIGS. 11 and FIGS. 35, the first encoding / decoding unit (220) includes encoder logic (222) and decoder logic (224). When transmitting a signal, the encoder logic (222) receives data (TX_DATA[n:0]) to be transmitted from a communication entity, for example, a processor unit or a memory device, and generates a TX signal (TX[7:0]) and a TX enable signal (TX_EN[7:0]) that drive the first PHY unit (210) using a symbol that matches the data 1:1. The TX signal (TX[7:0]) and the TX enable signal (TX_EN[7:0]) generated by the encoder logic (222) are converted into the form of current through a current conveyor and then output to a link unit through each I / O pad. When data is received, the decoder logic (224) receives six PAM4 comparison signals (RX[5:0]) output from the second PHY unit (310), restores them into 24 symbols, and converts the restored symbols into digital values ​​of data (RX_DATA[n:0]). Examples of encoding and decoding methods for symbols are shown in Table 4 above. Referring again to Table 4, it shows the 24 symbols defined by graph coloring theory, the assignment of decimal and 24-base numbers to the corresponding symbols, and the definition of the signal value per transmission line (PAM4 value / value per transmission line) for each corresponding symbol. In addition, the comparison values ​​of six distinct receive comparators are indicated in RX[0] to RX[5], and the results of the six comparators are represented as distinct decimal values ​​RX[0:5] with 6 bits. When link units with four transmission lines are each driven by PAM4 signals, a total of 256 possible cases are possible. However, as previously explained, using graph coloring theory, the number of cases where the sum of the PAM4 signals is "0" and the results of the six comparators have unique, non-overlapping values ​​is 24. In this embodiment, only 24 symbols are used for communication. Decimal data from 0 to 23 can be defined as base-24 symbols as follows. [0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F,G,H,I,J,K,L,M,N] That is, when expressing decimal data as base-24 data, numbers greater than 10 in decimal can be assigned base-24 numbers in alphabetical order. Although the assignment was made as described above in the present invention, this is merely an example, and any method of notation is possible as long as it is a symbolic symbol capable of distinguishing 24 values. FIG. 36 is a diagram for explaining symbol restoration by the first communication unit or the second communication unit shown in FIG. 11. Referring to FIGS. 11 and FIGS. 36, when 24-digit data [0, C, 1, 4, 9, 3, D, J, A, L, 0] (or decimal data with the same meaning [0, 12, 1, 4, 9, 3, 13, 19, 10, 21, 0]) is transmitted from the first communication unit (200) through the link unit (100), the process of finding a symbol (mapping) from the signal received by the second communication unit (300) through the link unit (100) and decoding the transmitted signal is shown. Transmitted or received data is transmitted or received at a predetermined clock data (CD) rate. In FIG. 36, the data recovery process performed at the receiver of the second communication unit (300) is described, but the encoding process performed at the transmitter proceeds in the reverse order of the recovery process performed at the receiver, so a separate description is omitted. If data with CD=0 is received, the value of RX[0:5] is binary

[0100] It can be seen that this binary value corresponds to the A0 symbol in the symbol table 4 above. The A0 symbol represents 0 in decimal, and the base-24 value also represents 0. This process is defined as decoding, and it is the case where 0 in decimal or 0 in base-24 is received. When data with CD=1 is received, the value of RX[0:5] is binary [111011]. It can be seen that this binary value corresponds to the B0 symbol in the symbol table 4 above. The B0 symbol represents the decimal number 12, and the base-24 value represents C. When data with CD=2 to CD=10 is received, the data is received and decoded in the same manner as described above, and the transmitted data value is recovered from the difference of the received PAM4 signal. As described above, the present invention can solve various problems occurring in high-speed parallel transmission systems. While it is possible to transmit by configuring multiple existing high-speed serial signal transmission methods (e.g., USB, SATA, PCI Express, etc.) in parallel, the present invention is clearly distinguished from the existing method in the following respects. Conventional high-speed serial signal transmission methods define a single communication unit called a "channel" and implement data transmission by configuring multiple channels in parallel. However, this method has disadvantages such as hardware complexity for configuring individual channels and high power consumption. In particular, SerDes (Serializer / Deserializer) are essential in high-speed serial transmission methods, and additional clock generation and PLLs (Phase-Locked Loops) are required to convert parallel data to serial data or vice versa. This increases system complexity and power consumption, making it inefficient in environments where transmission lines are short and easy to manage. On the other hand, the present invention provides improved performance compared to the existing Non-Return-to-Zero (NRZ) method through differential signaling by applying PAM signals to high-speed parallel transmission lines (e.g., T-link, TSV-link). The present invention converts the signal to be transmitted into a PAM signal (e.g., PAM3, PAM4, PAM5, PAM6, etc.) to increase the number of bits that can be transmitted per transmission line, thereby enabling the transmission of more data using fewer transmission lines. This significantly reduces hardware complexity and power consumption compared to existing parallel systems and increases the efficiency of high-speed parallel transmission. In addition, the present invention is designed so that the electrical signal of the transmission line is always maintained constant, thereby preventing extreme changes in energy consumption according to data patterns. In the case of a system composed of 1024 (1024 bits) transmission lines in a conventional high-speed parallel communication where one transmission line uses 1 pJ / bit for data transmission, the energy (power) consumed by the transmission line is theoretically 0 pJ when the previous data and the current data are identical during data transmission. On the other hand, when all previous data is '0' and all current data is "1", the energy consumed (power) charged from VDDQ (I / O Power, Supply) becomes 1024 pJ. Conversely, when all previous data is 1 and all current data is 0, the energy consumed (power) discharged from VSSQ (I / O Power Ground) becomes 1024 pJ, so the ratio of minimum energy consumed (power) to maximum energy consumed (power) reaches an extreme value (a theoretical value of infinity). This places a heavy burden on the power supply system and can cause signal quality degradation (SNR, BER, etc.). However, the present invention is designed to maintain constant power consumption, so that the ratio of maximum to minimum energy theoretically approaches "1," thereby simplifying the power supply system and ensuring communication stability. In addition, power consumption per bit is lower than that of existing technologies, offering the advantage of reducing overall system power consumption and lowering heat generation. In addition, the present invention is designed such that during the process of encoding / decoding transmission data into PAM-based differential signals, the sum of the electrical signals applied to the transmission line is always "0" for each unit (e.g., 3, 4, 5, 6, etc.) constituting the transmission line (e.g., T-link, TSV-link). This drastically reduces the difference between the maximum peak power and the average power consumption (RMS power) that may occur in conventional parallel signal transmission methods, and consequently, minimizes power consumption. In addition, the present invention has the effect of not only reducing power consumption of a data transmission system at the system level, but also lowering the difficulty of designing power and signal wiring for the power supply system, PCB, silicon interposer, and glass interposer, and reducing manufacturing costs. In this way, the present invention improves the problems of energy consumption imbalance, SNR, and BER compared to existing parallel communication methods, and guarantees a high data transmission rate with fewer transmission lines and lower power consumption. Although the invention has been described above with reference to embodiments, those skilled in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and scope of the invention as described in the following claims. <Explanation of Symbols> 10: Transmission line 21: First process unit 22 : 1st Encoder / Decoder 23 : 1st Transmit / Receive Buffer 31 : 2nd transmit / receive buffer 32 : 2nd encoder / decoder 33: 2nd Process Unit 200: 1st Communication Unit 210: 1st PHY Unit 220: 1st Encoding / Decoding Unit 230: 1st Pre-encoder 240: 1st Post-decoder 310: 2nd PHY Unit 320: 2nd Encoding / Decoding Unit 330: 2nd Pre-encoder 340: 2nd Post-decoder 300: 2nd Communication Unit

Claims

1. A step of inputting a first condition, a second condition, a third condition, and a fourth condition to be verified in a program prepared for selecting a symbol - wherein the first condition is a condition in which the sum of difference values ​​based on the common voltage of all transmission lines is 0V, the second condition is a condition in which adjacent transmission lines have different signal levels, the third condition is a condition in which elements have different differential signals converted into differential signals through signal level comparison between adjacent transmission lines, and the fourth condition is a condition in which elements have different differential signals converted into differential signals through signal level comparison between non-adjacent transmission lines; A step of inputting the number of transmission lines and the number of signal levels and determining the type of signal level; Step of initializing the candidate list and the result list; A step of inputting all possible cases that may occur in a transmission line into the above candidate list, considering the number of received transmission lines, the number of signal levels, and the types of signal levels; A step of extracting one element from the above candidate list; If the above-mentioned retrieved element is checked as satisfying the above-mentioned first condition, the retrieved element is entered into the result list, and then feedback is given to the step of retrieving one element; If the above-mentioned retrieved element is checked as satisfying the above-mentioned second condition, the retrieved element is entered into the result list, and then feedback is provided to the step of retrieving one element; If the above-mentioned retrieved element is checked as satisfying the above-mentioned third condition, the retrieved element is entered into the result list, and then feedback is provided to the step of retrieving one element; If the above-mentioned one retrieved element is checked as satisfying the above-mentioned fourth condition, the step of inputting the retrieved element into the result list and then feeding back to the step of retrieving one element; and A symbol selection method characterized by including a step of outputting a result list when it is checked that there are no remaining elements in the candidate list.

2. A symbol selection method according to claim 1, characterized in that the element refers to each of the cases according to the number of transmission lines and the number of signal levels.

3. A link unit including multiple transmission lines; A first communication unit connected to one side of the above-mentioned link unit to perform transmission and reception of a Pulse Amplitude Modulation (PAM) signal; and It includes a second communication unit connected to the other side of the above link unit to perform transmission / reception of PAM signals, The number of PAM signal levels driving the transmission line is greater than or equal to the number of transmission lines, the sum of the PAM values ​​of each transmission line is "0", and signal pairs in which the PAM values ​​of each transmission line driving simultaneously have different signal levels are assigned to the vertices and line segments of an inference graph shape using graph coloring theory and defined as symbols according to the determined relationship. A data communication system characterized in that each of the first communication unit and the second communication unit encodes transmitted data to match a corresponding symbol and transmits it, and decodes and restores received data.

4. In paragraph 3, each of the first communication unit and the second communication unit is, A PHY unit comprising one or more DRV blocks that convert a TX signal of an externally input voltage level into current and output it to a transmission line through an I / O pad, and one or more RCV blocks that receive a PAM signal transmitted through the link unit, wherein one side is connected to one side of the link unit to transmit / receive the PAM signal; and A data communication system characterized by including an encoding / decoding unit, one side of which is connected to the other side of the PHY unit.

5. In paragraph 4, the above DRV block is, A first TX buffer that buffers a first TX signal; A first TX resistor, one end of which is connected to the output terminal of the first TX buffer and the other end of which is connected to an I / O pad; A second TX buffer that buffers a second TX signal; and A data communication system characterized by including a second TX resistor, one end of which is connected to the output terminal of the second TX buffer and the other end of which is connected to the I / O pad.

6. In paragraph 4, the above DRV block is, A PAM encoding unit that encodes a TX signal according to a TX enable signal; A first buffer comprising a front-end inverter enabled by a TX enable signal to invert a TX signal, and a rear-end inverter connected to the rear end of the front-end inverter and enabled by a TX enable signal to invert a signal inverted by the front-end inverter; and A data communication system characterized by including a voltage-current converter that converts a PAM signal buffered by the first buffer into a current.

7. In paragraph 4, the above DRV block is, A first TX buffer that buffers a first TX signal; A first TX resistor connected to the output terminal of the first TX buffer; A second TX buffer that buffers the second TX signal; A second TX resistor, one end of which is connected to the output terminal of the second TX buffer; and A data communication system characterized by including a current conveyor comprising an X-port connected to the common terminal of the first TX resistor and the second TX resistor, a Y-port to which a common mode voltage on the transmission line is applied, and a ZP-port connected to an I / O pad.

8. In paragraph 4, the above DRV block is, A first TX buffer that buffers a first TX signal; A first TX resistor connected to the output terminal of the first TX buffer; A second TX buffer that buffers the second TX signal; A second TX resistor, one end of which is connected to the output terminal of the second TX buffer; A current conveyor comprising an X-port connected to the common terminal of the first TX resistor and the second TX resistor, a Y-port to which a common mode voltage on the transmission line is applied, and a ZP-port connected to an I / O pad; and A data communication system characterized by including a pre-emphasis circuit that temporarily increases or decreases the strength of a TX signal applied to the X-port of a current conveyor, comprising a pre-amper buffer that is enabled by a TX enable signal and buffers a pre-emphasis signal, a variable resistor, and a variable capacitor.

9. In paragraph 4, the above RCV block is, A voltage generation unit comprising a plurality of RC parallel circuits and converting the current of a PAM signal provided through the transmission line into a voltage; and A data communication system characterized by including a plurality of differential voltage comparators and a voltage comparator module that differentially compares PAM signals converted into voltage by the voltage generation unit.

10. A data communication system according to claim 9, wherein in each of the RC parallel circuits, the R value is the value of an intended circuit component between 10Ω and 300Ω, and the C value is the value of an unintended parasitic capacitance component or an intended capacitance component.

11. A data communication system according to claim 9, wherein each of the differential voltage comparators includes differential voltage comparators that receive a current bias and detect a difference in the input voltage of a gate.

12. In paragraph 4, the above RCV block is, A voltage generation unit comprising a plurality of current conveyors and a plurality of RC parallel circuits disposed at the output end of the current conveyor, and converting the current of a PAM signal provided through the transmission line into a voltage; and A data communication system characterized by including a plurality of differential voltage comparators and a voltage comparator module that differentially compares PAM signals converted into voltage by the voltage generation unit.

13. In Clause 12, the voltage comparator module is, A first differential voltage comparator that outputs a first differential voltage obtained by differentially comparing a first voltage and a second voltage provided from the voltage generation unit; A second differential voltage comparator that outputs a second differential voltage obtained by comparing the second voltage and the third voltage provided from the voltage generation unit; A third differential voltage comparator that outputs a third differential voltage obtained by comparing the third voltage and the fourth voltage provided from the voltage generation unit; A fourth differential voltage comparator that outputs a fourth differential voltage obtained by comparing the first voltage and the fourth voltage provided from the voltage generation unit; A fifth differential voltage comparator that outputs a fifth differential voltage obtained by comparing the first voltage and the third voltage provided from the voltage generation unit; and A data communication system characterized by including a sixth differential voltage comparator that outputs a sixth differential voltage obtained by comparing the second voltage and the fourth voltage provided from the voltage generation unit.

14. A data communication system according to the 13th, wherein the first to sixth differential voltage comparators operate in response to a clock.

15. In paragraph 14, each of the first to sixth differential voltage comparators is, A data communication system characterized by including a differential ARM (Analog Re-generative Memory) latch voltage comparator that detects the difference in input voltage of a gate using a comparison clock.

16. In paragraph 15, the differential ARM (Analog Re-generative Memory) latch voltage comparator is, A differential voltage comparator that determines an output signal by comparing two input signals, amplifying the difference between VIN(+) and VIN(-) and determining the output signal based on the amplified difference; and A data communication system characterized by including an SR-latch that stores the output state of the above-mentioned differential voltage comparator and maintains it for a certain period of time.

17. In paragraph 4, the above RCV block is, A voltage generation unit comprising a plurality of current conveyors and a plurality of R circuits disposed at the output end of the current conveyor, and converting the current of a PAM signal provided through the transmission line into a voltage; and A data communication system characterized by including a plurality of differential voltage comparators and a voltage comparator module that differentially compares PAM signals converted into voltage by the voltage generation unit.

18. A data communication system according to claim 17, wherein the voltage generating unit further comprises a variable resistor, one end of which is connected to the transmission line and the other end of which is connected to the current conveyor.

19. In paragraph 4, each of the first communication unit and the second communication unit is, A data communication system characterized by further including a pre-encoder, one side of which is connected to the other side of the encoding / decoding unit, and which receives data to be transmitted from a processor unit or memory device during signal transmission and performs pre-encoding.

20. In paragraph 4, each of the first communication unit and the second communication unit is, A data communication system characterized by further including a post decoder, one side of which is connected to the other side of the encoding / decoding unit, which processes post-decoding of the received data upon data reception.

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