System and method for designing general-purpose input / output test configuration on basis of no-code

Abstract

The present invention relates to a system and method for designing, on the basis of no-code, a general-purpose input / output test configuration which performs test signal transmission / reception between a plurality of IP blocks and general-purpose input / outputs (GPIOs) inside a system-on-chip (SOC) in a test mode. The system for designing a GPIO test configuration according to an embodiment of the present invention comprises: a memory configured to store one or more instructions; and at least one processor configured to execute the one or more instructions stored in the memory. The one or more instructions include instructions for: generating at least one GPIO test instance on the basis of GPIO test component information; providing a configuration value input environment of the GPIO test instance; determining the types, the number, ports, and connections of sub-modules constituting the GPIO test instance on the basis of a configuration value of the GPIO test instance; and generating a hardware code corresponding to the GPIO test configuration on the basis of the sub-modules and ports for each GPIO test instance, connections, and a hardware code logic.

Description

No-code-based general-purpose I / O test configuration design system and method

[0001] The present invention relates to a system and method for designing a general-purpose input / output (GPIO) test configuration, and more specifically, to a system and method for designing a general-purpose input / output test configuration based on no-code that performs test signal transmission and reception between a plurality of IP blocks inside a system-on-chip (SoC) and general-purpose input / output (GPIO) in test mode.

[0002] The present invention is based on the research results of the research project "Development of DFT system design automation solution in System on chip" (Executing organization: Itda Semiconductor Co., Ltd., Research period: September 1, 2024 to August 31, 2027), which was conducted with support from Scale-up TIPS (Project No.: RS-2024-00507894), organized by the Ministry of SMEs and Startups of the Republic of Korea and managed by the Technology Promotion Agency for SMEs (TIPA).

[0003] A System-on-Chip (SoC) is a technology designed to implement complex electronic systems on a single chip by integrating various Intellectual Property (IP) blocks, such as a central processing unit (CPU), memory, digital signal processing units, and analog circuits, onto a single semiconductor chip.

[0004] Figure 1 is a block diagram illustrating a conventional system-on-chip (SoC).

[0005] The SoC includes multiple IP blocks (111, 112, 113), and each IP block (111, 112, 113) has one or more ports for transmitting and receiving signals with an external device. The SoC includes a General Purpose Input / Output (GPIO) (120) for interfacing with an external device. The General Purpose Input / Output (120) consists of tens to hundreds of GPIO pads, and each GPIO pad is connected to an external device of the SoC to transmit and receive data or to detect the state of the internal circuit of the SoC.

[0006] IP blocks (111, 112, 113) may include processor blocks, memory blocks, multimedia blocks, network blocks, logic blocks, security blocks, interface blocks, hard macro blocks, etc.

[0007] In the case of a typical SoC, since the number of IP block ports is much greater than the number of GPIO pads, the GPIO pads must be able to be selectively connected to multiple ports, and for this purpose, an input / output multiplexer (IOMUX) (130) may be used.

[0008] The input / output multiplexer (130) allows a single GPIO pad to be connected to any of the multiple ports according to a control signal, thereby enabling flexible reconfiguration of the connection between the ports inside the SoC and the GPIO pad. For example, the same GPIO pad may be configured to be connected to a port of a security block at a specific time to transmit encryption-related data, and at another time to be connected to a port of a sensor interface block to receive sensor data.

[0009] Meanwhile, SoCs must support a test mode to detect functional defects and verify circuit operation after manufacturing, and to this end, a Design-for-Test (DFT) structure must be incorporated. Conventional SoC designs often consider only I / O connection configurations centered on functional operation, and since no separate test path is provided for GPIO pads, there has been a problem in that GPIO defects cannot be sufficiently verified during the manufacturing process or during the testing phase after mass production.

[0010] To solve these problems, recent I / O multiplexers are being designed to simultaneously perform the DFTMUX function for internal circuit observation and control in test mode as well as in function mode. However, if an I / O multiplexer is designed with a structure that supports both function mode and test mode in this way, the following problems may occur.

[0011] First, design complexity increases. Since multiple ports are connected to a single GPIO pad and separate path selection control must be configured for both functional and test modes, the path selection logic of the I / O multiplexer becomes very complex. Furthermore, as multiple control signals and data paths overlap, wiring complexity, area, and power consumption increase, making it difficult to analyze the timing and ensure the reliability of the entire SoC.

[0012] In addition, while the DFT structure itself is inserted by EDA (Electronic Design Automation) tools, the preceding Pre-DFT work must mostly be performed manually by DFT engineers. Generally, since functional designers and DFT designers perform design tasks individually, design errors and omitted tests may occur due to a lack of information sharing between them regarding GPIO-related I / O multiplexer settings, port-pad mapping, and mode switching settings.

[0013] In addition, since defects such as short, open, and leakage between GPIO pads are difficult to detect with general logic tests alone, a direct control and observation path in test mode is required. However, in conventional structures, the test paths of GPIO pads are not clearly defined or are inconsistent, which leads to a problem where the overall test coverage is limited.

[0014] Furthermore, in the SoC design flow, DFT is often perceived as a separate area from functional design; consequently, functional designers design without considering DFT, and DFT designers insert DFT structures without a sufficient understanding of functional behavior. In particular, although the configuration for GPIO testing should be established during the Pre-DFT phase, it tends to remain a gray zone due to unclear responsibility.

[0015] The objective of the present invention is to provide a system and method for designing a general-purpose I / O test configuration based on no code, wherein multiple connection paths between the ports of an IP block and general-purpose I / O (GPIO) pads are configured in hardware, and a test path among the multiple connection paths can be flexibly selected using a controller in test mode.

[0016] The present invention may be implemented in various ways, including a device (system), a method, a computer program stored on a computer-readable medium, or a computer-readable medium on which a computer program is stored.

[0017] A no-code-based general-purpose input / output test configuration design system according to one embodiment of the present invention includes a memory configured to store at least one instruction, a GPIO test component storage in which GPIO test component information is stored, a hardware code logic storage in which hardware code logic for generating a designed GPIO test configuration into hardware code is stored, and at least one processor configured to execute at least one instruction stored in the memory. The at least one instruction includes instructions for creating at least one GPIO test instance based on GPIO test component information, providing an environment for inputting configuration values ​​of the GPIO test instance, determining the type, number, port, and connection of submodules configuring the GPIO test instance based on the configuration values ​​of the GPIO test instance, and generating hardware code corresponding to the GPIO test configuration based on the submodules, ports, connections, and hardware code logic for each GPIO test instance.

[0018] The GPIO test instance includes at least one of a pad group controller instance, a GPIO router instance, a GPIO multiplexer instance, and a hard macro interface instance.

[0019] The setting value input environment is displayed in a table format.

[0020] The configuration value of the pad group controller instance includes a list of GPIO pads associated with the pad group controller instance and a pad test operation control configuration value for each GPIO pad.

[0021] At least one command includes commands for determining the number of pad interface submodules that constitute a pad group controller instance based on the configuration value of the pad group controller instance, and the internal components and internal connections of the pad interface submodules.

[0022] The configuration value of the GPIO multiplexer instance includes the port configuration value of the IP block connected for each GPIO pad in at least one test mode and at least one mapping group.

[0023] At least one instruction includes instructions for determining the internal components and internal connections of a pad mode selection submodule that configures a GPIO multiplexer instance based on the configuration value of the GPIO multiplexer instance, the number of mapping group submodules, the internal components and internal connections of the mapping group submodules, and the connection between the pad mode selection submodule and the mapping group submodule.

[0024] At least one instruction further includes instructions for determining the number of flip-flops and connections of the test controller submodule included in the GPIO test instance based on the configuration value of the GPIO test instance.

[0025] The test controller submodule is implemented based on the built-in IEEE1687 standard.

[0026] At least one command further includes commands for creating at least two types of GPIO test instances based on GPIO test component information and for receiving and processing connections between the two types of GPIO test instances.

[0027] A no-code-based general-purpose input / output test configuration design method according to one embodiment of the present invention is performed by at least one processor in a computer system comprising a GPIO test component repository storing GPIO test component information and a hardware code logic repository storing hardware code logic for generating a designed GPIO test configuration as hardware code. The no-code-based GPIO test configuration design method includes the steps of: creating at least one GPIO test instance based on GPIO test component information; providing an environment for inputting setting values ​​of the GPIO test instance; determining the type, number, port, and connection of sub-modules configuring the GPIO test instance based on the setting values ​​of the GPIO test instance; and generating hardware code corresponding to the GPIO test configuration based on the sub-modules, ports, connections, and hardware code logic for each GPIO test instance.

[0028] The GPIO test instance includes at least one of a pad group controller instance, a GPIO router instance, a GPIO multiplexer instance, and a hard macro interface instance.

[0029] The setting value input environment is displayed in a table format.

[0030] The configuration value of the pad group controller instance includes a list of GPIO pads associated with the pad group controller instance and a pad test operation control configuration value for each GPIO pad.

[0031] A no-code-based GPIO test configuration design method further includes the step of determining the number of pad interface submodules configuring the pad group controller instance and the internal components and internal connections of the pad interface submodules based on the configuration values ​​of the pad group controller instance.

[0032] The configuration value of the GPIO multiplexer instance includes the port configuration value of the IP block connected for each GPIO pad in at least one test mode and at least one mapping group.

[0033] A no-code-based GPIO test configuration design method further includes the step of determining the internal components and internal connections of a pad mode selection submodule configuring a GPIO multiplexer instance based on the configuration values ​​of the GPIO multiplexer instance, the number of mapping group submodules, the internal components and internal connections of the mapping group submodules, and the connections between the pad mode selection submodule and the mapping group submodule.

[0034] A no-code-based GPIO test configuration design method further includes the step of determining the number of flip-flops and connections of a test controller submodule included in a GPIO test instance based on the configuration values ​​of the GPIO test instance.

[0035] The test controller submodule is implemented based on the built-in IEEE1687 standard.

[0036] A no-code-based GPIO test configuration design method further includes the step of creating at least two types of GPIO test instances based on GPIO test component information, and the step of receiving and processing connections between the two types of GPIO test instances.

[0037] According to the present invention, a general-purpose input / output test configuration can be designed based on no code, wherein multiple connections between the ports of an IP block and general-purpose input / output (GPIO) pads are pre-established in hardware, and a test path among the multiple connections can be flexibly selected using a controller in test mode.

[0038] According to the present invention, a no-code-based general-purpose I / O test configuration that operates in various test scenarios in test mode can be designed by an operator without coding knowledge or general-purpose I / O test process knowledge.

[0039] The effects of the present invention are not limited to those mentioned above, and other unmentioned effects will be clearly understood by a person skilled in the art to which the present invention pertains (referred to as "person skilled in the art") from the description in the claims.

[0040] Figure 1 is a block diagram illustrating a conventional system-on-chip (SoC).

[0041] FIG. 2 is a block diagram illustrating a system-on-chip including a general-purpose input / output test configuration to be designed through the present invention.

[0042] Figure 3 is a detailed configuration diagram of the pad group controller of Figure 2.

[0043] Figure 4 is an internal configuration diagram of an SoC with multiple GPIO routers arranged.

[0044] Figure 5 is a detailed configuration diagram of the GPIO router of Figures 2 and 4.

[0045] Figure 6 is a detailed configuration diagram illustrating the GPIO multiplexer of Figure 2.

[0046] Figure 7 is a detailed configuration diagram of the hard macro interface of Figure 2.

[0047] FIG. 8 is a configuration diagram of a no-code-based general-purpose input / output test configuration design system according to the present invention.

[0048] FIG. 9 is a diagram showing an example of a display screen of a no-code-based general-purpose input / output test configuration design system according to the present invention.

[0049] FIG. 10 is an operation flowchart illustrating a no-code-based general-purpose input / output test configuration design method according to the present invention.

[0050] FIG. 11 shows an exemplary computing device for carrying out the above-described method and / or embodiments, etc.

[0051] [Explanation of the symbol]

[0052] 810: Screen window processing unit 811: Command window processing unit

[0053] 812: Content Window Processing Unit 813: Design Window Processing Unit

[0054] 814: Configuration Window Processor 820: GPIO Test Configuration Processor

[0055] 821: GPIO Test Configuration Management Unit 822: GPIO Test Instance Management Unit

[0056] 823: Table processing unit 824: Sub-module configuration unit

[0057] 830: Data Storage 831: GPIO Test Component Storage

[0058] 832: GPIO Test Configuration Repository 833: GPIO Test Instance Repository

[0059] 834: Hardware code logic storage 840: Hardware code processing unit

[0060] 841: Submodule code generation unit 842: Port code generation unit

[0061] 843: Connection Code Generation Section

[0062] Hereinafter, specific details for implementing the present invention will be described in detail with reference to the attached drawings. However, in the following description, specific descriptions regarding widely known functions or configurations will be omitted if there is a risk of unnecessarily obscuring the essence of the present invention.

[0063] In the attached drawings, identical or corresponding components are assigned the same reference numerals. Additionally, in the description of the following embodiments, the description of identical or corresponding components may be omitted. However, even if a description of a component is omitted, it is not intended that such component is not included in any embodiment.

[0064] The advantages and features of the embodiments disclosed in this specification, and the methods for achieving them, will become clear by referring to the embodiments described below in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms, and these embodiments are provided merely to fully inform a person skilled in the art of the scope of the invention.

[0065] The terms used in this specification will be briefly explained, and the disclosed embodiments will be described in detail. The terms used in this specification have been selected to be as widely used as possible, taking into account their functions in the present invention; however, these terms may vary depending on the intent of those skilled in the relevant field, case law, or the emergence of new technologies. Additionally, in specific cases, terms may be arbitrarily selected by the applicant, and in such cases, their meanings will be described in detail in the relevant description of the invention. Therefore, the terms used in this invention should be defined not merely by their names, but based on their meanings and the overall content of the present invention.

[0066] In this specification, singular expressions include plural expressions unless the context clearly specifies them as singular. Additionally, plural expressions include singular expressions unless the context clearly specifies them as plural. Throughout the specification, when a part is described as including a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components.

[0067] In the present invention, terms such as 'comprising', 'comprising', etc. may indicate the presence of features, steps, actions, elements and / or components, but do not exclude the addition of one or more other functions, steps, actions, elements, components and / or combinations thereof.

[0068] In the present invention, where a specific component is described as being 'combined,' 'combined,' 'connected,' 'associated,' or 'reacted' to any other component, the specific component may be directly combined, combined, connected, and / or associated with, or reacted to the other component, but is not limited thereto. For example, one or more intermediate components may exist between the specific component and the other component. Additionally, in the present invention, "and / or" may include each of the one or more listed items or a combination of at least some of the one or more items.

[0069] In the present invention, terms such as 'first', 'second', etc., are used to distinguish a specific component from another component, and the components described above are not limited by these terms. For example, the 'first' component may be used to refer to an element of the same or similar form as the 'second' component.

[0070] General Purpose Input / Output (GPIO) Test Configuration

[0071] FIG. 2 is a block diagram illustrating a system-on-chip including a general-purpose input / output test configuration to be designed through the present invention.

[0072] A system-on-chip may be composed of a general-purpose input / output (GPIO) consisting of multiple GPIO pads and multiple IP blocks. The multiple GPIO pads constituting the general-purpose input / output may be divided into at least two pad groups (211, 212, 213). Each pad group (211, 212, 213) may be grouped based on placement location and may include one or more GPIO pads. Each GPIO pad may belong to at least one pad group (211, 212, 213), and one GPIO pad may constitute one pad group.

[0073] FIG. 2 illustrates a system-on-chip composed of three pad groups (211, 212, 213) and six IP blocks (221, 222, 223, 224, 225, 226), but the number of pad groups and IP blocks is not limited thereto. Each pad group (211, 212, 213) may consist of an equal number of GPIO pad(s) or a different number of GPIO pad(s). For example, the first pad group (211) may consist of n1 GPIO pads, the second pad group (212) may consist of n2 GPIO pads, and the third GPIO pad (213) may consist of n3 GPIO pads. Here, n1, n2, and n3 may be the same natural number or different natural numbers.

[0074] Each GPIO pad can be connected to a different IP block for each test mode and may operate as an input or an output. To this end, pad operation control is required to control the operation of the GPIO pad. Each GPIO pad may be provided with a pad input that is input from within the SoC to the GPIO pad and a pad output that is output from the GPIO pad to within the SoC, along with multiple pad operation control signals. The pad operation control signals may include a drive strength (DS) signal to determine the output drive strength of the pad, a pull enable (PE) signal to determine whether the pad's pull circuit is enabled, a pull up / down (PU) signal to determine one of pull-up and pull-down in the pad's pull circuit enabled state, an input enable (IE) signal to determine the pad's operation as an input, and an output enable (OE) signal to determine the pad's operation as an output. The drive strength (DS) signal, pull enable (PE) signal, pull up / down (PU) signal, input enable (IE) signal, and output enable (OE) signal are each independent pad operation control signals, and can be collectively referred to as pad operation control signals.

[0075] Pad inputs include pad function inputs input to GPIO pads in function mode and pad test inputs input to GPIO pads in test mode. Pad outputs include pad function outputs output from GPIO pads in function mode and pad test outputs output from GPIO pads in test mode.

[0076] IP blocks (221, 222, 223, 224, 225, 226) may include processor blocks, memory blocks, multimedia blocks, network blocks, logic blocks, security blocks, interface blocks, hard macro blocks, etc. IP blocks that are not hard macro blocks may be collectively referred to as non-hard macro blocks. That is, non-hard macro blocks may include processor blocks, memory blocks, multimedia blocks, network blocks, logic blocks, security blocks, interface blocks, etc.

[0077] The six IP blocks (221, 222, 223, 224, 225, 226) can be divided into multiple block groups. Multiple IP blocks constituting the SoC can be distributed and arranged within the SoC, and multiple IP blocks can be grouped into block groups based on their placement locations. In FIG. 2, it is assumed that the first IP block (221), the second IP block (222), and the third IP block (223) are grouped into the first block group, the fourth IP block (224) and the fifth IP block (225) are grouped into the second block group, and the sixth IP block (226) is grouped into the third block group. The number of IP blocks constituting each block group is not limited to a specific number, and the number of block group(s) and the IP block(s) belonging to each block group can be freely determined and changed by the SoC designer.

[0078] In FIG. 2, the first IP block (221), the second IP block (222), the fourth IP block (224), and the sixth IP block (226) may be hard macro blocks, and the third IP block (223) and the fifth IP block (225) may be non-hard macro blocks. The number of hard macro blocks and the number of non-hard macro blocks constituting the SoC can be freely determined and changed by the SoC designer.

[0079] The general-purpose input / output (GPIO) test configuration includes a first pad group controller (231) that performs pad function input / output and pad function operation control in function mode and first pad test input / output and pad test operation control for each of a plurality of GPIO pads constituting a first pad group (211), and a first hard macro interface (241) that transmits and receives port input / output in test mode for each of a plurality of ports constituting a first IP block (221). The port input / output may include at least one of the first pad test input / output, function port input / output, and register test data.

[0080] The General Purpose Input / Output (GPIO) test configuration may further include a second pad group controller (232) and a third pad group controller (233). The second pad group controller (232) performs pad function input / output and pad function operation control in function mode for each of the plurality of GPIO pads constituting the second pad group (212), and performs second pad test input / output and pad test operation control in test mode. The third pad group controller (233) performs pad function input / output and pad function operation control in function mode for each of the plurality of GPIO pads constituting the third pad group (213), and performs third pad test input / output and pad test operation control in test mode. Additional pad group controllers may be included depending on the number of pad groups of the General Purpose Input / Output (GPIO), and it is preferable that the pad groups and pad group controllers be configured to correspond one-to-one.

[0081] The first hard macro interface (241) may receive at least one of the first pad test input / output from the first pad group controller (231) or the second pad test input / output from the second pad group controller (232). The first hard macro interface (241) may transmit and receive port input / output to each of the plurality of ports constituting the first IP block (221) in test mode. This port input / output may include at least one of the pad test input / output, function port input / output, and register test data transmitted from the pad group controller.

[0082] The general-purpose input / output (GPIO) test configuration may further include a second hard macro interface (242) that performs port input / output for each of the plurality of ports constituting the second IP block (222) in test mode, a fourth hard macro interface (244) that performs port input / output for each of the plurality of ports constituting the fourth IP block (224), and a sixth hard macro interface (246) that performs port input / output for each of the plurality of ports constituting the sixth IP block (226).

[0083] In test mode, the second hard macro interface (242) can receive pad test input / output from at least one of the first and second pad group controllers (231, 232). The fourth hard macro interface (244) can receive pad test input / output from at least one of the first, second, and third pad group controllers (231, 232, 233). The sixth hard macro interface (246) can receive pad test input / output from at least one of the second and third pad group controllers (232, 233).

[0084] The General Purpose Input / Output (GPIO) test configuration may further include GPIO multiplexers (MUX) (251, 252, 253) placed in each block group. The SoC of the example in FIG. 2 consists of three block groups, and thus includes three GPIO multiplexers (251, 252, 253). Each GPIO multiplexer (251, 252, 253) supports multiple inputs and outputs so that GPIO pads of at least one pad group can be connected to at least one IP block.

[0085] The first pad test input / output of the first pad group controller (231) and the second pad test input / output of the second pad group controller (232) are connected to the input side of the first GPIO multiplexer (251). The first hard macro interface (241), the second hard macro interface (242), and the third IP block (223) may be optionally connected to the output side of the first GPIO multiplexer (251). Through the first GPIO multiplexer (251), the GPIO pads of the first pad group (211) and the second pad group (212) may be physically connected to the corresponding ports of the first IP block (221), the second IP block (222), and the third IP block (223), respectively.

[0086] The first pad test input / output of the first pad group controller (231), the second pad test input / output of the second pad group controller (232), and the third pad test input / output of the third pad group controller (233) are connected to the input side of the second GPIO multiplexer (252). The fourth hard macro interface (244) and the fifth IP block (225) may be optionally connected to the output side of the second GPIO multiplexer (252). Through the second GPIO multiplexer (252), the GPIO pads of the first pad group (211), the second pad group (212), and the third pad group (213) may be physically connected to the corresponding ports of the fourth IP block (224) and the fifth IP block (225), respectively.

[0087] The second pad test input / output of the second pad group controller (232) and the third pad test input / output of the third pad group controller (233) are connected to the input side of the third GPIO multiplexer (253). The sixth hard macro interface may be connected to the output side of the third GPIO multiplexer (253). Through the third GPIO multiplexer (253), the GPIO pads of the second pad group (212) and the third pad group (213) may each be physically connected to the corresponding port of the sixth IP block (226).

[0088] The first IP block (221), the second IP block (222), the fourth IP block (224), and the sixth IP block (226), which are hard macro blocks, can be connected to the first GPIO multiplexer (251), the second GPIO multiplexer (252), and the third GPIO multiplexer (253) through the first hard macro interface (241), the second hard macro interface (242), the fourth hard macro interface (244), and the sixth hard macro interface (246), respectively. Meanwhile, the third IP block (223) and the fifth IP block (225), which are non-hard macro blocks, can be connected to the first GPIO multiplexer (251) and the second GPIO multiplexer (252), respectively, without mediating a hard macro interface.

[0089] The General Purpose Input / Output (GPIO) test configuration may further include multiple GPIO routers. The 1-1 GPIO router (261) distributes the first pad test input / output of the first pad group controller (231) to the first GPIO multiplexer (251). The 1-2 GPIO router (262) receives the first pad test input / output of the first pad group controller (231) through the 1-1 GPIO router (261) and distributes it to the second GPIO multiplexer (252). The 2-1 GPIO router (263) distributes the second pad test input / output of the second pad group controller (232) to the first GPIO multiplexer (251). The 2-2 GPIO router (264) receives the 2nd pad test input / output of the 2nd pad group controller (232) through the 2-1 GPIO router (263) and distributes it to the 2nd GPIO multiplexer (252). The 2-3 GPIO router (265) receives the 2nd pad test input / output of the 2nd pad group controller (232) through the 2-2 GPIO router (264) and distributes it to the 3rd GPIO multiplexer (253). The 3-1 GPIO router (266) distributes the 3rd pad test input / output of the 3rd pad group controller (233) to the 2nd GPIO multiplexer (252). The 3-2 GPIO router (267) receives the 3rd pad test input / output of the 3rd pad group controller (233) through the 3-1 GPIO router (266) and distributes it to the 3rd GPIO multiplexer (253).

[0090] Pad group controller

[0091] Figure 3 is a detailed configuration diagram of the pad group controller of Figure 2.

[0092] The pad group controller of FIG. 3 may be any one of the first pad group controller (231), the second pad group controller (232), and the third pad group controller (233) of FIG. 2.

[0093] A pad group controller includes at least one pad interface (310, 320) configured to correspond to each GPIO pad (301, 302), and a test controller (330) that outputs a test mode signal for determining an operation mode to the pad interface (310, 320) and pad test operation control signals for controlling pad operation in the test mode. GPIO pads (301, 302) connected to a single pad group controller may form the same pad group. It is preferable that the number of pad interfaces included in the pad group controller be equal to the number of GPIO pads forming the pad group. The operation modes of the pad interfaces may include a test mode and a function mode.

[0094] Each corresponding GPIO pad (301, 302) is connected to the pad interface (310, 320). The pad interface (310, 320) provides pad operation control (PAD CTRL) signals to the GPIO pad (301, 302), receives a pad output (PAD OUT) signal from the GPIO pad (301, 302), and provides a pad input (PAD IN) signal to the GPIO pad (301, 302). Pad operation control signals may include a drive strength (DS) signal for determining the output drive strength of the pad, a pull enable (PE) signal for determining whether the pad's pull circuit is activated, a pull up / down (PU) signal for determining one of pull up and pull down in the activated state of the pad's pull circuit, an input enable (IE) signal for determining the pad's operation as an input, and an output enable (OE) signal for determining the pad's operation as an output.

[0095] A GPIO function controller (304) and a GPIO router (305) can be connected to the pad interface (310, 320). The operation mode of the pad interface (310, 320) is determined by the control of the test controller (330), and the operation mode may include a function mode or a test mode.

[0096] In function mode, the GPIO function controller (304) outputs pad function input (PAD FUNC IN) signals and pad function operation control (PAD FUNC CTRL) signals to pad interfaces (310, 320) and receives pad function output (PAD FUNC OUT) signals from each pad interface (310, 320). In test mode, the GPIO router (305) outputs pad test input (PAD TEST IN) signals to each pad interface (310, 320) and receives pad test output (PAD TEST OUT) signals from each pad interface (310, 320).

[0097] A first pad interface (310) can be connected to the first GPIO pad (301), and an n-th pad interface (320) can be connected to the n-th GPIO pad (302). A pad group consists of a total of n GPIO pads, and a pad interface corresponding one-to-one can be connected to each GPIO pad.

[0098] The first pad interface (310) and the nth pad interface (320) receive a TEST MODE signal from the test controller (330) indicating whether the test mode is enabled or disabled. When the test mode is disabled, each pad interface (310, 320) operates in function mode, and when the test mode is enabled, each pad interface (310, 320) operates in test mode.

[0099] The signal flow when the first pad interface (310) operates in function mode is as follows. The GPIO function controller (304) outputs pad function operation control (PAD FUNC CTRL 1) signals to the first pad interface (310) to control the operation of the first GPIO pad (301), and the first pad interface (310) provides pad operation control (PAD CTRL 1) signals to the first GPIO pad (301) based on the pad function operation control (PAD FUNC CTRL 1) signals. In addition, a pad output (PAD OUT 1) signal generated from the first GPIO pad (301) is received by the first pad interface (310), and the first pad interface (310) outputs a pad function output (PAD FUNC OUT 1) signal to the GPIO function controller (304) based on the pad output (PAD OUT 1) signal. Additionally, a pad function input (PAD FUNC IN 1) signal generated by the GPIO function controller (304) is input to the first pad interface (310), and the first pad interface (310) outputs a pad input (PAD IN 1) signal to the first GPIO pad (301) based on the pad function input (PAD FUNC IN 1) signal.

[0100] Meanwhile, the signal flow when the first pad interface (310) operates in test mode is as follows. The test controller (330) outputs pad test operation control (PAD TEST CTRL 1) signals to the first pad interface (310) to control the operation of the first GPIO pad (301), and the first pad interface (310) outputs pad operation control (PAD CTRL 1) signals to the first GPIO pad (301) based on the pad test operation control (PAD TEST CTRL 1) signals. In addition, a pad output (PAD OUT 1) signal generated from the first GPIO pad (301) is input to the first pad interface (310), and the first pad interface (310) outputs a pad test output (PAD TEST OUT 1) signal to the GPIO router (305) based on the pad output (PAD OUT 1) signal. Additionally, a pad test input (PAD TEST IN 1) signal input from the GPIO router (305) is input to the first pad interface (310), and the first pad interface (310) outputs a pad input (PAD IN 1) signal to the first GPIO pad (301) based on this pad test input (PAD TEST IN 1) signal.

[0101] Similarly, the signal flow when the n-th pad interface (320) operates in function mode is as follows. The GPIO function controller (304) outputs pad function operation control (PAD FUNC CTRL n) signals for controlling the operation of the n-th GPIO pad (302) to the n-th pad interface (320), and the n-th pad interface (320) outputs pad operation control (PAD CTRL n) signals to the n-th GPIO pad (302) based on the pad function operation control (PAD FUNC CTRL n) signals. Additionally, a pad output (PAD OUT n) signal is input from the n-th GPIO pad (302) to the n-th pad interface (320), and the n-th pad interface (320) outputs a pad function output (PAD FUNC OUT n) signal to the GPIO function controller (304) based on the pad output (PAD OUT n) signal. Additionally, a pad function input (PAD FUNC IN n) signal input from the GPIO function controller (304) is input to the n-th pad interface (320), and the n-th pad interface (320) outputs a pad input (PAD IN n) signal to the n-th GPIO pad (302) based on this pad function input (PAD FUNC IN n) signal.

[0102] Meanwhile, the signal flow when the n-th pad interface (320) operates in test mode is as follows. The test controller (330) outputs pad test operation control (PAD TEST CTRL n) signals to the n-th pad interface (320) to control the operation of the n-th GPIO pad (302), and the n-th pad interface (320) outputs pad operation control (PAD CTRL n) signals to the n-th GPIO pad (302) based on the pad test operation control (PAD TEST CTRL n) signals. Additionally, a pad output (PAD OUT n) signal is input from the n-th GPIO pad (302) to the n-th pad interface (320), and the n-th pad interface (320) outputs a pad test output (PAD TEST OUT n) signal to the GPIO router (305) based on the pad output (PAD OUT n) signal. Additionally, a pad test input (PAD TEST IN n) signal input from the GPIO router (305) is transmitted to the n-th pad interface (320), and the n-th pad interface (320) outputs a pad input (PAD IN n) signal to the n-th GPIO pad (302) based on the pad test input (PAD TEST IN n) signal.

[0103] The test controller (330) may be a controller based on the IEEE 1687 standard (IJTAG: Internal Joint Test Action Group). The test controller (330) can set the test mode register (331) and the test operation control register (332) through the IJTAG interface. Each register (331, 332) may be configured as a test data register (TDR) that operates in a shift manner.

[0104] The test mode register (331) may be composed of a single flip-flop and outputs a test mode signal that determines whether the first pad interface (310) and the n-th pad interface (320) will operate in test mode or function mode. This test mode signal may be a 1-bit control signal indicating the activation or deactivation of the test mode.

[0105] The test operation control register (332) may be composed of multiple flip-flops and may output multiple pad test operation control (PAD TEST CTRL 1, PAD TEST CTRL n) signals corresponding to each pad interface. For example, if the pad test operation control (PAD TEST CTRL 1) signals for controlling the operation of the first GPIO pad are composed of a total of five control signals, including drive strength (DS), pull enable (PE), pull up / down (PU), input enable (IE), and output enable (OE), the test operation control register (332) may output control signals that determine the value or activation status of each control signal. At this time, the test operation control register (332) may include flip-flops corresponding to each control signal for the first GPIO pad. Two or more flip-flops may be used to determine the value of a single control signal. For example, since a control value of 2 bits or more may be required for the drive strength (DS), multiple flip-flops may be used to configure the drive strength control signal. Additionally, the test operation control register (332) may additionally include flip-flops that determine the value or activation status of the pad test operation control signals for the nth GPIO pad.

[0106] GPIO Router

[0107] Figure 4 is an internal configuration diagram of an SoC with multiple GPIO routers arranged.

[0108] As mentioned in the description of FIG. 2, the SoC (400) is composed of multiple IP blocks, and the multiple IP blocks can be grouped into multiple block groups (430, 440, 450, 460, 470) according to their placement location. FIG. 4 is an example of an SoC composed of five block groups.

[0109] The SoC (400) includes a pad group (410) composed of a plurality of GPIO pads, and the pad group (410) is typically placed on the outer edge of the SoC (400) to facilitate signal input and output with the outside.

[0110] Additionally, the SoC (400) includes a pad group controller (420) positioned near the pad group (410). The pad group controller (420) is configured to perform different functions depending on the operation mode for each GPIO pad constituting the pad group (410). More specifically, the pad group controller (420) performs pad function input / output and pad function operation control for each GPIO pad in function mode. Additionally, when test mode is enabled, the pad group controller (420) performs pad test input / output and pad test operation control for each GPIO pad. This enables testing of the internal circuitry and pad operation of the SoC (400) and can be utilized to verify the electrical characteristics and operating status of the pads after manufacturing or during the system initialization phase.

[0111] To this end, it is desirable that the input / output signals of the GPIO pads be configured to be linked with multiple IP blocks placed inside the SoC. That is, the input / output signals of the GPIO pads must be distributed to multiple block groups to which each IP block belongs. However, due to the layout characteristics inside the SoC, some block groups must be physically separated from the pad group (410) or the pad group controller (420). In such cases, a means of transmission is required to efficiently distribute and collect pad test input / output signals to each block group.

[0112] As such a means of transmission, a plurality of GPIO routers may be included. For example, the first GPIO router (431) receives a pad test output signal from the pad group controller (420) and distributes it to the first block group (430) and the lower third GPIO router (451). Additionally, it receives pad test input signals from the first block group (430) and the lower third GPIO router (451), respectively, and transmits them to the pad group controller (420).

[0113] Meanwhile, if all IP blocks included in the second block group (440) do not use the GPIO pads of the pad group (410), a separate GPIO router that distributes pad test input / output to the second block group (440) may be omitted. In this case, the component connected to the first GPIO router (431) as a subordinate GPIO router becomes the third GPIO router (451).

[0114] The third GPIO router (451) distributes the pad test output distributed from the upper first GPIO router (431) to the third block group (450) and the lower fourth GPIO router (461), and transmits the pad test input received from the third block group (450) and the lower fourth GPIO router (461) to the upper first GPIO router (431). The fourth GPIO router (461) distributes the pad test output distributed from the upper third GPIO router (451) to the fourth block group (460) and the lower fifth GPIO router (471), and transmits the pad test input received from the fourth block group (460) and the lower fifth GPIO router (471) to the upper third GPIO router (451). The 5th GPIO router (471) transmits the pad test output distributed from the upper 4th GPIO router (461) to the 5th block group (470) and transmits the pad test input input from the 5th block group (470) to the upper 4th GPIO router (461).

[0115] Accordingly, the pad test output from the GPIO pad can be distributed to the first block group (430), the third block group (450), the fourth block group (460), and the fifth block group (470) sequentially through the first GPIO router (431), the third GPIO router (451), the fourth GPIO router (461), and the fifth GPIO router (471). Additionally, the pad test input output from the fifth block group can be input to the GPIO pad sequentially through the fifth GPIO router (471), the fourth GPIO router (461), the third GPIO router (451), and the first GPIO router (431). A pad test input output from the fourth block group (460) can be input to a GPIO pad through the fourth GPIO router (461), the third GPIO router (451), and the first GPIO router (431) in sequence, a pad test input output from the third block group (450) can be input to a GPIO pad through the third GPIO router (451) and the first GPIO router (431), and a pad test input output from the first block group (430) can be input to a GPIO pad through the first GPIO router (431).

[0116] Figure 5 is a detailed configuration diagram of the GPIO router of Figures 2 and 4.

[0117] The GPIO router of FIG. 5 may be any one of the 1-1 GPIO router (261), 1-2 GPIO router (262), 2-1 GPIO router (263), 2-2 GPIO router (264), 2-3 GPIO router (265), 3-1 GPIO router (266), or 3-2 GPIO router (267) of FIG. 2, or may correspond to any one of the 1 GPIO router (431), 3 GPIO router (451), or 4 GPIO router (461) of FIG. 4. The GPIO router includes a plurality of GPIO splitter cells (510, 520) that correspond to each GPIO pad, one side of which is connected to a pad group controller or an upper GPIO router, and the other side of which is connected to a block group and a lower GPIO router.

[0118] Each GPIO splitter cell (510, 520) may include a logical OR operator that performs a logical OR operation on a pad test input (PAD TEST IN) signal output from a block group and a pad test input (PAD TEST IN) signal input from a lower GPIO router and outputs the result to an upper direction (pad group controller or upper GPIO router), and a plurality of buffers that distribute a pad test output (PAD TEST OUT) input from a pad group controller or upper GPIO router to a block group and a lower GPIO router.

[0119] The GPIO router can implement a bidirectional test signal transmission structure that efficiently aggregates pad test input signals from the lower level and transmits them to the upper level, while simultaneously reliably distributing pad test output signals from the upper level via multiple paths.

[0120] GPIO multiplexer

[0121] The SoC can operate in various test mode types depending on the type of test target and the test scope, and the operation method of IP blocks and port I / O may vary according to each test mode type. For example, test mode types may include scan test mode, memory BIST (Built-In Self-Test) mode, logic BIST (Built-In Self-Test) mode, JTAG (Joint Test Action Group) test mode, IJTAG (Internal Joint Test Action Group) test mode, and Automatic Test Equipment interface test mode.

[0122] Depending on each of these test mode types, different data signals for performing tests may be provided to each port of the IP block, and the input / output direction of the port may also be dynamically configured. For example, in the SoC implementation shown in FIG. 2, in the first test mode type, a first pad among the first pad group (211) of the SoC may operate as an input pad, and the input pad may be connected to the first port of the first IP block (221). In this case, a pad test input signal may be transmitted from the first port of the first IP block (221) to the first pad of the first pad group (211).

[0123] Additionally, in the second test mode type, the first pad of the first pad group (211) operates as an output pad and can be connected to the third port of the second IP block (222). In this case, a pad test output signal output from the first pad of the first pad group (211) is transmitted to the third port of the second IP block (222). Additionally, in the third test mode type, the first pad of the first pad group (211) operates as an output pad and can be connected to the fourth port of the first IP block (221). In this case, a pad test output signal output from the first pad of the first pad group (211) is transmitted to the fourth port of the first IP block (221).

[0124] In this way, the first pad of the first pad group (211) can be connected to the first port of the first IP block (221) as an input pad, connected to the third port of the second IP block (222) as an output pad, or connected to the fourth port of the first IP block (223) as an output pad, depending on the test mode type. In other words, for each GPIO pad, the input / output direction and the connection target port must be dynamically set according to the test mode type.

[0125] Referring to FIG. 2, each GPIO pad of the first pad group (211) can be connected to one port selected according to the test mode type among the ports of the first IP block (221) to the fifth IP block (225). That is, the port of the IP block to which each GPIO pad is connected may differ depending on the test environment settings. Similarly, each GPIO pad of the second pad group (212) can also be connected to one port according to the test mode type among the ports of the first IP block (221) to the sixth IP block (226), and each GPIO pad of the third pad group (213) can be selectively connected to one port according to the test mode type among the ports of the fourth IP block (224) to the sixth IP block (226).

[0126] As such, it is desirable that the ports of the IP blocks connected to each GPIO pad of the pad group be selectively configured according to the designer's intent for each test mode type. This allows the SoC designer to set the optimal test path based on test requirements or the configuration of the test equipment.

[0127] To implement this port connection flexibility, all GPIO pads within a pad group are connected to a GPIO multiplexer, and each GPIO pad can have a physical connection path to the ports dynamically established by the GPIO multiplexer.

[0128] In other words, the GPIO multiplexer selects and connects a specific port to each GPIO pad based on control signals input for each test mode type, and blocks connections to the remaining ports, thereby ensuring that only a single port is connected in correspondence with a single test mode type. This configuration allows for flexible support of multiple test scenarios for each GPIO pad, while simultaneously preventing signal collisions or electrical interference by blocking unnecessary paths.

[0129] For example, the first GPIO multiplexer (251) illustrated in FIG. 2 is configured to be hardware-connectable to a first pad included in a first pad group (211) with a first port of a first IP block (221), a third port of a second IP block (222), and a fourth port of a third IP block (223). The ports connected to the first pad are not limited to the first port of the first IP block (221), the third port of the second IP block (222), and the fourth port of the third IP block (223), and may be configured to be connected to any port of the first IP block to the third IP block according to the intention of the SoC designer.

[0130] And, the first GPIO multiplexer (251) controls the first pad to be connected only to the first port of the first IP block (221) in the first test mode type, controls the first pad to be connected only to the third port of the second IP block (222) in the second test mode type, and controls the first pad to be connected only to the fourth port of the third IP block (223) in the third test mode type.

[0131] In this way, the GPIO multiplexer has a hardware configuration in which a single GPIO pad can be connected to multiple ports, but by operating to be connected to only a single port per test mode, it can provide a structure that satisfies the functional requirements of various test modes.

[0132] Conversely, from the perspective of the port, a single port may be selectively connected to any one of multiple GPIO pads in a specific test mode type.

[0133] Figure 6 is a detailed configuration diagram illustrating the GPIO multiplexer of Figure 2.

[0134] The GPIO multiplexer includes a first pad mode selector (611) configured to be connected to a first GPIO pad (601) and receive a test mode signal from a test controller (660) to selectively connect the first GPIO pad (601) to one of a first mapping group (620) or a second mapping group (630); a second pad mode selector (612) configured to be connected to a second GPIO pad (602) and receive a test mode signal from a test controller (660) to connect the second GPIO pad (602) to one of a first mapping group (620) or a third mapping group (640); and a first mapping group (621) configured to receive a Map Select signal (Map Select 1) from a test controller (660) to switch the connection relationship between the first GPIO pad (601) and the second GPIO pad (602), and between the first port (651) and the second port (652).

[0135] A GPIO multiplexer can flexibly change the connection relationships between each GPIO pad, mapping group, and each port based on test mode signals and map selection signals. This allows for support of various connection scenarios in specific test mode types, and since any single port can be selectively connected to one of multiple GPIO pads, it can improve design freedom and test flexibility.

[0136] The GPIO multiplexer may additionally include a third pad mode selector (not shown) and a fourth pad mode selector (not shown). The third pad mode selector is connected to a third GPIO pad (not shown) and receives a test mode signal from a test controller (660) to selectively connect the third GPIO pad to a second mapping group (630). Additionally, the fourth pad mode selector is connected to a fourth GPIO pad (not shown) and receives a test mode signal from a test controller (660) to selectively connect the fourth GPIO pad to a third mapping group (640). The test controller (660) provides a map select signal (Map Select 2) to the second mapping group (630) and a map select signal (Map Select 3) to the third mapping group (640) to control the operation mode of each mapping group.

[0137] The first mapping group (620) is configured to switch the connection between the GPIO pad and the port according to the map select signal (Map Select 1). The first mapping group (620) includes a first-1 pad-port map connection unit (621) configured to operate when the first map is selected and to connect the first GPIO pad (601) to the first port (651) and to connect the second GPIO pad (602) to the second port (652), and a first-2 pad-port map connection unit (622) configured to operate when the second map is selected and to connect the first GPIO pad (601) to the second port (652) and to connect the second GPIO pad (602) to the first port (651).

[0138] The second mapping group (630) is configured to switch the connection between the GPIO pad and the port according to the Map Select signal (Map Select 2). The second mapping group (630) includes a second-1 pad-port map connection unit (631) configured to operate during the first map selection and to connect the first GPIO pad (601) to the third port (653) and to connect the third GPIO pad to the fourth port (654), and a second-2 pad-port map connection unit (632) configured to operate during the second map selection and to connect the first GPIO pad (601) to the fourth port (654) and to connect the third GPIO pad to the third port (653).

[0139] The third mapping group (640) is configured to switch the connection between the GPIO pad and the port according to the Map Select signal (Map Select 3). The third mapping group (640) includes a third-1 pad-port map connection unit (641) configured to operate during the first map selection and to connect the second GPIO pad (602) to the fifth port (655) and the fourth GPIO pad to the sixth port (656), and a third-2 pad-port map connection unit (642) configured to operate during the second map selection and to connect the second GPIO pad (602) to the sixth port (656) and the fourth GPIO pad to the fifth port (655).

[0140] Here, the number of test mode types, the number of mapping groups, the number of GPIO pads and ports connected to each mapping group, and the number of pad-port map connections per mapping group may vary depending on the designer's design and the system's requirements.

[0141] The test controller (660) may be a controller based on the IEEE 1687 standard, i.e., IJTAG (Internal Joint Test Action Group). The test controller (660) enables the output of a test mode signal (TEST MODE) and map select signals (Map Select 1 ~ Map Select 3) by setting the mode & map select register (661) through the IJTAG interface. The mode & map select register (661) may be composed of a test data register (TDR) that operates in a shift manner and may internally include logic elements such as flip-flops.

[0142] The operation of the GPIO multiplexer of FIG. 6 will be explained below.

[0143] The GPIO multiplexer dynamically switches the connection status between each GPIO pad, mapping group, and each port according to the test mode signal (TEST MODE) and map selection signals (Map Select 1 ~ Map Select 3) output from the mode & map selection register (661) of the test controller (660).

[0144] The test controller (660) operates according to the IEEE 1687 standard, namely the IJTAG (Internal Joint Test Action Group) method. The test controller (660) controls the mode & map select register (661) in a shift manner through the IJTAG interface. The mode & map select register (661) is configured to output a test mode signal (TEST MODE) and map select signals (Map Select 1 ~ Map Select 3) according to the shift input value. The test mode signal is distributed simultaneously to all pad mode selectors. That is, all pad mode selectors receive a common test mode signal and control all GPIO pads to operate in the same test mode type. Meanwhile, individual map select signals can be input to each mapping group.

[0145] The first pad mode selector (611) receives a test mode signal and determines whether the first GPIO pad (601) is connected to either the first mapping group (620) or the second mapping group (630). The second pad mode selector (612) receives a test mode signal and determines whether the second GPIO pad (602) is connected to either the first mapping group (620) or the third mapping group (640). Additionally, the third pad mode selector selectively connects the third GPIO pad to the second mapping group (630). The fourth pad mode selector selectively connects the fourth GPIO pad to the third mapping group (640).

[0146] According to the map selection signal (Map Select 1) input from the mode & map selection register (661), when the first map is selected, the first-1 pad-port map connection part (621) of the first mapping group (620) operates to connect the first GPIO pad (601) to the first port (651) and the second GPIO pad (602) to the second port (652). When the second map is selected, the first-2 pad-port map connection part (622) operates to connect the first GPIO pad (601) to the second port (652) and the second GPIO pad (602) to the first port (651).

[0147] Additionally, according to the map selection signal (Map Select 2) input from the mode & map selection register (661), when the first map is selected, the 2-1 pad-port map connection part (631) of the second mapping group (630) operates to connect the first GPIO pad (601) to the third port (653) and the third GPIO pad to the fourth port (654). When the second map is selected, the 2-2 pad-port map connection part (632) operates to connect the first GPIO pad (601) to the fourth port (654) and the third GPIO pad to the third port (653).

[0148] Additionally, according to the map selection signal (Map Select 3) input from the mode & map selection register (661), when the first map is selected, the 3-1 pad-port map connection part (641) of the 3rd mapping group (640) operates to connect the 2nd GPIO pad (602) to the 5th port (655) and the 4th GPIO pad to the 6th port (656). When the 2nd map is selected, the 3-2 pad-port map connection part (642) operates to connect the 2nd GPIO pad (602) to the 6th port (656) and the 4th GPIO pad to the 5th port (655).

[0149] Through this operation, the connection relationship between each GPIO pad and port can be switched in real time according to the test mode signal and map selection signal. Since the same port can be selectively connected to one of multiple GPIO pads, it supports various test scenarios and allows test configurations to be easily expanded without design changes, even in complex systems.

[0150] Hard Macro Interface

[0151] Figure 7 is a detailed configuration diagram of the hard macro interface of Figure 2.

[0152] The hard macro interface of FIG. 7 may be one of the first hard macro interface (241), the second hard macro interface (242), the fourth hard macro interface (244), and the sixth hard macro interface (246) of FIG. 2. If the IP block is a hard macro block, the hard macro interface may be placed between the GPIO multiplexer and the IP block.

[0153] The hard macro interface provides port I / O to each port of the hard macro block in test mode. The port I / O may include at least one of pad test I / O, function port I / O, and register test data transmitted from the pad group controller. Through these various I / O paths, the hard macro interface enables flexible control and verification of each port of the hard macro block under test mode, and allows for the selective configuration of appropriate signal paths according to various test purposes. Accordingly, logic testing, signal flow verification, and fault diagnosis within the hard macro block can be performed efficiently.

[0154] A port of a hard macro block (703) is connected to the hard macro interface, and a hard macro function controller (701) that provides function port input / output to the hard macro port in function mode and test mode, and a GPIO multiplexer (702) that performs pad test input / output with a GPIO pad in test mode are connected.

[0155] The hard macro interface includes a plurality of hard macro interface units (710) configured to correspond to one port of the hard macro block and transmitting port input / output to the corresponding hard macro port in test mode, and a test controller (711) that controls register test data to be output.

[0156] The hard macro interface unit (710) includes decoding logic (713) that selects one of register test data, pad test input / output transmitted from the GPIO multiplexer (702), and function port input / output transmitted from the hard macro function controller (701), and connects it to a port of the hard macro block (703). The hard macro interface unit (710) further includes a first buffer and a second buffer (714, 715) inserted into the input path and output path, respectively, between the decoding logic (713) and the port of the hard macro block (703).

[0157] Depending on the test mode type, the hard macro port may need to transmit and receive function port I / O identical to that of the function mode. For example, to test the performance of other hard macro blocks or other ports within the same hard macro block, function port I / O identical to that of the function mode may need to be transmitted and received on a specific port. Additionally, depending on the test mode type, pad test I / O transmitted and received from GPIO pads may need to be transmitted and received through the corresponding port. In this case, it is possible to test whether signal transmission and reception between the GPIO pad and the port is performed normally.

[0158] For another test mode type, predetermined register test data may need to be input into a hard macro port. In this case, the register test data is set to a fixed value and provided through the port to configure test scenarios. Conversely, in certain test mode types, the port may not be used for testing.

[0159] The SoC designer can pre-set the type of data to be input / output to the hard macro port according to each test mode type, and the decoding logic (713) is configured to select at least one of pad test input / output, function port input / output, and register test data for each test mode type based on the SoC designer's settings and connect it to the corresponding port.

[0160] The test controller (711) may be a controller based on the IEEE 1687 standard (IJTAG: Internal Joint Test Action Group). The test controller (711) can set the test data setting register (712) through the IJTAG interface. The register (712) may each be composed of a test data register (TDR) that operates in a shift manner.

[0161] The test data setting register (712) may be configured as a flip-flop and provides register test data that is output to a port of a hard macro block according to the test mode type. This register test data may be a single-bit or multi-bit signal, and to support multi-bit data, the test data setting register (712) may include multiple flip-flops.

[0162] General Purpose Input / Output (GPIO) Test Configuration Design System

[0163] FIG. 8 is a configuration diagram of a no-code-based general-purpose input / output (GPIO) test configuration design system according to the present invention. The no-code GPIO test configuration design system according to the present invention can be implemented as a computer system.

[0164] A no-code-based GPIO test configuration design system according to the present invention may include a screen window processing unit (810) that detects user input and outputs the processing result of the user input to a display screen; a GPIO test configuration processing unit (820) that designs a GPIO test configuration by creating at least one GPIO test instance based on GPIO test component information and establishing a connection between GPIO test instances; a data storage unit (830) that stores GPIO test component information, a designed GPIO test configuration, and hardware code logic; and a hardware code processing unit (840) that generates hardware code corresponding to the designed GPIO test configuration using the hardware code logic.

[0165] In the present invention, the term "GPIO test component" may refer to tools that can be utilized in designing a General Purpose Input / Output (GPIO) test configuration. The GPIO test component may include a pad group controller component, a GPIO router component, a GPIO multiplexer component, and a hard macro interface component. The GPIO test component may be displayed as an icon in the component window.

[0166] In the present invention, a GPIO test instance may be a GPIO test component added to the design window by user operation. That is, a GPIO test instance may be a GPIO test component included in the GPIO test configuration. When a user drags and drops any GPIO test component icon from the component window into the design window area, a GPIO test instance corresponding to that GPIO test component may be created.

[0167] A GPIO test configuration may include multiple GPIO test instances. A GPIO test instance created based on a pad group controller component is called a pad group controller instance, a GPIO test instance created based on a GPIO router component is called a GPIO router instance, a GPIO test instance created based on a GPIO multiplexer component is called a GPIO multiplexer instance, and a GPIO test instance created based on a hard macro interface component is called a hard macro interface instance. In the case of the GPIO test configuration of FIG. 2, it may be designed to include three pad group controller instances, seven GPIO router instances, three GPIO multiplexer instances, and four hard macro interface instances.

[0168] By generating hardware code based on a designed GPIO test instance, the general-purpose I / O test configuration of FIG. 2 can be implemented. For example, by generating hardware code based on a pad group controller instance, the pad group controller of FIG. 2 and FIG. 3 can be implemented, and by generating hardware code based on a GPIO router instance, the GPIO router of FIG. 2, FIG. 4 and FIG. 5 can be implemented. By generating hardware code based on a GPIO multiplexer instance, the GPIO multiplexer of FIG. 2 and FIG. 6 can be implemented, and by generating hardware code based on a hard macro interface instance, the hard macro interface of FIG. 2 and FIG. 7 can be implemented.

[0169] Each GPIO test instance of the present invention may include a plurality of submodules.

[0170] For example, a pad group controller instance may include at least one pad interface submodule and a test controller submodule. If hardware code is generated based on the pad interface submodule, the pad interface (310, 320) of FIG. 3 can be implemented, and if hardware code is generated based on the test controller submodule, the test controller (330) of FIG. 3 can be implemented.

[0171] A GPIO router instance may include multiple GPIO splitter cell submodules. By generating hardware code based on the GPIO splitter cell submodules, the GPIO splitter cells (510, 520) of FIG. 5 can be implemented.

[0172] A GPIO multiplexer instance may include a plurality of pad mode selection submodules and a plurality of mapping group submodules. If hardware code is generated based on the pad mode selection submodules, the pad mode selection (611, 612) of FIG. 6 can be implemented, and if hardware code is generated based on the mapping group submodules, the mapping group (620, 630, 640) of FIG. 6 can be implemented.

[0173] A hard macro interface instance may include a plurality of hard macro interface unit submodules and test controller submodules. If hardware code is generated based on the hard macro interface unit submodules, the hard macro interface unit (710) of FIG. 7 can be implemented, and if hardware code is generated based on the test controller submodules, the test controller (711) of FIG. 7 can be implemented.

[0174] FIG. 9 is a diagram showing an example of a display screen of a no-code-based general-purpose input / output (GPIO) test configuration design system according to the present invention.

[0175] The display screen of the no-code-based GPIO test configuration design system of the present invention may include a command window (910) into which user commands are entered, a component window (920) in which GPIO test component icons are displayed, a content window (930) which provides an environment for adding, deleting, and changing a list of GPIO test configurations under design and hierarchically displays information on GPIO test instances included in each GPIO test configuration under design, a design window (940) which displays a diagram of the GPIO test configuration under design and provides an environment for adding, deleting, and changing GPIO test instances included in the GPIO test configuration under design, and a setting window (950) which provides an environment for setting the type, number, and connection of submodules included in the GPIO test instance selected in the design window (940).

[0176] The command window (910) may include a CHECK button for receiving a check command for errors in the GPIO test instances included in the GPIO test configuration under design and the diagram of the GPIO test configuration under design, an UNCHECK button for receiving a command to disable the check results, a SAVE button for receiving a save command for the diagram of the GPIO test configuration displayed in the design window (940), and a GENRTL button for receiving a hardware code generation command for the diagram of the GPIO test configuration displayed in the design window (940).

[0177] Icons of GPIO test components that can be used to design a GPIO test configuration may be displayed in the component window (920). The GPIO test components may include a pad group controller component, a GPIO router component, a GPIO multiplexer component, and a hard macro interface component. Each GPIO test component internally includes multiple submodules. For example, a pad group controller instance includes at least one pad interface submodule and a test controller submodule, and a GPIO router instance includes multiple GPIO splitter cell submodules. A GPIO multiplexer instance includes multiple pad mode selector submodules and multiple mapping group submodules, and a hard macro interface instance includes multiple hard macro interface unit submodules and a test controller submodule. The type, number, and connection of the submodules included in each GPIO test instance may be determined according to the instance settings.

[0178] The content window (930) displays a list of GPIO test configurations under design and provides an environment for adding, deleting, and changing GPIO test configurations under design. Additionally, under each list of GPIO test configurations under design, a list of GPIO test instances included in the corresponding GPIO test configuration under design is displayed.

[0179] The design window (940) displays a diagram of the GPIO test configuration under design and provides an environment for adding, deleting, and changing GPIO test instances included in the GPIO test configuration under design. When a user moves any GPIO test component from the component window (920) to the design window (940) using a drag-and-drop operation, the GPIO test configuration under design may include a GPIO test instance corresponding to that GPIO test component.

[0180] The configuration window (950) provides a functional configuration environment for the GPIO test instance selected in the design window (940). Through the configuration window (950), instance configuration values ​​can be entered in a table format, and based on this, the type, number, and connection of submodules included in the GPIO test instance can be determined.

[0181] Screen window processing unit (810)

[0182] The screen window processing unit (810) may include a command window processing unit (811) that displays a button for receiving user commands in the command window (910) and detects the input of each button in the command window (910) to perform an action corresponding to the input button; a content window processing unit (812) that hierarchically displays a list of GPIO test configurations under design and a list of GPIO test instances included in each GPIO test configuration under design in the content window (930) and detects user input in the content window (930) to perform an action corresponding to the user input; a design window processing unit (813) that displays a diagram of a GPIO test configuration under design selected by the user in the design window (940) and detects user input in the design window (940) to perform an action corresponding to the user input; and a setting window processing unit (814) that inputs instance setting values ​​for GPIO test instances in a table form in the setting window (950).

[0183] When the CHECK button is selected, the command window processing unit (811) performs an error check operation on the diagram of the GPIO test configuration under design, etc., so that the part where the error occurred is displayed. When the UNCHECK button is selected, the part of the error displayed on the diagram of the GPIO test configuration under design is restored to its original state and displayed. When the SAVE button is selected, the work content of the GPIO test configuration under design displayed in the design window (940) is saved to the data storage (830). When the GENRTL button is selected, hardware code for the GPIO test configuration under design displayed in the design window (940) is generated.

[0184] The content window processing unit (812) provides an environment for adding, deleting, and changing the list of GPIO test configurations under design and the list of GPIO test instances included in each GPIO test configuration under design. The content window processing unit (812) can hierarchically display GPIO test instance list information under each GPIO test configuration under design. The user can add, delete, or rename the GPIO test configurations under design in the content window (930), and in response to the user's input, the GPIO test configurations under design can be added, deleted, or changed in the GPIO test configuration repository (832). When the user changes the name of a GPIO test configuration under design, the content window processing unit (812) can cause not only the name of the GPIO test configuration under design but also the names of the GPIO test instances under that GPIO test configuration under design to be changed in bulk.

[0185] The design window processing unit (813) displays a diagram of the GPIO test configuration under design in the design window (940) and provides an environment for adding, deleting, and changing GPIO test instances that constitute the GPIO test configuration under design. When a user performs an action to add any GPIO test component of the component window (920) to the design window (940), the design window processing unit (813) detects this and causes the operation to add a GPIO test instance to be performed.

[0186] The configuration window processing unit (814) displays configuration information of the GPIO test configuration during design and detects user input in the configuration window (950) to perform an action corresponding to the user input. In particular, instance configuration values ​​for configuring submodules of the GPIO test instance are input in a table format.

[0187] Data storage (830)

[0188] The data storage (830) may include a component storage (831) that stores GPIO test component information, a GPIO test configuration storage (832) that stores a list of GPIO test instances included in the GPIO test configuration being designed, a GPIO test instance storage (833) that stores functional information of individual GPIO test instances included in the GPIO test configuration being designed, and a hardware code logic storage (834) that stores hardware code logic for generating hardware code based on the designed GPIO test configuration information.

[0189] The GPIO test components stored in the component repository (831) may include a pad group controller component, a GPIO router component, a GPIO multiplexer component, and a hard macro interface component. Each GPIO test component may include multiple submodules. The component repository (831) may store the type of submodule, the creation rule for each submodule, the port creation rule, and the connection creation rule with other components for each GPIO test component.

[0190] The GPIO test configuration repository (832) stores a list of GPIO test instances included in the GPIO test configuration being designed. When designing the GPIO test configuration of FIG. 2, the GPIO test configuration repository (832) may store a list of three pad group controller instances, a list of seven GPIO router instances, a list of three GPIO multiplexer instances, and a list of four hard macro interface instances.

[0191] The GPIO test instance storage (833) stores configuration information for each GPIO test instance included in the GPIO test configuration during design. The configuration values ​​of the GPIO test instances can be provided in a table form through the configuration window (950).

[0192] Table 1 is an example of an instance configuration value input table that determines the types, number, and connections of submodules that make up a pad group controller instance. Based on the configuration values ​​of the pad group controller instance, the number of pad interface submodules that make up the pad group controller instance, as well as the internal components and internal connections of the pad interface submodules, are determined.

[0193] GPIODSPEPUIEOE1GPIO02GPIO13GPIO24GPIO35GPIO46GPIO57GPIO6

[0194] To configure a pad group controller instance, pad test operation control settings for the GPIO pads connected to the pad group controller instance are input. As for this pad test operation control, one of Drive Strength (DS), Pull Enable (PE), Pull Up / Down (PU), Input Enable (IE), or Output Enable (OE) can be configured to be active. Submodules of the pad group controller instance are configured based on the pad test operation control settings. As shown in the example in Table 1, when pad test operation control settings for seven GPIO pads are input, the pad group controller instance can be configured to include seven pad interface submodules. Additionally, the test controller submodule can be configured to include a flip-flop block for test mode control and multiple flip-flop blocks for pad test operation control for each of the seven pad interface submodules. Furthermore, connections between each pad interface submodule and the corresponding GPIO pad can be determined.

[0195] Table 2 is an example of an instance configuration value input table that determines the type, number, and connection of submodules configuring a GPIO multiplexer instance.

[0196] Pad Group GPIO Test Mode 1 Test Mode 2 Mapping Group 1 Mapping Group 2 Mapping Group 1 Mapping Group 2 Pad Group Name GPIO0I, PCIE_IN0I, PCIE_IN2PLL_AA_ICP0PLL_AA_ICP4GPIO1I, PCIE_IN1I, PCIE_IN3PLL_AA_ICP1PLL_AA_ICP5GPIO2I, PCIE_IN2I, PCIE_IN4PLL_AA_ICP2PLL_AA_ICP6GPIO3I, PCIE_IN3I, PCIE_IN5PLL_AA_ICP3PLL_AA_ICP0GPIO4I, PCIE_IN4I, PCIE_IN6PLL_AA_ICP4PLL_AA_ICP1GPIO5I, PCIE_IN5I, PCIE_IN0PLL_AA_ICP5PLL_AA_ICP2GPIO6I, PCIE_IN6I, PCIE_IN1PLL_AA_ICP6PLL_AA_ICP3

[0197] To configure a GPIO multiplexer instance, port information of IP blocks connected to each GPIO pad in test mode and mapping group is input as a setting value. The internal circuitry of the pad mode selection submodule can be configured according to the number of test modes setting value, and the number of mapping group submodules can be configured according to the number of mapping groups setting value. Additionally, the connection between the mapping group submodule and the port of the IP block can be configured according to the port information connected to the GPIO pad for each test mode. Furthermore, the test controller submodule can be configured to include a flip-flop block for controlling test modes and a plurality of flip-flop blocks for controlling mapping group selection.

[0198] The hardware code logic storage (834) stores hardware code logic for generating hardware code based on the designed GPIO test configuration, GPIO test instance information, and submodule information configuring the GPIO test instance. The hardware code logic storage (834) may include hardware code logic corresponding to the submodule of each GPIO test instance, hardware code logic corresponding to the port formed in each submodule, and hardware code logic corresponding to the connection between each submodule and an external component.

[0199] GPIO test configuration processing unit (820)

[0200] The GPIO test configuration processing unit (820) includes a GPIO test configuration management unit (821), a GPIO test instance management unit (822), a table processing unit (823), and a sub-module setting unit (824).

[0201] The GPIO test configuration management unit (821) manages the GPIO test configuration during design overall. It comprehensively performs tasks such as creating, adding, deleting, and renaming GPIO test configurations according to user commands received through the command window (910), content window (930), and design window (940). The GPIO test configuration management unit (821) stores the GPIO test configuration during design in the GPIO test configuration repository (832).

[0202] The GPIO test instance management unit (822) creates a GPIO test instance corresponding to a GPIO test component when a user drags and drops a GPIO test component icon onto the design window (940) while the GPIO test configuration is displayed in the design window (940). The GPIO test instance management unit (822) processes user operations input from the design window (940) to establish connections (logical connection relationships) between GPIO test instances. Additionally, the list of created GPIO test instances and connection information are stored in the GPIO test instance storage (833).

[0203] The table processing unit (823) collects and structures the configuration values ​​of the GPIO test instance input through the configuration window (950). The table processing unit (823) receives user input in the form of a table displayed in the configuration window (950) and stores it as instance configuration values ​​in the GPIO test instance storage (833). At this time, the table processing unit (823) may perform a primary validation check to see if the input instance configuration values ​​do not violate the SoC hardware structure and DFT design rules.

[0204] The sub-module configuration unit (824) determines the quantity and type of sub-modules configuring the GPIO test instance, the number of flip-flops configuring the internal test controller sub-module, and connections based on the result of the table processing unit (823). For example, it is assumed that instance configuration values ​​for configuring the GPIO multiplexer of FIG. 6 are input. Based on the instance configuration values, the sub-module configuration unit (824) determines the internal circuit configuration of two pad mode selection unit sub-modules, adds ports to each pad mode selection unit sub-module, and adds connections to each GPIO pad for each port. Additionally, the sub-module configuration unit (824) determines the internal circuit configuration of three mapping group sub-modules, adds ports to each mapping group sub-module, adds connections between each mapping group sub-module and the pad mode selection unit sub-module, adds connections between the mapping group sub-module and the port, adds connections between the pad mode selection unit sub-module and the test controller sub-module, and adds connections between the mapping group sub-module and the test controller sub-module. In addition, determine the number of flip-flops constituting the test controller submodule. Ensure that the test controller submodule is implemented based on the built-in IEEE1687 standard.

[0205] Hardware code processing unit (840)

[0206] The hardware code processing unit (840) generates hardware code for the designed GPIO test configuration. The hardware code processing unit (840) includes a submodule code generation unit that generates hardware code corresponding to a submodule configuring the GPIO test instance, a port code generation unit (842) that generates hardware code corresponding to a port added to the submodule of the GPIO test instance, and a connection code generation unit (843) that generates hardware code corresponding to a connection included in the GPIO test instance.

[0207] The hardware code processing unit (840) can be executed when the GENRTL button of the command window (910) is selected. The user can execute the GENRTL button by selecting it while a diagram of the GPIO test configuration under design is displayed in the design window (940), and can also verify in advance whether there are errors in the diagram by executing the check button before executing the GENRTL button.

[0208] FIG. 10 is an operation flowchart illustrating a no-code method for designing a GPIO test configuration according to the present invention. The no-code method for designing a GPIO test configuration according to the present invention can be executed by a processor of a computer system.

[0209] The computer system includes a component repository that stores GPIO test component information and a hardware code logic repository that stores hardware code logic for generating a designed GPIO test configuration into hardware code.

[0210] The processor creates a GPIO test instance based on GPIO test component information (S1010). This step of creating a GPIO test instance can be performed by the user selecting one of the GPIO test component icons displayed in the component window and dragging and dropping it into the design window area. The GPIO test instances include a pad group controller instance, a GPIO router instance, a GPIO multiplexer instance, and a hard macro interface instance. Depending on the GPIO test configuration, at least two steps of creating a pad group controller instance may be repeated. Additionally, in the GPIO test configuration, at least one type of GPIO test instance among the GPIO router instance, GPIO multiplexer instance, and hard macro interface instance may not be created, or all types of GPIO test instances may be created repeatedly multiple times.

[0211] The processor establishes connections between GPIO test instances (S1020). For example, it establishes a connection between a pad group controller instance and a GPIO pad, establishes a connection between a pad group controller instance and a GPIO router instance or a GPIO multiplexer instance, establishes a connection between a GPIO router instance and a GPIO multiplexer instance, establishes a connection between a GPIO multiplexer instance and a hard macro interface instance, and establishes a connection between a GPIO multiplexer instance or a hard macro interface instance and an IP block.

[0212] To specify the function of the GPIO test instance, the processor receives and processes instance setting values ​​for each GPIO test instance in the form of a table (S1030). When a user selects any GPIO test instance in the design window, the input environment for the instance setting values ​​of the selected GPIO test instance is displayed in the configuration window in the form of a table. The user can input instance setting values ​​using this table.

[0213] For example, instance configuration values ​​for a pad group controller instance may include a list of GPIO pads associated with the pad group controller instance and pad test operation control configuration values ​​for each GPIO pad. Additionally, instance configuration values ​​for a GPIO multiplexer instance may include at least one test mode and port configuration values ​​of IP blocks connected per GPIO in at least one mapping group.

[0214] The processor can perform a primary validation of the instance configuration values ​​entered by the user against the SoC design rules and then save them to the GPIO test instance storage.

[0215] Next, the processor determines the type, number, port, and connection of submodules included in each GPIO test instance based on the instance configuration value entered by the user, the submodule type, submodule creation rule, port creation rule, and connection creation rule for each GPIO test component, and determines the number and connection of flip-flops constituting the test controller submodule included in the GPIO test instance (S1040).

[0216] Next, when the user selects the GenRTEL button in the command window, the processor generates hardware code corresponding to the GPIO test configuration using the hardware code logic stored in the hardware code logic repository (S1050). That is, it generates hardware code corresponding to the submodule determined for each GPIO test instance, generates hardware code corresponding to the port added to each submodule, and generates hardware code corresponding to the connection of each GPIO test instance and submodule.

[0217] FIG. 11 illustrates an exemplary computing device (1100) for performing the above-described method and / or embodiment, etc. According to one embodiment, the computing device (1100) may be implemented using hardware and / or software configured to interact with a user. Here, the computing device (1100) may include, but is not limited to, a laptop, a desktop, a workstation, a personal digital assistant, a server, a blade server, a main frame, etc. The components of the above-described computing device (1100), their connection relationships, and their functions are intended to be exemplary and are not intended to limit the embodiments of the invention described and / or claimed herein.

[0218] The computing device (1100) includes a processor (1110), memory (1120), storage device (1130), communication device (1140), a high-speed interface (1150) connected to the memory (1120) and a high-speed expansion port, and a low-speed interface (1160) connected to the low-speed bus and storage device. Each of the components (1110, 1120, 1130, 1140, 1150, and 1160) may be interconnected using various buses and may be mounted on the same mainboard or connected in other suitable ways. The processor (1110) may be configured to process instructions of a computer program by performing basic arithmetic, logic, and input / output operations. For example, the processor (1110) can process instructions stored in memory (1120), storage device (1130), etc., and / or instructions executed within the computing device (1100) to display graphic information on an external input / output device (1170), such as a display device coupled to a high-speed interface (1150).

[0219] The communication device (1140) may provide a configuration or function for the input / output device (1170) and the computing device (1100) to communicate with each other via a network, and may provide a configuration or function to support the input / output device (1170) and / or the computing device (1100) communicating with other external devices, etc. For example, a request or data generated by the processor of an external device according to any program code may be transmitted to the computing device (1100) via a network under the control of the communication device (1140). Conversely, a control signal or command provided under the control of the processor (1110) of the computing device (1100) may be transmitted to another external device via the communication device (1140) and the network.

[0220] In FIG. 11, a computing device (1100) is depicted as including one processor (1110), one memory (1120), etc., but is not limited thereto, and the computing device (1100) may be implemented using multiple memories, multiple processors and / or multiple buses, etc. Additionally, in FIG. 11, it is described as having one computing device (1100), but is not limited thereto, and multiple computing devices may interact and perform operations necessary to execute the method described above.

[0221] Memory (1120) can store information within a computing device (1100). According to one embodiment, memory (1120) may be composed of a volatile memory unit or a plurality of memory units. Additionally or alternatively, memory (1120) may be composed of a non-volatile memory unit or a plurality of memory units. Furthermore, memory (1120) may be composed of other forms of computer-readable media, such as a magnetic disk or an optical disk. Additionally, memory (1120) may store an operating system and at least one program code and / or instruction.

[0222] The storage device (1130) may be one or more mass storage devices for storing data for the computing device (1100). For example, the storage device (1130) may be a computer-readable medium including a magnetic disc such as a hard disk or removable disk, an optical disc, a semiconductor memory device such as an EPROM (Erasable Programmable Read-Only Memory), an EEPROM (Electrically Erasable PROM), or a flash memory device, or may be configured to include such a computer-readable medium. Additionally, a computer program may be tangibly implemented on such a computer-readable medium.

[0223] The high-speed interface (1150) and the low-speed interface (1160) may be means for interaction with an input / output device (1170). For example, the input device may include a device such as a camera including an audio sensor and / or an image sensor, a keyboard, a microphone, a mouse, etc., and the output device may include a device such as a display, a speaker, a haptic feedback device, etc. In another example, the high-speed interface (1150) and the low-speed interface (1160) may be means for interfacing with a device in which the configuration or function for performing input and output is integrated into one, such as a touchscreen, etc.

[0224] According to one embodiment, the high-speed interface (1150) manages bandwidth-intensive operations for the computing device (1100), while the low-speed interface (1160) may manage less bandwidth-intensive operations than the high-speed interface (1150), but such function assignments are merely exemplary. According to one embodiment, the high-speed interface (1150) may be coupled to high-speed expansion ports capable of accommodating memory (1120), an input / output device (1170), and various expansion cards (not shown). Additionally, the low-speed interface (1160) may be coupled to a storage device (1130) and a low-speed expansion port. Furthermore, the low-speed expansion port, which may include various communication ports (e.g., USB, Bluetooth, Ethernet, wireless Ethernet), may be coupled to one or more input / output devices (1170), such as a keyboard, a pointing device, or a scanner, or to a networking device such as a router or a switch via a network adapter.

[0225] The computing device (1100) may be implemented in a number of different forms. For example, the computing device (1100) may be implemented as a standard server or as a group of such standard servers. Additionally or alternatively, the computing device (1100) may be implemented as part of a rack server system or as a personal computer such as a laptop computer. In this case, components from the computing device (1100) may be combined with other components within any mobile device (not shown). The computing device (1100) may include one or more other computing devices or be configured to communicate with one or more other computing devices.

[0226] In FIG. 11, the input / output device (1170) is depicted as not being included in the computing device (1100), but is not limited thereto and may be configured as a single device with the computing device (1100). Additionally, in FIG. 11, the high-speed interface (1150) and / or low-speed interface (1160) are depicted as elements configured separately from the processor (1110), but are not limited thereto and the high-speed interface (1150) and / or low-speed interface (1160) may be configured to be included in the processor (1110).

[0227] The methods and / or various embodiments described above may be realized in digital electronic circuits, computer hardware, firmware, software, and / or combinations thereof. Various embodiments of the present invention may be executed by a data processing device, for example, one or more programmable processors and / or one or more computing devices, or implemented as a computer program stored on a computer-readable medium and / or on a computer-readable medium. The computer program described above may be written in any form of programming language, including a compiled language or an interpreted language, and may be distributed in any form, such as a standalone program, a module, or a subroutine. The computer program may be distributed through a single computing device, a plurality of computing devices connected through the same network, and / or a plurality of computing devices distributed to be connected through a plurality of different networks.

[0228] The above-described methods and / or various embodiments may be performed by one or more processors configured to execute one or more computer programs that process, store, and / or manage any functions, functions, etc. by operating based on input data or generating output data. For example, the methods and / or various embodiments of the present invention may be performed by special-purpose logic circuits such as a Field Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (ASIC), and an apparatus and / or system for performing the methods and / or embodiments of the present invention may be implemented as a special-purpose logic circuit such as an FPGA or an ASIC.

[0229] One or more processors executing a computer program may include one or more processors of a general-purpose or special-purpose microprocessor and / or any type of digital computing device. The processor may receive instructions and / or data from each of read-only memory and random access memory, or receive instructions and / or data from read-only memory and random access memory. In the present invention, components of a computing device performing the methods and / or embodiments may include one or more processors for executing instructions and one or more memories for storing instructions and / or data.

[0230] According to one embodiment, a computing device may exchange data with one or more mass storage devices for storing data. For example, the computing device may receive and / or receive data from a magnetic disc or an optical disc, and may transfer data to a magnetic disc or an optical disc. A computer-readable medium suitable for storing instructions and / or data associated with a computer program may include, but is not limited to, any form of non-volatile memory including semiconductor memory devices such as EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electrically Erasable PROM), and flash memory devices. For example, the computer-readable medium may include magnetic discs such as internal hard disks or removable disks, photomagnetic discs, CD-ROMs, and DVD-ROMs.

[0231] To provide interaction with a user, the computing device may include, but is not limited to, a display device for providing or displaying information to the user (e.g., CRT (Cathode Ray Tube), LCD (Liquid Crystal Display), etc.) and a pointing device (e.g., keyboard, mouse, trackball, etc.) on which the user can provide input and / or commands, etc. on the computing device. That is, the computing device may further include any other type of device for providing interaction with the user. For example, the computing device may provide any form of sensory feedback to the user for interaction with the user, including visual feedback, auditory feedback and / or tactile feedback. In this regard, the user may provide input to the computing device through various gestures such as visual, vocal, and motion.

[0232] In the present invention, various embodiments may be implemented in a computing device comprising back-end components (e.g., data servers), middleware components (e.g., application servers), and / or front-end components. In this case, the components may be interconnected by any form or medium of digital data communication, such as a communication network. According to one embodiment, the communication network may be composed of a wired network such as Ethernet, Power Line Communication, telephone line communication devices, and RS-serial communication, a mobile communication network, a Wireless LAN (WLAN), a wireless network such as Wi-Fi, Bluetooth, and ZigBee, or a combination thereof. For example, the communication network may include a Local Area Network (LAN), a Wide Area Network (WAN), etc.

[0233] A computing device based on the exemplary embodiments described herein may be implemented using hardware and / or software configured to interact with a user, including a user device, a user interface (UI) device, a user terminal, or a client device. For example, the computing device may include a portable computing device such as a laptop computer. Additionally or alternatively, the computing device may include, but is not limited to, Personal Digital Assistants (PDAs), tablet PCs, game consoles, wearable devices, Internet of Things (IoT) devices, Virtual Reality (VR) devices, Augmented Reality (AR) devices, etc. The computing device may further include other types of devices configured to interact with a user. Additionally, the computing device may include a portable communication device suitable for wireless communication over a network such as a mobile communication network (e.g., a mobile phone, a smartphone, a wireless cellular phone, etc.). A computing device may be configured to communicate wirelessly with a network server using wireless communication technologies and / or protocols such as radio frequency (RF), microwave frequency (MWF) and / or infrared frequency (IRF).

[0234] Various embodiments of the present invention, including specific structural and functional details, are exemplary. Accordingly, the embodiments of the present invention are not limited to those described above and may be implemented in various other forms. Furthermore, the terms used in the present invention are intended to describe some embodiments and are not to be interpreted as limiting the embodiments. For example, singular words and the above may be interpreted to include plural forms unless the context clearly indicates otherwise.

[0235] In this invention, unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which such concepts belong. Furthermore, commonly used terms, such as those defined in advance, should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology.

[0236] Although the present invention has been described in relation to some embodiments, various modifications and changes may be made without departing from the scope of the invention as understood by a person skilled in the art to which the invention pertains. Furthermore, such modifications and changes should be considered to fall within the scope of the claims appended to this specification.

Claims

1. As a system for designing GPIO test configurations based on no-code, Memory configured to store at least one instruction, GPIO test component repository where GPIO test component information is stored, A hardware code logic repository for storing hardware code logic for generating a designed GPIO test configuration into hardware code, and It includes at least one processor configured to execute at least one instruction stored in the memory, and The above at least one instruction is, Based on the above GPIO test component information, at least one GPIO test instance is created, and It provides an environment for inputting configuration values ​​of the above GPIO test instance, and Based on the configuration values ​​of the above GPIO test instance, the type, number, port, and connection of the submodules constituting the above GPIO test instance are determined, and Instructions for generating hardware code corresponding to a GPIO test configuration based on the submodules, ports, and connections for each GPIO test instance and the hardware code logic, No-code based GPIO test configuration design system.

2. In Paragraph 1, The above GPIO test instance comprises at least one of a pad group controller instance, a GPIO router instance, a GPIO multiplexer instance, and a hard macro interface instance. No-code based GPIO test configuration design system.

3. In Paragraph 2, The above setting value input environment is displayed in a table format, No-code based GPIO test configuration design system.

4. In Paragraph 2, The configuration value of the above pad group controller instance includes a list of GPIO pads associated with the above pad group controller instance and a pad test operation control configuration value for each GPIO pad, No-code based GPIO test configuration design system.

5. In Paragraph 4, The above at least one instruction is, Commands for determining the number of pad interface submodules constituting the pad group controller instance based on the configuration values ​​of the pad group controller instance, and the internal components and internal connections of the pad interface submodules. No-code based GPIO test configuration design system.

6. In Paragraph 2, The configuration value of the above GPIO multiplexer instance includes the port configuration value of an IP block connected for each GPIO pad in at least one test mode and at least one mapping group, No-code based GPIO test configuration design system.

7. In Paragraph 6, The above at least one instruction is, Commands for determining the internal components and internal connections of a pad mode selection submodule configuring the GPIO multiplexer instance based on the configuration values ​​of the GPIO multiplexer instance, the number of mapping group submodules, the internal components and internal connections of the mapping group submodules, and the connection between the pad mode selection submodule and the mapping group submodule. No-code based GPIO test configuration design system.

8. In Paragraph 1, The above at least one instruction is, Further including commands for determining the number of flip-flops and connections of a test controller submodule included in the GPIO test instance based on the configuration value of the GPIO test instance, No-code based GPIO test configuration design system.

9. In Paragraph 8, The above test controller submodule is implemented based on the built-in IEEE1687 standard, No-code based GPIO test configuration design system.

10. In Paragraph 2, The above at least one instruction is, Based on the above GPIO test component information, at least two types of GPIO test instances are created, and Further including commands for receiving and processing connections between the above two or more types of GPIO test instances, No-code based GPIO test configuration design system.

11. A no-code-based GPIO test configuration design method performed by at least one processor in a computer system comprising a GPIO test component repository storing GPIO test component information and a hardware code logic repository storing hardware code logic for generating a designed GPIO test configuration as hardware code, The step of creating at least one GPIO test instance based on the above GPIO test component information, and A step of providing an input environment for setting values ​​of the above GPIO test instance, A step of determining the type, number, port, and connection of submodules constituting the GPIO test instance based on the configuration values ​​of the GPIO test instance, and A step comprising generating hardware code corresponding to a GPIO test configuration based on the submodules, ports, connections, and hardware code logic for each GPIO test instance. No-code based GPIO test configuration design method.

12. In Paragraph 11, The above GPIO test instance comprises at least one of a pad group controller instance, a GPIO router instance, a GPIO multiplexer instance, and a hard macro interface instance. No-code based GPIO test configuration design method.

13. In Paragraph 12, The above setting value input environment is displayed in a table format, No-code based GPIO test configuration design method.

14. In Paragraph 12, The configuration value of the above pad group controller instance includes a list of GPIO pads associated with the above pad group controller instance and a pad test operation control configuration value for each GPIO pad, No-code based GPIO test configuration design method.

15. In Paragraph 14, The method further includes the step of determining the number of pad interface submodules constituting the pad group controller instance, and the internal components and internal connections of the pad interface submodules, based on the configuration values ​​of the pad group controller instance. No-code based GPIO test configuration design method.

16. In Paragraph 12, The configuration value of the above GPIO multiplexer instance includes the port configuration value of an IP block connected for each GPIO pad in at least one test mode and at least one mapping group, No-code based GPIO test configuration design method.

17. In Paragraph 16, The method further includes the step of determining the internal components and internal connections of the pad mode selection submodule configuring the GPIO multiplexer instance based on the configuration values ​​of the GPIO multiplexer instance, the number of mapping group submodules, the internal components and internal connections of the mapping group submodules, and the connections between the pad mode selection submodule and the mapping group submodule. No-code based GPIO test configuration design method.

18. In Paragraph 11, The method further includes the step of determining the number of flip-flops and connections of a test controller submodule included in the GPIO test instance based on the configuration values ​​of the GPIO test instance. No-code based GPIO test configuration design method.

19. In Paragraph 18, The above test controller submodule is implemented based on the built-in IEEE1687 standard, No-code based GPIO test configuration design method.

20. In Paragraph 12, The step of creating at least two types of GPIO test instances based on the above GPIO test component information, and A method further comprising the step of receiving and processing connections between the above two or more types of GPIO test instances, No-code based GPIO test configuration design method.

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