High-efficiency Class-D amplifier with reduced EMI generation

Abstract

A class D amplifier includes a signal processing block. The signal processing block generates a first processed signal indicating a difference between a first differential signal and a second differential signal when a duty cycle of the first differential signal is greater than a duty cycle of the second differential signal. The signal processing block generates a first processed signal indicating a reference DC level when a duty cycle of the first differential signal is less than a duty cycle of the second differential signal. The signal processing block generates a second processed signal indicating a difference between the second differential signal and the first differential signal when a duty cycle of the second differential signal is greater than a duty cycle of the first differential signal, and generates a second processed signal indicating a reference DC level when a duty cycle of the second differential signal is less than a duty cycle of the first differential signal.

Description

[0001] This application is a divisional application of a Chinese patent application with an application date of May 8, 2015, application number 201510234028.6, and name “High Efficiency Class D Amplifier with Reduced EMI Generation”. Technical Field

[0002] The present disclosure relates to the technical field of class-D audio amplifiers, and more particularly to a class-D amplifier design having reduced EMI compared to conventional class-D amplifiers. Background Art

[0003] Portable electronic devices such as smart phones and tablet computers are popular with consumers. These portable electronic devices are capable of playing back audio and therefore employ audio amplifiers. Because these portable electronic devices are powered by batteries, reducing energy consumption is a business need, and class D audio amplifiers, which are more efficient than class AB audio amplifiers, can potentially be applied to these electronic devices.

[0004] A Class D amplifier is an electronic amplifier in which the amplifying device (usually a MOSFET) operates as an electronic switch rather than a linear gain device as in other amplifiers. The analog signal to be amplified is converted to a sequence of square pulses before being applied to the amplifying device. Because the signal to be amplified is a sequence of constant amplitude pulses, the amplifying device switches back and forth rapidly between conductive and non-conductive states. After amplification, the output pulse sequence can be converted back to an analog signal by passing it through a passive low-pass filter.

[0005] As described above, an advantage of a Class D amplifier is that it can be more efficient than other amplifiers because less power is dissipated as heat in the active devices. However, the switching of the active devices results in increased EMI, which is particularly undesirable in smartphones and tablets. In this regard, an improved Class D amplifier that reduces EMI is commercially desirable. Summary of the invention

[0006] This Summary is provided to present a selection of concepts that are further described below in the Detailed Description. This Summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used as an aid in limiting the scope of the claimed subject matter.

[0007] The electronic device according to the present disclosure includes a first comparator and a second comparator configured to convert a first analog audio input signal and a second analog audio input signal into a first audio square wave and a second audio square wave, respectively. The logic block is coupled to receive the first audio square wave and the second audio square wave from the first comparator and the second comparator. The logic block is configured to generate a first processed audio signal representing the difference between the first audio square wave and the second audio square wave when the duty cycle of the first audio square wave is greater than the duty cycle of the second audio square wave, generate a first processed audio signal with a reference DC level when the duty cycle of the first audio square wave is less than the duty cycle of the second audio square wave, generate a second processed audio signal representing the difference between the second audio square wave and the first audio square wave when the duty cycle of the second audio square wave is greater than the duty cycle of the first audio square wave, and generate a second processed audio signal with a reference DC level when the duty cycle of the second audio square wave is less than the duty cycle of the first audio square wave. The first output stage and the second output stage are coupled to the logic block and configured to generate a first audio output signal and a second audio output signal based on the first processed audio signal and the second processed audio signal, respectively.

[0008] Another embodiment relates to a Class D amplifier including a signal processing block, the signal processing block being configured to generate a first processed signal representing a difference between a first differential signal and a second differential signal when a duty cycle of the first differential signal is greater than a duty cycle of the second differential signal, to generate a first processed signal representing a reference DC level when the duty cycle of the first differential signal is less than the duty cycle of the second differential signal, to generate a second processed signal representing a difference between the second differential signal and the first differential signal when the duty cycle of the second differential signal is greater than the duty cycle of the first differential signal, and to generate a second processed signal representing a reference DC level when the duty cycle of the second differential signal is less than the duty cycle of the first differential signal.

[0009] A method feature aspect relates to a method of amplifying an audio signal. The method includes receiving a first analog signal, the first analog signal being an analog signal. The method also includes receiving a second analog signal, the second analog signal being a complement of the analog signal. The first analog input signal and the second analog input signal are converted into a first square wave and a second square wave. A first processed signal representing a difference between the first square wave and the second square wave is generated when the duty cycle of the first square wave is greater than the duty cycle of the second square wave. A first processed signal as a reference DC level is generated when the duty cycle of the first square wave is less than the duty cycle of the second square wave. A second processed signal representing a difference between the second square wave and the first square wave is generated when the duty cycle of the second square wave is greater than the duty cycle of the first square wave. A second processed signal as a reference DC level is generated when the duty cycle of the second square wave is less than the duty cycle of the first square wave, and a first output signal and a second output signal are generated based on the first processed signal and the second processed signal, respectively, using respective first output stages and second output stages. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a schematic diagram of a Class D amplifier according to the present disclosure.

[0011] Figure 2 is an operation in which the signal generator is a sawtooth wave generator Figure 1 Timing diagram of a Class D amplifier.

[0012] Figure 3 The signal generator is a sawtooth wave generator. Figure 1 Schematic diagram of an embodiment of the logical building blocks of a Class-D amplifier.

[0013] Figure 4 The signal generator is a triangle wave generator. Figure 1 Flowchart of the operation of a Class D amplifier.

[0014] Figure 5 is an operation in which the signal generator is a triangle wave generator Figure 1 Timing diagram of a Class D amplifier. DETAILED DESCRIPTION

[0015] One or more embodiments will be described below. These described embodiments are merely examples of implementation techniques as limited only by the appended claims. Additionally, in order to provide a focused description, irrelevant features of the actual implementation may not be described in the specification.

[0016] Reference Figure 1 , a class D amplifier 100 with a bridge-tied load 160 will now be described. The structure of the class D amplifier 100 will first be described, and its operation will then be described.

[0017] The class D amplifier 100 includes a first analog audio input channel 110a and a second analog audio input channel 110b. The first and second analog audio input channels 110a, 110b each include an identical fully differential amplifier 112. The fully differential amplifier 112 includes an input resistor Rin and a feedback resistor R1, which sets a gain. The output of the fully differential amplifier 112 is fed back to another fully differential amplifier 114, which has an input resistor R2 and a feedback capacitor C. The non-inverting output of the fully differential amplifier 114 is fed to the non-inverting input of the comparator 120a, and the inverting output of the fully differential amplifier 114 is fed to the non-inverting input of the comparator 120b. The signal generator 130 is coupled to the inverting inputs of the comparators 120a and 120b.

[0018] The outputs of comparators 120a and 120b are sent to logic block 140, which has outputs that are fed to output stage 150a and output stage 150b. Output stage 150a includes driver 152a, having an input coupled to the output of logic block 140. Output stage 150a also includes a first PMOS transistor P1 and a first NMOS transistor N1. The first PMOS transistor P1 has a source coupled to a power supply Vcc, and a gate coupled to a first output of driver 152a. Diode D1 is coupled between the source and drain of the first PMOS transistor P1. The first NMOS transistor N1 has a source coupled to the drain of the first PMOS transistor P1, a drain coupled to ground GND, and a gate coupled to a second output of driver 152a. Diode D2 is coupled between the source and drain of the first NMOS transistor N1.

[0019] The output stage 150b includes a driver 152b having an input coupled to the output of the logic block 140. The output stage 150b also includes a second PMOS transistor P2 and a second NMOS transistor N2. The second PMOS transistor P2 has a source coupled to the power supply Vcc and a gate coupled to the first output of the driver 150b. A diode D3 is coupled between the source and the drain of the second PMOS transistor P2. The second NMOS transistor N2 has a source coupled to the drain of the second PMOS transistor P2, a drain coupled to the ground GND, and a gate coupled to the second output of the driver 152b. A diode D4 is coupled between the source and the drain of the second NMOS transistor N2.

[0020] The load 160 has a first input terminal coupled to the drain of the first PMOS transistor P1 and the source of the first NMOS transistor N1, and a second input terminal coupled to the drain of the second PMOS transistor P2 and the source of the second NMOS transistor N2. A resistor Rfb is coupled between the load 160 and the input terminal of the fully differential amplifier 114. The load 160 may include, for example, an analog speaker.

[0021] Reference Figure 3 , the structure of the logic block 140 will now be described. The logic block 140 includes a first inverter 202a having an input coupled to the output CMPp of the comparator 120b and an output coupled to a first input of an AND gate 204a. The AND gate 204a has a second input coupled to the output of the comparator 120a and an output Vp coupled to the first output stage 150a.

[0022] Logic block 140 also includes a second inverter 202b having an input coupled to the output CMPn of comparator 120a and an output coupled to a first input of an AND gate 204b. AND gate 204b has a second input coupled to the output of comparator 120b and an output Vn coupled to the second output stage 150b.

[0023] Now refer to Figure 1-Figure 3 The operation of the class D amplifier 100 is described. The input terminals of the fully differential amplifier 112 receive the first and second analog audio input signals, respectively. The fully differential amplifier 112 removes common mode noise from the first and second analog audio input signals, and outputs the first and second analog audio input signals with the common mode noise removed as first and second differential signals to the fully differential amplifier 114 for removing unwanted DC offsets from the first and second analog audio input signals. In some applications, the first and second analog audio input signals may be separate single input signals and not differential signals, as known to those skilled in the art.

[0024] The first analog audio output signal Vdn is then sent from the fully differential amplifier 114 to the comparator 120a, which compares the first analog audio input signal with the sawtooth waveform generated by the signal source or waveform generator 130. This results in the generation of a first audio square wave CMPp having a duty cycle proportional to the amplitude of the first analog audio input signal. The first analog audio input signal and the waveform generated by the waveform generator 130 are compared in Figure 2 The sawtooth wave is shown after the label SWATOOTH, while the first audio square wave is shown after the label CMPP.

[0025] Similarly, the second audio output signal Vdp is fed from the fully differential amplifier 114 to the comparator 120b, which also compares the second analog audio input signal with the triangle wave or sawtooth wave generated by the waveform generator 130. This also results in the generation of a second audio square wave CMPn having a duty cycle proportional to the amplitude of the second analog audio input signal. Figure 2 It is shown next to the label CMPN.

[0026] The logic block 140 receives the first audio square wave and generates a first processed audio signal Vp therefrom. The logic block 140 generates the first processed audio signal Vp by performing a logical AND operation on the inverse of the first audio square wave and the second audio square wave through its AND gate 204a. When the duty cycle of the first audio square wave is greater than the duty cycle of the second audio square wave (reference numeral 300), the first processed audio signal thus represents the difference between the first audio square wave and the second audio square wave. When the duty cycle of the first audio square wave is less than the duty cycle of the second audio square wave (reference numeral 302), the first processed audio signal thus represents a reference DC level or a common mode voltage.

[0027] The logic block 140 also generates a second processed audio signal Vn from the second audio square wave. The logic block 140 generates the second processed audio signal Vn by performing a logical AND operation on the inversion of the first audio square wave and the second audio square wave through its AND gate 204b. When the duty cycle of the second audio square wave is greater than the duty cycle of the first audio square wave (reference numeral 302), the second processed audio signal thus represents the difference between the second audio square wave and the first audio square wave. When the duty cycle of the second audio square wave is less than the duty cycle of the first audio square wave (reference numeral 300), the second processed audio signal Vn thus represents a reference DC level or common mode voltage.

[0028] As shown by observing the first and second processed audio signals Vp, Vn, the first and second processed audio signals are not high at the same time, and only one audio signal is high during a single cycle of the triangle or sawtooth wave, and the audio signal is high only once during the single cycle. Therefore, during a single cycle, P1 and N2 switch, or during the single cycle, P2 and N2 switch, but not both pairs of transistors.

[0029] With a conventional class D amplifier, the first processed audio signal and the second processed audio signal can be high at the same time. Therefore, in a conventional class D amplifier, transistors P1, N2 and P2, N2 will each switch twice during a single cycle of the triangle wave or sawtooth wave. The class D amplifier described herein thus reduces the amount of switching by 50% compared to conventional designs, resulting in greatly reduced EMI.

[0030] The driver 152a receives the first processed audio signal and amplifies it. When the first processed audio signal Vp is at a logic high, the first NMOS transistor N2 is turned off, and the first PMOS transistor P1 is turned on and generates a high first audio output signal OUTp. When the first processed audio signal Vp is at a logic low, the first PMOS transistor P1 is turned off, and the first NMOS transistor N1 is turned on and pulls the first audio output signal OUTp low.

[0031] The driver 152b also receives the second processed audio signal and drives the power MOS devices P2, N2. When the second processed audio signal Vn is at a logic high, the second NMOS transistor N2 is turned off, and the second PMOS transistor P1 is turned on and generates a high second audio output signal OUTn. When the second processed audio signal Vn is at a logic low, the second PMOS transistor P2 is turned off, and the second NMOS transistor N2 is turned on and pulls the second audio output signal OUTn low.

[0032] The first audio output signal OUTp will Figure 2 On the other hand, the second audio output signal OUTn will Figure 2 The load signal, labeled LOAD, is pulled negative. The load signal represents the difference between the first audio output signal and the second audio output signal OUTp, OUTn. Therefore, if the first audio output signal and the second audio output signal OUTp, OUTn are both high at the same time and lack overlapping transitions, as is possible with a conventional Class D amplifier, the load signal will transition four times during a given time period. However, if Figure 2 As shown, as a result of the operations performed by the logic block 140, the first and second audio output signals OUTp, OUTn will not be high at the same time. Therefore, the signal at the load will only transition twice during the same given time period, as opposed to four times in conventional systems. This reduces the number of signal transitions at the load by half.

[0033] It will be appreciated that waveform generator 130 may generate a triangular wave instead of a sawtooth wave. This may result in CMPp and CMPn output by comparators 120a and 120b not having simultaneous transitions. In this case, logic block 140 will now refer to Figure 4-Figure 5 Flowchart 300 describes the generation of Vp and Vn.

[0034] Due to the differential amplifier 112, Vdp and Vdn are fully differential output signals, and the frequency of the triangle wave is higher than the frequency of the analog audio input signal. Therefore, the width of P1 is equal to the width of P2, and the width of P3 is equal to Figure 5 The width of P4.

[0035] Logic block 140 monitors CMPp and CMPn to sense the first rising edge (step 302). If CMPp has a rising edge before CMPn (step 304a), logic block 140 samples from the rising edge of CMPp to the rising edge of CMPn (step 306a). This shows that Figure 5 , and this time period is referred to as P1. Logic block 140 starts outputting Vp high at the start of sampling (step 308a), and turns Vp low at an elapsed time of 2*P1 (step 310a), also as Figure 5 As shown in . Logic block 140 then returns to monitoring CMPp and CMPn (step 302 ). The load finally receives an output signal of 2*P1=P1+P2=CMPP-CMPN.

[0036] If CMPn has the first rising edge before CMPp (step 304b), logic block 140 samples from the rising edge of CMPn to the rising edge of CMPp (step 306b). Logic block 140 begins outputting Vn high at the start of sampling (step 308b), and thereafter turns Vn low at an elapsed time equal to twice the length of time from the rising edge of CMPn to the rising edge of CMPp (step 310b). Logic block 140 then returns to monitoring CMPp and CMPn (step 302).

[0037] In the case where CMPp and CMPn rise simultaneously (step 305), logic block 140 takes no action, Vp and Vn remain low (step 307), and continues to monitor CMPp and CMPn (step 302).

[0038] While the present disclosure has been described with reference to a limited number of embodiments, those skilled in the art, having been taught by the present disclosure, will appreciate that other embodiments can be envisioned that do not depart from the scope of the present disclosure as described herein. Accordingly, the scope of the present disclosure should be limited only by the appended claims.

Claims

1. An electronic device, comprising: a first comparator and a second comparator configured to convert the first analog audio input signal and the second analog audio input signal into a first audio square wave and a second audio square wave, respectively, by comparing the first analog audio input signal and the second analog audio input signal with a sawtooth wave; a logic block coupled to receive the first audio square wave and the second audio square wave from the first comparator and the second comparator, and configured to: A first processed audio signal representing a difference between the first audio square wave and the second audio square wave is generated when the duty cycle of the first audio square wave is greater than the duty cycle of the second audio square wave, and is generated to have a pulse representing twice the time period from a rising edge of the first audio square wave to a rising edge of the second audio square wave, generating the first processed audio signal having a reference DC level when the duty cycle of the first audio square wave is smaller than the duty cycle of the second audio square wave, A second processed audio signal representing a difference between the second audio square wave and the first audio square wave is generated when the duty cycle of the second audio square wave is greater than the duty cycle of the first audio square wave, and is generated to have a pulse representing twice the time period from a rising edge of the second audio square wave to a rising edge of the first audio square wave, and generating the second processed audio signal having the reference DC level when the duty cycle of the second audio square wave is smaller than the duty cycle of the first audio square wave; as well as A first output stage and a second output stage are coupled to the logic block and configured to generate a first audio output signal and a second audio output signal based on the first processed audio signal and the second processed audio signal, respectively.

2. The electronic device according to claim 1, wherein: The logical blocks include: A first inverter and a second inverter configured to receive the first audio square wave and the second audio square wave and output the inverse of the first audio square wave and the second audio square wave; a first AND gate configured to generate the first processed audio signal having the first logic level based on the inversion of the second audio square wave having the first logic level and the first audio square wave; and A second AND gate is configured to generate the second processed audio signal having the first logic level based on the inversion of the first audio square wave having the first logic level and the second audio square wave.

3. The electronic device according to claim 1, wherein: The first output stage comprises: a first amplifier configured to receive the first processed audio signal and generate a first amplified audio signal, a first PMOS transistor having a drain, a source coupled to a power supply voltage, and a gate for receiving the first amplified audio signal, and a first NMOS transistor having a source coupled to ground, a drain coupled to the drain of the first PMOS transistor, and a gate for receiving the first amplified audio signal, wherein the first PMOS transistor cooperates with the first NMOS transistor to generate the first audio output signal; and wherein the second output stage comprises: a second amplifier configured to receive the second processed audio signal and generate a second amplified audio signal, a second PMOS transistor having a drain, a source coupled to a power supply voltage, and a gate for receiving the second amplified audio signal, and a second NMOS transistor having a source coupled to ground, a drain coupled to the drain of the second PMOS transistor, and a gate for receiving the second amplified audio signal, The second PMOS transistor and the second NMOS transistor cooperate to generate the second audio output signal.

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