An EtherCAT master system with dual data channels

Abstract

The present application discloses an EtherCAT master station system with dual data channels, including a microprocessor, a random access unit, an FPGA module and an Ethernet physical layer module, and a group of servo slave stations are connected through the Ethernet physical layer module; the EtherCAT master station protocol stack is operated and maintained by cooperating with the microprocessor through the random access unit; the process data driver module uses the process data image residing in the FPGA storage module as the data source, and uses the real-time data channel to realize the periodic communication of the master station; the microprocessor does not need to take away the process data image, but performs byte access through the address mapping communication bus. The present application optimizes the data transmission path by hardware, reduces the delay and jitter of periodic communication, can realize a shorter master station cycle, and is suitable for high-speed interpolation motion control of CNC machine tools.

Description

Technical Field

[0001] The present application relates to the field of industrial Ethernet field communications, and in particular to an EtherCAT master station system suitable for high-speed communications in industrial automation. Background Art

[0002] Beckhoff initially promoted the EtherCAT protocol. One of its main advantages is that it can use a general architecture of a processor plus an external network card to implement the master station function. The data link layer and application layer of the EtherCAT protocol are both implemented by software. In view of the low operating efficiency of the single cache of the general network card and the low real-time performance of the system soft interrupt, the EtherCAT protocol uses a slave station distributed clock mechanism to make up for the shortcomings of the master station in terms of real-time performance, and can achieve nanosecond-level multi-axis synchronization accuracy. This solution is easy to implement, low-cost, and portable, and can meet the performance requirements of most application scenarios (communication cycle is more than 500μs).

[0003] Since the above solutions cannot meet the needs of some applications that have high requirements for the real-time performance of the master station, many patents have proposed various improvement solutions for the real-time performance of the EtherCAT master station.

[0004] Patent document CN201510107162.X discloses an FPGA-based EtherCAT master station device, in which the master station uses FPGA to implement the EtherCAT protocol data link layer function. The application layer program and the EtherCAT protocol driver module of the master station are synchronized with the isochronous interrupt generated by the FPGA. This solution uses the FPGA protocol driver module to share the EtherCAT message processing task of the processor, thereby improving the efficiency of the EtherCAT data link layer. In terms of the message scheduling strategy, in each interrupt cycle, one frame of periodic messages and one frame of non-periodic messages are sent respectively, and periodic messages are sent first.

[0005] Patent document CN201510870564.5 discloses a method for building an embedded EtherCAT master station based on ARM. This solution uses ARM to share the distributed clock, state machine, frame operation and other program tasks of the CNC system CPU on the EtherCAT master station. The CPU and ARM use FPGA memory to realize the interaction of instructions and data, thereby achieving the purpose of reducing the host computing tasks and improving the running speed.

[0006] Patent document CN201511031363.2 discloses an EtherCAT communication system master station and communication method, which uses FPGA to implement the EtherCAT protocol data link layer function. The CPU application sends instructions and data to the FPGA transceiver unit, and the FPGA transceiver unit implements message processing; the initiation time of periodic messages is controlled by the FPGA distributed clock unit, overcoming the instability caused by soft interrupts.

[0007] Existing solutions mainly focus on using additional co-processing units to replace the host processor to complete the work of the EtherCAT protocol data link layer, thereby improving the processing efficiency of messages. Using the parallel processing and hardware implementation characteristics of FPGA to realize the assembly and parsing of EtherCAT messages can accelerate the process to a certain extent, and the path planning of data flow is also one of the main factors affecting the real-time performance of the master station. In the existing solutions, there is still the phenomenon of repeated data migration. Furthermore, the real-time performance of the EtherCAT master station is mainly determined by the periodic process data communication. The communication protocol is implemented indiscriminately using hardware, which not only wastes resources but also loses flexibility. Summary of the invention

[0008] The purpose of this application is to provide an EtherCAT master station system with dual data channels. While retaining the original standard data channel of the traditional EtherCAT master station, a bypass real-time data channel is opened and used for periodic process data communication, further shortening the processing time of the communication stack software, and realizing high-frequency, low-jitter isochronous transmission of process data and fast clock-synchronous motion control.

[0009] In order to achieve the above tasks, this application adopts the following technical solutions:

[0010] An EtherCAT master station system with dual data channels includes a microprocessor, a random access unit, an FPGA module and an Ethernet physical layer module, and is connected to a group of servo slave stations through the Ethernet physical layer module; the EtherCAT master station protocol stack is operated and maintained by the random access unit in cooperation with the microprocessor;

[0011] The FPGA module is used to provide a standard data channel and a bypass real-time data channel at the data link layer of the EtherCAT protocol at the same time; wherein the standard data channel is used to convert the EtherCAT message provided by the microprocessor into a data stream and send it to the Ethernet physical layer module, or to restore the data stream uploaded by the Ethernet physical layer module into a data message and transfer it to the microprocessor; the bypass real-time data channel is used to synchronize with the periodic pulse signal initiated by the clock module in the FPGA module, directly extract information from the process data mirror area residing in the FPGA module, generate a process data message and send it to the Ethernet physical layer module, or to restore the data stream uploaded by the Ethernet physical layer module into a message, and extract valid information from it and update it to the process data mirror area;

[0012] The microprocessor is used to implement byte access to the process data mirror area through the microprocessor interface module according to the needs of the application layer task;

[0013] The Ethernet physical layer module is used to convert the data stream from the FPGA module into a differential signal and send it to the physical medium. The message processed by each servo slave station is returned to the EtherCAT master station through the physical medium, and then converted into a data stream by the Ethernet physical layer module and enters the FPGA module.

[0014] Furthermore, the FPGA module includes the microprocessor interface module, clock module, storage module, process data driver module, scheduling module and Ethernet module, wherein:

[0015] The storage module is connected to the microprocessor interface module, the process data driving module and the scheduling module respectively; the process data driving module is connected to the microprocessor interface module and the clock module; the clock module is connected to the scheduling module and the Ethernet module; and the Ethernet module is connected to the Ethernet physical layer.

[0016] Furthermore, the microprocessor interface module includes three data interaction submodules: a control register module, a status register module and a storage unit control module, wherein:

[0017] The control register module and the status register module include multiple registers, and the microprocessor writes control data into a specific register of the control register module or reads feedback data from a specific register of the status register module through an address mapping communication bus, thereby realizing status control of the FPGA module;

[0018] The storage unit control module converts the read and write requests initiated by the microprocessor through the address mapping communication bus into read and write signals for the memory in the FPGA module, thereby realizing low-latency, variable-length data burst transmission;

[0019] The microprocessor interface module also includes a hardware interrupt signal line from the FPGA module, which is used to transmit the synchronous interrupt signal initiated by the process data driving module to the microprocessor.

[0020] Further, the storage module includes the process data mirror area, as well as a real-time sending buffer, a real-time receiving buffer, a standard sending buffer and a standard receiving buffer, wherein:

[0021] The process data mirror area is respectively connected to the process data driving module and the storage unit control module in the microprocessor interface module, and is mutually exclusively accessed by the microprocessor and the process data driving module; the A ports of the real-time sending buffer and the real-time receiving buffer are both connected to the process data driving module, and the process data driving module writes and reads messages; the A ports of the standard sending buffer and the standard receiving buffer are both connected to the storage unit control module in the microprocessor interface module, and the microprocessor writes and reads messages; the B ports of the real-time sending buffer, the real-time receiving buffer, the standard sending buffer and the standard receiving buffer are indirectly connected to the Ethernet module through the scheduling module.

[0022] Furthermore, the process data driver module is responsible for obtaining the process data from the process data mirror area and encapsulating it into a process data message, and then writing it into the real-time sending buffer after the isochronous pulse signal is generated in each cycle; when the Ethernet module receives the process data message and writes it into the real-time receiving buffer, the process data driver module is responsible for extracting the process data from the real-time receiving buffer and updating it to the process data mirror area, and after completion, sending a synchronous interrupt signal to the microprocessor.

[0023] Furthermore, the clock module provides two pulse signal outputs, one of which is an isochronous pulse signal, which is generated by the clock module period, and its period is set by the microprocessor through the register in the microprocessor interface module; the other signal output is an advanced pulse signal, and its output time is based on the generation time of the isochronous pulse signal and is advanced by a variable time amount.

[0024] Furthermore, the scheduling module includes a finite state machine having a standard state, a transition state and a real-time state, for coordinating the sharing of the Ethernet interface by the real-time data channel and the standard data channel, and the state machine repeatedly cycles and switches in the order of the standard state-transition state-real-time state;

[0025] When the state machine is in the standard state, the Ethernet module connects to the standard data channel, accepts and processes data sending and receiving requests for the microprocessor; when it is in the transition state, the Ethernet module connects to the standard data channel, but no longer accepts new data sending requests, and unfinished sending operations and unfinished receiving operations will continue to execute; when it is in the real-time state, the Ethernet module connects to the real-time data channel, accepts and processes real-time data sending and receiving requests for the process data driver module.

[0026] Furthermore, the Ethernet module adopts 100Mbps full-duplex mode, uses automatic negotiation, and is internally divided into two completely independent sub-modules, a sending module and a receiving module, which are respectively responsible for sending and receiving EtherCAT data frames.

[0027] Furthermore, the process of assembling and parsing the process data frame by the process data driver module includes:

[0028] During the configuration of the EtherCAT system, the process data message is generated in advance according to the process data message format and written into the real-time transmission buffer. After each isochronous pulse signal occurs, the process data driver module directly fills the entire process data in the process data mirror area into the process data sub-message data field in the real-time transmission buffer, and no changes are made to the parts other than the sub-message data field; after each termination pulse signal is generated, the process data is extracted from the sub-message data field in the received process data frame and overwritten to the process data mirror area.

[0029] Furthermore, by utilizing the concurrent execution characteristics of FPGA, a pipeline method is adopted to realize the concurrent execution of assembling and sending process data frames:

[0030] When the isochronous pulse signal is generated, the Ethernet module immediately reads and sends the message from the real-time send buffer. At the same time, the process data driver module reads the process data from the process data mirror area and overwrites it to the sub-message data field of the process data frame being sent.

[0031] In summary, according to the characteristics of EtherCAT protocol process data communication with high real-time requirements and high repeatability of message processing operations, this application has the following technical features compared with the prior art:

[0032] 1. Reduce the time delay of periodic communication and minimize the master station cycle time.

[0033] ① A high-performance, high-bandwidth, and low-latency address mapping communication method is adopted to migrate the process data image from the memory to the FPGA block memory, saving the time of data copying; ② The sending and receiving FIFO structures are cancelled to further reduce the data transmission delay; ③ The pipeline method is used to realize the concurrent execution of message assembly and message sending, achieving faster data frame sending response.

[0034] 2. Reduce the jitter of periodic communication of the master station.

[0035] The process data communication process is completely based on hardware implementation. In theory, the real-time performance of the master station's periodic communication is not affected by the software. There is only jitter on the hardware devices. It is suitable for high-speed interpolation motion control of CNC machine tools.

[0036] 3. Periodic communication has less restriction on non-periodic communication. Since the master station system of the present application adopts a round-robin scheduling strategy to share an Ethernet interface resource, the two communication channels fully occupy the right to use the resource in their respective time slices, so the degree of mutual interference is smaller.

[0037] 4. Compatible with master station solutions based on common architecture.

[0038] The master station system of the present application provides dual data channels. In the transplantation of the master station platform, only an interface driver based on the standard data channel needs to be implemented to realize the master station communication function.

[0039] 5. Save resources and costs, and facilitate expansion and upgrading.

[0040] Most of the non-time-critical protocol functions of the EtherCAT master station in this application are implemented by software, and only a small number of time-critical parts are implemented by hardware, which is conducive to the expansion and upgrade of the EtherCAT protocol and saves more resources and costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 It is a schematic diagram of the overall structure of the master station system of an embodiment of the present application;

[0042] Figure 2 is a schematic diagram of the structure of a microprocessor interface module according to an embodiment of the present application;

[0043] Figure 3 It is a schematic diagram of the scheduling strategy of the standard and real-time data channels of an embodiment of the present application;

[0044] Figure 4 is a schematic diagram of the structure of a sending module in an Ethernet module according to an embodiment of the present application;

[0045] Figure 5 It is a schematic diagram of the structure of a receiving module in an Ethernet module according to an embodiment of the present application.

[0046] Explanation of the numbers in the figure: 1 microprocessor, 2 random access unit, 3 microprocessor interface module, 3.1 status register module / control register module, 3.2 storage unit control module, 4 storage module, 4.1 process data mirror area, 4.2 real-time sending buffer, 4.3 real-time receiving buffer, 4.4 standard sending buffer, 4.5 standard receiving buffer, 5 process data driver module, 6 clock module, 7 scheduling module, 8 Ethernet module, 9 Ethernet physical layer module. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0048] See also Figure 1 An embodiment of the present application provides an EtherCAT master station system with dual data channels, including a microprocessor 1, a random access unit 2, an FPGA module 10 and an Ethernet physical layer module 9; the microprocessor 1 interacts with the FPGA module 10 through the microprocessor interface module 3 using an address mapping communication bus, and the FPGA module 10 interacts with the Ethernet physical layer module 9 through the Ethernet module 8. The master station system is connected to a group of servo slaves through the Ethernet physical layer module 9, and the EtherCAT master station protocol stack is operated and maintained by the random access unit 2 in cooperation with the microprocessor 1 in the form of a software program.

[0049] The FPGA module 10 provides both a standard data channel and a bypass real-time data channel at the data link layer of the EtherCAT protocol; wherein the standard data channel is responsible for converting the EtherCAT message provided by the microprocessor 1 into a data stream, and sending it to the Ethernet physical layer module 9 in a 100Mbps full-duplex mode, or restoring the data stream uploaded by the Ethernet physical layer module 9 into a data message and transferring it to the microprocessor 1; the bypass real-time data channel is used to synchronize with the periodic pulse signal initiated by the clock module 6 in the FPGA module 10, directly extract information from the process data mirror area 4.1 residing in the storage module 4 of the FPGA module 10, generate a process data message and send it to the Ethernet physical layer module 9, or restore the data stream uploaded by the Ethernet physical layer module 9 into a message, and extract valid information from it and update it to the process data mirror area 4.1.

[0050] The microprocessor 1 does not need to take away the entire process data mirror, but according to the needs of the application layer task, it implements byte access to the process data mirror area 4.1 through the address mapping communication bus and the microprocessor interface module 3. The Ethernet physical layer module 9 converts the data stream from the FPGA module 10 into a differential signal and sends it to the physical medium; the message processed by each servo slave station returns to the master station through the physical medium, and then enters the FPGA module 10 after being converted into a data stream by the Ethernet physical layer module 9.

[0051] In the present application, the FPGA module 10 includes six parts: a microprocessor interface module 3, a storage module 4, a process data driver module 5, a clock module 6, a scheduling module 7 and an Ethernet module 8. Each part is described below.

[0052] (1) Microprocessor interface module 3

[0053] The microprocessor interface module 3 serves as a bridge for interaction between the microprocessor 1 and other sub-modules in the FPGA module 10. It adopts an address mapping communication bus that uses five independent channels: a read address channel, a write address channel, a read data channel, a write data channel, and a write response channel. Each channel consists of a signal set and uses a bidirectional handshake signal mechanism.

[0054] See also Figure 2 , the microprocessor interface module 3 includes three data interaction submodules: a control register module 3.1, a status register module and a storage unit control module 3.2.

[0055] The control register module 3.1 and the status register module are used to enable the microprocessor 1 to realize state control of the FPGA module 10. The specific implementation process includes: the control register module 3.1 and the status register module contain multiple registers, and the microprocessor 1 writes control data to a specific register of the control register module 3.1 through an address mapping communication bus, or reads feedback data from a specific register of the status register module, thereby realizing state control of the FPGA module 10.

[0056] The storage unit control module 3.2 is used to enable the microprocessor 1 to access the storage unit byte by byte; specifically, the storage unit control module 3.2 converts the read and write requests initiated by the microprocessor 1 through the address mapping communication bus into read and write signals for the memory in the FPGA module 10, thereby realizing low-latency, variable-length data burst transmission.

[0057] The microprocessor interface module 3 also includes a hardware interrupt signal line from the FPGA module 10 for transmitting the synchronous interrupt signal pdo_intr initiated by the process data driver module 5 to the microprocessor 1 .

[0058] (2) Storage module 4

[0059] The storage module 4 is composed of a dual-port random block memory (BRAM) of an FPGA module 10, and is divided into five parts: a process data mirror area 4.1, a real-time sending buffer 4.2, a real-time receiving buffer 4.3, a standard sending buffer 4.4, and a standard receiving buffer 4.5. The A and B ports of the process data mirror area 4.1 are respectively connected to the process data driver module 5 and the storage unit control module 3.2 in the microprocessor interface module 3, and are mutually exclusive accessed by the microprocessor 1 and the process data driver module 5; the A ports of the real-time sending buffer 4.2 and the real-time receiving buffer 4.3 are both connected to the process data driver module 5, and the process data driver module 5 writes and reads messages; the A ports of the standard sending buffer 4.4 and the standard receiving buffer 4.5 are both connected to the storage unit control module 3.2 in the microprocessor interface module 3, and are written and read by the microprocessor 1; the B ports of the four transceiver buffers: the real-time sending buffer 4.2, the real-time receiving buffer 4.3, the standard sending buffer 4.4, and the standard receiving buffer 4.5 are indirectly connected to the Ethernet module 8 through the interface selector in the scheduling module 7.

[0060] (3) Process data driver module 5

[0061] The process data driver module 5 is responsible for obtaining the process data from the process data mirror area 4.1 and encapsulating it into a process data message, and then writing it into the real-time sending buffer 4.2 after the isochronous pulse signal pdo_begin signal is generated in each cycle; when the Ethernet module 8 receives the process data message and writes it into the real-time receiving buffer 4.3, the process data driver module 5 is responsible for extracting the process data from the real-time receiving buffer 4.3 and updating it to the process data mirror area 4.1, and after completion, sending a synchronous interrupt signal pdo_intr to the microprocessor 1.

[0062] (4) Clock module 6

[0063] The clock module 6 provides two pulse signal outputs, one of which is an isochronous pulse signal pdo_begin, which is generated periodically by the clock module 6, and its period is set by the microprocessor 1 through the register cycle_time in the microprocessor interface module 3; the other signal output is an advance pulse signal pdo_pre, and its output time is based on the generation time of pdo_begin, and is advanced by a variable time amount. This variable time amount is calculated by the clock module 6 based on the current value of the standard send message length register tx_byte located in the microprocessor interface module 3.

[0064] (5) Scheduling module 7

[0065] The scheduling module 7 adopts a rotation scheduling strategy. The scheduling module 7 includes a finite state machine with three states (standard state, transition state and real-time state) to coordinate the sharing of the Ethernet interface between the real-time data channel and the standard data channel. The state machine repeatedly cycles and switches in the order of standard state-transition state-real-time state. When the state machine is in the standard state, the Ethernet module 8 connects to the standard data channel, accepts and processes data transmission and reception requests for the microprocessor 1; when it is in the transition state, the Ethernet module 8 connects to the standard data channel, but no longer accepts new data transmission requests, and unfinished transmission operations and unfinished reception operations will continue to be executed. When it is in the real-time state, the Ethernet module 8 connects to the real-time data channel, accepts and processes real-time data transmission and reception requests for the process data driver module 5. Among them, the pdo_begin pulse signal is used as the trigger condition for the transition state to the real-time state; the pdo_pre pulse signal is used as the trigger condition for the transition state to the transition state; the termination pulse signal pdo_end is generated by the Ethernet module 8, indicating that all process data frames in this cycle are correctly received, as the trigger condition for the transition from the real-time state to the standard state.

[0066] (6) Ethernet module 8

[0067] The Ethernet module uses 100Mbps full-duplex mode and uses automatic negotiation. It is divided into two completely independent sub-modules, the sending module and the receiving module, which are responsible for sending and receiving EtherCAT data frames respectively. Neither the sending module nor the receiving module uses the FIFO structure. The sending module provides the Ethernet physical layer module 9 with a clock frequency of 25MHz TX_CLK, and the receiving module directly uses the input clock RX_CLK provided by the Ethernet physical layer module 9 to the FPGA as the driving source clock.

[0068] According to the characteristics that the values ​​of the Ethernet frame header, EtherCAT frame header, sub-message header and the WKC part at the end of the process data communication message structure are fixed after the EtherCAT communication system is initialized, this application proposes a new method for assembling and parsing process data frames:

[0069] During the configuration of the EtherCAT system, the process data message is generated in advance according to the process data message format and written into the real-time transmission buffer 4.2. After each pdo_begin signal occurs, the process data driver module 5 directly fills the entire process data of the process data mirror area 4.1 into the process data sub-message data field (from the frame start address to the backward offset of 26 bytes) in the real-time transmission buffer 4.2, and no changes are made to the parts other than the sub-message data field; after each pdo_end signal is generated, the process data is extracted from the sub-message data field (from the frame start address to the backward offset of 26 bytes) in the received process data frame, and overwritten to the process data mirror area 4.1.

[0070] If the length of the process data exceeds the capacity of a standard Ethernet message frame, it is split into multiple fragments and multiple process data frames are sent continuously. The pdo_end pulse signal is generated after all process data messages are correctly received, and then the process data is extracted from the multiple frames and finally spliced ​​together.

[0071] This application also proposes a method for realizing real-time compensation of local clock drift of slave stations based on bypass real-time channel:

[0072] The first EtherCAT data frame for process data communication sent in each cycle contains two sub-messages. The first sub-message is the process data sub-message of the logical addressing read and write command (LRW), and the second sub-message is the message of the one-read-many-write command (ARMW). The second sub-message is used to read the value (system time) of the register 0x910-0x917 of the reference clock slave and write it into the register 0x910-0x917 of other slaves, which is used for the slave to adjust its own time control loop. When the data frame returns to the master station, the system time in the second sub-message is parsed and written into the register system_time in the microprocessor interface module 3 for reading by the microprocessor 1.

[0073] In combination with the above improved process data frame assembly and parsing method, this application proposes to utilize the concurrent execution characteristics of FPGA and adopt a pipeline method to realize the assembly and sending concurrent execution of process data frames:

[0074] When the isochronous pulse signal pdo_begin is generated, the Ethernet module 8 immediately reads and sends the message from the real-time sending buffer 4.2, and at the same time, the process data driver module 5 reads the process data from the process data mirror area 4.1 and covers the sub-message data field of the process data frame being sent. Since the read data is located at the starting address 0 of the data frame, and the write data is located at the address offset 26 bytes from the starting address, and the read clock frequency is 25Mhz (100Mbps) which is much smaller than the write clock frequency, there is no conflict.

[0075] In view of the situation where there are too many servo slaves, this application proposes the following solutions:

[0076] If the length of the process data image exceeds the capacity of a standard Ethernet message frame, it is split into multiple fragments and multiple process data frames are sent continuously. The pdo_end pulse signal is generated after all process data messages are correctly received, and then the process data is extracted from the multiple frames and finally spliced ​​together.

[0077] In one embodiment of the present application:

[0078] The microprocessor 1 and the FPGA module 10 can specifically adopt the ZYNQ-7000 series SoC of Xilinx, which mainly integrates the ARM Cortex-A9 dual-core processor and the Xilinx FPGA programmable logic resources. The embodiment of the present application only uses the FPGA resources and one of the ARM microprocessors 1. The microprocessor 1 is connected to the FPGA module 10 via the on-chip bus AXI4 of the SoC. The random access unit 2 can adopt a double-rate synchronous dynamic random access memory (DDR SDRAM). The Ethernet physical layer module 9 can adopt a PHY chip or E-BUS. It can run with or without an operating system. The embodiment of the present application needs to be equipped with the EtherCAT master station protocol stack software library, and an open source master station (Simple OpenSource EtherCATMaster, the IgH EtherCAT Master or other), a commercial master station or a self-developed master station protocol stack can be adopted. The embodiment of the present application also needs to implement the message transceiver interface driver for the standard data channel and the real-time data channel respectively.

[0079] Figure 2 It is a structural diagram of the microprocessor interface module 3 of the embodiment of the present application. The microprocessor interface module 3 is a bridge for the microprocessor 1 to interact with other submodules in the FPGA module 10, wherein the connection between the microprocessor 1 and the microprocessor 1 interface adopts the on-chip bus AXI4, which can realize high-performance, high-bandwidth, and low-latency data transmission. The control and status register module can be an FPGA AXI IP core package shell provided by Xilinx, and the storage unit control module 3.2 can be an AXI BRAM Controller of the Xilinx IP core library. The hardware interrupt signal line pdo_intr is used to transmit the interrupt synchronization signal initiated by the FPGA module 10 (10) to the microprocessor 1, notifying the microprocessor 1 that the latest process data image has been refreshed.

[0080] Figure 3It is a schematic diagram of the scheduling strategy of the real-time data channel and the standard data channel of the embodiment of the present application. The initial state of the state machine of the scheduling module 7 is the standard state. The master station uses the standard data channel to initialize and configure the EtherCAT system. When the initialization is completed, the clock module 6 is enabled, and the clock module 6 starts to generate a pulse signal, and the state machine of the scheduling module 7 starts to rotate. The signal pdo_pre is generated first, at which time the state machine switches from the standard state to the transition state, and the Ethernet module 8 no longer accepts new transmission requests; then the signal pdo_begin is generated, at which time the state machine switches from the transition state to the real-time state, and the process data starts to be sent; then pdo_end is generated, and the state machine switches from the real-time state to the standard state. At this time, the process data frame has been sent and received, and the process data frame begins to be parsed; finally, the signal pdo_intr is generated, at which time the process data frame is parsed, notifying the microprocessor 1 that the process data image has been refreshed and the next cycle has begun.

[0081] Figure 4 It is a structural diagram of the sending module in the Ethernet module 8 of the embodiment of the present application. If the state machine of the scheduling module 7 is in the standard state, the sending module selects the register tx_en located in the control and status register module as the enable drive; if the state machine of the scheduling module 7 is in the real-time state, the pdo_begin signal of the clock module 6 is selected as the enable drive. When the enable signal occurs, the state machine of the sending module switches to state 1; at the same time, the address register is reset, and path ① is selected as the data input of the medium-independent interface module 3. After the current guide code and the start delimiter are sent, the state machine of the sending module immediately switches to state 2, and path ② is selected as the input. State 2 is a conditional loop, which repeatedly reads data from the real-time sending buffer 4.2 and the standard sending buffer 4.4 and forwards it to the medium-independent interface module 3 and the CRC32 check module until the number of bytes sent is equal to the value in the register tx_byte. If tx_byte is less than 60 bytes, 0 is continuously input to fill it to 60 bytes. Then the state machine switches to state 3, and the final output value of the CRC32 check module is appended to the end of the data stream.

[0082] Figure 5It is a structural diagram of the receiving module in the Ethernet module 8 of the embodiment of the present application. When the receiving module detects that the Ethernet physical layer module 9 has a data frame, the state machine is immediately switched to state 1 and starts to monitor the preamble. If 7 consecutive 0x55s are detected and the next one is 0x5d, it is immediately switched to state 2 to start receiving data; otherwise, the state machine returns to the idle state and is ready to monitor the next signal. After the bit width conversion, the data stream is directly transferred to the real-time receiving buffer 4.3 and the standard receiving buffer 4.5, and the CRC32 check module synchronously calculates the check result of the data stream. When the data frame is received, the final output result of the CRC32 check module is compared with the 32 bits at the end of the data frame. If the check is correct and the state machine of the current scheduling module 7 is in the standard state or transition state, the register new_recv in the control and status register module is notified that the microprocessor 1 has received a new message; if the check is correct and the state machine of the current scheduling module 7 is in the real-time state, a pdo_end pulse signal is generated; if the check is incorrect, the assertion that the data frame is received is not issued, and the register fcs_err in the control and status register module is incremented by 1.

[0083] The communication process of the embodiment of the present application is described from the overall logical flow:

[0084] Standard delivery process:

[0085] The microprocessor 1 copies the message to be sent from the random access unit 2 to the standard sending buffer 4.4 through the address mapping communication bus, and then sets the value of the register tx_byte to the message length, and then sets the register tx_en to 1, and initiates a sending request to the FPGA module 10. If the FPGA module 10 accepts the request, it starts the execution process of the above-mentioned sending module to send data outward, waits for 960ns after the sending is completed, and then clears the register tx_en. After the microprocessor 1 detects that tx_en becomes 0, it can initiate a new sending request again.

[0086] Standard Receiving Process:

[0087] The data stream enters the FPGA module 10 from the Ethernet physical layer module 9. The receiving module in the Ethernet module 8 receives and writes into the standard receiving buffer 4.5. After the reception is completed, if the CRC32 check passes, the register new_recv is set to 1. The microprocessor 1 finds that a new data frame has been received by polling the register new_recv, and then takes the message away through the storage unit control module 3.2. Finally, new_recv is cleared to 0 to notify the FPGA that the message has been used.

[0088] Real-time sending process:

[0089] After the synchronous interrupt pdo_intr is generated, the data in the process data mirror area 4.1 is the latest state of the slave. The application can access this data for task calculation through address mapping communication. After the calculation is completed, the data used for slave control is written into the process data mirror area 4.1, and the microprocessor 1 continues to execute other tasks. After pdo_begin is generated, the state machine of the scheduling module 7 switches to the real-time state, and the sending module starts to read data from the real-time sending buffer 4.2 and send it to the Ethernet physical layer module 9. At the same time, the process data driver module 5 copies the process data from the process data mirror area 4.1 and writes it to the sub-message data field of the EtherCAT data frame being sent. Since the location of the read data is located at the starting address 0 of the data frame, and the location of the write data is located at the address offset 26 bytes backward from the starting address, and the read clock frequency is 25Mhz (100Mbps) which is much smaller than the write clock frequency, there is no conflict.

[0090] Real-time receiving process:

[0091] The data stream enters the FPGA module 10 from the Ethernet physical layer module 9. The receiving module in the Ethernet module 8 receives and writes to the real-time receiving buffer 4.3. After receiving, if the CRC32 check passes, a pdo_end pulse signal is generated. At this time, the state machine of the scheduling module 7 switches to the standard state, and the process data driver module 5 starts from the position offset 26 bytes backward from the starting address of the data frame, and copies the data in the sub-message data field to the process data mirror area 4.1. After the copy is completed, a synchronous interrupt signal pdo_intr is sent to the microprocessor 1 to enter the next cycle.

[0092] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. An EtherCAT master station system with dual data channels, characterized in that: The system comprises a microprocessor (1), a random access unit (2), an FPGA module (10) and an Ethernet physical layer module (9), and is connected to a group of servo slave stations via the Ethernet physical layer module (9); the random access unit (2) cooperates with the microprocessor (1) to operate and maintain the EtherCAT master station protocol stack; The FPGA module (10) is used to simultaneously provide a standard data channel and a bypass real-time data channel at the data link layer of the EtherCAT protocol; wherein the standard data channel is used to convert the EtherCAT message provided by the microprocessor (1) into a data stream and send it to the Ethernet physical layer module (9), or to restore the data stream uploaded by the Ethernet physical layer module (9) into a data message and transfer it to the microprocessor (1); the bypass real-time data channel is used to synchronize with the periodic pulse signal initiated by the clock module (6) in the FPGA module (10), directly extract information from the process data mirror area (4.1) residing in the FPGA module (10), generate a process data message and send it to the Ethernet physical layer module (9), or to restore the data stream uploaded by the Ethernet physical layer module (9) into a message, extract valid information from it, and update it to the process data mirror area (4.1); The microprocessor (1) is used to implement byte access to the process data mirror area (4.1) through a microprocessor interface module (3) according to the needs of application layer tasks; the FPGA module (10) comprises a microprocessor interface module (3), a clock module (6), a storage module (4), a process data driver module (5), a scheduling module (7) and an Ethernet module (8), wherein: the storage module (4) is connected to the microprocessor interface module (3), the process data driver module (5) and the scheduling module (7) respectively, the process data driver module (5) is connected to the microprocessor interface module (3) and the clock module (6), the clock module (6) is connected to the scheduling module (7) and the Ethernet module (8), and the Ethernet module (8) is connected to the Ethernet physical layer module (9) and the scheduling module (7); The microprocessor interface module (3) serves as a bridge for the microprocessor (1) to interact with other submodules in the FPGA module (10), and adopts an address mapping communication bus. The bus uses five independent channels: a read address channel, a write address channel, a read data channel, a write data channel, and a write response channel. Each channel is composed of a signal set and uses a bidirectional handshake signal mechanism. The Ethernet physical layer module (9) is used to convert the data stream from the FPGA module (10) into a differential signal and send it to the physical medium. The message processed by each servo slave station is returned to the EtherCAT master station through the physical medium, and then converted into a data stream by the Ethernet physical layer module (9) and enters the FPGA module (10).

2. The EtherCAT master station system with dual data channels according to claim 1, characterized in that: The microprocessor interface module (3) comprises three data interaction submodules: a control register module (3.1), a status register module and a storage unit control module (3.2), wherein: The control register module (3.1) and the status register module include a plurality of registers, and the microprocessor (1) writes control data into a specific register of the control register module (3.1) or reads feedback data from a specific register of the status register module via an address mapping communication bus, thereby achieving status control of the FPGA module (10); The storage unit control module (3.2) converts the read / write request initiated by the microprocessor (1) via the address mapping communication bus into a read / write signal for the storage module (4) in the FPGA module (10), thereby realizing low-latency, variable-length data burst transmission; The microprocessor interface module (3) also includes a hardware interrupt signal line from the FPGA module (10), which is used to transmit the synchronous interrupt signal initiated by the process data drive module (5) to the microprocessor (1).

3. The EtherCAT master station system with dual data channels according to claim 1, characterized in that: The storage module (4) comprises the process data mirror area (4.1), as well as a real-time sending buffer (4.2), a real-time receiving buffer (4.3), a standard sending buffer (4.4) and a standard receiving buffer (4.5), wherein: The process data mirror area (4.1) is respectively connected to the process data drive module (5) and the storage unit control module (3.2) in the microprocessor interface module (3), and is mutually exclusive accessed by the microprocessor (1) and the process data drive module (5); the A ports of the real-time sending buffer (4.2) and the real-time receiving buffer (4.3) are both connected to the process data drive module (5), and the process data drive module (5) writes and reads messages; the A ports of the standard sending buffer (4.4) and the standard receiving buffer (4.5) are both connected to the storage unit control module (3.2) in the microprocessor interface module (3), and the microprocessor (1) writes and reads messages; the B ports of the real-time sending buffer (4.2), the real-time receiving buffer (4.3), the standard sending buffer (4.4) and the standard receiving buffer (4.5) are indirectly connected to the Ethernet module (8) through the interface selector in the scheduling module (7).

4. The EtherCAT master station system with dual data channels according to claim 1, characterized in that: The process data driving module (5) is responsible for obtaining process data from the process data mirror area (4.1) and encapsulating it into a process data message after the isochronous pulse signal of each cycle is generated, and then writing it into the real-time sending buffer (4.2); When the Ethernet module (8) receives the process data message and writes it into the real-time receiving buffer (4.3), the process data driving module (5) is responsible for extracting the process data from the real-time receiving buffer (4.3) and updating it to the process data mirror area (4.1), and after completion, sends a synchronous interrupt signal to the microprocessor (1).

5. The EtherCAT master station system with dual data channels according to claim 1, characterized in that: The clock module (6) provides two pulse signal outputs, one of which is an isochronous pulse signal, which is periodically generated by the clock module (6), and whose period is set by the microprocessor (1) through a register in the microprocessor interface module (3); the other is an advanced pulse signal, whose output time is based on the generation time of the isochronous pulse signal and is advanced by a variable time amount.

6. The EtherCAT master station system with dual data channels according to claim 1, characterized in that: The scheduling module (7) includes a finite state machine having a standard state, a transition state and a real-time state, which is used to coordinate the sharing of the Ethernet interface by the real-time data channel and the standard data channel, and the state machine repeatedly switches in a cycle in the order of standard state-transition state-real-time state; When the state machine is in a standard state, the Ethernet module (8) is connected to a standard data channel, and receives and processes data transmission and reception requests from the microprocessor (1); when it is in a transition state, the Ethernet module (8) is connected to a standard data channel, but no longer receives new data transmission requests, and unfinished transmission operations and unfinished reception operations continue to be executed; when it is in a real-time state, the Ethernet module (8) is connected to a real-time data channel, and receives and processes real-time data transmission and reception requests from the process data driver module (5).

7. The EtherCAT master station system with dual data channels according to claim 1, characterized in that: The Ethernet module (8) adopts 100Mbps full-duplex mode and uses automatic negotiation. It is internally divided into two completely independent submodules, a sending module and a receiving module, which are respectively responsible for sending and receiving EtherCAT data frames.

8. The EtherCAT master station system with dual data channels according to claim 4, characterized in that: The process of assembling and parsing the process data frame by the process data driving module (5) comprises: During the configuration of the EtherCAT system, a process data message is generated in advance according to the process data message format and written into the real-time sending buffer (4.2); after each isochronous pulse signal is generated, the process data driving module (5) directly fills the entire process data of the process data mirror area (4.1) into the process data sub-message data field in the real-time sending buffer (4.2), and the parts other than the sub-message data field are no longer changed; after each termination pulse signal is generated, the process data is extracted from the sub-message data field in the received process data frame and overwritten into the process data mirror area (4.1).

9. The EtherCAT master station system with dual data channels according to claim 3, characterized in that: Taking advantage of the concurrent execution characteristics of FPGA, a pipeline method is used to implement the assembly and sending of process data frames for concurrent execution: When the isochronous pulse signal is generated, the Ethernet module (8) immediately reads and sends the message from the real-time sending buffer (4.2), and at the same time the process data driver module (5) reads the process data from the process data mirror area (4.1) and overwrites the sub-message data field of the process data frame being sent.

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