A radar signal processing method based on FPGA

Abstract

The application discloses a radar signal processing method based on FPGA, which comprises the following steps: S1, receiving analog echo signals by a radar, and transmitting the signals to an FPGA end through an LVDS differential signal after sampling by an ADC; S2, generating valid data according to an input frame enable signal by the FPGA end; S3, performing a first-dimensional FFT operation on the valid data to obtain distance-dimension spectrum data, arranging the distance-dimension spectrum data into continuous data streams by using a ping-pong buffer mechanism, and performing a second-dimensional FFT operation on the continuous data streams to obtain speed-dimension spectrum data; S4, reading pre-stored background data through an AXI bus during wave position residence, and performing cancellation processing on the background data and two-dimensional spectrum data obtained by current calculation; S5, performing video accumulation on distance-dimension spectrum data of the same distance unit in a plurality of pulse repetition periods of a single wave position to obtain video accumulation data; and S6, writing the cancellation two-dimensional spectrum data and the video accumulation data into a processing system DDR through an AXI bus arbitration module.

Description

Technical Field

[0001] This invention belongs to the field of radar signal processing technology, and specifically relates to a radar signal processing method based on FPGA. Background Technology

[0002] Radar can simultaneously acquire target range and velocity information by transmitting pulse signals and processing the echo signals. The core of signal processing is to perform two Fast Fourier Transforms (FFTs) on the echo signals: the first FFT is performed along the range dimension to achieve pulse compression; the second FFT is performed along the pulse dimension (velocity dimension) to extract the target velocity.

[0003] In the above processing flow, the second FFT requires the input data to be a continuous sequence of "different pulses within the same range cell". However, the output of the first FFT is a sequence of "different pulses within the same range cell". This "fast time / slow time" data stream format conversion, i.e., corner processing, is a challenge for FPGA-based signal processing. Traditional processing methods often require large-capacity external memory and complex address jump logic, resulting in large processing delays and complex control. Simultaneously, radar systems also face fixed background interference such as strong ground clutter, requiring real-time background cancellation to improve the signal-to-noise ratio. Furthermore, to enhance the detection capability of small targets, video accumulation of multiple pulses is also necessary.

[0004] In the Xilinx ZYNQ platform-based processing solution, the PL (FPGA) and PS (ARM processor) share DDR memory through the AXI bus. How to efficiently organize the above complex data flow, coordinate the access of multiple tasks such as range-dimensional FFT, range-dimensional FFT, background cancellation, and video accumulation to the AXI bus, and avoid bus conflicts and data congestion is the core issue for achieving high-performance real-time radar signal processing. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to overcome the shortcomings of the prior art and provide an FPGA-based radar signal processing method with strong real-time performance and high data throughput, thereby efficiently realizing the complete link from ADC data acquisition to secondary FFT operation, background cancellation and video accumulation, and effectively managing access to the AXI bus of the PS terminal DDR.

[0006] The technical solution adopted in this invention is as follows: This invention includes the following steps: S1. The radar receives the analog echo signal, which is sampled by the ADC and then transmitted to the ZYNQ FPGA terminal via LVDS differential signal. S2, the timing and control signal generation module on the FPGA side generates valid data for a series of global timing control signals, including frame validity and linear frequency modulation pulse start, based on the externally input frame enable signal; S3. Perform windowing processing and first-dimensional FFT operation on the effective data to obtain distance dimension spectrum data. Use the ping-pong buffer mechanism to organize the distance dimension spectrum data into a continuous data stream. Perform second-dimensional FFT operation on the continuous data stream to complete Doppler processing and obtain velocity dimension spectrum data. S4. During the wave position dwell period, the pre-stored background data is read through the AXI bus and canceled with the currently calculated two-dimensional spectrum data. The two-dimensional spectrum data includes the distance dimension spectrum data and the velocity dimension spectrum data. S5. Within multiple pulse repetition periods of a single wave position, video accumulation is performed on the distance dimension spectrum data of the same distance unit to obtain video accumulation data. S6. After the canceled two-dimensional spectrum data and video accumulation data are arbitrated through the AXI bus, they are written into the processing system DDR in a time-division manner.

[0007] Furthermore, in S1, the radar receives the analog echo signal, which is then sampled by the ADC and transmitted to the ZYNQ FPGA via LVDS differential signal transmission, including: The radar receives the serial LVDS data output by the ADC, decodes it into parallel data through the double data rate interface, and extracts the effective sampled data of multiple channels based on the frame synchronization flag.

[0008] Furthermore, the timing and control signal generation module on the FPGA side of S2 generates valid data for a series of global timing control signals, including frame activation and linear frequency modulation pulse start, based on the externally input frame enable signal. The timing and control signal generation module receives a narrow pulse waveform switching indication signal from the processing system or turntable communication module, and widens the waveform switching indication signal into a frame enable signal with a preset clock cycle width to adapt to the timing requirements of subsequent processing.

[0009] Furthermore, in S3, windowing processing and a first-dimensional FFT operation are performed on the effective data to obtain distance-dimensional spectral data. Using a ping-pong buffering mechanism, the distance-dimensional spectral data is organized into a continuous data stream. A second-dimensional FFT operation is then performed on the continuous data stream to complete Doppler processing and obtain velocity-dimensional spectral data, including: The first-dimensional FFT operation is used to perform a first fast Fourier transform on the effective data stream to obtain the target's range dimension information; the ping-pong buffer mechanism is used to cache the output results after the windowing processing and the first-dimensional FFT operation processing link, and to organize the range dimension spectrum data of the same range unit into a continuous data stream within multiple pulse repetition periods; the second FFT processing unit performs a second-dimensional FFT operation to perform a second fast Fourier transform on the data stream to obtain the target's velocity dimension information.

[0010] Furthermore, in S4, during the wave position dwell period, pre-stored background data is read via the AXI bus and canceled out with the currently calculated two-dimensional spectrum data. The two-dimensional spectrum data includes the distance-dimensional spectrum data and the velocity-dimensional spectrum data, including: In the full-channel data stream output by the second FFT processing unit, the data of the preset channel to be canceled is extracted in real time; during the waveform dwell period, the background data of the corresponding distance unit and channel is read from the processing system DDR through the AXI bus; the data of the channel to be canceled extracted in real time and the background data are subjected to difference calculation in the background cancellation module to achieve background cancellation.

[0011] Furthermore, in S5, within multiple pulse repetition periods of a single wavelength position, video accumulation is performed on the range-dimensional spectral data of the same range cell, including: The video accumulation module in the FPGA performs multi-cycle video accumulation processing on the distance dimension spectrum data. That is, it performs non-coherent accumulation on the signal of the same channel in the same distance unit within 2048 consecutive pulse cycles to improve the signal-to-noise ratio. The accumulation results are written to the DDR of the processing system via the AXI bus.

[0012] Furthermore, in S6, the canceled two-dimensional spectrum data and video accumulation data are arbitrated via the AXI bus and then written into the processing system DDR in a time-division manner, including: The AXI bus arbitration module, based on the timing characteristics of radar signal processing, performs time-division arbitration and unified scheduling of read / write requests from the PS-side DDR for windowing processing, first-dimensional FFT operation processing, second-dimensional FFT operation processing, background cancellation module, and video accumulation module. Specifically, in the early stage of a wave position, the AXI bus prioritizes responding to write requests for the first-dimensional FFT operation processing results; in the later stage of a wave position, the AXI bus prioritizes responding to write requests for the second-dimensional FFT operation processing results, the background data read requests, and the video accumulation result write requests.

[0013] Furthermore, the preset clock cycle in the frame enable signal with the preset clock cycle width is 30 clock cycles, and timing pulses are precisely generated through counting and delay to adapt to the timing requirements of subsequent processing flows.

[0014] Furthermore, the ping-pong buffer mechanism adopts a dual-clock-domain ping-pong buffer, which operates in two clock domains: the write side follows the ADC clock, and the read side follows the system bus clock.

[0015] The beneficial effects of this invention are: 1. This invention implements ADC data decoding, FFT operation and transformation, and video accumulation all on the FPGA side, which improves data processing speed and meets the high real-time requirements of radar.

[0016] 2. This invention adopts a dual-clock domain ping-pong buffer structure, which utilizes the Block RAM on the FPGA chip to complete the data format conversion, avoiding frequent access to external DDR, and reducing processing latency and bus bandwidth pressure.

[0017] 3. This invention implements digital background cancellation and video accumulation processing on the FPGA side, which significantly improves target detection performance and reduces the computational burden on the PS side.

[0018] 4. This invention uses a dedicated AXI bus arbitration module to schedule DDR access requests from multiple data streams based on timing, effectively preventing bus congestion and ensuring the orderly transmission of high-throughput data. Attached Figure Description

[0019] Figure 1 This is a flowchart illustrating the present invention; Figure 2 This is a schematic diagram of the data acquisition and result writing process of the present invention. Detailed Implementation

[0020] like Figure 1 As shown, in this embodiment, the present invention includes the following steps: S1. The radar receives the analog echo signal, samples it using an ADC, and then transmits it to the ZYNQ FPGA via LVDS differential signal transmission. Specifically, this includes: The radar receives analog echo signals, processes them using an ADC sampling module, and then outputs serial LVDS data via an LVDS differential signal processing module. At the receiving end, the serial LVDS data is decoded into parallel data using a double data rate interface, and the effective sampled data from multiple channels is extracted based on the frame synchronization flag. Finally, these effective sampled data are transmitted to the ZYNQ FPGA for further processing.

[0021] S2, the timing and control signal generation module on the FPGA side generates valid data for a series of global timing control signals, including frame activation and linear frequency modulation pulse start, based on the externally input frame enable signal. Specifically, this includes: The timing and control signal generation module receives a narrow pulse waveform switching indication signal from the processing system or turntable communication module. The waveform switching indication signal is a narrow pulse, which is then widened into a frame enable signal lasting about 30 clock cycles. The timing pulse is then accurately generated through counting and delay to generate valid data for a series of global timing control signals, including frame validity and the start of linear frequency modulation pulse, to adapt to the timing requirements of subsequent processing.

[0022] S3. Windowing and first-dimensional FFT operations are performed on the effective data to obtain distance-dimensional spectrum data. Using a ping-pong buffering mechanism, the distance-dimensional spectrum data is organized into a continuous data stream. A second windowing and second-dimensional FFT operation are then performed on the continuous data stream to complete Doppler processing and obtain velocity-dimensional spectrum data. Specifically, this includes: The first-dimensional FFT operation is used to perform a first fast Fourier transform on the effective data stream to obtain the target's distance dimension information; the ping-pong buffer mechanism is used to cache the link output results of the distance dimension FFT processing unit and organize the distance dimension spectrum data of the same distance unit into a continuous data stream within multiple pulse repetition periods; the second FFT processing unit performs a second-dimensional FFT operation to perform a second fast Fourier transform on the data stream to obtain the target's velocity dimension information.

[0023] The complete chain from data acquisition to result writing is as follows: Figure 2 As shown, the FPGA receives and decodes ADC data, generating a valid frame signal. The range-dimensional FFT processing unit includes a windowing processing unit and a first FFT processing unit, used to perform windowing processing and fast Fourier transform on the time-domain sampled data to complete pulse compression and obtain the target's range-dimensional information, i.e., range-dimensional spectrum data. The ping-pong buffer mechanism uses a dual-clock-domain ping-pong buffer, which operates in two clock domains: the write side follows the ADC clock, and the read side follows the system bus clock. The dual-clock-domain ping-pong buffer utilizes two RAM blocks (Ping-Pong Buffer), switching between them for writing based on the chirp start signal. After receiving a complete coherent processing interval (CPI) of data, the read side continuously reads out, efficiently completing the conversion of the data stream from "fast time" order to "slow time" order (corner processing) with extremely low latency and on-chip storage overhead. The second FFT processing unit performs a second-dimensional FFT operation on this continuous data stream to obtain the target's velocity-dimensional information, i.e., velocity-dimensional spectrum data.

[0024] S4. During the wave position dwell period, pre-stored background data is read via the AXI bus and canceled out with the currently calculated two-dimensional spectrum data. The two-dimensional spectrum data includes the distance-dimensional spectrum data and the velocity-dimensional spectrum data, specifically including: In the full-channel data stream output by the second FFT processing unit, the data of the preset channel to be canceled is extracted in real time; during the waveform dwell period, the background data of the corresponding distance unit and channel is read from the processing system DDR through the AXI bus; the data of the channel to be canceled extracted in real time and the background data are subjected to difference calculation in the background cancellation module to achieve background cancellation.

[0025] S5. Within multiple pulse repetition periods of a single wavelength position, video accumulation is performed on the range-dimensional spectral data of the same range cell to obtain video accumulation data, specifically including: The FPGA performs multi-cycle video accumulation processing on the distance dimension spectrum data, that is, non-coherent accumulation of the signal of the same channel of the same distance unit within 2048 consecutive pulse cycles to improve the signal-to-noise ratio. The accumulation results are written to the DDR of the processing system via the AXI bus.

[0026] Specifically, within a single pulse, a dual-port RAM is used to accumulate the range-dimensional spectral data (after modulus or logarithm calculation) of the same range cell for each pulse. After accumulating 2048 pulses, the result is written to PS DDR.

[0027] S6. After the canceled two-dimensional spectrum data and video accumulation data are arbitrated through the AXI bus arbitration module, they are written into the processing system DDR in a time-division manner, specifically including: The AXI bus arbitration module, based on the timing characteristics of radar signal processing, performs time-division arbitration and unified scheduling of read / write requests from the windowing processing, first-dimensional FFT operation processing, second-dimensional FFT operation processing, background cancellation module, and video accumulation module to the PS-side DDR. Specifically, in the early part of a wave position, the AXI bus prioritizes responding to write requests for the range-dimensional FFT results; in the later part of a wave position, after the range-dimensional FFT write is completed, the AXI bus prioritizes responding to write requests for the first-dimensional FFT operation results; in the later part of a wave position, the AXI bus prioritizes responding to write requests for the second-dimensional FFT operation results, background data read requests, and video accumulation result write requests. Simultaneously, the video accumulation results are also written to the DDR during this period.

[0028] Although the embodiments of the present invention are described with reference to actual solutions, they do not constitute a limitation on the meaning of the present invention. Modifications to the embodiments and combinations with other solutions based on this specification will be obvious to those skilled in the art.

Claims

1. A method for FPGA-based radar signal processing, characterized in that, Includes the following steps: S1. The radar receives the analog echo signal, which is sampled by the ADC and then transmitted to the ZYNQ FPGA terminal via LVDS differential signal. S2, the timing and control signal generation module on the FPGA side generates valid data for a series of global timing control signals, including frame validity and linear frequency modulation pulse start, based on the externally input frame enable signal; S3. Perform windowing processing and first-dimensional FFT operation on the effective data to obtain distance dimension spectrum data. Utilize the ping-pong buffer mechanism, which adopts a dual-clock domain ping-pong buffer. The dual-clock domain ping-pong buffer operates in two clock domains, with the write side following the ADC clock and the read side following the system bus clock. Organize the distance dimension spectrum data into a continuous data stream. Perform a second-dimensional FFT operation on the continuous data stream to complete Doppler processing and obtain velocity dimension spectrum data. S4. During the wave position dwell period, pre-stored background data is read via the AXI bus and canceled out with the currently calculated two-dimensional spectrum data. The two-dimensional spectrum data includes the distance-dimensional spectrum data and the velocity-dimensional spectrum data, including: In the full-channel data stream output by the second FFT processing unit, the data of the preset channel to be canceled is extracted in real time; during the wave position dwell period, the background data of the corresponding distance unit and channel is read from the processing system DDR through the AXI bus; the data of the channel to be canceled extracted in real time and the background data are subjected to difference calculation in the background cancellation module to achieve background cancellation; S5. Within multiple pulse repetition periods of a single wave position, video accumulation is performed on the distance dimension spectrum data of the same distance unit to obtain video accumulation data. S6. After the canceled two-dimensional spectrum data and video accumulation data are arbitrated through the AXI bus, they are written into the processing system DDR in a time-division manner, including: The AXI bus arbitration module, based on the timing characteristics of radar signal processing, performs time-division arbitration and unified scheduling of read / write requests from the windowing processing, first-dimensional FFT operation processing, second-dimensional FFT operation processing, background cancellation module, and video accumulation module to the PS-side DDR. Specifically, in the early stage of a wave position, the AXI bus prioritizes responding to the write request for the range-dimensional FFT result; in the later stage of a wave position, after the range-dimensional FFT write is completed, the AXI bus prioritizes responding to the write request for the first-dimensional FFT operation result; in the later stage of a wave position, the AXI bus prioritizes responding to the write request for the second-dimensional FFT operation result, the read request for the background data, and the write request for the video accumulation result. Simultaneously, the video accumulation result is also written to DDR during this period.

2. The radar signal processing method based on FPGA according to claim 1, characterized in that: In S1, the radar receives analog echo signals, which are then sampled by an ADC and transmitted to the ZYNQ FPGA via LVDS differential signal transmission, including: The radar receives the serial LVDS data output by the ADC, decodes it into parallel data through the double data rate interface, and extracts the effective sampled data of multiple channels based on the frame synchronization flag.

3. The radar signal processing method based on FPGA according to claim 2, characterized in that: The timing and control signal generation module on the FPGA side of S2 generates valid data for a series of global timing control signals, including frame activation and linear frequency modulation pulse start, based on the externally input frame enable signal. The timing and control signal generation module receives a narrow pulse waveform switching indication signal from the processing system or turntable communication module, and widens the waveform switching indication signal into a frame enable signal with a preset clock cycle width to adapt to the timing requirements of subsequent processing.

4. The radar signal processing method based on FPGA according to claim 3, characterized in that: In S3, windowing processing and a first-dimensional FFT operation are performed on the effective data to obtain distance-dimensional spectral data. Using a ping-pong buffering mechanism, the distance-dimensional spectral data is organized into a continuous data stream. A second-dimensional FFT operation is then performed on this continuous data stream to complete Doppler processing and obtain velocity-dimensional spectral data, including: The first-dimensional FFT operation is used to perform a first fast Fourier transform on the effective data stream to obtain the target's range dimension information; the ping-pong buffer mechanism is used to cache the output results after the windowing processing and the first-dimensional FFT operation processing link, and to organize the range dimension spectrum data of the same range unit into a continuous data stream within multiple pulse repetition periods; the second FFT processing unit performs a second-dimensional FFT operation to perform a second fast Fourier transform on the data stream to obtain the target's velocity dimension information.

5. The FPGA-based radar signal processing method according to claim 4, characterized in that: In S5, video accumulation is performed on the range dimension spectral data of the same range cell within multiple pulse repetition periods of a single wavelength, including: The video accumulation module in the FPGA performs multi-cycle video accumulation processing on the distance dimension spectrum data. That is, it performs non-coherent accumulation on the signal of the same channel in the same distance unit within 2048 consecutive pulse cycles to improve the signal-to-noise ratio. The accumulation results are written to the DDR of the processing system via the AXI bus.

6. The FPGA-based radar signal processing method according to claim 3, characterized in that: The preset clock cycle width of the frame enable signal is 30 clock cycles, and timing pulses are precisely generated through counting and delay to adapt to the timing requirements of subsequent processing.

7. The radar signal processing method based on FPGA according to claim 4, characterized in that: The ping-pong buffer mechanism employs a dual-clock-domain ping-pong buffer, which operates in two clock domains: the write side follows the ADC clock, and the read side follows the system bus clock.

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