semiconductor equipment

Abstract

A semiconductor device includes: a processor configured to perform a rendering operation on an image frame to obtain rendering data and write the obtained rendering data to a memory device; and a display controller configured to perform a read operation on the memory device to which the rendering data is written to obtain the image data. The semiconductor device also includes a micro-timing circuit configured to transmit a start signal to the display controller based on the execution level of the rendering operation. The display controller is further configured to initiate a read operation based on the transmitted start signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based upon and claims the benefit of priority from Korean Patent Application No. 10-2019-0066676 filed on June 5, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The present disclosure relates to semiconductor devices. Background Art

[0004] Recently, technologies for increasing the refresh rate of display devices have attracted attention. To prevent phenomena such as sputtering or frame drops, image frames are displayed at a corresponding speed when the refresh rate increases. However, as the resolution of image frames tends to increase, there are limitations to increasing the speed of image frame rendering. Summary of the Invention

[0005] According to an embodiment, a semiconductor device includes: a processor configured to: perform a rendering operation of an image frame to obtain rendering data; and write the obtained rendering data to a memory device; and a display controller configured to perform a read operation on the memory device to which the rendering data is written to obtain the image data. The semiconductor device also includes a micro-timing circuit configured to transmit a start signal to the display controller based on the execution level of the rendering operation. The display controller is further configured to initiate a read operation based on the transmitted start signal.

[0006] According to an embodiment, a semiconductor device includes: a processor configured to perform a rendering operation of an image frame to obtain rendering data and write the obtained rendering data to a frame buffer; and a micro-timing circuit configured to monitor a write pointer indicating a point at which the rendering data is written to the frame buffer when the processor performs the rendering operation, and to send the monitored write pointer based on the monitored write pointer reaching a predetermined area or position in the frame buffer. The semiconductor device also includes a display controller configured to perform a read operation on the frame buffer to which the rendering data is written based on the sent write pointer to obtain image data.

[0007] According to an embodiment, a semiconductor device includes: a memory device including a first frame buffer and a second frame buffer; a first processor configured to perform a first rendering operation on a first image frame to obtain first rendering data and write the obtained first rendering data to the first frame buffer; and a second processor configured to perform a second rendering operation on a second image frame to obtain second rendering data and write the obtained second rendering data to the second frame buffer. The semiconductor device also includes a micro-timing circuit configured to control the operation of a display controller based on the degree of execution of each of the first rendering operation and the second rendering operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram of a semiconductor device according to an embodiment.

[0009] Figure 2 is a block diagram of a semiconductor device according to an embodiment.

[0010] Figure 3 are diagrams illustrating the operation of the semiconductor device according to the embodiment.

[0011] Figure 4 is a block diagram of a semiconductor device according to an embodiment.

[0012] Figure 5 、 Figure 6 and Figure 7 is a diagram of a frame buffer according to an embodiment.

[0013] Figure 8 is a block diagram of a semiconductor device according to an embodiment.

[0014] Figure 9 is a block diagram of a semiconductor device according to an embodiment.

[0015] Figure 10 is a block diagram of a semiconductor device according to an embodiment.

[0016] Figure 11 is a block diagram of a frame buffer according to an embodiment.

[0017] Figure 12 is a block diagram of a semiconductor device according to an embodiment. DETAILED DESCRIPTION

[0018] Aspects of the embodiments provide a semiconductor device for shortening the time taken after rendering of an image frame until a display controller displays the rendered image data.

[0019] Hereinafter, example embodiments will be described with reference to the accompanying drawings.

[0020] Figure 1is a block diagram showing a semiconductor device 1 according to the embodiment.

[0021] refer to Figure 1 , the semiconductor device 1 may include a central processing unit (CPU) 10, a graphics processing unit (GPU) 20, a hardware acceleration circuit 30 (HW ACC), a digital signal processor 40 (DSP), a memory device 50, a micro-sequential (MS) circuit 60, a display device 70, and a storage device 80. The CPU 10, the GPU 20, the hardware acceleration circuit 30, the digital signal processor 40, the memory device 50, the micro-sequential circuit 60, the display device 70, and the storage device 80 may transmit and receive data to and from each other through a bus 90.

[0022] The CPU 10 can control the semiconductor device 1 and perform calculations related to the program executed on the semiconductor device 1. The GPU 20 is a dedicated processing device designed to quickly perform mathematical calculations for image rendering. The hardware acceleration circuit 30 is a device designed to accelerate calculations separately from the CPU 10 and the GPU 20. In this specification, although the hardware acceleration circuit 30 may be understood as a device that performs calculations for image rendering separately from the GPU 20, the scope of the present disclosure is not limited thereto.

[0023] On the other hand, the digital signal processor 40 digitally processes digital signals using various algorithms. The memory device 50 provides a space that can temporarily store data used in the semiconductor device 1. The display device 70 is used to provide information about the work performed in the semiconductor device 1 to the user. The storage device 80 provides a space that can non-temporarily store data used in the semiconductor device 1.

[0024] In an embodiment, although the memory device 50 may include a dynamic random access memory (DRAM), the scope of the present disclosure is not limited thereto.

[0025] The micro-timing circuit 60 is a hardware device that performs a series of controls to shorten the time taken after a device (e.g., the GPU 20 or the hardware acceleration circuit 30) performs a rendering operation of an image frame until the display device 70 displays the rendered frame. In this article, the series of controls refers to the control of the work procedures performed when a device such as the GPU 20 or the hardware acceleration circuit 30 generates rendering data and writes it to the memory device 50 until the display device 70 reads the memory device 50 and displays the rendering data.

[0026] When a device such as the GPU 20 or the hardware acceleration circuit 30 generates rendering data, writes it on the memory device 50, and then generates an interrupt on the CPU 10 (different from the method in which the CPU 10 controls the display device 70 to read the memory device 50 (i.e., the method in which the CPU 10 executes software for performing the series of controls)), the micro-timing circuit 60 can perform the above-mentioned series of controls in hardware between the GPU 20 or the hardware acceleration circuit 30 and the display device 70 without the intervention of the CPU 10.

[0027] Therefore, in this specification, considering the feature of not intervening in the operation of the CPU 10, only the GPU 20 or the hardware acceleration circuit 30 may be referred to as a “processor”.

[0028] Figure 2 is a block diagram of a semiconductor device 2 according to an embodiment, Figure 3 is a diagram illustrating the operation of the semiconductor device 2 according to the embodiment.

[0029] refer to Figure 2 , the semiconductor device 2 includes a GPU 20 , a memory device 50 , an MS circuit 60 , and a display device 70 .

[0030] The GPU 20 may perform a rendering operation of an image frame to generate rendering data RD, and write the generated rendering data RD on the memory device 50 .

[0031] The memory device 50 may include a frame buffer (FB) 52 that can be accessed by the GPU 20. That is, the GPU 20 may write the generated rendering data RD on the frame buffer 52 of the memory device 50.

[0032] The display device 70 may include a display controller 72, a display interface 74, and a display 76. The display controller 72 performs a read operation for reading the memory device 50 to obtain the image data ID. In addition, the display controller 72 synthesizes the image data ID to generate synthesized image data CID, and can display the synthesized image data CID on the display 76 through the display interface 74.

[0033] The micro timing circuit 60 may transmit a start signal SS to the display controller 72 according to the execution degree of the rendering operation of the GPU 20. Then, the display controller 72 may start a read operation in response to the start signal SS received from the micro timing circuit 60.

[0034] After completing the rendering operation, the GPU 20 may transmit a notification signal NS to the micro-timing circuit 60. In addition, the micro-timing circuit 60 may transmit a start signal SS to the display controller 72 in response to the notification signal NS. Then, the display controller 72 may immediately start the reading operation in response to the start signal SS received from the micro-timing circuit 60.

[0035] That is, according to the semiconductor device 2, the micro-timing circuit 60 can directly notify the display controller 72 that the GPU 20 has completed the rendering operation without the intervention of the CPU 10, and the display controller 72 can immediately start reading after receiving the notification. Therefore, the time taken from the GPU 20 performing the rendering operation of the image frame until the display device 70 displays the rendered frame can be significantly reduced.

[0036] For example, reference Figure 3 Considering the signal "Frame Start from Micro-Timing Circuit" after the GPU 20 completes writing the rendering data RD to the frame buffer 52 and the "Frame Buffer Ready IRQ" signal transitions from low to high, a high signal (first high signal) represented by a dashed line and a high signal (second high signal) represented by a solid line are shown. Here, the first high signal indicates the time point at which the display controller 72 can begin reading the frame buffer 52 when processed by software (SW) with the intervention of the CPU 10, while the second high signal indicates the time point at which the display controller 72 can begin reading the frame buffer 52 when processed by the micro-timing circuit 60 without the intervention of the CPU 10. Since the time delayed by the software (SW) is reduced, the time between the high signal of the frame start (second high signal) and the high signal of VSYNC can be ensured to be the same as that of VFP. From this fact, it can be understood that the micro-timing circuit 60 significantly reduces the time it takes from the GPU 20 performing the image frame rendering operation until the display device 70 displays the rendered frame.

[0037] Reference again Figure 2 Although the GPU 20 is illustrated as a GPU, the scope of the present disclosure is not limited thereto, and the GPU 20 may include any device that performs a rendering operation of an image frame.

[0038] On the other hand, although the notification signal NS may include an interrupt signal, the scope of the present disclosure is not limited thereto.

[0039] Figure 4 is a block diagram of a semiconductor device 3 according to an embodiment, Figure 5 、 Figure 6 and Figure 7 is a diagram of a frame buffer according to an embodiment.

[0040] refer to Figure 4, the semiconductor device 3 includes a GPU 20 , a memory device 50 , an MS circuit 60 , and a display device 70 .

[0041] The main description and Figure 2 When the GPU 20 performs a rendering operation, the micro-timing circuit 60 may monitor (MON) the memory device 50 on which the rendering data RD is written. If the monitoring result satisfies a predetermined condition, the micro-timing circuit 60 may send a start signal SS to the display controller 72. Then, the display controller 72 may start a read operation in response to the start signal SS received from the micro-timing circuit 60.

[0042] The micro-timing circuit 60 may monitor the amount of rendering data RD written on the memory device 50. When the monitored amount exceeds a predetermined value, the micro-timing circuit 60 may send a start signal SS to the display controller 72. The display controller 72 may then immediately start a read operation in response to the start signal SS received from the micro-timing circuit 60.

[0043] Herein, the expression “the amount of rendering data RD written on the storage device 50 exceeds a predetermined value” refers to a case where there is no operational problem even if the display controller 72 reads the area written on the storage device 50 in advance (even at a point in time when the GPU 20 has not completed the rendering operation).

[0044] On the other hand, refer to Figures 5 to 7 , the micro-timing circuit 60 may monitor a write pointer WP indicating a point at which the rendering data RD is written into the memory device 50. When the monitored write pointer WP reaches a predetermined area or position, the micro-timing circuit 60 may send a start signal SS to the display controller 72. The display controller 72 may then immediately start a read operation in response to the start signal SS received from the micro-timing circuit 60.

[0045] For example, reference Figure 5 When the GPU 20 performs a rendering operation, the micro-timing circuit 60 can detect that the write pointer WP reaches the first position POS1 when monitoring the frame buffer 52 of the memory device 50. The micro-timing circuit 60 can then send a start signal SS to the display controller 72, and the display controller 72 can read the area from the beginning of the frame buffer 52 to the first position POS1 in response to the start signal SS received from the micro-timing circuit 60, and display the area on the display 76 through the display interface 74 or use the area to generate synthesized image data CID.

[0046] Next, refer to Figure 6While continuously monitoring the frame buffer 52 of the memory device 50, the micro-sequential circuit 60 may detect that the write pointer WP reaches the second position POS2. The micro-sequential circuit 60 may then send a start signal SS to the display controller 72, and the display controller 72 may read the region from the first position POS1 to the second position POS2 of the frame buffer 52 in response to the start signal SS.

[0047] Next, refer to Figure 7 While continuously monitoring the frame buffer 52 of the memory device 50, the micro-sequential circuit 60 may detect that the write pointer WP reaches the third position POS3. The micro-sequential circuit 60 may then send a start signal SS to the display controller 72, and the display controller 72 may read the area from the second position POS2 to the third position POS3 of the frame buffer 52 in response to the start signal.

[0048] According to the semiconductor device 3, the micro-timing circuit 60 directly notifies the display controller 72 that the display controller 72 can read the memory device 50 even before the GPU 20 completes the rendering operation, and the display controller 72 can immediately start the reading operation upon receiving the notification. Therefore, the time taken for the display device 70 to display the rendered frame after the GPU 20 starts the rendering operation of the image frame can be significantly reduced.

[0049] Figure 8 is a block diagram of a semiconductor device 4 according to the embodiment.

[0050] refer to Figure 8 , the semiconductor device 4 includes a GPU 20 , a memory device 50 , an MS circuit 60 , and a display device 70 .

[0051] The main description and Figure 4 When the GPU 20 performs a rendering operation, the micro-timing circuit 60 may monitor (MON) the memory device 50 on which the rendering data RD is written. If the monitoring result satisfies a predetermined condition, the micro-timing circuit 60 may send a write pointer WP to the display controller 72. The display controller 72 may then perform a read operation based on the write pointer WP received from the micro-timing circuit 60.

[0052] The micro-timing circuit 60 may monitor a write pointer WP indicating a point at which rendering data RD is written on the memory device 50. When the monitored write pointer WP reaches a predetermined area or position, the micro-timing circuit 60 may send the write pointer WP to the display controller 72.

[0053] Then, the display controller 72 can determine a reading time point of the frame buffer 52 based on the write pointer WP received from the micro timing circuit 60. That is, by determining whether the display controller 72 actively reads the frame buffer 52 immediately based on the write pointer WP, or by determining whether to read the frame buffer 52 after waiting for a predetermined time, the display controller 72 can be flexibly operated according to the purpose of implementation.

[0054] On the other hand, the display controller 72 can determine the read region of the frame buffer 52 based on the write pointer WP received from the micro sequential circuit 60. That is, by determining which region of the frame buffer 52 the display controller 72 actively performs reading based on the write pointer WP, the display controller 72 can be flexibly operated according to the implementation purpose.

[0055] Figure 9 is a block diagram of a semiconductor device 5 according to the embodiment.

[0056] refer to Figure 9 , the semiconductor device 5 includes a GPU 20, a hardware acceleration circuit 30, a memory device 50, an MS circuit 60, and a display device 70. The memory device 50 may include a first frame buffer (FB1) 52 accessible by the GPU 20 and a second frame buffer (FB2) 54 accessible by the hardware acceleration circuit 30.

[0057] The GPU 20 may perform a first rendering operation of a first image frame to generate first rendering data RD1 , and may write the generated first rendering data RD1 on a first frame buffer 52 in the memory device 50 .

[0058] The hardware acceleration circuit 30 performs a second rendering operation of the second image frame to generate second rendering data RD2 , and may write the generated second rendering data RD2 on the second frame buffer 54 in the memory device 50 .

[0059] The display device 70 may include a display controller 72, a display interface 74, and a display 76. The display controller 72 performs a read operation for reading the memory device 50 to obtain the image data ID. In addition, the display controller 72 synthesizes the image data ID to generate synthesized image data CID, and can display the synthesized image data CID on the display 76 through the display interface 74.

[0060] The synthesized image data CID may include first image data derived from the first rendering data RD1 and second image data derived from the second rendering data RD2. For example, the first image data may be displayed on the background of the display 76, and the second image data may be displayed on the foreground of the display 76, or the first image data may be displayed on one area of ​​the display 76, and the second image data may be displayed on another area of ​​the display 76.

[0061] The micro timing circuit 60 may control the operation of the display controller 72 according to the degree of execution of the first rendering operation and the second rendering operation.

[0062] After completing one or both of the first rendering operation and the second rendering operation, one or both of the GPU 20 and the hardware acceleration circuit 30 may send a notification signal NS2 to the micro-timing circuit 60. In addition, the micro-timing circuit 60 may send a start signal SS to the display controller 72 in response to the notification signal NS2. The display controller 72 may then immediately start a read operation on one or both of the first frame buffer 52 and the second frame buffer 54 in response to the start signal SS received from the micro-timing circuit 60.

[0063] That is, according to the semiconductor device 5, the micro-timing circuit 60 can directly notify the display controller 72 that one or both of the GPU 20 and the hardware acceleration circuit 30 have completed the rendering operation without the intervention of the CPU, and the display controller 72 can immediately start the reading operation after receiving the notification. Therefore, it is possible to significantly reduce the time it takes for the display device 70 to display the rendered frame after one or both of the GPU 20 and the hardware acceleration circuit 30 have completed the rendering operation of the image frame.

[0064] Although GPU 20 is shown as a GPU and hardware acceleration circuit 30 is shown as a hardware acceleration circuit, the scope of the present disclosure is not limited thereto. GPU 20 or hardware acceleration circuit 30 may include any device that performs a rendering operation of an image frame.

[0065] On the other hand, although the notification signal NS2 may include an interrupt signal, the scope of the present disclosure is not limited thereto.

[0066] Figure 10 is a block diagram of a semiconductor device 6 according to an embodiment, Figure 11 is a diagram of a frame buffer according to an embodiment.

[0067] refer to Figure 10 , semiconductor device 6 includes GPU 20, hardware acceleration circuit 30, memory device 50, MS circuit 60, and display device 70. Memory device 50 may include a first frame buffer 52 accessible by GPU 20 and a second frame buffer 54 accessible by hardware acceleration circuit 30.

[0068] The main description and Figure 9 The micro-timing circuit 60 may monitor (MON) the memory device 50 on which the first rendering data RD1 and the second rendering data RD2 are written. If the monitoring result satisfies a predetermined condition, the micro-timing circuit 60 may transmit a start signal SS to the display controller 72. The display controller 72 may then immediately start a read operation on one or both of the first frame buffer 52 and the second frame buffer 54 in response to the start signal SS received from the micro-timing circuit 60.

[0069] The micro-timing circuit 60 may monitor the amount of the first rendering data RD1 and the second rendering data RD2 written on the memory device 50. When the monitored amount exceeds a predetermined value, the micro-timing circuit 60 may send a start signal SS to the display controller 72. The display controller 72 may then immediately start a read operation on one or both of the first frame buffer 52 and the second frame buffer 54 in response to the start signal SS received from the micro-timing circuit 60.

[0070] On the other hand, refer to Figure 11 The micro-timing circuit 60 may monitor a first write pointer WP1 and a second write pointer WP2, wherein the first write pointer WP1 indicates a point at which the first rendering data RD1 is written into the first frame buffer 52, and the second write pointer WP2 indicates a point at which the second rendering data RD2 is written into the second frame buffer 54. When one or both of the monitored first write pointer WP1 and second write pointer WP2 reach a predetermined area or position of one or both of the first frame buffer 52 and the second frame buffer 54, the micro-timing circuit 60 may send a start signal SS to the display controller 72. The display controller 72 may then immediately start a read operation on one or both of the first frame buffer 52 and the second frame buffer 54 in response to the start signal SS received from the micro-timing circuit 60.

[0071] For example, reference Figure 11 When the GPU 20 and the hardware acceleration circuit 30 perform a rendering operation, the micro-timing circuit 60 can detect that the first write pointer WP1 reaches the third position POS3 while monitoring the first frame buffer 52 of the memory device 50. The micro-timing circuit 60 can then send a start signal SS to the display controller 72, and the display controller 72 can read the area up to the third position POS3 of the first frame buffer 52 in response to the start signal SS received from the micro-timing circuit 60, and display the area on the display 76 through the display interface 74, or use the area to generate synthesized image data CID.

[0072] On the other hand, the micro-timing circuit 60 may detect that the second write pointer WP2 reaches the fourth position POS4 while monitoring the second frame buffer 54 of the memory device 50. The micro-timing circuit 60 may then send a start signal SS to the display controller 72, and the display controller 72 may read the area up to the fourth position POS4 of the second frame buffer 54 in response to the start signal SS received from the micro-timing circuit 60, and display the area on the display 76 through the display interface 74, or generate synthesized image data CID using the area.

[0073] According to the semiconductor device 6, the micro-timing circuit 60 can directly notify the display controller 72 that the display controller 72 can read the memory device 50 even before the GPU 20 and the hardware acceleration circuit 30 complete the rendering operation, and the display controller 72 can immediately start the reading operation after receiving the notification. Therefore, it is possible to significantly reduce the time taken by the display device 70 to display the rendered frame after one or both of the GPU 20 and the hardware acceleration circuit 30 start the rendering operation of the image frame.

[0074] Figure 12 is a block diagram of a semiconductor device 7 according to the embodiment.

[0075] refer to Figure 12 , the semiconductor device 7 includes a GPU 20, a hardware acceleration circuit 30, a memory device 50, an MS circuit 60, and a display device 70. The memory device 50 may include a first frame buffer 52 accessible by the GPU 20 and a second frame buffer 54 accessible by the hardware acceleration circuit 30.

[0076] The main description and Figure 10 The micro-timing circuit 60 can monitor (MON) the memory device 50 to which the first rendering data RD1 and the second rendering data RD2 are written. If the monitoring result satisfies a predetermined condition, the micro-timing circuit 60 can send one or both of the first write pointer WP1 and the second write pointer WP2 to the display controller 72. The display controller 72 then performs a read operation based on one or both of the first write pointer WP1 and the second write pointer WP2 received from the micro-timing circuit 60.

[0077] The micro timing circuit 60 may monitor a first write pointer WP1 indicating a point at which the first rendering data RD1 is written into the first frame buffer 52 and a second write pointer WP2 indicating a point at which the second rendering data RD2 is written into the second frame buffer 54. When one or both of the monitored first write pointer WP1 and second write pointer WP2 reach a predetermined area or position of one or both of the first frame buffer 52 and the second frame buffer 54, the micro timing circuit 60 may send one or both of the first write pointer WP1 and the second write pointer WP2 to the display controller 72.

[0078] Then, the display controller 72 can determine a reading time point of one or both of the first frame buffer 52 and the second frame buffer 54 based on one or both of the first write pointer WP1 and the second write pointer WP2 received from the micro timing circuit 60. That is, by determining whether the display controller 72 actively reads one or both of the first frame buffer 52 and the second frame buffer 54 immediately based on one or both of the first write pointer WP1 and the second write pointer WP2, or whether to read one or both of the first frame buffer 52 and the second frame buffer 54 after waiting for a predetermined time, the display controller 72 can be flexibly operated according to the implementation purpose.

[0079] On the other hand, the display controller 72 can determine the read area of ​​one or both of the first frame buffer 52 and the second frame buffer 54 based on one or both of the first write pointer WP1 and the second write pointer WP2 received from the micro timing circuit 60. That is, by determining which area of ​​one or both of the first frame buffer 52 and the second frame buffer 54 the display controller 72 actively performs reading based on one or both of the first write pointer WP1 and the second write pointer WP2, the display controller 72 can be flexibly operated according to implementation.

[0080] As the convention in the field of the present invention, the embodiment is described and shown in the accompanying drawings from the aspect of functional blocks, units and / or modules. It will be understood by those skilled in the art that these blocks, units and / or modules are physically realized by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc., wherein the electronic (or optical) circuits can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. When blocks, units and / or modules are realized by microprocessors etc., they can be programmed using software (for example, microcode) to perform the various functions discussed herein, and can be optionally driven by firmware and / or software. Alternatively, each block, unit and / or module can be realized by dedicated hardware or be implemented as a combination of dedicated hardware that performs some functions and a processor (for example, one or more programmed microprocessors and associated circuits) that performs other functions. In addition, without departing from the scope of the present invention, each block, unit and / or module of the embodiment can be physically divided into two or more interactive and discrete blocks, units and / or modules. Furthermore, without departing from the scope of the inventive concept, the blocks, units and / or modules of the embodiments may be physically combined into more complex blocks, units and / or modules.

[0081] At the end of the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the embodiments without departing substantially from the principles of the present disclosure. Therefore, the disclosed embodiments of the present disclosure are intended to be general and descriptive only and not for the purpose of limitation.

Claims

1. A semiconductor device comprising: The processor is configured to: Performing a rendering operation on the image frame to obtain rendering data; and writing the acquired rendering data on a storage device; a display controller configured to perform a read operation on the storage device on which the rendering data is written to obtain image data; as well as a micro-timing circuit configured to send a start signal to the display controller based on the execution level of the rendering operation, The display controller is further configured to start the reading operation based on the sent start signal, The execution level of the rendering operation includes one of the following: The rendering operation is completed, the amount of the rendering data written on the storage device exceeds a predetermined value, and A write pointer indicating a point at which the rendering data is written into the storage device reaches a predetermined area or position of the storage device.

2. The semiconductor device according to claim 1, wherein The processor is further configured to send a notification signal to the micro-timing circuit based on completion of the rendering operation, and The micro timing circuit is further configured to send the start signal to the display controller based on the sent notification signal.

3. The semiconductor device according to claim 2, wherein The notification signal includes an interrupt signal.

4. The semiconductor device according to claim 1, wherein The micro timing circuit is further configured to perform a monitoring operation on the memory device when the processor performs the rendering operation, and The micro timing circuit is further configured to send the start signal to the display controller based on the result of the monitoring operation meeting a predetermined condition.

5. The semiconductor device according to claim 4, wherein The micro timing circuit is further configured to monitor the amount of the rendering data written on the storage device, and The micro timing circuit is further configured to send the start signal to the display controller based on the monitored quantity exceeding a predetermined value. The semiconductor device according to claim 4 , wherein: The micro sequential circuit is further configured as follows: monitoring a write pointer indicating a point at which the rendering data is written to the storage device; as well as The start signal is sent to the display controller based on the monitored write pointer reaching a predetermined area or location of the memory device.

7. The semiconductor device according to claim 1, wherein The processor includes a first processor and a second processor, The first processor is configured to: Obtaining first rendering data; and storing the acquired first rendering data in a first frame buffer of the storage device, The second processor is configured to: Obtaining second rendering data; as well as The acquired second rendering data is stored in a second frame buffer of the storage device.

8. A semiconductor device comprising: The processor is configured to: Performing a rendering operation on the image frame to obtain rendering data; and Writing the acquired rendering data to the frame buffer; The micro-sequential circuit is configured as: monitoring, while the processor performs the rendering operation, a write pointer indicating a point at which the rendering data is written into the frame buffer; and sending the monitored write pointer based on the monitored write pointer reaching a predetermined area or position of the frame buffer; as well as The display controller is configured to perform a read operation on the frame buffer to which the rendering data is written based on the sent write pointer to obtain image data.

9. The semiconductor device according to claim 8, wherein The display controller is further configured to acquire a read time point of the frame buffer on which the rendering data is written based on the transmitted write pointer.

10. The semiconductor device according to claim 8, wherein The display controller is further configured to acquire a read area of ​​the frame buffer on which the rendering data is written based on the transmitted write pointer.

11. The semiconductor device according to claim 8, wherein The processor includes a first processor and a second processor, The frame buffer includes a first frame buffer and a second frame buffer. The first processor is further configured to: performing a first rendering operation on a first image frame to obtain first rendering data; and Writing the acquired first rendering data to the first frame buffer, The second processor is further configured to: performing a second rendering operation on a second image frame to obtain second rendering data; and writing the acquired second rendering data on the second frame buffer, and Wherein, the micro sequential circuit is further configured as follows: monitoring a first write pointer indicating a first point at which the first rendering data is written into the first frame buffer and a second write pointer indicating a second point at which the second rendering data is written into the second frame buffer; and Based on the monitored first write pointer reaching a first predetermined area or position of the first frame buffer and the monitored second write pointer reaching one or both of a second predetermined area or position of the second frame buffer, one or both of the monitored first write pointer and the monitored second write pointer are sent to the display controller.

12. The semiconductor device according to claim 11, wherein The display controller is further configured to obtain a read time point of one or each of the first frame buffer and the second frame buffer based on one or both of the transmitted first write pointer and the transmitted second write pointer.

13. The semiconductor device according to claim 11, wherein The display controller is further configured to acquire a read region of one or each of the first frame buffer and the second frame buffer based on one or both of the transmitted first write pointer and the transmitted second write pointer.

14. A semiconductor device comprising: a memory device comprising a first frame buffer and a second frame buffer; The first processor is configured to: performing a first rendering operation on a first image frame to obtain first rendering data; and Writing the acquired first rendering data to the first frame buffer; The second processor is configured to: performing a second rendering operation on the second image frame to obtain second rendering data; and Writing the acquired second rendering data to the second frame buffer; as well as a micro-timing circuit configured to control an operation of a display controller based on a degree of execution of each of the first rendering operation and the second rendering operation, The execution degree of each of the first rendering operation and the second rendering operation includes one of the following: The first rendering operation is completed, The second rendering operation is completed, a first amount of the first rendering data written on the storage device exceeds a predetermined value, a second amount of the second rendering data written on the storage device exceeds a predetermined value, a first write pointer indicating a first point at which the first rendering data is written into the first frame buffer reaches a first predetermined area or position of the first frame buffer, and A second write pointer indicating a second point at which the second rendering data is written into the second frame buffer reaches a second predetermined area or position of the second frame buffer.

15. The semiconductor device according to claim 14, wherein The first processor is further configured to send a first notification signal to the micro-timing circuit based on completion of the first rendering operation. The second processor is further configured to send a second notification signal to the micro-timing circuit based on completion of the second rendering operation, and The micro timing circuit is further configured to send a start signal to the display controller based on the sent first notification signal or the sent second notification signal.

16. The semiconductor device according to claim 15, wherein Each of the first notification signal and the second notification signal includes an interrupt signal.

17. The semiconductor device according to claim 14, wherein The micro sequential circuit is further configured to perform a monitoring operation on the storage device to which the first rendering data and the second rendering data are written, and The micro timing circuit is further configured to send a start signal to the display controller based on the result of the monitoring operation satisfying a predetermined condition.

18. The semiconductor device according to claim 17, wherein The micro timing circuit is further configured to monitor a first amount of the first rendering data written on the storage device and a second amount of the second rendering data written on the storage device, and The micro timing circuit is further configured to send the start signal to the display controller based on one or each of the monitored first quantity and the monitored second quantity exceeding a predetermined value.

19. The semiconductor device according to claim 17, wherein The micro sequential circuit is further configured as follows: monitoring a first write pointer indicating a first point at which the first rendering data is written into the first frame buffer and a second write pointer indicating a second point at which the second rendering data is written into the second frame buffer; as well as The start signal is sent to the display controller based on one or both of the monitored first write pointer reaching a first predetermined area or position of the first frame buffer and the monitored second write pointer reaching a second predetermined area or position of the second frame buffer.

20. The semiconductor device according to claim 18, wherein The micro sequential circuit is further configured as follows: monitoring a first write pointer indicating a first point at which the first rendering data is written into the first frame buffer and a second write pointer indicating a second point at which the second rendering data is written into the second frame buffer; as well as Based on the monitored first write pointer reaching a first predetermined area or position of the first frame buffer and the monitored second write pointer reaching one or both of a second predetermined area or position of the second frame buffer, one or both of the monitored first write pointer and the monitored second write pointer are sent to the display controller.

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