Integrated chip and method of forming the same
By introducing fin spacers into FinFET devices, the lateral growth of the epitaxial source/drain regions is controlled, solving the short-circuit problem between adjacent devices caused by the reduction in FinFET device size, and improving device performance and reliability.
CN113948509BActive Publication Date: 2026-07-24TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
View PDF 3 Cites 0 Cited by
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
- Filing Date
- 2021-06-11
- Publication Date
- 2026-07-24
Smart Images
Figure CN113948509B_ABST
Abstract
The present invention relates to integrated chips. An integrated chip can include a semiconductor substrate having sidewalls defining a plurality of fins. A dielectric material is disposed between the plurality of fins, and a gate structure is disposed over the dielectric material and around the plurality of fins. Epitaxial source / drain regions are disposed along opposite sides of the gate structure and include a plurality of source / drain segments disposed on the plurality of fins and doped epitaxial material disposed on and between the plurality of source / drain segments, respectively. A first source / drain segment of the plurality of source / drain segments extends laterally to different distances beyond opposite sides of an underlying first fin of the plurality of fins in opposite directions. Embodiments of the present invention also relate to methods of forming integrated chips.
Need to check novelty before this filing date? Find Prior Art