Silicon-based heterogeneous integrated optoelectronic chip and preparation method thereof

Abstract

This application relates to the field of optoelectronic integrated chip technology, and more specifically, to a silicon-based heterogeneous integrated optoelectronic chip and its fabrication method. A Si-on-SiC structure is fabricated using a direct bonding process for heterogeneous integration. The Si passive device layer is then patterned as a waveguide. Subsequently, a III-V epitaxial material is bonded to the Si passive device layer again using a direct bonding process. Through these two direct bonding processes, a silicon carbide-on-silicon-on-III-V group (III-V on Si on SiC) structure is formed. Active device design and patterning are performed on the III-V semiconductor active layer. The patterned structure design enables the coupling of light from the III-V semiconductor active layer to the Si passive device layer, thereby forming an on-chip integrated chip integrating active and passive devices. The method provided by this invention achieves a scalable, highly integrated, low-loss, and high-thermal-conductivity optoelectronic integrated chip, while simplifying the fabrication process and reducing costs.

Description

Technical Field

[0001] This application relates to the field of optoelectronic integrated chip technology, and more specifically, to a silicon-based heterogeneous integrated optoelectronic chip and its fabrication method. Background Technology

[0002] With the rise of artificial intelligence, the amount of information and data is exploding. The continuous exponential shrinkage of electronic chip feature sizes has opened up avenues for integrating higher-density, higher-speed devices and achieving low-cost integration technologies and communications, thus building transmission links with Tbps-level data rates. However, this also highlights the limitations of electrical interconnects in digital processing systems, with system performance increasingly constrained by the interconnect medium. Therefore, optical interconnects are considered a highly attractive alternative. Among the many photonic integrated circuit (PIC) platforms, silicon-on-insulator (SOI) PICs are currently the most mature and widely used platform. However, since silicon is an indirect bandgap material, it is difficult to use it directly as a high-efficiency on-chip light source. Before realizing reliable and efficient silicon-based light emitters, non-silicon-based light source solutions must be considered. Therefore, it is necessary to introduce III-V group direct bandgap materials through heterogeneous integration technology to fabricate on-chip light sources.

[0003] However, for heterogeneous integration of III-V on SOI (III-V on Silicon-on-Insulator), the following problems exist: First, regarding the substrate, there are issues: 1. In terms of thermal conductivity: the thermal conductivity of the SiO2 buried oxide layer in the SOI structure is extremely low, only 1.4 W / m·K, significantly lower than typical semiconductor materials such as silicon (149 W / m·K), indium phosphide (68 W / m·K), and silicon carbide (490 W / m·K). Finally, and most importantly, the indirect bandgap characteristic of silicon makes it difficult to use as an on-chip light source. Traditional SOI cannot overcome this limitation, so most designs are passive devices using external light sources for testing. To solve the light source problem, III-V semiconductors need to be heterogeneously integrated onto silicon to achieve on-chip integrated lasers. However, lasers generate considerable heat during operation. The increased thermal load within the high-density laser chip alters the light output, reduces device performance, and shortens the overall device lifespan. This creates a trade-off between high packaging density and effective laser performance, making it quite difficult for photonic light sources to adapt to applications with limited physical space. 2. Heat dissipation is difficult to overcome effectively: The buried oxide layer (SiO2) in SOI wafers has extremely low thermal conductivity (approximately 1.3 to 1.4 W / (m·K)), making it difficult to effectively dissipate the heat generated during device operation, resulting in heat accumulation. Under high-power operating conditions, heat accumulation will lead to a significant increase in device temperature, causing problems such as decreased gain, reduced output power, and wavelength drift, severely restricting the output performance and long-term operational reliability of the device. 3. Heat accumulation induces thermal degradation of III-V materials. During operation, the temperature of active devices on III-V on SOI wafers rises sharply, leading to significant degradation in device performance, especially as the laser output power easily exhibits saturation characteristics when a small current is injected. Furthermore, thermal management is particularly critical when device density is high and multiple active devices are integrated within a limited chip area. III-V on SOI wafers generate significant thermal stress during high-temperature processes. Due to the significant mismatch in thermal expansion coefficients between InP and Si materials, the InP layer will be subjected to thermal stress exceeding 100 MPa, leading to crystal quality degradation and even thermal degradation, ultimately causing device failure. Secondly, in the field of heterogeneous integration, while monolithic integration is an ideal solution for on-chip integration of indium phosphide (InP), several drawbacks significantly hinder its development: First, limitations in substrate and production scale: InP wafers are relatively small (typically 2-6 inches), making it difficult to meet the requirements of large-scale, low-cost industrial production; second, high requirements for consistency in epitaxial growth processes: to combine different components onto the same InP chip, multiple epitaxial growth cycles are usually required, which can easily increase defect density and necessitates extremely high control over material uniformity.In contrast, hybrid integration is not limited by lattice matching, so this is currently the main technological approach. However, micro-transfer and flip-chip bonding technologies have extremely stringent requirements for the alignment accuracy between devices and silicon waveguides, posing significant challenges to manufacturing costs and automation levels when achieving industrial-grade high-density optical integration. Therefore, although silicon photonic circuits have a cost advantage, integrating prefabricated laser diode (LD) chips with planar optical paths using micro-transfer or flip-chip bonding technologies is time-consuming and costly, ultimately significantly increasing the overall cost of assembly and packaging. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of existing silicon-on-insulator (SiI-III) chips, such as poor heat dissipation, easy device failure, and high manufacturing cost. This invention provides a silicon-based heterogeneous integrated optoelectronic chip and its fabrication method, which effectively improves the heat dissipation capability of the device and reduces the fabrication difficulty.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: A silicon-based heterogeneous integrated optoelectronic chip is provided, comprising, from bottom to top: SiC substrate; Si passive device layer: directly bonded to the SiC substrate using a bonding process; III-V group semiconductor active layer: directly bonded to the Si passive device layer using a bonding process.

[0006] This invention provides a silicon-based heterogeneous integrated optoelectronic chip that incorporates SiC, a material with high thermal conductivity, as a substrate. Structurally, this brings the active device layer closer to the ultra-high thermal conductivity SiC substrate, significantly improving heat dissipation and effectively suppressing the impact of thermal effects on device performance. Furthermore, this invention employs a direct bonding process for heterogeneous integration to fabricate a Si-on-SiC structure, and then again uses a direct bonding process to bond III-V semiconductor materials to the Si passive device layer. Through these two direct bonding processes, a silicon carbide-silicon-III-V group semiconductor (III-V on Si on SiC) structure is formed. In practical applications, the desired functional devices can be fabricated by patterning the Si passive device layer and the III-V semiconductor active layer. This invention integrates III-V active, Si passive, and SiC substrates, solving the heat dissipation bottleneck caused by buried oxide layers in traditional heterogeneous integration on SOI platforms. Effective heat dissipation measures alleviate the problem of heat accumulation that leads to crystal quality degradation or even thermal degradation, thereby reducing device energy loss and improving device lifespan. Additionally, the direct bonding method simplifies the device fabrication process and reduces costs.

[0007] Furthermore, it also includes a thermally insulating coupler disposed on the Si passive device layer and the III-V semiconductor active layer, for effectively coupling light from the III-V semiconductor active layer to the Si passive device layer.

[0008] Furthermore, the thermally adiabatic coupler includes a III-V group active waveguide and a silicon waveguide coupled to the III-V group active waveguide; the width or refractive index of the III-V group active waveguide gradually decreases along the optical transmission direction; the width or refractive index of the silicon waveguide gradually increases or remains constant along the optical transmission direction.

[0009] Furthermore, by utilizing the high refractive index characteristics of the silicon waveguide in the Si passive device layer and placing the III-V semiconductor active layer directly above the silicon waveguide, the optical mode field is localized within the silicon waveguide, thereby constraining the optical field in the passive waveguide and thus coupling the optical field from the III-V semiconductor active layer to the Si passive device layer.

[0010] Furthermore, optoelectronic chips include on-chip lasers, electroabsorption modulators, or photodetectors.

[0011] Furthermore, the III-V group semiconductor active layer, from bottom to top, includes an n-InP layer, a multiple quantum well layer, a p-InP layer, a p-InGaAs layer, and a metal contact electrode located on the Si passive device layer.

[0012] Furthermore, the III-V group semiconductor active layer, from bottom to top, includes an n-InP layer, a multiple quantum well layer, and a buffer layer n located on the Si passive device layer. + -InP, P-type contact layer p + -InGaAs, and metal contact electrodes.

[0013] Furthermore, the III-V semiconductor active layer, from bottom to top, includes an n-InP layer, a multiple quantum well layer, a p-InP layer, and a metal contact electrode located on the Si passive device layer.

[0014] This invention also provides a method for fabricating a silicon-based heterogeneous integrated optoelectronic chip, comprising the following steps: S1. Wafer bonding: Pre-treatment of SiC wafers and SOI wafers, the pre-treatment including surface cleaning and plasma activation treatment; S2. Room temperature bonding: The activated SiC and SOI wafer are aligned and bonded at room temperature to obtain SOI-SiC samples. S3. Bonding Annealing: The bonded SOI-SiC sample is placed in a bonding device for annealing treatment; S4. Removal of SOI substrate: The substrate thickness is reduced by chemical mechanical polishing, followed by etching to remove the substrate silicon and silicon dioxide buried oxide layer, retaining the Si passive device layer; thus obtaining a Si on SiC wafer; S5. Spin-coating photoresist: Plasma activation treatment is performed on the Si on SiC wafer, followed by spin-coating photoresist; S6. Waveguide Patterning: The designed waveguide device structure is transferred to the Si passive device layer using electron beam lithography, and waveguide patterns are formed by reactive ion etching. S7. Bonding III-V semiconductor active layer: Pre-process the Si on SiC wafer and the III-V epitaxial wafer, and then perform bonding annealing; S8. Substrate Removal: The InP substrate layer is removed by CMP thinning combined with wet etching, while the III-V group semiconductor active layer is retained for active device fabrication; resulting in a III-V on Si on SiC wafer; S9. Spin-coating photoresist: Plasma activation treatment is performed on the III-V on Si on SiC wafer after the substrate has been removed, followed by spin-coating photoresist; S10. Active device patterning: Electron beam lithography is used to pattern the III-V on Si on SiC wafer with spin-coated photoresist, and the device structure is formed by wet etching of the III-V semiconductor active layer. S11. Deposition of cladding and windowing: A silicon dioxide cladding is deposited on the surface of a patterned device using plasma-enhanced chemical vapor deposition (PECVD), and windowing is performed in specific areas. S12. Electroplated metal electrodes: P-type and / or n-type metal contact electrodes are deposited on the device surface through a stripping process to finally complete the device fabrication.

[0015] This invention discloses a method for fabricating a silicon-based heterogeneous integrated optoelectronic chip. The method employs a direct bonding process for heterogeneous integration to fabricate a Si-on-SiC structure, and then performs waveguide patterning on the Si passive device layer. Subsequently, a III-V epitaxial material is bonded to the Si passive device layer again using a direct bonding process. Through these two direct bonding processes, a silicon carbide-on-silicon-on-III-V group (III-V on Si on SiC) structure is formed. Active device design and patterning are performed on the III-V semiconductor active layer. The patterned structure design enables the coupling of light from the III-V semiconductor active layer to the Si passive device layer, thereby forming an on-chip integrated chip integrating active and passive devices. The method provided by this invention achieves a scalable, highly integrated, low-loss, and high-thermal-conductivity optoelectronic integrated chip, while simplifying the fabrication process and reducing costs.

[0016] Furthermore, step S3 includes setting an annealing temperature of 250~300℃ in a vacuum environment and applying mechanical pressure to the SOI-SiC sample.

[0017] Compared with the prior art, the beneficial effects of the present invention are: 1. The present invention provides a silicon-based heterogeneous integrated optoelectronic chip that integrates a III-V active-Si passive-SiC substrate, which solves the heat dissipation bottleneck caused by the buried oxide layer in the SOI platform in traditional heterogeneous integration. The effective heat dissipation measures alleviate the problem of heat accumulation that leads to crystal quality deterioration or even thermal degradation, thereby reducing device energy loss and improving device lifespan.

[0018] 2. The present invention provides a method for fabricating a silicon-based heterogeneous integrated optoelectronic chip, which forms a silicon carbide-on-silicon III-V group through two direct bonding processes, forming an on-chip integrated chip that integrates active and passive devices. The method provided by the present invention realizes a scalable, highly integrated, low-loss and high thermal conductivity optoelectronic integrated chip, while simplifying the manufacturing process and reducing costs. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the silicon-based heterogeneous integrated optoelectronic chip structure in Example 1; Figure 2 This is a schematic diagram of a heterogeneous integrated laser structure in Example 2, where the optical mode is mainly confined within a silicon waveguide; the arrows in the diagram indicate the direction of photon propagation. Figure 3 The following is a schematic diagram of the thermal coupler structure in Example 2, where (a) represents a three-dimensional structural schematic diagram of the thermal coupler, (b) represents a thermal coupler with the width of the silicon waveguide changing from thin to wide, and (c) represents a thermal coupler with the silicon waveguide remaining a wide waveguide. Figure 4 This is a schematic diagram of the semiconductor laser structure in Example 3; Figure 5 This is a schematic diagram of the electroabsorption modulator structure in Example 4; Figure 6 This is a schematic diagram of the semiconductor detector structure in Example 5; Figure 7 This is a schematic diagram of the fabrication process of a silicon-based heterogeneous integrated optoelectronic chip in Example 6; Figure 8 This is a schematic diagram of the device structure of the integrated chip in Example 7; Figure 9 This is a schematic diagram comparing the changes in thermal stress in different structures.

[0020] In the attached figures: 1. SiC substrate; 2. Si passive device layer; 3. III-V group semiconductor active layer; 31. n-InP layer; 32. Multiple quantum well layer; 33. p-InP layer; 34. p-InGaAs layer; 35. Metal contact electrode; 351. p-type metal electrode; 352. n-type metal electrode; 36. Buffer layer; 37. P-type contact layer; 38. Active region; 4. Bonding dielectric layer; 5. Optical mode; 6. Silicon waveguide; 7. Active waveguide. Detailed Implementation

[0021] The present invention will be further described below with reference to specific embodiments. The accompanying drawings are for illustrative purposes only, representing schematic diagrams rather than actual physical objects, and should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some components in the drawings may be omitted, enlarged, or reduced, and do not represent the actual dimensions of the product. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0022] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0023] Example 1 This embodiment is a first embodiment of a silicon-based heterogeneous integrated optoelectronic chip, such as... Figure 1 As shown, the silicon-based heterogeneous integrated optoelectronic chip includes, from bottom to top: SiC substrate 1; Si passive device layer 2: directly bonded to the SiC substrate 1 using a bonding process; III-V group semiconductor active layer 3: directly bonded to the Si passive device layer 2 using a bonding process.

[0024] The thermal conductivity of the silicon carbide substrate (490 W / (m·K)) is significantly higher than that of the traditional InP substrate (68-80 W / (m·K)) and the buried oxide layer in the SOI structure (1.4 W / (m·K)). Combined with the high thermal conductivity of silicon in the Si passive device layer 2 (150 W / (m·K)), a highly efficient heat dissipation channel is formed. Compared with the heat dissipation bottleneck caused by the buried oxide layer in the traditional heterogeneous integration of SOI platforms, this solution introduces the high thermal conductivity material SiC as the substrate and structurally positions the active device layer closer to the ultra-high thermal conductivity SiC substrate 1, significantly improving the heat dissipation effect and effectively suppressing the impact of thermal effects on device performance. At the same time, the effective heat dissipation measures alleviate the problem of heat accumulation that leads to crystal quality degradation or even thermal degradation, thereby reducing device energy loss and improving device lifespan.

[0025] In addition, in this embodiment, a III-V on Si on SiC semiconductor structure is designed through two direct bonding processes. Active devices (such as lasers and detectors) are fabricated by utilizing the active properties of III-V materials, and passive devices (such as waveguide structures) are fabricated using mature Si processes. The high refractive index of silicon or the design of thermally insulating couplers are used to efficiently couple light from the active device layer to the passive waveguide device layer, thereby forming an on-chip integrated chip that integrates active and passive devices. This results in an effective and technically feasible scalable, highly integrated, low-loss, and high-thermal-conductivity optoelectronic integrated chip.

[0026] In this embodiment, the system compares the differences in heat dissipation performance and the resulting thermal stress differences between III-V on Si on SiC wafers (where the Si passive device layer 2 is only 220 nm thick, and its influence is negligible compared to the III-V and SiC layers, and can be equivalently regarded as a III-V on SiC structure), traditional III-V on SOI substrates, and traditional III-V on SiO2 substrates. The impact of different substrate structures on the thermal management characteristics of the device is evaluated through thermodynamic simulation and experimental verification.

[0027] according to Figure 9The results show that introducing the Si-on-SiC structure significantly improves thermal conductivity. Compared to traditional III-V on SOI and III-V on SiO2 substrates, under the same thermal power injection conditions (e.g., 800 mW), the temperature of the III-V on SiO2 substrate exceeds 700 K, the temperature of the traditional III-V on SOI substrate is close to 450 K, while the temperature of the III-V on Si on SiC substrate 1 remains at approximately 320 K. Simulation results further verify that the thermal conductivity of silicon carbide (SiC) (490 W / (m·K)) is significantly higher than that of silicon dioxide (1.4 W / (m·K)). This conclusion confirms the feasibility of achieving high thermal conductivity by fabricating III-V on Si on SiC wafers using direct bonding technology.

[0028] Furthermore, in practice, since the Si waveguide layer in III-V on Si on SiC and III-V on SOI structures is sufficiently small compared to the buried oxide layers of silicon carbide and silicon dioxide, it is practically possible to approximate the thermal distribution of the III-V on SOI structure with III-V on SiO2 and the thermal distribution of the III-V on Si on SiC structure with III-V on Si. Figure 9 It can be seen that introducing a silicon carbide substrate can greatly alleviate the thermal stress problem in III-V on Si on SiC structures. When the implantation power is 1W, the stress in III-V on Si on SiC does not exceed 10MPa, while the stress in III-V on SOI is greater than 40MPa, and the stress in III-V on SiO2 exceeds 150MPa. This is because the coefficients of thermal expansion of silicon and silicon carbide are relatively close (silicon is approximately 2.6 × 10⁻⁶). -6 / K, silicon carbide is approximately 4.0 × 10⁻⁶. -6 / K), compared to the thermal mismatch between III-V materials and silicon (InP is approximately 4.6 × 10⁻⁶ K), -6 The III-V on Si on SiC structure generates less thermal stress during temperature cycling, which alleviates the problem of heat accumulation that leads to crystal quality deterioration or even thermal degradation, thereby reducing device energy loss and helping to improve device reliability.

[0029] In summary, this embodiment provides a silicon-based heterogeneous integrated optoelectronic chip that incorporates SiC, a material with high thermal conductivity, as a substrate. Structurally, this brings the active device layer closer to the ultra-high thermal conductivity SiC substrate 1, significantly improving heat dissipation and effectively suppressing the impact of thermal effects on device performance. Furthermore, this invention employs a direct bonding process for heterogeneous integration to fabricate a Si-on-SiC structure, and then again uses a direct bonding process to bond III-V group semiconductor materials to the Si passive device layer 2. Through these two direct bonding processes, a silicon carbide-on-silicon-on-III-V group semiconductor (III-V on Si on...) structure is formed. In practical applications, the desired functional devices can be fabricated by patterning the Si passive device layer 2 and the III-V semiconductor active layer 3. This invention integrates the III-V active-Si passive-SiC substrate 1, solving the heat dissipation bottleneck caused by the buried oxide layer in the traditional heterogeneous integration of SOI platform. The effective heat dissipation measures alleviate the problem of heat accumulation that leads to crystal quality degradation or even thermal degradation, thereby reducing device energy loss and improving device lifespan. In addition, this invention adopts a direct bonding method, which simplifies the device fabrication process and reduces costs.

[0030] Example 2 This embodiment is a second embodiment of a silicon-based heterogeneous integrated optoelectronic chip. This embodiment is similar to Embodiment Two, except that in this embodiment, through patterning design and processing of the Si passive device layer 2 and the III-V group semiconductor active layer 3, such as... Figure 2 As shown, a method for implementing a semiconductor on-chip laser is provided.

[0031] In this embodiment, a III-V on Si on SiC wafer is first fabricated using a direct bonding process. Then, the III-V semiconductor active layer 3 is patterned using photolithography and etching processes. Finally, a lift-off process is used to deposit contact metal electrodes, thereby fabricating an on-chip light source. Structurally, this light source consists of a P-type metal contact electrode 35, a p-InGaAs layer 34, a p-InP layer 33, a multiple quantum well layer 32 (QWs), an n-InP layer 31, and an N-type metal contact electrode 35, forming an on-chip semiconductor laser. Simultaneously, the Si layer serves as a passive device layer, while SiC acts as a high thermal conductivity substrate layer.

[0032] The core innovation of the on-chip laser structure provided in this embodiment lies in replacing the traditional SOI substrate with a Si-on-SiC substrate 1. In this Si-on-SiC substrate 1 structure, the refractive index of silicon (n=3.47) is significantly higher than that of the upper InP layer (n=3.15) and the lower silicon carbide layer (n=2.7), forming a longitudinal refractive index difference, thereby achieving effective confinement of the optical field and generating an optical waveguide effect. In terms of thermal management, the thermal conductivity of the silicon carbide substrate is as high as 490 W / (m·K), and the thermal conductivity of silicon is about 150 W / (m·K), both of which are far superior to the 68-80 W / (m·K) of the traditional InP substrate and the 1.4 W / (m·K) of the silicon dioxide buried oxide layer. This excellent heat dissipation characteristic can significantly suppress the temperature rise of the device under high power operation and avoid performance degradation caused by heat accumulation. This structure effectively solves the heat dissipation bottleneck caused by the extremely low thermal conductivity of the buried oxide layer in traditional SOI, thereby eliminating problems such as device temperature rise, gain attenuation, output power reduction, and wavelength drift caused by heat accumulation. In terms of optical coupling mechanism, efficient optical field transmission from the III-V group semiconductor active layer 3 to the Si passive device layer 2 was achieved through an adiabatic coupling structure, and finally a high thermal conductivity optoelectronic integrated chip integrating high-density active device and passive device transmission functions was constructed.

[0033] Example 3 This embodiment is a third embodiment of a silicon-based heterogeneous integrated optoelectronic chip. This embodiment is similar to Embodiment 1, except that in this embodiment, through patterning design and processing of the Si passive device layer 2 and the III-V group semiconductor active layer 3, such as... Figure 3 As shown, an implementation of an on-chip semiconductor electroabsorption modulator is provided.

[0034] In this embodiment, electron beam lithography was used to pattern and etch the Si passive device layer 2, which was then directly bonded to a III-V semiconductor wafer. Based on the bonded III-V on Si on SiC wafer, active device design and fabrication were carried out.

[0035] In this embodiment, a III-V on Si on SiC wafer is first fabricated using a direct bonding process. Then, the active layer 3 of the III-V semiconductor is patterned using photolithography and etching processes. Finally, a lift-off process is used to deposit contact metal electrodes, successfully fabricating a III-V on Si on SiC electro-absorption modulator (EAM) based on heterogeneous integration. The electro-absorption modulator provided in this embodiment mainly includes the following structure: p + -InGaAs (heavily doped indium gallium arsenide) layers are typically used as p-type contact layers 37, providing good ohmic contact; n +The InP (heavily doped indium phosphide) layer serves as a buffer layer 36 or an etch stop layer, while also exhibiting low resistance. The multi-quantum well layer 32 acts as the core layer of the electro-absorption modulator. Optical signals in the silicon waveguide (Si passive device layer 2) are coupled into the modulation region of the multi-quantum well layer 32 via an adiabatic-coupled tapered waveguide. The modulated optical signal is then coupled back into the silicon waveguide from the adiabatic-coupled tapered waveguide. This structure ensures a smooth transition of the optical field mode, achieving efficient modulation while reducing optical loss. The SiC substrate layer 1, with its high thermal conductivity, aids in device heat dissipation. The device operates by propagating light in the silicon waveguide and coupling it to the III-V multi-quantum well absorption layer via an evanescent wave. When a voltage is applied through the electrodes, an electric field is generated in the multi-quantum well region, inducing the quantum-confined Stark effect (QCSE). This causes a redshift in the absorption spectrum and alters the absorption coefficient of the material, thereby modulating the propagation of a large optical signal and achieving high-speed electro-optic modulation. From a device structure perspective, III-V on Si on SiC is also suitable for fabricating III-V Mach-Zehnder modulators or micro-ring modulators; from a carrier modulation mechanism perspective, it can be extended to the fabrication of carrier depletion-type and carrier injection-type modulators, as well as carrier accumulation-type modulators; and from a modulation method perspective, it can be extended to MOS capacitor structure modulation based on plasmonic dispersion or electro-optic modulation (EOM). All of the above structures are feasible and should be covered within the scope of this invention.

[0036] Example 4 This embodiment is a fourth embodiment of a silicon-based heterogeneous integrated optoelectronic chip. This embodiment is similar to Embodiment 1, except that in this embodiment, through patterning design and processing of the Si passive device layer 2 and the III-V group semiconductor active layer 3, such as... Figure 4 As shown, a method for implementing a semiconductor detector is provided.

[0037] In this embodiment, active device design and fabrication were carried out on a bonded III-V on Si on SiC wafer. First, a direct bonding process was used to fabricate the III-V on Si on SiC wafer. Then, the III-V semiconductor active layer 3 was patterned using photolithography and etching processes. Finally, a lift-off process was used to deposit contact metal electrodes, successfully fabricating a heterogeneous integrated III-V photodetector. The layered structure of the device from top to bottom is as follows: p-type metal electrode 351, p-InP layer 33, active region 38, n-type metal electrode 352, n-InP layer 31, Si passive device layer 2, and SiC substrate 1.

[0038] The refractive index of InP (approximately 3.17 @ 1550 nm) is lower than that of InGaAs (approximately 3.54 @ 1550 nm), the active region 38 material. Together with the active region 38, they form a "high-low-high" refractive index distribution structure, thereby vertically confining the optical field mode within the active region 38. The active region 38 is composed of alternating layers of InGaAs and InGaAsP or InAlAs. The absorption wavelength and absorption coefficient are modulated through quantum confinement effects. This structure can be further designed for monolithic integration of electroabsorption modulators and detectors. SiC, as an ideal heat dissipation substrate for high-performance detectors, has a significantly higher thermal conductivity (approximately 490 W / (m·K)) than Si (approximately 150 W / (m·K)) and InP (approximately 68 W / (m·K)). It can efficiently dissipate the heat generated in the active region 38, which is crucial for high-power operation and maintaining device stability. At the same time, its electrical insulation properties simplify device isolation design.

[0039] When light is incident on a conductor material with a half-bandgap, if the photon energy is higher than the material's bandgap, photogenerated carriers will be excited. Under the influence of an applied electric field, these carriers migrate directionally to form a photocurrent. This photoconductive effect can be used to convert optical signals into electrical signals. In waveguide detectors, light propagates horizontally (waveguide axis), and its absorption length (approximately 10-50 μm) can be significantly greater than the active region thickness (approximately 0.2-0.5 μm). In contrast, in conventional vertically incident detectors, light is incident perpendicularly from the surface, and its quantum efficiency (increasing with increasing absorption layer thickness) and response bandwidth (increasing with decreasing thickness) are limited by the absorption layer thickness.

[0040] Example 5 This embodiment is the fifth embodiment of a silicon-based heterogeneous integrated optoelectronic chip. Similar to embodiments one through four, the difference lies in that this embodiment focuses on the core objective of coupling the optical field from the active device layer to the passive waveguide layer. The coupling mechanism and structural design are systematically described, highlighting that achieving efficient optical coupling remains a key technological challenge for III-V group semiconductor heterogeneous integrated chips. This embodiment provides two methods for coupling the optical field from the active device layer to the passive waveguide layer.

[0041] like Figure 5 As shown, this is the first implementation method provided in this embodiment. Figure 5 In the structure shown, the thickness of the Si passive device layer 2 is as large as possible. Silicon dioxide or air is filled around the silicon waveguide 6 located in the middle of the Si passive device layer 2. The III-V semiconductor active layer 3 is located directly above the middle silicon waveguide 6. By utilizing the high refractive index characteristics of the silicon waveguide 6, the optical mode field is mainly localized within the silicon waveguide 6. Thus, the optical field can be constrained in the passive waveguide without additional coupling structures, thereby realizing the coupling of light from the active device to the passive device.

[0042] like Figure 6 As shown, this is the second implementation method provided in this embodiment, such as... Figure 6 As shown, an adiabatic coupler is provided, whose working principle is based on the principle of adiabatic evolution: during the propagation of the light field, structural parameters (such as waveguide width or refractive index; in this case, width variation is taken as an example) change slowly, keeping the light field mode relatively stable and avoiding rapid changes, thereby achieving efficient energy transfer and mode conversion. Its three-dimensional structure is shown below. Figure 6 As shown in (a), the structure comprises three functional regions: the left region confines the optical field to the III-V active waveguide 7; the right region enables efficient transfer of the optical field to the passive waveguide; and the middle region is an adiabatic coupler that transfers the optical field from the active region to the silicon waveguide 6. In this adiabatic coupler, the width of the III-V waveguide gradually decreases along the optical transmission direction, while the width of the silicon waveguide 6 gradually increases (the silicon waveguide 6 can be designed in a gradually increasing width mode, such as...). Figure 6 As shown in (b) above, or maintain a constant width mode as shown in [example] Figure 6 (as shown in (c)). After a certain length, the optical field will be completely transferred from the III-V waveguide to the silicon waveguide 6.

[0043] Example 6 This embodiment illustrates a method for fabricating a silicon-based heterogeneous integrated optoelectronic chip. The method provided in this embodiment is used to fabricate the silicon-based heterogeneous integrated optoelectronic chips described in Embodiments 1 to 5 above. This embodiment details a direct bonding process based on plasma activation treatment, used to fabricate Si-on-SiC wafers and III-V-on-SiC wafers. Compared to heterogeneous integration technologies such as micro-transfer or flip-chip bonding, the direct bonding process has lower requirements for device alignment accuracy, a simpler operation procedure, and higher process maturity.

[0044] like Figure 7 As shown, the specific preparation process includes the following steps: Step S1. Wafer bonding: Pre-treatment of SiC wafers and SOI wafers, including surface cleaning and plasma activation treatment.

[0045] Step S2. Room temperature bonding: The activated SiC and SOI wafer are aligned and bonded at room temperature to obtain SOI-SiC samples.

[0046] Step S3. Bonding Annealing: The bonded SOI-SiC sample is placed in a bonding device for annealing treatment. The annealing temperature is set at 250~300℃ in a vacuum environment, and mechanical pressure is applied to the SOI-SiC sample.

[0047] Step S4. Remove SOI substrate: Thin the substrate by chemical mechanical polishing, and then remove the substrate silicon and silicon dioxide buried oxide layer by wet or dry etching, retaining the Si passive device layer 2; to obtain Si on SiC wafer.

[0048] Step S5. Spin-coating photoresist: Plasma activation treatment is performed on the Si on SiC wafer to enhance the adhesion of the photoresist, followed by spin-coating of the photoresist.

[0049] Step S6. Waveguide patterning: The designed waveguide device structure is transferred to the Si passive device layer 2 using electron beam lithography, and the waveguide pattern is formed by reactive ion etching.

[0050] Step S7. Bonding III-V semiconductor active layer 3: Perform pretreatment similar to step S1 on the Si on SiC wafer and the III-V epitaxial wafer, and then perform bonding annealing, which is similar to step S3.

[0051] Step S8. Substrate removal: The InP substrate layer is removed by CMP thinning process combined with wet etching, and the III-V semiconductor active layer 3 is retained for active device fabrication; thus, a III-V on Si on SiC wafer is obtained.

[0052] Step S9. Spin-coating photoresist: The III-V on Si on SiC wafer with the substrate removed is subjected to plasma activation treatment, followed by spin-coating photoresist.

[0053] Step S10. Active device patterning: The III-V on Si on SiC wafer with spin-coated photoresist is patterned using electron beam lithography, and the device structure is formed by wet etching of the III-V semiconductor active layer 3.

[0054] S11. Deposition of cladding and windowing: A silicon dioxide cladding is deposited on the surface of a patterned device using plasma-enhanced chemical vapor deposition (PECVD), and windowing is performed in specific areas.

[0055] Step S12. Electroplating metal electrodes: P-type and / or n-type metal contact electrodes 35 are deposited on the device surface through a stripping process, thus completing the device fabrication.

[0056] This invention discloses a method for fabricating a silicon-based heterogeneous integrated optoelectronic chip. The method employs a direct bonding process for heterogeneous integration to fabricate a Si-on-SiC structure. A waveguide patterning process is performed on the Si passive device layer 2. Then, a III-V epitaxial material is bonded to the Si passive device layer 2 again using a direct bonding process. Through these two direct bonding processes, a silicon carbide-on-silicon-on-III-V group (III-V on Si on SiC) structure is formed. Active device design and patterning are performed on the III-V semiconductor active layer 3. The patterned structure design enables the coupling of light from the III-V semiconductor active layer 3 to the Si passive device layer 2, thereby forming an on-chip integrated chip integrating active and passive devices. The method provided by this invention achieves a scalable, highly integrated, low-loss, and high-thermal-conductivity optoelectronic integrated chip, while simplifying the fabrication process and reducing costs.

[0057] Example 7 This embodiment provides a device structure for an integrated chip. The device structure and fabrication method used in this embodiment are similar to those in the previous embodiments. The specific design process in this embodiment includes: firstly, performing spin coating, photolithography, etching, and deposition processes on the III-V on Si on SiC wafer fabricated by direct bonding; then, transferring the designed waveguide structure patterned to the III-V active layer and the six silicon waveguide layers. A specific example is... Figure 8 As shown. The main device structure includes: 1. On-chip integrated laser: Enables light emission; 2. Adiabatic Coupler (AC): Enables optical coupling from the active device layer to the passive waveguide layer; 3. Optical waveguide: used for optical signal transmission; 4.1×2 Multimode Interference Coupler (MMI): Enables beam splitting; 5. Grating Coupler (GC) and End-face Coupler: Enables coupling of output light with external devices; 6. Micro-Ring Modulator (MRM) and Mach-Zehnder Modulator (MZM): These devices convert electrical signals into optical signals. The aforementioned devices together constitute the optical system architecture of this novel on-chip integrated chip.

[0058] As can be seen from this embodiment, the silicon-based heterogeneous integrated optoelectronic chip and its fabrication method provided by the present invention can have their specific structure expanded according to actual needs, while achieving high integration.

[0059] In the specific implementation of the above embodiments, the technical features can be combined in any non-contradictory way. For the sake of brevity, not all possible combinations of the above technical features are described. However, as long as the combination of these technical features is not contradictory, it should be considered to be within the scope of this specification.

[0060] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively describe all embodiments here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A silicon-based heterogeneous integrated optoelectronic chip, characterized in that, From bottom to top, they include: SiC substrate (1); Si passive device layer (2): directly bonded to the SiC substrate (1) using a bonding process; III-V group semiconductor active layer (3): directly bonded to the Si passive device layer (2) using a bonding process.

2. The silicon-based heterogeneous integrated optoelectronic chip according to claim 1, characterized in that, It also includes a thermally insulating coupler disposed on the Si passive device layer (2) and the III-V semiconductor active layer (3) for effectively coupling light from the III-V semiconductor active layer (3) to the Si passive device layer (2).

3. The silicon-based heterogeneous integrated optoelectronic chip according to claim 2, characterized in that, The thermally adiabatic coupler includes a III-V group active waveguide (7) and a silicon waveguide (6) coupled to the III-V group active waveguide (7); the width or refractive index of the III-V group active waveguide (7) gradually decreases along the optical transmission direction; the width or refractive index of the silicon waveguide (6) gradually increases or remains constant along the optical transmission direction.

4. The silicon-based heterogeneous integrated optoelectronic chip according to claim 1, characterized in that, By utilizing the high refractive index characteristics of the silicon waveguide (6) of the Si passive device layer (2), and by placing the III-V semiconductor active layer (3) directly above the silicon waveguide (6), the optical mode field is localized within the silicon waveguide (6), thereby constraining the optical field in the passive waveguide and thus coupling the optical field from the III-V semiconductor active layer (3) to the Si passive device layer (2).

5. The silicon-based heterogeneous integrated optoelectronic chip according to any one of claims 1 to 4, characterized in that, Optoelectronic chips include on-chip lasers, electroabsorption modulators, or photodetectors.

6. The silicon-based heterogeneous integrated optoelectronic chip according to any one of claims 1 to 4, characterized in that, The III-V semiconductor active layer (3) includes, from bottom to top, an n-InP layer (31), a multi-quantum well layer (32), a p-InP layer (33), a p-InGaAs layer (34), and a metal contact electrode (35) located on the Si passive device layer (2).

7. The silicon-based heterogeneous integrated optoelectronic chip according to any one of claims 1 to 4, characterized in that, The III-V group semiconductor active layer (3) includes, from bottom to top, an n-InP layer (31), a multi-quantum well layer (32), a buffer layer (36), a P-type contact layer (37), and a metal contact electrode (35) located on the Si passive device layer (2).

8. The silicon-based heterogeneous integrated optoelectronic chip according to any one of claims 1 to 4, characterized in that, The III-V semiconductor active layer (3) includes, from bottom to top, an n-InP layer (31), a multi-quantum well layer (32), a p-InP layer (33), and a metal contact electrode (35) located on the Si passive device layer (2).

9. A method for fabricating a silicon-based heterogeneous integrated optoelectronic chip according to any one of claims 1 to 8, characterized in that, Includes the following steps: S1. Wafer bonding: Pre-treatment of SiC wafers and SOI wafers, the pre-treatment including surface cleaning and plasma activation treatment; S2. Room temperature bonding: The activated SiC and SOI wafer are aligned and bonded at room temperature to obtain SOI-SiC samples. S3. Bonding Annealing: The bonded SOI-SiC sample is placed in a bonding device for annealing treatment; S4. Removal of SOI substrate: The substrate thickness is reduced by chemical mechanical polishing, followed by etching to remove the substrate silicon and silicon dioxide buried oxide layer, retaining the Si passive device layer (2); to obtain Si on SiC wafer; S5. Spin-coating photoresist: Plasma activation treatment is performed on the Si on SiC wafer, followed by spin-coating photoresist; S6. Waveguide patterning: The designed waveguide device structure is transferred to the Si passive device layer (2) using electron beam lithography, and waveguide pattern is formed by reactive ion etching. S7. Bonding III-V semiconductor active layer (3): Pre-process the Si on SiC wafer and the III-V epitaxial wafer, and then perform bonding annealing; S8. Substrate removal: The InP substrate layer is removed by CMP thinning process combined with wet etching, and the III-V group semiconductor active layer (3) is retained for active device fabrication; III-V on Si on SiC wafer is obtained; S9. Spin-coating photoresist: Plasma activation treatment is performed on the III-V on Si on SiC wafer after the substrate has been removed, followed by spin-coating photoresist; S10. Active device patterning: Electron beam lithography is used to pattern the III-V on Si on SiC wafer with spin-coated photoresist, and the device structure is formed by wet etching of the III-V semiconductor active layer (3). S11. Deposition of cladding and windowing: A silicon dioxide cladding is deposited on the surface of a patterned device using plasma-enhanced chemical vapor deposition (PECVD), and windowing is performed in specific areas. S12. Electroplated metal electrodes: P-type and / or n-type metal contact electrodes (35) are deposited on the device surface through a stripping process to finally complete the device fabrication.

10. The method for fabricating a silicon-based heterogeneous integrated optoelectronic chip according to claim 9, characterized in that, Step S3 includes setting an annealing temperature of 250~300℃ in a vacuum environment and applying mechanical pressure to the SOI-SiC sample.

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