Matrix switch self-test method, matrix switch and automatic test system

Abstract

The present application relates to a matrix switch self-test method, a matrix switch and an automatic test system. There are multiple nodes on the matrix, and the multiple nodes are arranged in an array; the matrix switch self-test method includes: performing a first fault test on a first node and a second node to determine whether the first node and the second node have a fault, and the first node and the second node are nodes of different types; when the first fault test result is that a fault exists, obtaining a test node group from the matrix, the test node group includes a third node and a fourth node, and the nodes in the test node group are different nodes on the same column of the matrix as the first node and the second node; performing a second fault test on the first node and the second node respectively through the test node group to determine the faulty nodes in the first node and the second node. The present application solves the problem in the related art that it is impossible to perform fault tests on nodes of high-density matrix switches.

Description

Technical Field

[0001] The present application relates to the technical field of matrix switches, and in particular to a matrix switch self-test method, a matrix switch and an automatic test system. Background Art

[0002] The switch network is an important part of the automatic test system. It is responsible for controlling the direction of signal flow and is the key to the interface design for realizing automatic testing. Among them, the matrix switch is an important automatic test device for completing signal switching between multiple objects under test and multiple test instruments. With the increase in the number and complexity of the objects under test, the density requirements for the matrix switch are getting higher and higher. At present, in the relevant technology, it is impossible to perform fault testing on the nodes of the high-density matrix switch, resulting in the inability to determine the specific faulty node when a node of the high-density matrix switch fails, so that the faulty node of the high-density matrix switch cannot be repaired in time, affecting the operator's normal work using the high-density matrix switch. Therefore, how to perform fault testing on the nodes of the high-density matrix switch has become an urgent problem to be solved. Summary of the invention

[0003] The present application provides a matrix switch self-test method, a matrix switch and an automatic test system to solve the problem in the related art that it is impossible to perform fault testing on nodes of a high-density matrix switch.

[0004] In a first aspect, the present application provides a matrix switch self-test method, wherein there are multiple nodes on the matrix, and the multiple nodes are arranged in an array; the matrix switch self-test method includes: performing a first fault test on a first node and a second node to determine whether the first node and the second node have faults, and the first node and the second node are nodes of different types; when the first fault test result is that a fault exists, obtaining a test node group from the matrix, the test node group includes a third node and a fourth node, and the nodes in the test node group and the first node and the second node are different nodes on the same column of the matrix; performing a second fault test on the first node and the second node respectively through the test node group to determine the faulty nodes existing in the first node and the second node.

[0005] In a second aspect, the present application provides a matrix switch, which is applied to the matrix switch self-test method described in the first aspect above, and the matrix switch includes: a matrix component, wherein the rows and columns of the matrix component are both greater than or equal to 4; a relay component, wherein the relay component is used to control the closing or opening of the loop where the node is located; an analog-to-digital converter, wherein the analog-to-digital converter is respectively connected to the matrix component and the relay component, and the analog-to-digital converter is used to convert the on-voltage or off-voltage of the test loop into a data quantity, and output the data quantity.

[0006] In a third aspect, the present application provides an automatic testing system, which includes the matrix switch of the second aspect and a controller connected to the matrix switch, and is used to perform a fault test on the matrix switch.

[0007] In a fourth aspect, the present application provides an electronic device, including a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus;

[0008] Memory, used to store computer programs;

[0009] The processor is used to implement the steps of the matrix switch self-test method of any embodiment of the first aspect when executing the program stored in the memory.

[0010] In a fifth aspect, a computer-readable storage medium is provided, in which a computer program is stored. When the computer program is executed by a processor, the steps of the matrix switch self-test method of any embodiment of the first aspect are implemented.

[0011] The above technical solution provided by the embodiment of the present application has the following advantages compared with the prior art:

[0012] In a matrix switch self-checking method provided by an embodiment of the present application, there are a plurality of nodes on the matrix, and the plurality of nodes are arranged in an array; the matrix switch self-checking method comprises: performing a first fault test on a first node and a second node to determine whether the first node and the second node have a fault, the first node and the second node are nodes of different types, so that the first node and the second node of the matrix switch can be subjected to a fault test; when the result of the first fault test is that a fault exists, obtaining a test node group from the matrix, the test node group including a third node and a fourth node, and the nodes in the test node group and the first node and the second node are different nodes on the same column of the matrix; through the test The node group performs a second fault test on the first node and the second node respectively to determine the faulty node existing in the first node and the second node. According to the matrix switch self-test method of the embodiment of the present invention, the first node and the second node are respectively subjected to a second fault test by the test node group on the matrix, so that the faulty node existing in the first node and the second node can be determined, which is convenient for the operator to repair the faulty node in time. Moreover, the present embodiment can perform a fault test on the nodes of the high-density matrix switch without the need for an external test device, which not only solves the problem in the related art that the nodes of the high-density matrix switch cannot be fault tested, but also improves the convenience of performing a fault test on the nodes of the high-density matrix switch. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0014] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0015] Figure 1 A schematic diagram of the structure of an optional 4X4 matrix switch provided according to an embodiment of the present application;

[0016] Figure 2 A schematic structural diagram of a disconnected state of a relay assembly of an optional matrix switch provided according to an embodiment of the present application;

[0017] Figure 3 A schematic structural diagram of a closed state of a relay assembly of an optional matrix switch provided according to an embodiment of the present application;

[0018] Figure 4 A schematic diagram of the structure of an optional mXn matrix switch provided according to an embodiment of the present application;

[0019] Figure 5 A schematic diagram of an optional matrix switch self-test method flow chart provided according to an embodiment of the present application;

[0020] Figure 6 A schematic diagram of another optional matrix switch self-test method flow chart provided according to an embodiment of the present application;

[0021] Figure 7 A schematic diagram of another optional matrix switch self-test method flow chart provided according to an embodiment of the present application;

[0022] Figure 8 A schematic diagram of another optional matrix switch self-test method flow chart provided according to an embodiment of the present application;

[0023] Fig. 9 A schematic diagram of another optional matrix switch self-test method flow chart provided according to an embodiment of the present application;

[0024] Fig.10 A schematic diagram of another optional matrix switch self-test method flow chart provided according to an embodiment of the present application;

[0025] Fig.11A schematic diagram of another optional matrix switch self-test method flow chart provided according to an embodiment of the present application;

[0026] Fig.12 A schematic diagram of another optional matrix switch self-test method flow chart provided according to an embodiment of the present application;

[0027] Fig.13 A schematic diagram of an optional electronic device structure provided in an embodiment of the present application.

[0028] Reference numerals:

[0029] Matrix component 110 , node 111 , relay component 120 , analog-to-digital converter 130 , resistor 140 . DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0031] In order to solve the problem mentioned in the background technology, according to one aspect of an embodiment of the present application, an embodiment of a matrix switch is provided.

[0032] like Figure 1 As shown, it is a schematic diagram of the structure of an optional 4X4 matrix switch provided in an embodiment of the present application. The matrix switch in the embodiment of the present application may include a matrix component 110, a relay component 120, and an analog-to-digital converter 130, and the rows and columns of the matrix are both equal to 4. The matrix may include a plurality of nodes 111, and any two nodes 111 of different types on the same column are used as the first node and the second node to perform a first fault test on them to determine whether the first node and the second node have a fault.

[0033] In the embodiment of the present application, when the first fault test result is that there is a fault, an arbitrary test node group is obtained from the matrix, and the test node group may include a third node and a fourth node, and the third node and the fourth node may be nodes 111 of different types, and the first node and the second node form a first test loop, and the relay component 120 may be a self-test relay, and the relay component 120 is arranged in the first test loop. When the first test loop is turned on, the first node, the second node, and the relay component 120 are all closed; when the first test loop is disconnected, the first node, the second node, the relay, and the first node and the second node may be disconnected.

[0034] It should be noted that the types of nodes 111 include: nodes 111 not connected to the ground wire, and nodes 111 connected to the ground wire. In the above embodiment, the first node and the second node are nodes 111 of different types. When the first node is a node 111 not connected to the ground wire, the second node is a node 111 connected to the ground wire; when the first node is a node 111 connected to the ground wire, the second node is a node 111 not connected to the ground wire. Similarly, the third node and the fourth node are nodes 111 of different types. When the third node is a node 111 not connected to the ground wire, the fourth node is a node 111 connected to the ground wire; when the third node is a node 111 connected to the ground wire, the fourth node is a node 111 not connected to the ground wire.

[0035] like Figure 2 As shown, it is a structural schematic diagram of a closed state of a relay assembly 120 of an optional matrix switch provided according to an embodiment of the present application, such as Figure 3 , which is a schematic diagram of the structure of the disconnected state of the relay assembly 120 of an optional matrix switch provided in an embodiment of the present application. When the relay assembly 120 is closed, the relay assembly 120 is connected to both the first node and the second node, thereby forming a first test loop; when the relay assembly 120 is disconnected, the relay assembly 120 is disconnected from both the first node and the second node, and the first test loop is also disconnected.

[0036] It should be noted that the relay component 120 of the embodiment of the present application can be a self-test relay. When the matrix switch is not self-tested, the relay component 120 is in a suspended state to prevent the relay component 120 from affecting the function of the matrix switch. When the matrix switch needs to be self-tested, that is, the on-off function or on-resistance of the matrix switch is tested, the relay component 120 is connected to the first test circuit to allow the matrix switch to perform self-test.

[0037] In some embodiments of the present invention, the number of rows and columns of the matrix component 110 is greater than or equal to 4, the relay component 120 is used to control the closing or opening of the loop where the node 111 is located, the analog-to-digital converter 130 is connected to the matrix component 110 and the relay component 120 respectively, and the analog-to-digital converter 130 is used to convert the on-voltage or off-voltage of the test loop into data volume and output the data volume. The matrix switch of the embodiment of the present invention can perform fault testing on the node 111 of the matrix without external testing equipment, which solves the problem that the node 111 of the high-density matrix switch cannot be fault tested in the related art.

[0038] like Figure 4As shown, it is a structural schematic diagram of an optional mXn matrix switch provided by an embodiment of the present application. The row m of the matrix switch is greater than or equal to 4, and the column n is greater than or equal to 4. Any two nodes 111 of the matrix switch are connected to the relay component 120 as a group, and any two nodes 111 are used as the first node and the second node. The first node and the second node are different nodes 111 on the same column of the matrix, and the first node and the second node are nodes 111 of different types. When it is necessary to perform a fault test on the first node and the second node, the relay component 120 and the first node and the second node are all closed, a preset voltage is input into the first test loop and the on-voltage in the first test loop is detected, the first node and / or the second node are disconnected to obtain the disconnection voltage of the first test loop, and when the on-voltage is equal to the first preset threshold value and the disconnection voltage is equal to the second preset threshold value, it is determined that there is no fault in the first node and the second node; when the on-voltage is not equal to the first preset threshold value and / or the disconnection voltage is not equal to the second preset threshold value, it is determined that there is a fault in the first node and the second node.

[0039] In some embodiments of the present invention, when the test result of the matrix switch of the above embodiment is that the first node and the second node have a fault, the fault node in the first node and the second node can also be specifically determined. Obtain any test node group from the matrix, the test node group may include a third node and a fourth node, the third node and the fourth node are nodes 111 of different types, and the test node group is a fault-free node. When the first node is tested for a fault, the first node and the fourth node are closed, the first node and the fourth node are nodes 111 of different types, and the relay assembly 120 connected to the first node is closed at the same time, and the relay assembly 120 connected to the fourth node is closed, thereby forming a second test loop, inputting a preset voltage into the second test loop and detecting the conduction voltage in the second test loop, disconnecting the third node and / or the fourth node, and obtaining the disconnection voltage in the second test loop, when the conduction voltage is equal to the first preset threshold value, and the disconnection voltage is equal to the second preset threshold value, it is determined that the first node does not have a fault; when the conduction voltage is not equal to the first preset threshold value and / or the disconnection voltage is not equal to the second preset threshold value, it is determined that the first node has a fault. Similarly, when the second node is subjected to a fault test, the second node and the third node are closed, the second node and the third node are different types of nodes 111, and at the same time, the relay assembly 120 connected to the second node is closed, and the relay assembly 120 connected to the third node is closed, thereby forming a third test loop, inputting a preset voltage into the third test loop and detecting the on-voltage in the third test loop, disconnecting the second node and / or the third node, and obtaining the off-voltage in the third test loop, when the on-voltage is equal to the first preset threshold value and the off-voltage is equal to the second preset threshold value, it is determined that there is no fault at the second node; when the on-voltage is not equal to the first preset threshold value and / or the off-voltage is not equal to the second preset threshold value, it is determined that there is a fault at the second node.

[0040] It should be noted that the types of nodes 111 include: nodes 111 not connected to the ground wire, and nodes 111 connected to the ground wire. In the above embodiment, the first node and the second node are nodes 111 of different types. When the first node is a node 111 not connected to the ground wire, the second node is a node 111 connected to the ground wire; when the first node is a node 111 connected to the ground wire, the second node is a node 111 not connected to the ground wire. Similarly, the third node and the fourth node are nodes 111 of different types. When the third node is a node 111 not connected to the ground wire, the fourth node is a node 111 connected to the ground wire; when the third node is a node 111 connected to the ground wire, the fourth node is a node 111 not connected to the ground wire. The embodiment of the present application does not specifically limit this.

[0041] It should be noted that, when the preset voltage is 3.3V, the first preset threshold is 0V, the second preset threshold is 3.3V, and the preset voltage may be the same as the second preset threshold.

[0042] It should be noted that this embodiment can determine whether there is a fault in the first node and the second node based on the preset voltage and the on-voltage. When the preset voltage and the on-voltage are the same, it can be concluded that there is no fault in the first node and the second node. When the preset voltage and the on-voltage are different, it can be concluded that there is a fault in at least one node 111 of the first node and the second node. The embodiment of the present application does not specifically limit this.

[0043] It is understandable that after the first node and the second node fault test of the matrix switch of the above embodiment is completed, the fault node results existing in the first node and the second node can be output, so that the fault node can be repaired in time to improve the accuracy of the matrix switch. After the first node and the second node are tested, the untested node 111 in the matrix can also be tested for faults until all nodes of the matrix are tested.

[0044] In some embodiments of the present application, the matrix switch may be an 8X256 matrix switch, that is, the matrix has 8 rows and 256 columns. The rows and columns of the matrix switch may be the same or different, and the embodiments of the present application do not specifically limit this.

[0045] In some embodiments of the present invention, the test loop may further include a resistor 140. When a preset voltage is input to the test loop of the matrix, a current will be generated in the test loop, so that the analog-to-digital converter 130 can test the contact resistance between the nodes 111 in the test loop, and judge whether the working performance of the node is normal based on the contact resistance. It is understandable that when the voltage and current between the nodes 111 of the matrix switch exceed a certain threshold, the contact resistance between the nodes 111 will decrease, affecting the closing and opening functions of the nodes 111, so that the working performance of the node can be judged based on the size of the contact resistance between the nodes 111. In some embodiments, the resistor 140 can be selected with a smaller resistance value, for example, 10Ω, so that the analog-to-digital converter 130 can more accurately test the contact resistance between the nodes 111, avoiding the resistor 140 having an excessively large resistance value that affects the calculation of the contact resistance value.

[0046] According to another aspect of the embodiments of the present application, the present application further provides an embodiment of a matrix switch self-test method, which is applied to the matrix switch of the above embodiment to perform a fault test on the node 111 of the matrix switch.

[0047] like Figure 5As shown, it is a schematic flow chart of an optional matrix switch self-test method provided according to an embodiment of the present invention. In the matrix of the matrix switch self-test method of this embodiment, there are multiple nodes 111 on the matrix, and the multiple nodes 111 are arranged in an array. The method may include the following steps:

[0048] Step S210, performing a first fault test on the first node and the second node to determine whether the first node and the second node have faults, the first node and the second node being nodes 111 of different types;

[0049] In the embodiment of the present application, a first fault test is performed on the first node and the second node of the matrix switch. The first fault test is used to determine whether there is a fault in the first node and the second node. The result of the first fault test may be that there is a fault or not.

[0050] It should be noted that the types of nodes 111 include: nodes 111 not connected to the ground wire, and nodes 111 connected to the ground wire. In the above embodiment, the first node and the second node are nodes 111 of different types. When the first node is a node 111 not connected to the ground wire, the second node is a node 111 connected to the ground wire; when the first node is a node 111 connected to the ground wire, the second node is a node 111 not connected to the ground wire. The embodiment of the present application does not specifically limit this.

[0051] Step S220, when the first fault test result is that a fault exists, a test node group is obtained from the matrix, the test node group includes the third node and the fourth node, and the nodes in the test node group and the first node and the second node are different nodes 111 on the same column of the matrix;

[0052] Step S230: Perform a second fault test on the first node and the second node respectively through the test node group to determine the faulty node in the first node and the second node.

[0053] The matrix switch self-test method provided in this example can be applied to the matrix switch of the above embodiment, so as to perform fault testing on the node 111 on the matrix.

[0054] It should be understood that the above-mentioned steps S210, S220 and S230 are all automatically executed steps, and thus when the node 111 of the high-density matrix switch is fault tested, no external testing equipment is required, which not only solves the problem of being unable to perform fault testing on the node 111 of the high-density matrix switch, but also improves the convenience of the fault testing operation.

[0055] It should be noted that the types of nodes 111 include: nodes 111 not connected to the ground wire, and nodes 111 connected to the ground wire. In the above embodiment, the third node and the fourth node are nodes 111 of different types. When the third node is a node 111 not connected to the ground wire, the fourth node is a node 111 connected to the ground wire; when the third node is a node 111 connected to the ground wire, the fourth node is a node 111 not connected to the ground wire. The embodiment of the present application does not specifically limit this.

[0056] In an embodiment of the present invention, there are multiple nodes 111 on the matrix, and the multiple nodes 111 are arranged in an array. The matrix switch self-test method of the embodiment of the present invention includes: performing a first fault test on a first node and a second node to determine whether the first node and the second node have a fault, and the first node and the second node are different types of nodes 111, so that the first node and the second node of the matrix switch can be fault tested. When the result of the first fault test is that there is a fault, a test node group is obtained from the matrix, and the test node group includes a third node and a fourth node, and the nodes 111 in the test node group and the first node and the second node are different nodes 111 on the same column of the matrix. The second fault test is performed on the first node and the second node respectively through the test node group to determine the faulty node in the first node and the second node. According to the matrix switch self-test method of the embodiment of the present invention, the second fault test is performed on the first node and the second node respectively through the test node group on the matrix, so that the faulty node in the first node and the second node can be determined, which is convenient for the operator to repair the faulty node in time. Moreover, the present embodiment can perform a fault test on the node 111 of the high-density matrix switch without an external test device, which not only solves the problem that the node 111 of the high-density matrix switch cannot be fault tested in the related art, but also improves the convenience of performing a fault test on the node 111 of the high-density matrix switch.

[0057] like Figure 6 As shown, specifically, in the above step S210, the first fault test is performed on the first node and the second node to determine whether there is a fault in the first node and the second node, which can be implemented by the following steps S310, step S320, step S330, step S340, step S350 and step S360:

[0058] Step S310, conducting a first test loop formed by a first node and a second node;

[0059] In the embodiment of the present invention, Figure 1 As shown, the first node and the second node are both closed, and the relay assembly 120 connected to the first node and the second node is also closed, so that the first test loop formed by the first node and the second node is turned on.

[0060] Step S320, inputting a preset voltage into the first test loop, and obtaining the voltage in the first test loop as a conduction voltage;

[0061] Step S330, judging whether there is a fault at the first node and the second node according to the conduction voltage;

[0062] Step S340, and / or, disconnecting a first test loop formed by the first node and the second node;

[0063] Step S350, inputting a preset voltage into the first test loop, and obtaining the voltage in the first test loop as a disconnection voltage;

[0064] In the embodiment of the present application, the disconnection voltage in the first test loop can be the voltage in the first test loop obtained by disconnecting the first node, disconnecting the second node, or disconnecting both the first node and the second node. It should be noted that when the fault node existing in the first node and the second node is uncertain, that is, when the disconnection functions of the first node and the second node need to be tested for faults, the voltage of the first test loop obtained by disconnecting both the first node and the second node should be used as the disconnection voltage.

[0065] Step S360: Determine whether there is a fault at the first node and the second node according to the disconnection voltage.

[0066] In some embodiments of the present invention, whether there is a fault in the first node and the second node can be judged based on the on-voltage or the off-voltage, or can be judged based on both the on-voltage and the off-voltage.

[0067] Specifically, in an embodiment of the present application, a first fault test is performed on the first node and the second node to determine whether there is a fault in the first node and the second node. The test can be as follows: a first test loop formed by the first node and the second node is turned on, a preset voltage is input into the first test loop, and the voltage in the first test loop is obtained as a turn-on voltage. Based on the turn-on voltage, it is determined whether there is a fault in the first node and the second node.

[0068] In some embodiments of the present application, a first fault test is performed on the first node and the second node to determine whether there is a fault in the first node and the second node. Alternatively, a first test loop formed by the first node and the second node is disconnected, a preset voltage is input to the first test loop, and the voltage in the first test loop is obtained as a disconnection voltage, and based on the disconnection voltage, it is determined whether there is a fault in the first node and the second node.

[0069] In some embodiments of the present application, a first fault test is performed on the first node and the second node to determine whether there are faults in the first node and the second node. It can also be as follows: a first test loop formed by the first node and the second node is turned on, a preset voltage is input into the first test loop, and the voltage in the first test loop is obtained as a turn-on voltage, and then the first test loop formed by the first node and the second node is disconnected, and the voltage in the first test loop is obtained as a turn-off voltage, and based on the turn-on voltage and the turn-off voltage, it is determined whether there are faults in the first node and the second node.

[0070] It should be noted that this embodiment can determine whether there is a fault in the first node and the second node based on the preset voltage and the on-voltage. When the preset voltage and the on-voltage are the same, it can be concluded that there is no fault in the first node and the second node. When the preset voltage and the on-voltage are different, it can be concluded that there is a fault in at least one node 111 of the first node and the second node. The embodiment of the present application does not specifically limit this.

[0071] like Figure 7 As shown, specifically, in the above step S330, judging whether the first node and the second node have faults according to the on-voltage, and in step S360, judging whether the first node and the second node have faults according to the off-voltage, can be implemented by step S410:

[0072] Step S410, when the on-voltage is equal to the first preset threshold and the off-voltage is equal to the second preset threshold, it is determined that there is no fault in the first node and the second node, and the first fault test result is obtained that there is no fault.

[0073] In some embodiments of the present invention, when the on-voltage is equal to the first preset threshold value, and the off-voltage is equal to the second preset threshold value, it can be determined that there is no fault in the first node and the second node, so that the first fault test result is that there is no fault. It should be noted that when the preset voltage is 3.3V, the first preset threshold value is 0V, the second preset threshold value is 3.3V, the preset voltage and the second preset threshold value can be the same, when a 3.3V voltage is input into the first test loop formed by the first node and the second node, the on-voltage obtained is 0V, and the off-voltage obtained after disconnecting the first node and the second node is 3V, it can be determined that there is no fault in both the first node and the second node, so that the first fault test result is that there is no fault.

[0074] like Figure 8 As shown, specifically, in the above step S330, judging whether the first node and the second node have faults according to the on-voltage, and in step S360, judging whether the first node and the second node have faults according to the off-voltage, can be implemented by step S510:

[0075] Step S510, when the on-voltage is not equal to the first preset threshold and / or the off-voltage is not equal to the second preset threshold, it is determined that at least one node 111 of the first node and the second node has a fault, and a first fault test result is obtained that a fault exists.

[0076] In some embodiments of the present invention, when the on-voltage is not equal to the first preset threshold or the off-voltage is not equal to the second preset threshold, the first fault test result can be determined to be a fault. When the on-voltage is not equal to the first preset threshold and the off-voltage is not equal to the second preset threshold, the first fault test result can also be determined to be a fault. When the first fault test result is a fault, it can be obtained that at least one of the first node and the second node 111 has a fault, that is, the first node has a fault or the second node has a fault or the first node and the second node have a fault at the same time. It should be noted that when the preset voltage is 3.3V, the first preset threshold is 0V, and the second preset threshold is 3.3V, the on-voltage is not equal to 0V and / or the off-voltage is not equal to 3.3V, it is determined that at least one of the first node and the second node 111 has a fault, and the first fault test result is obtained to be a fault.

[0077] like Fig. 9 As shown, specifically, in the above step S230, the second fault test is performed on the first node and the second node respectively through the test node group to determine the faulty node in the first node and the second node, which can be implemented by the following steps S610, step S620, step S630 and step S640:

[0078] Step S610, conducting a second test loop formed by the first node and the fourth node, inputting a preset voltage into the second test loop, obtaining the voltage of the second test loop as the conduction voltage of the second test loop, and the first node and the fourth node are nodes 111 of different types, and the fourth node is a non-faulty node;

[0079] Step S620, conducting a third test loop formed by the second node and the third node, inputting a preset voltage into the third test loop, obtaining a voltage of the third test loop as a conduction voltage of the third test loop, and the second node and the third node are nodes 111 of different types, and the third node is a non-faulty node;

[0080] Step S630, when the conduction voltage of the second test loop is not equal to the first preset threshold, it is determined that there is a fault in the first node;

[0081] Step S640: When the on-voltage of the third test loop is not equal to the first preset threshold, it is determined that a fault exists at the second node.

[0082] In some embodiments of the present invention, the second fault test can be performed on the first node and the second node respectively through the test node group, so that the faulty node in the first node and the second node can be determined. Specifically, when judging whether the first node has a fault, the second test loop formed by the first node and the fourth node is turned on, and a preset voltage is input into the second test loop, and the voltage of the second test loop is obtained as the on-voltage of the second test loop. It should be noted that the first node and the fourth node are different nodes 111 on the same column of the matrix, and are different types of nodes 111, and the fourth node is a non-faulty node.

[0083] It should be noted that the types of nodes 111 include: nodes 111 not connected to the ground wire, and nodes 111 connected to the ground wire. In the above embodiment, the first node and the fourth node are nodes 111 of different types. When the first node is a node 111 not connected to the ground wire, the fourth node is a node 111 connected to the ground wire; when the first node is a node 111 connected to the ground wire, the fourth node is a node 111 not connected to the ground wire. The embodiment of the present application does not specifically limit this.

[0084] It should be noted that the acquisition of the fourth node may include arbitrarily selecting two nodes 111 of different types in the same column of the matrix to perform a first fault test. If the result of the first fault test is that there is no fault, the two nodes 111 can be used as a test node group, and one of the nodes 111 that is a different type from the first node can be used as the fourth node. In addition, it can also be obtained based on the comparison of different nodes 111. For example, when two nodes 111 of different types in the same column of the matrix are arbitrarily selected as the first node and the second node and the result of the first fault test is that there is no fault, arbitrarily select a node 111 of a different type from the first node from the matrix and perform the first fault test with the first node. If the result of the first fault test is also that there is no fault, then the arbitrarily selected node 111 is a fault-free node, thereby obtaining the fault-free node required in this embodiment as the fourth node.

[0085] In the embodiment of the present application, similarly, when determining whether the second node has a fault, the third test loop formed by the second node and the third node is turned on, and a preset voltage is input into the third test loop to obtain the voltage of the third test loop as the on-voltage of the third test loop. It should be noted that the second node and the third node are different nodes 111 on the same column of the matrix and are different types of nodes 111, and the third node is a fault-free node.

[0086] It should be noted that the types of nodes 111 include: nodes 111 not connected to the ground wire, and nodes 111 connected to the ground wire. In the above embodiment, the second node and the third node are nodes 111 of different types. When the second node is a node 111 not connected to the ground wire, the third node is a node 111 connected to the ground wire; when the second node is a node 111 connected to the ground wire, the third node is a node 111 not connected to the ground wire. The embodiment of the present application does not specifically limit this.

[0087] It should be noted that the acquisition of the third node may include arbitrarily selecting two nodes 111 of different types in the same column of the matrix to perform a first fault test. If the result of the first fault test is that there is no fault, the two nodes 111 can be used as a test node group, and one of the nodes 111 that is a different type from the second node can be used as the third node. In addition, it can also be obtained based on the comparison of different nodes 111. For example, when two nodes 111 of different types in the same column of the matrix are arbitrarily selected as the first node and the second node and the result of the first fault test is that there is no fault, arbitrarily select a node 111 of a different type from the second node from the matrix and perform a fault test with the second node. If the result of the first fault test is also that there is no fault, then the arbitrarily selected node 111 is a fault-free node, thereby obtaining the fault-free node required in this embodiment as the third node.

[0088] like Fig.10 As shown, specifically, in the above step S230, the second fault test is performed on the first node and the second node respectively through the test node group to determine the faulty node in the first node and the second node, which can also be implemented through the following steps S710, S720, S730 and S740:

[0089] Step S710, disconnecting the second test loop formed by the first node and the fourth node, inputting a preset voltage into the second test loop, obtaining the voltage of the second test loop as the disconnection voltage of the second test loop, and the first node and the fourth node are nodes 111 of different types, and the fourth node is a non-faulty node;

[0090] Step S720, disconnecting the third test loop formed by the second node and the third node, inputting a preset voltage into the third test loop, obtaining the voltage of the third test loop as the disconnection voltage of the third test loop, and the second node and the third node are different types of nodes 111, and the third node is a non-faulty node;

[0091] Step S730, when the disconnection voltage of the second test loop is not equal to the second preset threshold, it is determined that there is a fault in the first node;

[0092] Step S740: When the disconnection voltage of the third test loop is not equal to the second preset threshold, it is determined that a fault exists in the second node.

[0093] In some embodiments of the present invention, the faulty node in the first node and the second node can also be determined by the disconnection voltage of the second test loop and the third test loop. Specifically, the second test loop formed by the first node and the fourth node is disconnected, and a preset voltage is input into the second test loop, and the voltage of the second test loop is obtained as the disconnection voltage of the second test loop, and the first node and the fourth node are nodes 111 of different types, and the fourth node is a non-faulty node. When the disconnection voltage of the second test loop is not equal to the second preset threshold, it is determined that the first node has a fault; similarly, the third test loop formed by the second node and the third node is disconnected, and a preset voltage is input into the third test loop, and the voltage of the third test loop is obtained as the disconnection voltage of the third test loop, and the second node and the third node are nodes 111 of different types, and the third node is a non-faulty node. When the disconnection voltage of the third test loop is not equal to the second preset threshold, it is determined that the second node has a fault.

[0094] like Fig.11 As shown, the matrix switch self-checking method, after performing a second fault test on the first node and the second node respectively through the test node group to determine the faulty node in the first node and the second node, can also include the following step S810:

[0095] Step S810: When determining whether a faulty node exists in the first node or the second node, output the faulty node result in the first node or the second node.

[0096] In some embodiments of the present invention, after performing a second fault test on the first node and the second node respectively through the test node group to determine the faulty nodes existing in the first node and the second node, the faulty node results existing in the first node and the second node obtained in the second fault test can also be output, so that the faulty nodes existing in the matrix switch can be repaired in time, and the accuracy of the closing and opening functions of the matrix switch node 111 is improved, so as to avoid the abnormal closing and opening functions of the matrix switch node 111 affecting the normal use of the matrix switch.

[0097] like Fig.12 As shown, in the above step S230, after the second fault test is performed on the first node and the second node respectively by the test node group to determine the faulty node in the first node and the second node, the matrix switch self-test method may further include step S910:

[0098] Step S910 , reselecting two untested nodes 111 from the matrix as the first node and the second node for testing, until all nodes 111 of the matrix are tested.

[0099] In some embodiments of the present invention, after performing a second fault test on the first node and the second node respectively through the test node group to determine the faulty node in the first node and the second node, two untested nodes 111 in the matrix can be reselected as the first node and the second node for testing until all nodes 111 of the matrix are tested. Therefore, according to the matrix switch self-test method of the embodiment of the present application, all nodes 111 of the matrix switch can be tested, so that the accuracy of the matrix switch is further improved.

[0100] It should be noted that the number of nodes 111 of the high-density matrix switch is large, and it is impossible to use external testing equipment to perform fault testing on all nodes 111 of the high-density matrix switch. However, the matrix switch self-test method of the embodiment of the present application can perform fault testing on all nodes 111 of the high-density matrix switch, which not only solves the problem that the nodes 111 of the high-density matrix switch cannot be fault tested in the related art, but also the embodiment of the present application can perform fault testing on the nodes 111 of the high-density matrix switch without external testing equipment, thereby improving the convenience of fault testing the nodes 111 of the high-density matrix switch.

[0101] According to another aspect of the embodiment of the present application, the embodiment of the present application also provides an automatic testing system, which includes the matrix switch of any of the above embodiments, and a controller connected to the matrix switch, and the controller is used to perform fault testing on the matrix switch 111.

[0102] According to another aspect of the embodiment of the present application, the embodiment of the present application further provides an electronic device, such as Fig.13 As shown, it includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus. The electronic device includes but is not limited to:

[0103] Memory, used to store computer programs;

[0104] The processor is used to execute the program stored in the memory. When the processor executes the computer program stored in the memory, the processor is used to execute the above-mentioned matrix switch self-test method.

[0105] The memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer executable programs, such as the matrix switch self-test method described in the embodiment of the present application. The processor implements the above-mentioned matrix switch self-test method by running the non-transitory software program and instructions stored in the memory.

[0106] The memory may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function; the data storage area may store and execute the above-mentioned matrix switch self-test method. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0107] The non-transient software program and instructions required to implement the above-mentioned matrix switch self-test method are stored in the memory, and when executed by one or more processors, the above-mentioned matrix switch self-test method is executed, for example, Figure 5 The method steps S210 to S230 described in Figure 6 The method steps S310 to S360 described in Figure 7 The method steps S310 to S340 and S410 described in Figure 8 The method steps S310 to S340 and S510 described in Fig. 9 Steps S210, S220 and S610 to S640 of the method described in Fig.10 Steps S210, S220 and S710 to S740 of the method described in Fig.11 The method described in steps S210 to S230 and step S810, Fig.12 The method steps S210 to S230 and step S910 described in .

[0108] The memory and processor in the above electronic device communicate through the communication bus and the communication interface. The communication bus can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. The communication bus can be divided into an address bus, a data bus, a control bus, etc.

[0109] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0110] The embodiment of the present invention further provides a storage medium storing computer executable instructions, wherein the computer executable instructions are used to execute the above matrix switch self-test method.

[0111] In one embodiment, the storage medium stores computer executable instructions, which are executed by one or more control processors, for example, by a processor in the above electronic device, so that the one or more processors can execute the above matrix switch self-test method, for example, execute Figure 5 The method steps S210 to S230 described in Figure 6 The method steps S310 to S360 described in Figure 7 The method steps S310 to S340 and S410 described in Figure 8 The method steps S310 to S340 and S510 described in Fig. 9 Steps S210, S220 and S610 to S640 of the method described in Fig.10 Steps S210, S220 and S710 to S740 of the method described in Fig.11 The method described in steps S210 to S230 and step S810, Fig.12 The method steps S210 to S230 and step S910 described in .

[0112] The above described embodiments are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0113] It is to be understood that the embodiments described herein may be implemented with hardware, software, firmware, middleware, microcode or a combination thereof. For hardware implementation, the processing unit may be implemented in one or more application specific integrated circuits (ASIC), digital signal processors (DSP), digital signal processing devices (DSPD), programmable logic devices (PLD), field programmable gate arrays (FPGA), general purpose processors, controllers, microcontrollers, microprocessors, other electronic units for performing the functions described in the present application or a combination thereof.

[0114] For software implementation, the technology described herein can be implemented by a unit that performs the functions described herein. The software code can be stored in a memory and executed by a processor. The memory can be implemented in the processor or outside the processor.

[0115] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0116] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0117] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0118] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0119] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0120] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a ROM, a RAM, a magnetic disk, or an optical disk.

[0121] It should be noted that, in this article, relational terms such as "first", "second", "third", "fourth", etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0122] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A matrix switch self-test method, characterized in that: There are multiple nodes on the matrix, and the multiple nodes are arranged in an array; The matrix switch self-test method comprises: Performing a first fault test on a first node and a second node to determine whether the first node and the second node have faults, the first node and the second node being nodes of different types; When the first fault test result is that a fault exists, a test node group is obtained from the matrix, the test node group includes a third node and a fourth node, and the nodes in the test node group and the first node and the second node are different nodes on the same column of the matrix; A second fault test is performed on the first node and the second node respectively through the test node group to determine the faulty node in the first node and the second node, including: turning on the second test loop formed by the first node and the fourth node, and inputting a preset voltage into the second test loop, obtaining the voltage of the second test loop as the turn-on voltage of the second test loop, and the first node and the fourth node are nodes of different types, and the fourth node is a fault-free node; turning on the third test loop formed by the second node and the third node, and inputting a preset voltage into the third test loop, obtaining the voltage of the third test loop as the turn-on voltage of the third test loop, and the second node and the third node are nodes of different types, and the third node is a fault-free node; when the turn-on voltage of the second test loop is not equal to the first preset threshold value, it is determined that the first node has a fault; when the turn-on voltage of the third test loop is not equal to the first preset threshold value, it is determined that the second node has a fault.

2. The matrix switch self-test method according to claim 1, characterized in that: The performing a first fault test on the first node and the second node to determine whether the first node and the second node have faults includes: Turning on a first test loop formed by the first node and the second node; Inputting a preset voltage into the first test loop, and obtaining a voltage in the first test loop as a conduction voltage; determining, according to the conduction voltage, whether the first node and the second node are faulty; and / or; disconnecting the first test loop formed by the first node and the second node; Inputting a preset voltage into the first test circuit, and obtaining the voltage in the first test circuit as a disconnection voltage; It is determined whether the first node and the second node are faulty according to the disconnection voltage.

3. The matrix switch self-test method according to claim 2, characterized in that: The determining, according to the on-voltage or the off-voltage, whether the first node and the second node are faulty includes: When the on-voltage is equal to a first preset threshold value, and the off-voltage is equal to a second preset threshold value, it is determined that there is no fault in the first node and the second node, and the first fault test result is that there is no fault.

4. The matrix switch self-test method according to claim 2, characterized in that: The determining, according to the on-voltage or the off-voltage, whether the first node and the second node are faulty includes: When the on-voltage is not equal to the first preset threshold and / or the off-voltage is not equal to the second preset threshold, it is determined that at least one of the first node and the second node has a fault, and the first fault test result is that a fault exists.

5. The matrix switch self-test method according to claim 1, characterized in that: The performing a second fault test on the first node and the second node respectively through the test node group to determine a faulty node in the first node and the second node further comprises: Disconnecting a second test loop formed by the first node and the fourth node, inputting a preset voltage into the second test loop, obtaining a voltage of the second test loop as a disconnection voltage of the second test loop, wherein the first node and the fourth node are nodes of different types, and the fourth node is a non-faulty node; Disconnecting a third test loop formed by the second node and the third node, inputting the preset voltage into the third test loop, obtaining a voltage of the third test loop as a disconnection voltage of the third test loop, wherein the second node and the third node are nodes of different types, and the third node is a non-faulty node; When the disconnection voltage of the second test loop is not equal to a second preset threshold, determining that the first node has a fault; When the disconnection voltage of the third test loop is not equal to the second preset threshold, it is determined that the second node has a fault.

6. The matrix switch self-test method according to claim 5, characterized in that: The matrix switch self-test method further comprises: When a faulty node among the first node and the second node is determined, the faulty node result among the first node and the second node is output.

7. The matrix switch self-test method according to claim 1, characterized in that: After performing a second fault test on the first node and the second node respectively through the test node group to determine a faulty node in the first node and the second node, the matrix switch self-checking method further includes: Two untested nodes are reselected from the matrix as the first node and the second node for testing until all nodes of the matrix are tested.

8. A matrix switch, characterized in that: The matrix switch self-check method according to any one of claims 1 to 7, wherein the matrix switch comprises: A matrix component, wherein both the number of rows and the number of columns of the matrix component are ≥ 4; A relay component, the relay component is used to control the closing or opening of the loop where the node is located; An analog-to-digital converter, the analog-to-digital converter is connected to the matrix component and the relay component respectively, and the analog-to-digital converter is used to convert the on-voltage or off-voltage of the test loop into a data quantity and output the data quantity.

9. An automatic testing system, comprising the matrix switch according to claim 8, and a controller, wherein the controller is connected to the matrix switch and is used to perform a fault test on the matrix switch.

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