Array substrate, manufacturing method and display device

Abstract

The embodiment of the present application provides an array substrate, a manufacturing method and a display device, wherein the array substrate includes a first region and a second region adjacent to each other, wherein a first low-temperature polysilicon layer, an intermediate film layer and a second low-temperature polysilicon layer are stacked along a first direction in the first region; a support column is provided between the first low-temperature polysilicon layer and the base substrate in the second region, the portion of the first low-temperature polysilicon layer lifted by the support column includes a first connection portion, and the second low-temperature polysilicon layer includes a second connection portion located in the second region and connected to the first connection portion; the extension distance of the second connection portion along the first direction is less than the spacing between the first low-temperature polysilicon layer and the second low-temperature polysilicon layer in the first region. With such a design, the depth of the via hole can be reduced or even directly connected after the via hole is omitted, so that the second low-temperature polysilicon layer absorbs more laser energy during the laser irradiation of the ELA device during the manufacturing process, thereby improving the crystallization quality; and after being conductively converted, the resistance is guaranteed to be normal, thereby improving the product yield.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of display devices, and in particular, to an array substrate, a manufacturing method and a display device. Background Art

[0002] In an array substrate using low temperature polysilicon (LTPS), there may be two thin film transistors (TFT) stacked up and down. The two stacked TFTs can be overlapped by vias in the low temperature polysilicon layers of the two TFTs, and then the low temperature polysilicon at the overlap is conductively connected to realize the connection of the drain terminals.

[0003] However, low-temperature polysilicon is formed by laser irradiation of amorphous silicon (a-Si) using an excimer laser annealing (ELA) device. During the production process, the amorphous silicon at the overlapping via position cannot absorb enough laser energy to achieve effective crystallization, affecting the product yield. Summary of the invention

[0004] In view of this, an object of the embodiments of the present application is to provide an array substrate, a manufacturing method and a display device.

[0005] In a first aspect, an embodiment of the present application provides an array substrate.

[0006] It includes a base substrate, and a first low-temperature polysilicon layer, an intermediate film layer, and a second low-temperature polysilicon layer arranged on one side of the base substrate;

[0007] The array substrate comprises a first region and a second region adjacent to each other, wherein in the first region, the first low-temperature polysilicon layer, the intermediate film layer and the second low-temperature polysilicon layer are stacked along a first direction perpendicular to the base substrate;

[0008] In the second region, a support column is provided between the first low-temperature polysilicon layer and the base substrate, and the support column makes the first low-temperature polysilicon layer protrude along the first direction; the portion of the first low-temperature polysilicon layer lifted by the support column includes a first connecting portion, and the second low-temperature polysilicon layer includes a second connecting portion located in the second region, and the second connecting portion is connected to the first connecting portion;

[0009] The extension distance of the second connection portion along the first direction is less than the spacing between the first low-temperature polysilicon layer and the second low-temperature polysilicon layer in the first region. With such a design, when the first low-temperature polysilicon layer and the second low-temperature polysilicon layer are connected at the position where the support column is lifted, the depth of the via hole can be reduced, and even the via hole can be omitted and the two layers can be directly connected. Thus, during the manufacturing process of the second low-temperature polysilicon layer, the portion where the second low-temperature polysilicon layer is connected to the first low-temperature polysilicon layer can absorb more laser energy when the ELA device is performing laser irradiation, thereby improving the crystallization quality; after being conductive, the resistance is guaranteed to be normal, thereby improving the product yield.

[0010] In a possible implementation, the support column includes a support top away from the substrate along the first direction and a peripheral wall connected to an edge of the support top, the peripheral wall extends around the first direction and is inclined relative to the substrate.

[0011] In a possible implementation manner, the second region includes a third region opposite to the support top, and an orthographic projection of the third region on the base substrate coincides with an orthographic projection of the support top on the base substrate;

[0012] A portion of the first low-temperature polysilicon layer located in the third region is the first connecting portion, and a portion of the second low-temperature polysilicon layer located in the third region is the second connecting portion.

[0013] In a possible implementation, the intermediate film layer is provided with an exposure opening in the third region, and in the first direction, the first connection portion is flush with the exposure opening or extends from the exposure opening to a side away from the base substrate; the second connection portion is in contact and connected with the first connection portion.

[0014] In a possible implementation manner, the intermediate film layer is provided with a connection via having a depth in the third region, the first connection portion is located at the bottom of the connection via, and the second connection portion is connected to the first connection portion through the connection via.

[0015] In a possible implementation manner, the second low-temperature polysilicon layer includes the second connecting portion, a third connecting portion and an intermediate connecting portion, the third connecting portion is located in the first region, and the intermediate connecting portion connects the second connecting portion and the third connecting portion;

[0016] The intermediate connection portion includes at least two sub-connection portions, and in the process of the third connection portion extending toward the second connection portion, the inclination angles of the sub-connection portions relative to the base substrate gradually decrease.

[0017] In a possible implementation, the support column is formed by patterning an inorganic insulating material, and the inorganic insulating material includes at least one of silicon oxide, silicon nitride and silicon oxynitride.

[0018] In a possible implementation, in the cross-sectional diagram corresponding to the first cross-section, the angle of the peripheral wall relative to the second direction is 20 to 50 degrees, and the distance of the support top along the second direction is greater than 1 um;

[0019] The first cross section is parallel to the first direction, and the second direction is perpendicular to the first direction.

[0020] In a possible implementation, the support column is made of silicon nitride, and a first barrier layer containing silicon oxide is further provided on the first low-temperature polysilicon layer facing the substrate, and the first barrier layer extends along the peripheral wall and the support top.

[0021] In a possible implementation manner, the array substrate includes a first thin film transistor and a second thin film transistor stacked along the first direction, and the second thin film transistor is farther away from the base substrate than the first thin film transistor;

[0022] The first thin film transistor includes a first active layer, a first gate, a first source and a first drain, and the second thin film transistor includes a second active layer, a second gate, a second source and a second drain; the first low-temperature polysilicon layer includes the first active layer, and the second low-temperature polysilicon layer includes the second active layer;

[0023] The first drain electrode and the second drain electrode are connected by connecting the first connecting portion and the second connecting portion.

[0024] In a possible implementation, the first low-temperature polysilicon layer and the second low-temperature polysilicon layer have different spacings in the first region; and an extension distance of the second connecting portion along the first direction is smaller than a minimum spacing between the first low-temperature polysilicon layer and the second low-temperature polysilicon layer in the first region.

[0025] In a possible implementation, the first active layer includes a first channel region, the array substrate includes a fourth region opposite to the first channel region, and an orthographic projection of the fourth region on the base substrate coincides with an orthographic projection of the first channel on the base substrate;

[0026] The first region includes the fourth region and a fifth region located between the fourth region and the first region; the distance between the first low-temperature polysilicon layer and the second low-temperature polysilicon layer in the fourth region is greater than the distance between the first low-temperature polysilicon layer and the second low-temperature polysilicon layer in the fifth region;

[0027] An extension distance of the second connection portion along the first direction is smaller than a distance between the first low-temperature polysilicon layer and the second low-temperature polysilicon layer in the fifth region.

[0028] In a possible implementation manner, the intermediate film layer includes a first gate insulating layer, a second gate insulating layer, and a second barrier layer, and the first gate insulating layer, the second gate insulating layer, and the second barrier layer are stacked along the first direction. In a second aspect, an embodiment of the present application provides a method for manufacturing an array substrate, which is used to manufacture the array substrate described in any one of the embodiments of the first aspect, and the manufacturing method includes:

[0029] providing a substrate base plate;

[0030] Making a support column on one side of the substrate base plate;

[0031] manufacturing a first low-temperature polysilicon layer and an intermediate film layer;

[0032] Performing patterning on the portion of the intermediate film layer supported by the support pillars, and exposing the first low-temperature polysilicon layer;

[0033] Depositing an amorphous silicon film layer, wherein the amorphous silicon film layer is connected to the exposed first low-temperature polysilicon layer;

[0034] crystallizing the amorphous silicon film layer to form a second low-temperature polysilicon layer;

[0035] A second connection portion in the second low temperature polysilicon layer connected to the first low temperature polysilicon layer is conductively connected.

[0036] In a possible implementation manner, the step of manufacturing a support column on one side of the substrate includes:

[0037] Silicon nitride film deposited at high temperature.

[0038] performing patterning on the silicon nitride film to form a support column;

[0039] Among them, the temperature range of high temperature deposition is 350 to 430 degrees Celsius.

[0040] In a third aspect, an embodiment of the present application provides a display device, comprising an array substrate as described in any one of the embodiments of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, the drawings described below are only one or more embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0042] Figure 1 A structural schematic diagram of an array substrate provided for related technology;

[0043] Figure 2 A schematic diagram of the structure of an array substrate provided in an embodiment of the present application;

[0044] Figure 3 A schematic diagram of the structure of another array substrate provided in an embodiment of the present application;

[0045] Figure 4 A schematic diagram of the structure of another array substrate provided in an embodiment of the present application;

[0046] Figure 5 for Figure 4 A partial enlarged view of the middle E area;

[0047] Figure 6 A schematic diagram of the structure of another array substrate provided in an embodiment of the present application.

[0048] Description of reference numerals:

[0049] 100 - a first thin film transistor, 200 - a second thin film transistor;

[0050] 1-substrate substrate, 2-first low-temperature polysilicon layer, 21-first channel region, 22-first connecting portion, 3-first interlayer insulating layer, 4-second barrier layer, 5-second gate insulating layer, 6-second interlayer insulating layer, 7-outer film layer, 8-second low-temperature polysilicon layer, 81-second channel region, 82-second connecting portion, 9-second gate layer, 10-second metal layer, 11-first metal layer, 12-first gate insulating layer, 13-first gate layer, 14-first barrier layer, 15-support column;

[0051] X: first direction, A: first area, B: second area, C: third area. DETAILED DESCRIPTION

[0052] Figure 1 A schematic diagram of the structure of an array substrate provided for related technology, such as Figure 1 As shown, the array substrate includes a base substrate 1, on which a first thin film transistor 100 and a second thin film transistor 200 are arranged. A direction away from the base substrate 1 and perpendicular to the base substrate 1 is defined as a first direction X, and the first thin film transistor 100 and the second thin film transistor 200 are stacked in the first direction, and the second thin film transistor 200 is away from the base substrate 1 relative to the first thin film transistor 100.

[0053] The first thin film transistor 100 includes a first active layer, a first gate electrode G1 , a first source electrode S1 , and a first drain electrode D1 , and the second thin film transistor 200 includes a second active layer, a second gate electrode G2 , a second source electrode S2 , and a second drain electrode D2 .

[0054] exist Figure 1 In the array substrate shown, on one side of the base substrate 1, a first barrier layer 14, a first low-temperature polysilicon layer 2, a first gate insulation layer 12, a first gate layer 13, a first interlayer insulation layer 3, a first metal layer 11, a second barrier layer 4, a second low-temperature polysilicon layer 8, a second gate insulation layer 5, a second gate layer 9, a second interlayer insulation layer 6, a second metal layer 10 and an outer film layer 7 are stacked along a first direction; it should be noted that the outer film layer 7 can be a flat layer, a barrier layer, etc. according to the structural setting of the second thin film transistor 200 away from the base substrate 1.

[0055] The first low-temperature polysilicon layer 2 includes a first active layer, the first gate layer 13 includes a first gate G1, the first active layer includes a first channel region 21 corresponding to the first gate G1, and conductive regions located on both sides of the first channel region 21. The first metal layer 11 includes a first source electrode S1, and the first source electrode S1 is connected to the first active layer through via holes in the first gate insulating layer 12 and the first interlayer insulating layer 3. The first drain electrode D1 is formed by doping and conductively conductive the first active layer.

[0056] The second low-temperature polysilicon layer 8 includes a second active layer, the second gate layer 9 includes a second gate G2, the second active layer includes a second channel region 81 corresponding to the second gate G2, and conductor regions located on both sides of the second channel region 81. The second metal layer 10 includes a second source electrode S2, and the second source electrode S2 is connected to the second active layer through via holes in the second gate insulating layer 5 and the second interlayer insulating layer 6. The second drain electrode D2 is formed by doping and conductorizing the second active layer.

[0057] The second low-temperature polysilicon layer 8 includes a connection portion, which is located on the side of the first gate G1 away from the first source S1 and the side of the second gate G2 away from the second source S2. The connection portion is overlapped with the first low-temperature polysilicon layer 2 through the via holes of the second barrier layer 4, the first interlayer insulating layer 3 and the first gate insulating layer 12. After the via overlap is achieved, the connection portion is heavily doped to achieve conductorization, and the conductorized connection portion realizes the connection between the first drain D1 and the second drain D2.

[0058] Low-temperature polysilicon is formed by laser irradiation of amorphous silicon using an excimer laser annealing (ELA) device. Before the second low-temperature polysilicon layer 8 is made, a via hole is formed at the position where the first low-temperature polysilicon layer 2 and the second low-temperature polysilicon layer 8 need to be overlapped by via holes; during the process of making the second low-temperature polysilicon layer 8, amorphous silicon (a-Si) is deposited, and the amorphous silicon includes the portion located at the via hole; and the amorphous silicon is laser irradiated using an ELA device to form a low-temperature polysilicon layer.

[0059] However, the amorphous silicon at the via position cannot absorb enough laser energy to achieve effective crystallization. Amorphous silicon with poor crystallization quality will cause abnormal resistance after being conductive, thus affecting the product yield.

[0060] In view of this, an embodiment of the present application provides an array substrate, wherein a support column is provided at a connection position between the first low-temperature polysilicon layer and the second low-temperature polysilicon layer 8, and the support column supports the first low-temperature polysilicon layer 2 and the intermediate film layer, wherein the intermediate film layer refers to a film layer located between the first low-temperature polysilicon layer 2 and the second low-temperature polysilicon layer 8, for example Figure 1 In the embodiment, the intermediate film layer includes a first gate insulating layer 12 , a first interlayer insulating layer 3 and a second barrier layer 4 .

[0061] Before manufacturing the second low-temperature polysilicon layer 8, the intermediate film layer is patterned to reduce the height of the intermediate film layer lifted by the support column relative to the base substrate 1, so that when manufacturing the second low-temperature polysilicon layer 8, the distance between the first low-temperature polysilicon layer 2 and the second low-temperature polysilicon layer 8 is smaller than the thickness of the intermediate film layer, or even 0.

[0062] With such a design, when the first low-temperature polysilicon layer 2 and the second low-temperature polysilicon layer 8 are connected at the position where the support column 15 is raised, the depth of the via can be reduced, and even the direct contact and connection of the via can be omitted. As a result, during the manufacturing process of the second low-temperature polysilicon layer 8, the part where the second low-temperature polysilicon layer 8 is connected to the first low-temperature polysilicon layer 2 can absorb more laser energy when the ELA equipment is performing laser irradiation, thereby improving the crystallization quality; after conductorization, the resistance is guaranteed to be normal, thereby improving the product yield.

[0063] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0064] Figure 2A schematic diagram of the structure of an array substrate provided in an embodiment of the present application is shown in FIG. Figure 2 As shown, a first thin film transistor 100 and a second thin film transistor 200 are arranged on a base substrate 1, and a direction away from the base substrate 1 and perpendicular to the base substrate 1 is defined as a first direction. Figure 2 Taking the orientation shown as an example, the first direction is the direction indicated by the arrow X, which is from bottom to top in the longitudinal direction. The first thin film transistor 100 and the second thin film transistor 200 are stacked in the first direction, and the second thin film transistor 200 is away from the base substrate 1 relative to the first thin film transistor 100. The first thin film transistor 100 and the second thin film transistor 200 are stacked, which is conducive to reducing the occupied area and is more common in high-resolution array substrates.

[0065] The first thin film transistor 100 includes a first active layer, a first gate electrode G1 , a first source electrode S1 , and a first drain electrode D1 , and the second thin film transistor 200 includes a second active layer, a second gate electrode G2 , a second source electrode S2 , and a second drain electrode D2 .

[0066] exist Figure 2 In the scheme shown, a first barrier layer 14, a first low-temperature polysilicon layer 2, a first gate insulation layer 12, a first gate layer 13, a first interlayer insulation layer 3, a first metal layer 11, a second barrier layer 4, a second low-temperature polysilicon layer 8, a second gate insulation layer 5, a second gate layer 9, a second interlayer insulation layer 6 and a second metal layer 10 are stacked along a first direction on one side of a substrate 1.

[0067] The first low-temperature polysilicon layer 2 includes a first active layer, the first gate layer 13 includes a first gate G1, the first active layer includes a first channel region 21 corresponding to the first gate G1, and conductive regions located on both sides of the first channel region 21. The first metal layer 11 includes a first source S1, and the first source S1 is connected to the first active layer through a via hole passing through the first gate insulating layer 12 and the first interlayer insulating layer 3. The first drain D1 is formed by doping and conductively conducting the first active layer. The first active layer also includes a first channel region corresponding to the first gate G1.

[0068] The second low-temperature polysilicon layer 8 includes a second active layer, the second gate layer 9 includes a second gate G2, the second active layer includes a second channel region 81 corresponding to the second gate G2, and conductor regions located on both sides of the second channel region 81. The second metal layer 10 includes a second source electrode S2, and the second source electrode S2 is connected to the second active layer through a via hole passing through the second gate insulating layer 5 and the second interlayer insulating layer 6. The second drain electrode D2 is formed by doping and conductorizing the second active layer, and the second active layer also includes a second channel region corresponding to the second gate G2.

[0069] The first gate insulating layer 12, the first interlayer insulating layer 3 and the second barrier layer 4 between the first low-temperature polycrystalline layer and the second low-temperature polycrystalline layer are defined herein as intermediate film layers, and the intermediate film layers may be different in products of different embodiments. The first low-temperature polycrystalline silicon layer 2 has a first side away from the substrate 1, the intermediate film layer is arranged on the first side, and has a second side away from the substrate 1, and the second low-temperature polycrystalline silicon layer 8 is arranged on the second side. In a first direction perpendicular to the substrate 1, the spacing between the first side and the second side is a first spacing.

[0070] The array substrate is defined herein to include adjacent first and second regions A and B. In the first region A, the first low-temperature polysilicon layer 2 , the intermediate film layer, and the second low-temperature polysilicon layer 8 are stacked along a first direction.

[0071] The second region B is the connection region between the first low-temperature polysilicon layer 2 and the second low-temperature polysilicon layer 8. The first low-temperature polysilicon layer 2 includes a first connection portion 22 located in the second region B, and the second low-temperature polysilicon layer 8 includes a second connection portion 82 connected to the first connection portion. The first connection portion 22 and the second connection portion 82 are connected in the second region B.

[0072] In the second area B of the array substrate, a support column 15 is arranged between the first low-temperature polycrystalline silicon layer 2 and the base substrate 1. The support column 15 is a columnar structure extending along the first direction, including a support top away from the base substrate 1 along the first direction and a peripheral wall connected to the edge of the support top, and the peripheral wall extends around the first direction.

[0073] The support column 15 is formed by patterning an inorganic insulating material, and the inorganic insulating material includes at least one of silicon nitride SiNx, silicon oxide SiOx, and silicon oxynitride SiNxOy. In the cross-sectional figure corresponding to the first cross-section, the angle of the peripheral wall relative to the second direction is 20 to 50 degrees, and the distance of the support top along the second direction is greater than 1um. Among them, the first cross-section is parallel to the first direction, and the second direction is perpendicular to the first direction. In other words, the peripheral wall is inclined to form a slope with a certain angle.

[0074] The support column 15 with a slope can avoid cracking of the film layer during the subsequent film layer deposition; at the same time, the deposition of the subsequent film layer on the slope can ensure good uniformity of the film thickness; in addition, the slope is beneficial to the stability of the photoresist thickness and the photoresist morphology after exposure during the graphic processing; and after the amorphous silicon covering of the second low-temperature polysilicon layer 8 is made, the slope is beneficial to the crystallization effect on the surface.

[0075] In a specific product, in the cross-sectional diagram corresponding to the first cross-section, the angle of the peripheral wall relative to the second direction is about 30 degrees, and the distance of the support top along the second direction is about 2 um.

[0076] In the embodiment where the support pillar 15 is made of silicon nitride, a first barrier layer 14 containing silicon oxide is further provided on the first low-temperature polysilicon layer 2 facing the base substrate 1 , and the first barrier layer 14 extends along the peripheral wall and the support top.

[0077] The first low-temperature polysilicon layer 2 extends along the peripheral wall and the support top, and the first low-temperature polysilicon layer 2 includes a portion lifted by the support column 15 and a portion not lifted by the support column 15. It can be understood that the portion lifted by the support column 15 is farther away from the substrate 1 than the portion not lifted by the support column 15. The first connecting portion 22 is the portion of the first low-temperature polysilicon layer 2 corresponding to the support top.

[0078] The support column 15 makes the second region B include the third region C, and the third region C is opposite to the support top in the first direction, that is, the orthographic projection of the third region C on the base substrate 1 coincides with the orthographic projection of the support top on the base substrate 1. The portion of the first low-temperature polysilicon layer 2 located in the third region C is the first connecting portion 22, and the portion of the second low-temperature polysilicon layer 8 located in the third region C is the second connecting portion 82.

[0079] The first side surface includes a first surface located in the third region C, and the second side surface includes a second surface located in the second region B. In the first direction, the second surface is flush with the first surface, or the second surface includes a first portion flush with the first surface and a second portion connected to the first portion, and the second portion is closer to the base substrate 1 relative to the first surface. In other words, the first spacing is 0 in the third region C, and the intermediate film layer is provided with an exposure opening in the third region C; the first connection portion 22 is exposed through the exposure opening.

[0080] The second connection portion 82 of the second low temperature polysilicon layer 8 is located in the third region C. The second connection portion 82 is directly connected to the first connection portion 22 through the exposed opening. That is, the extension distance of the second connection portion 82 along the first direction is the thickness of the second low temperature polysilicon layer 8 .

[0081] It can be seen from the above description that the second region B is the region where the support column 15 is located, and the first region A includes the region where the first channel region 21 and the second channel region 81 are located, and the region between the first channel region 21 and the second channel region 81 and the second region B. According to the film formation law of the film layer, the second low-temperature polysilicon layer 8 above the first gate G1 is raised. This article defines the region where the first channel region 21 is located as the fourth region, and the region between the fourth region and the second region in the first region A is the fifth region. The size of the first spacing in the fourth region is the sum of the thickness of the intermediate film layer and the thickness of the first gate G1; the value of the first spacing in the fifth region is the thickness of the intermediate film layer.

[0082] Therefore, the spacing between the first low-temperature polysilicon 2 and the second low-temperature polysilicon layer 8 in the fifth region is smaller than the spacing in the fourth region. In this embodiment, the extension distance of the second connecting portion 82 along the first direction is smaller than the spacing between the first low-temperature polysilicon 2 and the second low-temperature polysilicon layer 8 in the fifth region, that is, smaller than the minimum spacing between the first low-temperature polysilicon 2 and the second low-temperature polysilicon layer 8 in the first region A.

[0083] The second connection portion 82 in the second low-temperature polysilicon layer 8 is heavily doped to achieve conductorization, and the second connection portion after conductorization realizes the connection between the first drain electrode D1 and the second drain electrode D2. In other words, the second connection portion is actually a drain terminal connection line of the stacked thin-film transistor, which can play the role of a line with multiple uses. Since the via design not only takes into account the size of the hole itself, but also the edging of the hole by the subsequent film layer and the avoidance of other routing lines, the actual occupied layout area is large, and the difficulty of achieving high resolution will increase exponentially, so vias are an important limiting factor for high-resolution products. In the array substrate provided in the embodiment of the present application, the drain terminal connection of the stacked thin-film transistor is realized by a low-temperature polysilicon layer. Compared with the traditional metal routing via overlap, it avoids the generation of too many vias and can be applied to high-resolution products.

[0084] In the array substrate provided in the embodiment of the present application, the second low-temperature polysilicon layer 8 is in contact and connected with the first low-temperature polysilicon layer 2 through the exposed opening, and there is no via. When the second low-temperature polysilicon layer 8 is produced on the first side, ELA crystallization can be made continuous and thorough to ensure normal crystallization, thereby effectively improving the problem of abnormal overlap of the double-layer low-temperature polysilicon layer, and the implementation method is simple and the effect is good.

[0085] With respect to the array substrate provided in the above-mentioned embodiments, an embodiment of the present application provides a method for manufacturing an array substrate. It should be noted that the following manufacturing method focuses on describing the manufacturing process of the display panel backplane in the second area B. The first thin-film transistor 100 and the second thin-film transistor 200 can be manufactured at the same time as they are formed in the second area B, which will not be repeated here.

[0086] The production method includes:

[0087] Step 1: providing a substrate 1;

[0088] Step 2: Making a support column 15 on one side of the base substrate 1;

[0089] In the process of manufacturing the support pillar 15, a silicon nitride SiNx film is deposited at high temperature; the high temperature deposition range here is 350-430 degrees Celsius. For example, in one example, the silicon nitride SiNx film is deposited at 370 degrees Celsius.

[0090] The SiNx film deposited at a high temperature has a lower etching rate, and thus is convenient for forming a supporting column 15 with a slope.

[0091] After the silicon nitride SiNx film is manufactured, the silicon nitride SiNx film is patterned to form the support column 15. Herein, the patterning process includes photoresist coating, mask exposure, development, etching, photoresist stripping and the like, and a known mature preparation process can be used, which is not limited here.

[0092] Step 3: Fabricate a first low-temperature polysilicon layer 2 and an intermediate film layer.

[0093] The process of making the first low-temperature polysilicon layer 2 includes: depositing a first amorphous silicon layer, irradiating the first amorphous silicon layer with ELA equipment to crystallize it, and forming the first low-temperature polysilicon layer 2; the first low-temperature polysilicon layer 2 can also be doped and patterned according to design requirements.

[0094] Step 4: patterning the portion of the intermediate film layer supported by the support pillars 15 to expose the first low-temperature polysilicon layer 2 .

[0095] Step 5: depositing a second amorphous silicon film layer, wherein the second amorphous silicon film layer is connected to the exposed first low-temperature polysilicon layer 2 .

[0096] Step 6: Crystallize the amorphous silicon film layer to form a second low-temperature polysilicon layer 8 .

[0097] Here, the crystallization process can be achieved by using excimer laser annealing.

[0098] Step 7: Conducting the second connection portion in the second low-temperature polysilicon layer 8 connected to the first low-temperature polysilicon layer 2 .

[0099] In the array substrate manufactured by the above method, the second low-temperature polysilicon layer 8 is in contact and connected with the exposed first low-temperature polysilicon layer 2 without vias. When the second low-temperature polysilicon layer 8 is manufactured on the first side, ELA crystallization can be continuous and thorough to ensure normal crystallization, thereby effectively improving the problem of abnormal overlap of the double-layer low-temperature polysilicon layer. The implementation method is simple and the effect is good.

[0100] Figure 3 A schematic diagram of the structure of another array substrate provided in an embodiment of the present application is shown in FIG. Figure 3 As shown, the array substrate and Figure 2 The difference between the array substrate and the substrate in the middle is that the second side includes a third part corresponding to the second area B and a fourth part corresponding to the first area A. Along the first direction, the third part is away from the base substrate 1 relative to the fourth part. With this design, the second low-temperature polysilicon layer 8 forms a raised structure, which is more conducive to ELA crystallization.

[0101] Figure 4 A schematic diagram of the structure of another array substrate provided in an embodiment of the present application, Figure 5 for Figure 4 A partial enlarged view of the E area, such as Figure 4 and Figure 5 As shown, the array substrate and Figure 3 The difference between the array substrate and the low-temperature polysilicon layer 8 is that the second low-temperature polysilicon layer 8 includes a second connection portion 82, a third connection portion and an intermediate connection portion, the third connection portion is located in the first area A, and the intermediate connection portion connects the second connection portion 82 and the third connection portion. The intermediate connection portion includes at least two sub-connections, and the inclination angle of the sub-connection portion relative to the base substrate gradually decreases during the extension of the third connection portion to the second connection portion. For example, in Figure 5 In the embodiment, the intermediate connection portion includes sub-connection portions E1, E2 and E3, and the inclination angles of the sub-connection portions E1, E2 and E3 relative to the base substrate 1 gradually decrease.

[0102] Such a design facilitates process manufacturing and ensures the film formation quality of the second low-temperature polysilicon layer 8 .

[0103] Figure 6 A schematic diagram of the structure of another array substrate provided in an embodiment of the present application is shown in FIG. Figure 6 As shown, the intermediate film layer is provided with a connection via hole exposing the first side surface in the third region C, the connection via hole has a certain depth along the first direction, the first connection portion 22 is located at the bottom of the connection via hole, and the second low-temperature polysilicon layer 8 is overlapped with the first low-temperature polysilicon layer 2 through the connection via hole in the third region C. The second low-temperature polysilicon layer 8 includes a second connection portion 82, the second connection portion 82 is located on the side of the first gate G1 away from the first source S1, and the second gate G2 away from the second source S2, and the second connection portion 82 is overlapped with the first low-temperature polysilicon layer 2 in the third region C through the via hole penetrating the intermediate film layer.

[0104] Such a design can reduce the depth of the overlapping vias between the first low-temperature polysilicon layer 2 and the second low-temperature polysilicon layer 8, that is, along the first direction, the extension distance of the second connecting portion 82 is smaller than the spacing between the first low-temperature polysilicon layer 2 and the second low-temperature polysilicon layer 8 in the first area A, so that during the manufacturing process of the second low-temperature polysilicon layer 8, the portion where the second low-temperature polysilicon layer 8 is connected to the first low-temperature polysilicon layer 2, that is, the connecting portion, absorbs more laser energy when the ELA equipment is performing laser irradiation, thereby improving the crystallization quality; after conductorization, the resistance is guaranteed to be normal, thereby improving the product yield.

[0105] Figures 3 to 5 The method for making the display panel can refer to the above Figure 2 The description of the display panel production method is not repeated here.

[0106] An embodiment of the present application also provides a display device, which includes the array substrate in the above embodiment. The display device can be an LCD (Liquid Crystal Display) display device, an OLED (Organic Light-Emitting Diode) display device, a Mini LED (sub-millimeter light-emitting diode) display device or a Micro-LED (micro light-emitting diode) display device.

[0107] In the description of the embodiments of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0108] In the description of the embodiments of the present application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the embodiments of the present application can be understood according to specific circumstances.

[0109] In addition, the technical features involved in the different embodiments of the present application described above can be combined with each other as long as they do not conflict with each other.

[0110] So far, the technical solutions of the present application have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present application is obviously not limited to these specific embodiments. Without departing from the principles of the present application, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present application.

Claims

1. An array substrate, characterized in that: It includes a base substrate, and a first low-temperature polysilicon layer, an intermediate film layer, and a second low-temperature polysilicon layer arranged on one side of the base substrate; The array substrate comprises a first region and a second region adjacent to each other, wherein in the first region, the first low-temperature polysilicon layer, the intermediate film layer and the second low-temperature polysilicon layer are stacked along a first direction perpendicular to the base substrate; In the second region, a support column is disposed between the first low-temperature polysilicon layer and the base substrate, and the support column makes the first low-temperature polysilicon layer protrude along the first direction; The portion of the first low-temperature polysilicon layer lifted by the supporting pillar includes a first connecting portion, and the second low-temperature polysilicon layer includes a second connecting portion located in the second region, and the second connecting portion is connected to the first connecting portion; An extension distance of the second connection portion along the first direction is smaller than a distance between the first low-temperature polysilicon layer and the second low-temperature polysilicon layer in the first region.

2. The array substrate according to claim 1, characterized in that: The support column includes a support top away from the substrate along the first direction and a peripheral wall connected to the edge of the support top, the peripheral wall extends around the first direction and is inclined relative to the substrate.

3. The array substrate according to claim 2, characterized in that: The second region includes a third region opposite to the support top, and an orthographic projection of the third region on the base substrate coincides with an orthographic projection of the support top on the base substrate; A portion of the first low-temperature polysilicon layer located in the third region is the first connecting portion, and a portion of the second low-temperature polysilicon layer located in the third region is the second connecting portion.

4. The array substrate according to claim 3, characterized in that: The intermediate film layer is provided with an exposure opening in the third region; in the first direction, the first connection portion is flush with the exposure opening or extends from the exposure opening to a side away from the base substrate; and the second connection portion is in contact with and connected to the first connection portion.

5. The array substrate according to claim 3, characterized in that: The intermediate film layer is provided with a connection via having a depth in the third region, the first connection portion is located at the bottom of the connection via, and the second connection portion is connected to the first connection portion through the connection via.

6. The array substrate according to claim 3, characterized in that: The second low-temperature polysilicon layer includes the second connecting portion, a third connecting portion and an intermediate connecting portion, the third connecting portion is located in the first region, and the intermediate connecting portion connects the second connecting portion and the third connecting portion; The intermediate connection portion includes at least two sub-connection portions, and in the process of the third connection portion extending toward the second connection portion, the inclination angles of the sub-connection portions relative to the base substrate gradually decrease.

7. The array substrate according to any one of claims 2 to 6, characterized in that: The support column is formed by patterning an inorganic insulating material, wherein the inorganic insulating material includes at least one of silicon oxide, silicon nitride and silicon oxynitride.

8. The array substrate according to claim 7, characterized in that: In the cross-sectional diagram corresponding to the first cross-section, the angle of the peripheral wall relative to the second direction is 20 to 50 degrees, and the distance of the support top along the second direction is greater than 1um; The first cross section is parallel to the first direction, and the second direction is perpendicular to the first direction.

9. The array substrate according to claim 7, characterized in that: The support column is made of silicon nitride, and a first barrier layer containing silicon oxide is further provided on the first low-temperature polysilicon layer facing the substrate, and the first barrier layer extends along the peripheral wall and the support top.

10. The array substrate according to claim 1, characterized in that: The array substrate comprises a first thin film transistor and a second thin film transistor stacked along the first direction, wherein the second thin film transistor is farther away from the base substrate than the first thin film transistor; The first thin film transistor includes a first active layer, a first gate, a first source and a first drain, and the second thin film transistor includes a second active layer, a second gate, a second source and a second drain; the first low-temperature polysilicon layer includes the first active layer, and the second low-temperature polysilicon layer includes the second active layer; The first drain electrode and the second drain electrode are connected by connecting the first connecting portion and the second connecting portion.

11. The array substrate according to claim 10, characterized in that: The first low-temperature polysilicon layer and the second low-temperature polysilicon layer have different spacings in the first region; and an extension distance of the second connecting portion along the first direction is smaller than a minimum spacing between the first low-temperature polysilicon layer and the second low-temperature polysilicon layer in the first region.

12. The array substrate according to claim 11, characterized in that: The first active layer includes a first channel region, the array substrate includes a fourth region opposite to the first channel region, and an orthographic projection of the fourth region on the base substrate coincides with an orthographic projection of the first channel on the base substrate; The first area includes the fourth area and a fifth area located between the fourth area and the first area; The distance between the first low-temperature polysilicon layer and the second low-temperature polysilicon layer in the fourth region is greater than the distance between the first low-temperature polysilicon layer and the second low-temperature polysilicon layer in the fifth region; An extension distance of the second connection portion along the first direction is smaller than a distance between the first low-temperature polysilicon layer and the second low-temperature polysilicon layer in the fifth region.

13. The array substrate according to claim 10, characterized in that: The intermediate film layer includes a first gate insulating layer, a second gate insulating layer, and a second barrier layer, and the first gate insulating layer, the second gate insulating layer, and the second barrier layer are stacked along the first direction.

14. A method for manufacturing an array substrate, characterized in that: Used to manufacture the array substrate according to any one of claims 1 to 13, the manufacturing method comprising: providing a substrate base plate; Making a support column on one side of the substrate base plate; manufacturing a first low-temperature polysilicon layer and an intermediate film layer; Performing patterning on the portion of the intermediate film layer supported by the support pillars, and exposing the first low-temperature polysilicon layer; Depositing an amorphous silicon film layer, wherein the amorphous silicon film layer is connected to the exposed first low-temperature polysilicon layer; crystallizing the amorphous silicon film layer to form a second low-temperature polysilicon layer; A second connection portion in the second low temperature polysilicon layer connected to the first low temperature polysilicon layer is conductively connected.

15. The manufacturing method according to claim 14, characterized in that: The step of manufacturing a support column on one side of the substrate includes: Using high temperature deposited silicon nitride film; performing patterning on the silicon nitride film to form a support column; Among them, the temperature range of high temperature deposition is 350 to 430 degrees Celsius.

16. A display device, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 13.

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