A decoding method and device of a polar code, a computing device and a storage medium

Abstract

The application provides a polar code decoding method and device, a computing device and a storage medium. The technical scheme of the application comprises: obtaining a code block sequence of a polar code; performing a round of SC decoding on M-bit bits in the code block sequence in a maximum of L SC decoders in sequence every round; the SC decoding in each round of iteration is parallelly expanded on the surviving path of the last round, to generate a candidate path, and a maximum of L surviving paths in the current round are obtained from the candidate path; and when the SC decoding of the code block sequence is completed, the bit information of the surviving path with the minimum path metric value is taken as a decoding result. Compared with the traditional SCL decoding method, the technical scheme of the application provides more traversal samples every round, retains fewer surviving paths, has smaller memory resource and CPU resource consumption of SC decoding, is faster in path traversal speed, and is higher in decoding efficiency.

Description

Technical Field

[0001] This invention relates to the field of communications, and more particularly to a method, apparatus, computing device, and storage medium for decoding polar codes. Background Technology

[0002] Traditional polar code decoders use SCL decoders, which are L SC (Successive Cancellation) decoders that decode in parallel. After traversing the nodes of each decoding stage, the LLR estimates and bit values ​​of all paths are retained for subsequent path selection. Moreover, the LLR estimates and bit values ​​generated after the decision are inherited to the next node for continued computation if the path has not been eliminated.

[0003] When L is at its minimum value of 1, the SCL decoder degenerates into an SC decoder. In this case, if an error occurs during the decoding of a message bit, the subsequent message bit decoding will use the previous message bit estimate, leading to a more serious error propagation. The larger L is, the more LLR estimates and bit values ​​of all paths are retained for subsequent path selection. All data generated in this process needs to be stored in a cache. The larger the storage required, the more processors are needed, the more complex the path sorting becomes, and the greater the power consumption of the SCL decoder, which will greatly increase the hardware overhead.

[0004] Therefore, choosing the appropriate number L of SC decoders is the key to designing a polar code decoding method with low hardware overhead. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide a method, apparatus, computing device, and storage medium for decoding polar codes. The technical solution of the embodiments of the present invention includes: sequentially acquiring M bits from a polar code block sequence in each round and iteratively performing SC decoding on L decoders; in each round of SC decoding, M bits are extended in parallel on the surviving paths of the previous round to generate candidate paths, and at most L surviving paths and a path metric value for each surviving path are obtained; after the polar code block sequence completes SC decoding, the bit information of the surviving path with the smallest path metric value among the final surviving paths is taken as the decoding result. In some embodiments of the present invention, CRC check is also used to prune the candidate paths. In some embodiments of the present invention, L is less than or equal to 2. M-1 In some embodiments of the present invention, M = 4 and L = 8.

[0006] Embodiments of the present application generate candidate paths by parallel expanding M-bit according to the survived paths of the last round on each SC decoder in each round of iteration, which provides more traversed path samples for each SC decoder, and the selection of candidate paths is more accurate, while reducing the number of decoders and the number of survived paths by controlling the number of M, and the memory resource and / or CPU resource consumption of SC decoding is smaller, the path traversal speed is faster, and the decoding efficiency is higher.

[0007] In a first aspect, embodiments of the present application provide a decoding method of a polar code, comprising: obtaining a code block sequence of a polar code; obtaining SC decoding of M-bit in a maximum of L SC decoders in each round of iteration from the code block sequence in order, wherein the SC decoding of each round of iteration expands M-bit in parallel on the survived paths of the last round to generate candidate paths, and obtains a maximum of L survived paths in the current round from the candidate paths; and when the SC decoding of the code block sequence is completed, taking the bit information of the survived path with the minimum path metric value in the final survived path as a decoding result, wherein the path metric value and the bit information corresponding to the path are inversely changed with the probability of correct decoding.

[0008] According to the above, the SC decoding of each round of iteration expands M-bit in parallel on the survived paths of the last round to generate candidate paths, which provides more traversed samples for each round of the traditional SCL decoding method, and the number of survived paths is small, the memory resource and / or CPU resource consumption of SC decoding is smaller, the path traversal speed is faster, and the decoding efficiency is higher.

[0009] In a possible implementation of the first aspect, the SC decoding of each round of iteration expands M-bit in parallel on the survived paths of the last round to generate candidate paths, comprising: performing parallel traversal on the decoding result of the current obtained M-bit to obtain 2 M expansion paths; and each expansion path and any survived path of the last round form a candidate path for selecting the current survived path.

[0010] According to the above, the parallel traversal is performed on the decoding result of the current obtained M-bit to obtain 2 M expansion paths, which traverses more path samples on the same survived path of the last round, and the selection of the survived path is more accurate.

[0011] In a possible implementation of the first aspect, when the code block sequence comprises a plurality of sub-block sequences and each sub-block sequence comprises a plurality of CRC check bits, the method further comprises: when any sub-block sequence is added to the candidate path, performing CRC check on the bit information of the candidate path, and deleting the candidate path that fails the CRC check.

[0012] According to the above, the candidate paths that fail the CRC check are deleted, so that the path search is more accurate.

[0013] In a possible implementation of the first aspect, the method further includes: deinterleaving the sub-blocks before the CRC check.

[0014] According to the above, the inter-sub-block interleaving is removed in time, so that the sub-block decoding iteration results are subjected to the CRC check in time, and the candidate paths that fail the CRC check are deleted, so that the path search is more accurate.

[0015] In a possible implementation of the first aspect, L is less than or equal to 2 raised to the power of (M-1).

[0016] According to the above, the L paths that are 2 raised to the power of (M-1) are reserved, so that subsequent decoding is performed only in the L decoders, the memory resource and / or CPU resource consumption of the decoding is small, the path iteration speed is faster, and the decoding efficiency is higher.

[0017] In a possible implementation of the first aspect, M is equal to 4, and L is equal to 8.

[0018] According to the above, in each SC decoder, 4-bit bits are expanded in parallel according to the survivor paths of the previous round in each iteration, 16 extended paths are generated, and then 128 candidate paths are generated, so that the number of iteration path samples provided by each SC decoder is larger than that of the traditional SCL decoding method, the selection of the candidate paths is more accurate, 4-bit bits are expanded in each iteration, each decoder only needs to expand 16 paths, and only 8 survivor paths need to be reserved in each iteration, so that the memory resource and / or CPU resource consumption of the SC decoding is small, the path iteration speed is faster, and the decoding efficiency is higher on the basis of the accurate selection of the survivor paths.

[0019] In a possible implementation of the first aspect, the step of obtaining the maximum L survivor paths includes: performing bit iteration and LLR iteration on M-bit bits obtained and bit information of one of the survivor paths of the previous round in one SC decoder, to obtain a final LLR of the current M-bit bits expanded on the survivor path of the previous round; obtaining the path metric values of the candidate paths according to the final LLR and the path metric values of the survivor paths of the previous round; and selecting L paths with the minimum path metric values from the candidate paths as the survivor paths of the current round, and reserving the corresponding path metric values.

[0020] According to the above, in the SC decoding of each iteration, the final LLR calculation is completed at the same time as the M-bit bits, and the PM in the candidate paths is obtained according to the final LLR, so that the accuracy of the path search is improved.

[0021] In a possible implementation of the first aspect, the decoding method is used for decoding a polar code of a 5G control channel.

[0022] According to the above, the method of the embodiments of the present application can decode the polar code of the 5G control channel at low cost and high efficiency.

[0023] In the second aspect, the embodiments of the present application provide a decoding device of a polar code, comprising an acquisition module, an iterative decoding module and an output module; the acquisition module is configured to acquire a code block sequence of a polar code; the iterative decoding module is configured to perform a round of SC decoding on M bits in a maximum of L SC decoders according to a survival path of a previous round in each round of iteration from the code block sequence in sequence, wherein the SC decoding of each round of iteration is performed in parallel on the survival path of the previous round to expand M bits, to generate a candidate path, and to obtain a maximum of L survival paths in the current round from the candidate path; and the output module is configured to output bit information of a survival path with a minimum path metric value in the final survival path as a decoding result when the SC decoding of the code block sequence is completed, wherein the path metric value and the bit information corresponding to the path are inversely changed with a probability of correct decoding.

[0024] According to the above, by expanding M bits in parallel on each SC decoder according to the survival path of the previous round in each round of iteration, the candidate path is generated, the number of traversal path samples provided by each SC decoder is larger than that of the traditional SCL decoding method, the selection of the candidate path is more accurate, the number of decoders and the survival path are reduced by controlling the number of M, the memory resource and / or CPU resource consumption of the SC decoding is smaller, the path traversal speed is faster, and the decoding efficiency is higher.

[0025] In a possible implementation of the second aspect, the iterative decoding module comprises a path traversal module configured to perform parallel traversal on a decoding result of the current acquired M bits to obtain 2 M expansion paths; each of the expansion paths and any of the survival paths of the previous round form a candidate path, which is used to select the current survival path.

[0026] According to the above, by performing parallel traversal on the decoding result of the current acquired M bits to obtain 2 M expansion paths, the number of traversal path samples on the same survival path of the previous round is larger, and the selection of the survival path is more accurate.

[0027] In a possible implementation of the second aspect, when the code block sequence comprises a plurality of sub-block sequences and each sub-block sequence comprises a plurality of CRC check bits, the iterative decoding module further comprises a CRC check module configured to perform CRC check on bit information of the candidate path when any sub-block sequence is added to the candidate path, and to delete the candidate path that fails the CRC check.

[0028] Therefore, the candidate paths failing the CRC check are deleted, so that the path search is more accurate.

[0029] In a possible implementation of the second aspect, the CRC check module is further configured to de-interleave the sub-blocks before the CRC check.

[0030] Therefore, the sub-block decoding iteration result is subjected to the CRC check in time, and the candidate paths failing the CRC check are deleted, so that the path search is more accurate.

[0031] In a possible implementation of the second aspect, L is less than or equal to 2 raised to the power of (M-1).

[0032] Therefore, the 2 raised to the power of (M-1) L surviving paths are reserved, so that subsequent decoding is performed only in the L decoders, the memory resource and / or CPU resource consumption of the decoding is small, the path iteration speed is faster, and the decoding efficiency is higher.

[0033] In a possible implementation of the second aspect, the iterative decoding module further includes an SC iteration module, a PM determination module, and a path selection module, the SC iteration module is configured to perform bit iteration and LLR iteration on the bit information of one of the surviving paths in a previous round and the obtained M bits in one SC decoder, to obtain final LLRs of the current obtained M bits extended on the surviving path in the previous round; the PM determination module is configured to obtain the path metric values of the candidate paths according to the final LLRs and the path metric values of the surviving paths in the previous round; and the path selection module is configured to select L paths with the smallest path metric values from the candidate paths as the surviving paths in the current round, and reserve the corresponding path metric values.

[0034] Therefore, the final LLR calculation and the PM in the candidate paths are simultaneously completed on the M bits in the SC decoding of each iteration, so that the accuracy of the path search is improved.

[0035] In a possible implementation of the second aspect, M is equal to 4, and L is equal to 8.

[0036] According to the above, 16 extended paths are generated by parallel extension of 4-bit bits on each SC decoder according to the survivor paths of the last round in each round of iteration, and 128 candidate paths are generated, which provides more traversal path samples for each SC decoder relative to the conventional SCL decoding method, and the selection of the candidate paths is more accurate. Meanwhile, only 4-bit bits are extended in each round, each decoder only needs to extend 16 paths, and only 8 survivor paths need to be reserved in each round. On the basis of accurate selection of the survivor paths, the SC decoding has smaller memory resource and / or CPU resource overhead, faster path traversal speed, and higher decoding efficiency.

[0037] In a possible implementation of the second aspect, the decoding method is used for polar code decoding of a 5G control channel.

[0038] According to the above, the device of the embodiments of the present application can decode the polar code of the 5G control channel at low cost and high efficiency.

[0039] In a third aspect, the embodiments of the present application provide a computing device, comprising,

[0040] a bus;

[0041] a communication interface connected with the bus;

[0042] at least one processor connected with the bus; and

[0043] at least one memory connected with the bus and storing program instructions, the program instructions, when executed by the at least one processor, causing the at least one processor to execute any of the embodiments of the first aspect of the present application.

[0044] In a fourth aspect, the embodiments of the present application provide a computer readable storage medium, which stores program instructions, the program instructions, when executed by a computer, causing the computer to execute any of the embodiments of the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0045] Figure 1 a structural schematic diagram of an implementation scenario related to the embodiments of the present application;

[0046] Figure 2A a flowchart of a polar code decoding method embodiment one of the present application;

[0047] Figure 2B a flowchart of an SC decoding iteration of a polar code decoding method embodiment one of the present application;

[0048] Figure 3 a schematic diagram of BIT iteration and LLR iteration processes of the SC decoding method of the present application;

[0049] Figure 4A Input and output sequence diagram for the BIT iteration process of the SC decoding method of the present application;

[0050] Figure 4B Input and output sequence diagram for the LLR iteration process of the SC decoding method of the present application;

[0051] Figure 5A Flow diagram of the second embodiment of the decoding method of the polar code of the present application;

[0052] Figure 5B Flow diagram of the iteration of the SC decoding of the second embodiment of the decoding method of the polar code of the present application;

[0053] Figure 6A Structure diagram of the first embodiment of the decoding device of the polar code of the present application;

[0054] Figure 6B Structure diagram of the decoding iteration module of the first embodiment of the decoding device of the polar code of the present application;

[0055] Figure 7A Structure diagram of the second embodiment of the decoding device of the polar code of the present application;

[0056] Figure 7B Structure diagram of the decoding iteration module of the first embodiment of the decoding device of the polar code of the present application;

[0057] Figure 8 Structure diagram of the computing device of the embodiments of the present application. DETAILED DESCRIPTION

[0058] In the following description, the term “some embodiments” is described, which describes a subset of all possible embodiments, but it can be understood that “some embodiments” can be the same subset or different subset of all possible embodiments, and can be combined with each other without conflict.

[0059] In the following description, the terms “first\second\third, etc.” or module A, module B, module C, etc. are only used to distinguish similar objects or to distinguish different embodiments, and do not represent a specific order of the object. It can be understood that the specific order or sequence can be interchanged as permitted, so that the embodiments of the application described herein can be implemented in an order other than that illustrated or described herein.

[0060] In the following description, the labels representing steps such as S110, S120, etc. do not necessarily mean that the steps are executed in this order, and the order of the steps can be interchanged or executed simultaneously as permitted.

[0061] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application.

[0062] 1. Polar code, a kind of forward error correction block coding method, is used for signal transmission. The core of construction is to process by channel polarization, and the method is used on the encoding side to make each subchannel show different reliability. When the code length continues to increase, part of the channel will tend to be a perfect channel with capacity close to 1 (no error), and another part of the channel will tend to be a pure noise channel with capacity close to 0. Select the channel with capacity close to 1 to directly transmit information to approach the channel capacity.

[0063] 2. SC (Successive Cancellation, SC) decoding, a kind of serial cancellation decoding algorithm of polar code. The basic idea of SC decoding is to perform iterative calculation of soft information and hard decision information on the trellis. Given the code length N = 2 n , n is the polarization order, then the trellis is composed of n-level butterfly nodes. In the butterfly structure, the hard information is calculated and transmitted from left to right, and the soft information is calculated and transmitted from right to left, to obtain the LLR and estimated value of each bit.

[0064] 3. L LR (Log-Likelihood Ratio, LLR), log-likelihood ratio. Taking SC decoding as an example, according to the probability that the receiving end correctly judges the bit to be 0 and the probability that the receiving end correctly judges the bit to be 1, the LLR is output. The greater the value of LLR, the greater the probability that the receiving end correctly judges the bit to be 0; on the contrary, the smaller the value of LLR, the greater the probability that the receiving end correctly judges the bit to be 1.

[0065] 4. Path, the value combination of each bit of the input sequence formed by the branches.

[0066] 5. PM (Path Metric, PM), the posterior probability of SC decoding, which measures the probability of the correct decoding result of each bit information on a path. The greater the probability of the correct decoding result of each bit information on a path, the smaller the PM of the path.

[0067] In the embodiments of the present application, the M-bit bits obtained from the polar code block sequence in sequence each round are iterated on L decoders, the SC decoding of each round iteration is parallelly expanded on the surviving paths of the last round, candidate paths are generated, and the most L surviving paths and the path metric values of each surviving path are obtained therefrom; when the polar code block sequence is completed SC decoding, the bit information of the surviving path with the smallest path metric value in the final surviving path is taken as the decoding result. In some embodiments of the present application, the path is also pruned through CRC check. In some embodiments of the present application, L is equal to 2 raised to the power of (M-1). In some embodiments of the present application, M=4 and L=8.

[0068] The embodiments of the present application parallelly expand M-bit bits on each SC decoder according to the surviving paths of the last round each round of iteration, generate candidate paths, provide more traversal path samples for each SC decoder relative to the traditional SCL decoding method, the candidate path selection is more accurate, the number of decoders is reduced and the surviving paths are reserved by controlling the number of M, the memory resource and / or CPU resource overhead of SC decoding is smaller, the path traversal speed is faster, and the decoding efficiency is higher.

[0069] The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0070] Firstly, the embodiments of the present application will be described in conjunction with the accompanying drawings. Figure 1 The embodiments of the present application relate to an implementation scenario.

[0071] Figure 1 An implementation scenario of one example of the embodiments of the present application is introduced, which includes a sending device and a receiving device, and the two devices can be coupled through air transmission on different devices.

[0072] The sending device includes a polar code encoding unit, an inter-block interleaving unit, an OFDM radio frequency modulation unit and a transmitting antenna, the polar code encoding unit is used for sequentially adding CRC check bits, sub-block interleaving, polar code encoding and other processing to the information bit sequence, and generating polar code blocks, the polar code blocks are processed by the inter-block interleaving unit and the OFDM radio frequency modulation unit to generate wireless signals, and the wireless signals are transmitted through the transmitting antenna.

[0073] The receiving device includes a receiving antenna, an OFDM radio frequency demodulation unit, a de-inter-block interleaving unit and a polar code decoding unit, the receiving antenna receives wireless signals from the air, and the wireless signals are processed by the OFDM radio frequency demodulation unit and the de-inter-block interleaving unit to generate polar code blocks to be decoded, the polar code blocks are processed by the polar code decoding unit, the de-sub-block interleaving and the CRC check processing to generate the received information bit sequence.

[0074] The receiving device includes a receiving antenna, an OFDM radio frequency demodulation unit, a de-inter-block interleaving unit and a polar code decoding unit, the receiving antenna receives wireless signals from the air, and the wireless signals are processed by the OFDM radio frequency demodulation unit and the de-inter-block interleaving unit to generate polar code blocks to be decoded, the polar code blocks are processed by the polar code decoding unit, the de-sub-block interleaving and the CRC check processing to generate the received information bit sequence. Figure 1The radio frequency modulation and demodulation units of the examples are OFDM radio frequency modulation units and OFDM radio frequency demodulation units, and a typical application scheme is used for polar code encoding and decoding of a 5G control channel. It needs to be emphasized that when the polar code encoding and decoding are used for other systems, the radio frequency modulation and demodulation units are also based on the radio frequency mode of the other systems.

[0075] It also needs to be emphasized that the addition of the CRC check bit and the sub-block interleaving function of the polar code encoding unit is an optional function, and whether it is needed is determined according to the actual scene. The CRC check bit removal and sub-block deinterleaving functions of the polar code decoding unit are also optional functions, and whether they are needed is also determined according to the actual scene.

[0076] The following will be described in combination with Figures 2A to 5B The method embodiments of the present application are introduced.

[0077] In a first embodiment of a polar code decoding method, M-bit bits are obtained from a polar code block sequence in sequence every round for iteration SC decoding on L decoders. The SC decoding of each round iteration is parallelly expanded on the survivor path of the last round, generates a candidate path, and obtains the most L survivor paths and the path metric value of each survivor path from it; when the SC decoding of the polar code block sequence is completed, the bit information of the survivor path with the smallest path metric value in the final survivor path is taken as the decoding result. The method embodiment generates a candidate path by parallelly expanding M-bit bits on each SC decoder according to the survivor path of the last round every round of iteration, provides more traversal path samples for each SC decoder of the traditional SCL decoding method, and the candidate path selection is more accurate. At the same time, by controlling the number of M, the number of decoders and the reserved survivor path are reduced, the memory resource and / or CPU resource overhead of SC decoding is smaller, the path traversal speed is faster, and the decoding efficiency is higher.

[0078] A first embodiment of a polar code decoding method is executed in the polar code decoding unit of Figure 1 .

[0079] Figure 2A A flow of a first embodiment of a polar code decoding method of the present application is shown, which includes steps S110 to S160.

[0080] The method embodiment obtains 4 bits as preset bits for path iteration every round, that is, M=4, and the most 8 are reserved after the SC decoding of each round iteration, that is, L=8, and decoding is performed on 8 SC decoders every round. Among them, in order to facilitate description, taking the polar code block sequence length of 64 bits as an example, there is no limitation on whether the polar code block is divided into sub-blocks, and there is no limitation on whether it contains CRC.

[0081] S110: Obtain a polar code block to be decoded and the initial LLR of each bit thereof.

[0082] Wherein, the polar code block length is a power of 2. The embodiment of the method is described by taking 64 bits as an example.

[0083] Wherein, the initial LLR of each bit of the polar code block is the LLR in the radio frequency demodulation.

[0084] In some embodiments, the polar code block is obtained by radio frequency demodulating the radio frequency data received by the air interface. In other embodiments, the polar code block is obtained by radio frequency demodulating the radio frequency data received by the air interface and removing the inter-block interleaving.

[0085] Wherein, the polar code block to be decoded is also analyzed into several sub-blocks during encoding, each sub-block includes several CRC check bits, and the sub-block interleaving is performed before encoding.

[0086] For example, the above-mentioned air interface data is the control channel data of the 5G air interface. For another example, each sub-block of the DCI in the PBCH channel and the PDCCH channel includes 24 CRC check bits. The present application also supports decoding in theory for other cases with different numbers of CRC check bits.

[0087] S120: Obtain 4 bits (M bits) as preset bits in sequence from the polar code block sequence, expand 4 bits (M bits) on each surviving path of the last round in 8 (L) decoders, and perform parallel iterative SC decoding to obtain up to 8 (L) surviving paths and corresponding path metric values PM of the iteration.

[0088] Wherein, PM is the probability that each bit information in the corresponding path is correctly decoded. The smaller the value is, the greater the probability that the bit information of the entire path is correctly decoded is.

[0089] Wherein, Figure 2B The present step shows the flow of the iterative SC decoding according to the SC decoding method, including the following steps S1210 to S1240.

[0090] S1210: Generate 16 (2M) extended paths according to the value combination of the current 4-bit (M-bit) preset bits, and generate up to 128 (L*2M) candidate paths in combination with the up to 8 (L) surviving paths of the last round.

[0091] Wherein, there are 16 value combinations of 4-bit preset bits, so 16 extended paths are generated.

[0092] From the above, the embodiment of the method performs parallel traversal of M-bit bits during iterative SC decoding, and obtains 2 M extended paths on each surviving path of the last round, and the path samples are more.

[0093] S1220: In each decoder, the bit information corresponding to each surviving path of the previous round in the polar code block is fixed, and the polar code block is subjected to bit iteration (BIT iteration) and LLR iteration according to the SC decoding method, to obtain the final LLR of the current 4-bit (M-bit) bit extended from each surviving path of the previous round.

[0094] wherein the final LLR of the current 4-bit bit is the LLR of each bit in the 4-bit bit, including the LLR with an estimated value of 0 and the LLR with an estimated value of 1.

[0095] wherein the BIT iteration and the LLR iteration of each SC decoding in each round of iteration are the same, except that the number of fixed bits is different each time, and herein the SC decoding in each round of iteration is not distinguished.

[0096] The BIT iteration is performed first, and then the LLR iteration is performed. In each BIT iteration, the 64-bit BIT_IN sequence input in each iteration is grouped and calculated according to the SC decoding method, to obtain a new 64-bit BIT_Out, which is used as the 64-bit BIT_IN sequence input in the next iteration. In the first iteration, the sequence of the polar code block is used as the 64-bit BIT_IN sequence, and 64 bits are 2 raised to the power of 6, so 6 BIT iterations are performed.

[0097] Exemplarily, Figure 3 The BIT iteration process of the SC decoding method is shown, the first BIT iteration result BIT_Out is in reg_s9_array, which is used as the input of the second BIT iteration, the second BIT iteration result BIT_Out is in reg_s8_array, and so on, and the sixth BIT iteration result BIT_Out is in reg_s4_array. Figure 3 wherein Op_unit represents the change of the calculated grouping in the SC decoding, s is related to the number of groups of the grouping, and is also related to the order of the BIT iteration. When the sequence of the polar code block is 64 bits, s represents the (7-s)th BIT iteration, and the number of groups of the calculated grouping changes from 2 S to 2 S-1 .

[0098] Exemplarily, Figure 4A The input and output sequences of the BIT iteration process of the SC decoding method are shown. Grp (Group) represents the group number of the calculated grouping in the SC decoding, BIT_in represents the input sequence of each BIT iteration, BIT_Out represents the output sequence of each BIT iteration, and the contents in the table represent the grouping mode calculated in the SC decoding.

[0099] The LLR iteration direction is opposite to the BIT iteration direction. In each LLR iteration, the 64-bit LLR_IN sequence input in each iteration and the result of the corresponding BIT iteration are grouped and calculated according to the SC decoding method to obtain a new 64-bit LLR_Out, which is used as the 64-bit LLR_IN sequence input in the next iteration. In the first iteration, the initial LLR sequence of each bit of the polar code block (marked as Dec_In in the table) is used as the 64-bit LLR_IN sequence. The 64 bits are 2 raised to the power of 6, so 6 BIT iterations are performed. Figure 3

[0100] For example, Figure 3 The LLR iteration process is also shown. The BIT iteration result input in the first LLR iteration is the fifth BIT iteration result existing in reg_s5_array, the first LLR iteration result LLR_Out exists in reg_llr_array_pong, which is used as the LLR input of the second LLR iteration, the BIT iteration result input in the second LLR iteration is the fourth BIT iteration result existing in reg_s6_array, the second LLR iteration result LLR_Out exists in reg_llr_array_pong, which is used as the LLR input of the third LLR iteration, and so on. The BIT iteration result input in the sixth LLR iteration is the zeroth BIT iteration result, i.e., the sequence of the polar code block input in the first BIT iteration, and the sixth LLR iteration result is the final LLR of each bit of the polar code block. Figure 3 The s also relates to the order of the LLR iteration. When the polar code block sequence is 64 bits, s represents the s-th LLR iteration.

[0101] For example, Figure 4B The input and output sequences of the LLR iteration process of the SC decoding method are shown. Grp (Group) represents the group order of the grouping calculated in the SC decoding, LLR_in represents the LLR input sequence of each LLR iteration, LLR_Out represents the LLR output sequence of each LLR iteration, and the content in the table represents the grouping method calculated in the SC decoding.

[0102] S1230: According to the final LLR of the current 4-bit (M-bit) preset bit expanded from each surviving path of the last round, and combined with the evaluation traversal of the current 4-bit (M-bit) preset bit, the PM of each candidate path is calculated.

[0103] According to the evaluation traversal of the current 4-bit preset bit and the final LLR of the current 4-bit preset bit, soft decision is made according to the SC decoding method, and based on the result of the soft decision, the PM of each candidate path is obtained by accumulating on the basis of the PM of the corresponding surviving path of the last round.

[0104] ​S1240: Select the maximum 8 (L) candidate paths with the minimum PM value from the current candidate paths as the current survivor paths, and save the PM value of the paths.

[0105] From the above, the embodiment of the method performs parallel iteration of M-bit bits during iterative SC decoding, and retains a maximum of 2 M-1 survivor paths when M=4, which means that the number of survivor paths is small, the memory resource and / or CPU resource overhead of SC decoding is small, and the decoding efficiency is high.

[0106] S130: Determine whether the SC decoding of the entire polar code block is completed. If the decoding is completed, perform step S140, otherwise return to step S120.

[0107] S140: De-subblock-interleaves the bit information of the final survivor path.

[0108] In this step, the step is an optional step, and the step is performed when the polar code block includes subblock interleaving.

[0109] S150: Perform CRC check on the bit information of the final survivor path after de-subblock interleaving, and discard the final survivor path that fails the CRC check.

[0110] In this step, the step is an optional step, and the step is performed when the polar code block includes CRC check bits.

[0111] S160: Select the bit information of the path with the minimum PM value from the current survivor paths as the decoding result.

[0112] In this step, the path with the minimum PM value corresponds to the decoding result with the highest decoding probability. If there is no survivor path, the decoding fails.

[0113] It should be emphasized that steps S130 to S150 can also be run between steps S1220 and S1230, and in this case, the "final survivor path" of steps S140 to S150 is modified to "candidate path".

[0114] In summary, in the first embodiment of the decoding method of the polar code, M-bit bits are sequentially obtained from the polar code block sequence each round to perform the SC decoding of iteration on the L decoders, the SC decoding of iteration each round is parallelly expanded on the surviving paths of the last round to generate candidate paths, and the most L surviving paths and the path metric values of each surviving path are obtained therefrom; when the SC decoding of the polar code block sequence is completed, the bit information of the surviving path with the minimum path metric value in the final surviving path is taken as the decoding result. The embodiment of the method provides more traversal path samples for each SC decoder and more accurate candidate path selection relative to the traditional SCL decoding method by parallelly expanding M-bit bits on each SC decoder according to the surviving paths of the last round each round of iteration, reduces the number of decoders and the number of reserved surviving paths by controlling the number of M, and is smaller in memory resource and / or CPU resource consumption of the SC decoding, faster in path traversal speed, and higher in decoding efficiency.

[0115] The following will be described in combination with Figures 5A to 5B The second embodiment of the decoding method of the polar code is introduced.

[0116] In the second embodiment of the decoding method of the polar code, on the basis of the first embodiment of the decoding method of the polar code, the bit information of the path involved in the sub-block polar code is timely subjected to the CRC check when the decoding of the sub-block polar code is completed, and the candidate path that does not pass the CRC check is discarded in time, so that the path search of the SC decoding is more accurate and more block.

[0117] The second embodiment of the decoding method of the polar code is executed in the polar code decoding unit. Figure 1

[0118] Figure 5A The flow of the second embodiment of the decoding method of the polar code is shown, which comprises steps S210 to S240.

[0119] In order to facilitate comparison, the embodiment of the method continues to take the polar code block sequence length of 64 bits as an example, 4 bits are obtained as preset bits for path iteration each round, that is, M=4, the most 8 are reserved each round of iteration, that is, L=8, and decoding is performed on the 8 SC decoders each round, but the polar code block comprises sub-blocks and the sub-blocks are interleaved.

[0120] S210: Obtain the polar code block sequence to be decoded and the initial LLR of each bit thereof.

[0121] The method and advantages of the step are the same as those of the step S110 of the first embodiment of the decoding method of the polar code.

[0122] ​S220: Obtain 4 bits (M bits) in sequence from the polar code block sequence each round as preset bits, extend 4 bits (M bits) on each surviving path of the last round in 8 (L) decoders respectively, and perform iterative SC decoding in parallel to obtain up to 8 (L) surviving paths and corresponding path metric values PM of the iteration.

[0123] wherein PM is the probability of each bit information in the corresponding path being correctly decoded, and the smaller the value is, the greater the probability of the bit information of the entire path being correctly decoded is.

[0124] wherein, Figure 5B The present step shows the flow of the iterative SC decoding according to the SC decoding method, including the following steps S2210 to S2270.

[0125] S2210: Generate 16 (2M) extended paths according to the value combination of the current 4 bits (M bits) preset bits, and combine the up to 8 (L) surviving paths of the last round to generate up to 128 (L*2M) candidate paths.

[0126] wherein the method and advantages of the present step are the same as those of step S1210 of the decoding method embodiment one of a kind of polar code.

[0127] S1220: In each decoder, fix the bit information corresponding to each surviving path of the last round in the polar code block, perform bit iteration (BIT iteration) and LLR iteration on the polar code block according to the SC decoding method, and obtain the final LLR of the current 4 bits (M bits) of the extended paths of the last surviving paths.

[0128] wherein the method and advantages of the present step are the same as those of step S1220 of the decoding method embodiment one of a kind of polar code.

[0129] S2230: Determine whether the bit information corresponding to the current candidate path contains a new sub-block. If it contains a new sub-block, perform step S2240, otherwise perform step S2250.

[0130] S2240: De-subblock interleave and perform CRC check on the bit information corresponding to the current candidate path, and delete the candidate path that does not pass the CRC check.

[0131] wherein the bit information corresponding to each candidate path is de-subblock interleaved by KMax De-interleaver.

[0132] S2250: Determine whether there is a candidate path that passes the CRC check. If there is a candidate path that passes the CRC check, perform step S2260, otherwise terminate the decoding in advance.

[0133] From the above, by performing CRC check on the bit information of the candidate path in the middle process of the iterative SC decoding, and discarding the wrongly decoded path in time, the path search of the SC decoding is more accurate and more efficient.

[0134] S2260: According to the final LLR of the current 4-bit (M-bit) preset bit extended from each survivor path of the last round, and combined with the estimated value traversal of the current 4-bit (M-bit) preset bit, the PM of each candidate path is calculated.

[0135] The method and advantages of this step are the same as those of step S1230 of the decoding method embodiment one of a polar code.

[0136] S2270: From the current candidate paths, select the maximum 8 (L) candidate paths with the minimum PM as the current survivor paths, and save the PM values thereof.

[0137] The method and advantages of this step are the same as those of step S1240 of the decoding method embodiment one of a polar code.

[0138] S230: Determine whether the SC decoding of the entire polar code block is completed. If the decoding is completed, execute step S240, otherwise return to step S230.

[0139] S240: Select the bit information of the path with the minimum PM value from the current survivor paths as the decoding result.

[0140] In summary, in the decoding method embodiment two of a polar code, on the basis of the decoding method embodiment one of a polar code, when the decoding of a sub-block polar code is completed, the bit information of the path involved in the sub-block is checked in time by CRC, and the wrongly decoded candidate path is discarded in time, so that the path search of the SC decoding is more accurate and more efficient.

[0141] The following is based on Figures 6A to 7B The embodiments of the devices of the present application are introduced.

[0142] Figure 6A The structure of the decoding device embodiment one of a polar code of the present application is shown, which comprises an acquisition module 610, an iterative decoding module 620, a decision module 630, a deinterleaving module 640, a CRC check module 650 and an output module 660.

[0143] The acquisition module 610 is used for acquiring the polar code block to be decoded and the initial LLR of each bit thereof. Its working principle and advantages are described with reference to step S110 of the decoding method embodiment one of a polar code.

[0144] The iteration decoding module 620 is configured to obtain M bits from the sequence of the polar code block as preset bits in each round in sequence, extend the M bits on each surviving path of the last round in the L decoders respectively, perform the iterative SC decoding in parallel, and obtain the maximum L surviving paths and the corresponding path metric values PM of the SC decoding in the current iteration. For details, refer to step S120 of the first embodiment of the decoding method of the polar code.

[0145] wherein, Figure 6B The structure of the iteration decoding module 620 is shown, which includes a path traversal module 6210, an SC iteration module 6220, a PM determination module 6230, and a path selection module 6240.

[0146] The path traversal module 6210 is configured to generate 2M extended paths according to the value combination of the current M-bit preset bits, and generate a maximum of L*2M candidate paths in combination with the maximum L surviving paths of the last round. For details, refer to step S1210 of the first embodiment of the decoding method of the polar code.

[0147] The SC iteration module 6220 is configured to fix the bit information corresponding to each surviving path of the last round in the polar code block in each decoder, perform bit iteration and LLR iteration on the polar code block according to the SC decoding method, and obtain the final LLR of the current M-bit bit of the extended surviving path of the last round. For details, refer to step S1220 of the first embodiment of the decoding method of the polar code.

[0148] The PM determination module 6230 is configured to calculate the PM of each candidate path according to the final LLR of the current M-bit preset bit of the extended surviving path of the last round and the estimated value traversal of the current M-bit preset bit. For details, refer to step S1230 of the first embodiment of the decoding method of the polar code.

[0149] The path selection module 6240 is configured to select a maximum of L candidate paths with the minimum PM from the current candidate paths as the current surviving paths, and save the PM values thereof. For details, refer to step S1240 of the first embodiment of the decoding method of the polar code.

[0150] The decision module 630 is configured to determine whether the SC decoding of the entire polar code block is completed. For details, refer to step S130 of the first embodiment of the decoding method of the polar code.

[0151] The deinterleaving module 640 is configured to perform de-sub-block interleaving on the bit information of the final surviving path. For details, refer to step S140 of the first embodiment of the decoding method of the polar code.

[0152] The CRC checking module 650 is configured to perform CRC check on the bit information of the final surviving path after deinterleaving the sub-blocks, and discard the final surviving path that fails the CRC check. The working principle and advantages of the CRC checking module 650 can refer to step S150 of the decoding method for polar code in Embodiment One.

[0153] The output module 660 is configured to select the bit information of the path with the minimum PM value from the current surviving paths that pass the CRC check as the decoding result. The working principle and advantages of the output module 660 can refer to step S160 of the decoding method for polar code in Embodiment One.

[0154] Figure 7A An embodiment of a decoding device for polar code is shown, which comprises an obtaining module 710, an iterative decoding module 720, a decision module 730, and an output module 740.

[0155] The obtaining module 710 is configured to obtain the polar code block to be decoded and the initial LLR of each bit. The working principle and advantages of the obtaining module 710 can refer to step S210 of the decoding method for polar code in Embodiment Two.

[0156] The iterative decoding module 720 is configured to obtain M bits as preset bits in each round from the polar code block sequence in order, extend the M bits on each surviving path of the previous round in the L decoders respectively, and perform iterative SC decoding in parallel to obtain the maximum L surviving paths of the SC decoding in the current iteration and the corresponding path metric values PM. The working principle and advantages of the iterative decoding module 720 can refer to step S220 of the decoding method for polar code in Embodiment Two.

[0157] wherein, Figure 7B An embodiment of the iterative decoding module 720 is shown, which comprises a path traversal module 7210, an SC iteration module 7220, a sub-block judgment module 7230, a CRC checking module 7240, a CRC judgment module 7250, a PM determination module 7260, and a path selection module 7270.

[0158] The path traversal module 7210 is configured to generate the current 2M extended paths according to the value combination of the current M-bit preset bits, and generate the maximum L*2M candidate paths by combining the maximum L surviving paths of the previous round. The working principle and advantages of the path traversal module 7210 can refer to step S2210 of the decoding method for polar code in Embodiment Two.

[0159] The SC iteration module 7220 is configured to fix the bit information corresponding to each surviving path in the polar code block in each decoder, perform bit iteration and LLR iteration on the polar code block according to the SC decoding method, and obtain the final LLR of the current M-bit bit extended from each surviving path of the previous round. The working principle and advantages of the SC iteration module 7220 can refer to step S2220 of the decoding method for polar code in Embodiment Two.

[0160] The sub-block judgment module 7230 is configured to judge whether the bit information corresponding to the current candidate path contains a new sub-block. The working principle and advantages thereof can refer to step S2230 in the second embodiment of the decoding method of the polar code.

[0161] The CRC check module 7240 is configured to perform sub-block deinterleaving and CRC check on the bit information corresponding to the current candidate path, and delete the candidate path that fails to pass the CRC check. The working principle and advantages thereof can refer to step S2240 in the second embodiment of the decoding method of the polar code.

[0162] The CRC judgment module 7250 is configured to judge whether there is a candidate path that passes the CRC check. The working principle and advantages thereof can refer to step S2250 in the second embodiment of the decoding method of the polar code.

[0163] The PM determination module 7260 is configured to calculate the PM of the current candidate path according to the final LLR of the current M-bit preset bit of each surviving path in the last round of expansion, and the estimated value traversal of the current M-bit preset bit. The working principle and advantages thereof can refer to step S2260 in the second embodiment of the decoding method of the polar code.

[0164] The path selection module 7270 is configured to select the maximum L candidate paths with the minimum PM from the current candidate paths as the current surviving paths, and save the PM values thereof. The working principle and advantages thereof can refer to step S2270 in the second embodiment of the decoding method of the polar code.

[0165] The judgment module 730 is configured to judge whether the SC decoding of the entire polar code block is completed. The working principle and advantages thereof can refer to step S230 in the second embodiment of the decoding method of the polar code.

[0166] The output module 740 is configured to select the bit information of the path with the minimum PM value from the current surviving paths that pass the CRC verification as the decoding result. The working principle and advantages thereof can refer to step S240 in the second embodiment of the decoding method of the polar code.

[0167] The embodiment of the present application also provides a computing device, which is described below. Figure 8 The computing device 800 is described in detail.

[0168] The computing device 800 includes a processor 810, a memory 820, a communication interface 830, and a bus 840.

[0169] It should be understood that the communication interface 830 in the computing device 800 shown in the figure can be used for communication between other devices.

[0170] The processor 810 can be connected with the memory 820. The memory 820 can be used to store the program code and data. Therefore, the memory 820 can be a storage unit inside the processor 810, can be an external storage unit independent of the processor 810, or can be a component including the storage unit inside the processor 810 and the external storage unit independent of the processor 810.

[0171] Optionally, the computing device 800 can further include a bus 840. The memory 820 and the communication interface 830 can be connected with the processor 810 through the bus 840. The bus 840 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus 840 can be divided into an address bus, a data bus, a control bus, etc. For the convenience of representation, only one line is used in the figure, but it does not mean that there is only one bus or only one type of bus.

[0172] It should be understood that, in the embodiments of the present application, the processor 810 can be a central processing unit (CPU). The processor can also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) or other programmable logic devices, discrete gates or transistor logic, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor. Alternatively, the processor 810 can use one or more integrated circuits to execute related programs to implement the technical solutions provided by the embodiments of the present application.

[0173] The memory 820 can include read-only memories and random access memories, and provide instructions and data for the processor 810. A part of the processor 810 can also include a non-volatile random access memory. For example, the processor 810 can also store device type information.

[0174] When the computing device 800 is running, the processor 810 executes the computer execution instructions in the memory 820 to perform the operation steps of each method embodiment.

[0175] It should be understood that the computing device 800 according to the embodiments of the present application can correspond to the respective subject performing the method according to the embodiments of the present application, and the above and other operations and / or functions of the respective modules in the computing device 800 are respectively for realizing the respective processes of the methods of the method embodiments, and for brevity, will not be repeated here.

[0176] Those skilled in the art can clearly understand that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized in electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. A person skilled in the art can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0177] Those skilled in the art can clearly understand that, for the convenience and brevity of the description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0178] In several embodiments provided by the present application, it should be understood that the disclosed system, device and method can be implemented by other means. For example, the above-described device embodiments are merely illustrative, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed units can be indirect coupling or communication connection through some interfaces, devices or units, and can be electrical, mechanical or other forms.

[0179] The units described as separate components can or can not be physically separate, and the components displayed as units can or can not be physical units, i.e., can be located in one place, or can be distributed on multiple network units. Part or all of the units can be selected according to actual needs to realize the purpose of the method embodiment scheme.

[0180] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit.

[0181] If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application or the parts of the present application that essentially contribute to the prior art can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the coding method described in the various embodiments of the present application. The aforementioned storage medium includes a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various program code storage media.

[0182] The embodiments of the present application also provide a computer readable storage medium, which stores a computer program. The computer program is executed by a processor to perform the operation steps of the methods.

[0183] The computer storage medium of the embodiments of the present application can adopt any combination of one or more computer readable media. The computer readable medium can be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium can be, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or apparatus, or any combination of the above. More specific examples (non-exhaustive list) of the computer readable storage medium include an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this document, the computer readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, device or apparatus.

[0184] The computer readable signal medium can include a data signal propagated in a baseband or as a part of a carrier wave, in which a computer readable program code is borne. Such a propagated data signal can take various forms, including but not limited to an electromagnetic signal, an optical signal or any suitable combination of the above. The computer readable signal medium can also be any computer readable medium that is not a computer readable storage medium and that can transmit, propagate or transport a program for use by or in connection with an instruction execution system, device or apparatus.

[0185] The program code embodied on the computer readable media can be transmitted using any appropriate medium, including, but not limited to, wireless, wire line, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0186] Computer program code for carrying out operations of the present application can be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider).

[0187] Note that the above merely describes the preferred embodiments of the present application and the principles of the technology applied. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and that various obvious changes, reconfigurations and substitutions can be made without departing from the scope of the present application. Therefore, although the present application has been described in detail through the above embodiments, the present application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the concept of the present application, and all of them belong to the protection scope of the present application.

Claims

1. A decoding method of a polar code, characterized by, The method comprises the following steps: obtaining a code block sequence of a polar code; performing a round of SC decoding on M bits obtained from the code block sequence in sequence in a maximum of L SC decoders, wherein the round of SC decoding is performed on the surviving paths of the previous round, and M bits are extended in parallel to generate candidate paths, and a maximum of L surviving paths in the current round are obtained from the candidate paths; when the SC decoding of the code block sequence is completed, the bit information of the final surviving path with the minimum path metric value is selected as the decoding result, wherein the path metric value is inversely changed with the probability of correct decoding of the corresponding bit information; wherein the round of SC decoding is performed on the surviving paths of the previous round, and M bits are extended in parallel to generate candidate paths, comprising: The current acquired M-bit decoding result is traversed in parallel to obtain two M extended paths; each of the extended paths and any of the survivor paths of the last round form a candidate path, which is used to select the current survivor path.

2. The decoding method of claim 1, wherein, when the code block sequence comprises a plurality of sub-block sequences and each sub-block sequence comprises a plurality of CRC check bits, further comprising: when any sub-block sequence is added to the candidate paths, performing CRC check on the bit information of the candidate paths, and deleting the candidate paths that fail to pass the CRC check.

3. The decoding method of claim 2, wherein, Further comprising: de-interleaving between the sub-blocks before the CRC check.

4. The decoding method of claim 1, wherein, L is equal to 2M-1.

5. The decoding method of claim 1, wherein, M is equal to 4, and L is equal to 8.

6. The decoding method of any one of claims 1 to 5, wherein, The step of obtaining a maximum of L surviving paths comprises: bit-iterating and LLR-iterating the bit information of one of the surviving paths of the previous round with the obtained M bits in one SC decoder to obtain the final LLR of the current M bits extended on the surviving path of the previous round; obtaining the path metric value of each candidate path according to the final LLR and the path metric value of each surviving path of the previous round; selecting L paths with the minimum path metric value from the current candidate paths as the surviving paths of the current round, and retaining the corresponding path metric values.

7. A decoding apparatus of a polar code, characterized by comprising: comprising an obtaining module, an iterative decoding module, and an output module; the obtaining module is configured to obtain a code block sequence of a polar code; the iterative decoding module is configured to perform a round of SC decoding on M bits obtained from the code block sequence in sequence in a maximum of L SC decoders, wherein the round of SC decoding is performed on the surviving paths of the previous round, and M bits are extended in parallel to generate candidate paths, and a maximum of L surviving paths in the current round are obtained from the candidate paths, and the path metric value of each surviving path, wherein the path metric value is inversely changed with the probability of correct decoding of the corresponding bit information; the output module is configured to select the bit information of the surviving path with the minimum path metric value in the final surviving path as the decoding result when the SC decoding of the code block sequence is completed. The iterative decoding module comprises a path traversal module, configured to traverse the decoding result of the current acquired M bits in parallel to obtain two M extended paths; each of the extended paths forms a candidate path with any of the survivor paths of the previous round, used to select the current survivor path.

8. A computing device, comprising: comprising: a bus; a communication interface connected to the bus; at least one processor connected to the bus; and at least one memory connected to the bus and storing program instructions, wherein the program instructions, when executed by the at least one processor, cause the at least one processor to perform the decoding method of any one of claims 1 to 6.

9. A computer-readable storage medium having stored thereon program instructions, wherein, The program instructions, when executed by a computer, cause the computer to perform the decoding method of any one of claims 1 to 6.

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