Insulated gate bipolar transistor and method of manufacturing the same

Abstract

The application provides an insulated gate bipolar transistor and a manufacturing method thereof, and relates to the fields of semiconductor power devices and manufacturing. In order to effectively reduce the on-voltage drop, the hole concentration in the N-type charge storage layer will significantly increase, which will cause the field intensity in the N-type charge storage layer to exponentially increase when the insulated gate bipolar transistor is in reverse blocking, and the collector-emitter reverse blocking voltage to decrease. In the embodiment, a part of the conductive channel is replaced by a first P+ region, the introduction of the first P+ region can make the field intensity in the N-type charge storage layer decrease and share the rising field intensity with the N-drift region. However, the introduction of the first P+ region will reduce the conductance modulation effect of the N-type charge storage layer, so the N+ intercepting region, the trench intercepting region and the hole extraction region arranged along the extension direction of the trench in the first P+ region are repeatedly arranged, the extraction rate of the key carrier holes is artificially adjusted, and the balance problem of the saturation voltage drop, the reverse cut-off voltage, the short circuit characteristic and the switching speed can be solved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor power devices and manufacturing, and in particular, to an insulated gate bipolar transistor and a manufacturing method thereof. BACKGROUND

[0002] Insulated Gate Bipolar Transistor (IGBT) is a composite full-controlled voltage-driven power semiconductor device composed of BJT (bipolar transistor) and insulated gate field effect transistor. IGBT combines the advantages of the above two devices, has small driving power and low saturation voltage drop, and becomes an indispensable core device in modern power electronics technology. IGBT is developing towards higher current density and higher withstand voltage. In order to improve the current density, the saturation voltage drop needs to be reduced. In the components of the saturation voltage drop, the bulk resistance region determined by the degree of conductive modulation is the most important part. The degree of conductive modulation of IGBT products is not uniform, and the closer to the positive surface, the lower the degree of conductive modulation. Therefore, the concept of charge storage layer is introduced. With the increase of the doping concentration of the charge storage layer, the holding effect on the minority carriers will increase, which further reduces the saturation voltage drop. However, after increasing to a certain extent, the reverse blocking voltage of IGBT will also be reduced. With the increase of current density, the short-circuit resistance of IGBT will also be reduced, the switching speed will be slow and inconsistent, and the parameters of IGBT are mutually restricted, so a compromise design is needed. SUMMARY

[0003] In order to overcome the technical problems mentioned in the above technical background, the embodiments of the present application provide an insulated gate bipolar transistor and a manufacturing method thereof.

[0004] In a first aspect of the present application, an insulated gate bipolar transistor is provided, which comprises a plurality of three-dimensionally distributed unit cell structures, each of the unit cell structures comprising:

[0005] an N-drift region, an N-type charge storage layer, a P-type semiconductor region, a first P+ region, a second P+ region and an emitter metal layer which are sequentially stacked, wherein the junction depth of the first P+ region is greater than the junction depth of the second P+ region;

[0006] The unit cell structure further comprises a gate region and a source region. The gate region comprises a plurality of trenches extending from the P-type semiconductor region to the N-drift region, a gate oxide layer on the surface of the trench, a polysilicon gate on the surface of the gate oxide layer, and a gate-source isolation region. The gate region and the source region are isolated by the gate-source isolation region. The emitter metal layer covers the gate-source isolation region and the P-type semiconductor region.

[0007] The first P+ region is located between adjacent trenches of the gate region, and the second P+ region is located between the gate region and the source region.

[0008] The unit cell structure further comprises an N+ intercept region, a trench intercept region and a hole extraction region of a first P+ region in the gate region, wherein the unit cell structure comprises a plurality of repeated structures of the N+ intercept region and the trench intercept region.

[0009] In a possible embodiment of the present application, the first P+ region extends from the P-type semiconductor region to the N-drift region, and the junction depth of the first P+ region is greater than the depth of the trench.

[0010] The second P+ region extends from the P-type semiconductor region to the N-drift region, and the junction depth of the second P+ region is less than the film thickness of the P-type semiconductor region.

[0011] In a possible embodiment of the present application, the N+ intercept region, the trench intercept region and the hole extraction region are repeatedly arranged along the extension direction of the trench on the surface of the unit cell structure.

[0012] In a possible embodiment of the present application, in each unit cell structure,

[0013] The number of trenches is at least 3.

[0014] The number of N+ intercept regions is 2-10, the number of trench intercept regions is 1-5, and the number of hole extraction regions is 1-2.

[0015] In a possible embodiment of the present application, the unit cell structure further comprises: a collector metal region, a P-type collector region and an N-type electric field cutoff layer region which are sequentially stacked.

[0016] The N-drift region is located on the side of the N-type electric field cutoff layer region away from the collector metal region.

[0017] In a second aspect of the present application, a manufacturing method of an insulated gate bipolar transistor is provided, and the method comprises:

[0018] An N-type single crystal silicon is provided.

[0019] An N-type charge storage region is formed on a first surface of the N-type single crystal silicon.

[0020] A first P+ region is formed on the first surface of the N-type single crystal silicon.

[0021] A trench is formed on the first surface of the N-type single crystal silicon.

[0022] A gate oxide layer and a trench intercept region are formed by diffusion oxidation treatment.

[0023] depositing polysilicon on the surface of the gate oxide layer to obtain a polysilicon gate;

[0024] forming a P-type semiconductor region on both sides of the trench;

[0025] forming a source region and an N+ intercept region on the first surface of the N-type single crystal silicon;

[0026] forming a second P+ region on the first surface of the N-type single crystal silicon;

[0027] forming a gate-source isolation region and a hole extraction region on the first surface of the N-type single crystal silicon, wherein the gate oxide layer, the polysilicon gate, and the gate-source isolation region form a gate region;

[0028] forming an emitter metal layer on the first surface of the N-type single crystal silicon.

[0029] In a possible embodiment of the present application, the step of forming a trench on the first surface of the N-type single crystal silicon comprises:

[0030] coating a photoresist layer on the first surface of the N-type single crystal silicon;

[0031] forming a photoresist pattern by exposing and developing the photoresist layer to expose the region where the trench is to be formed;

[0032] etching the N-type single crystal silicon by dry etching to form a trench on the first surface of the N-type single crystal silicon.

[0033] In a possible embodiment of the present application, the step of forming a source region and an N+ intercept region on the first surface of the N-type single crystal silicon comprises:

[0034] coating a photoresist layer on the first surface of the N-type single crystal silicon;

[0035] forming a photoresist pattern by exposing and developing the photoresist layer to expose the region where the source region and the N+ intercept region are to be formed;

[0036] forming the source region and the N+ intercept region on the first surface of the N-type single crystal silicon by implanting phosphorus ions or arsenic ions.

[0037] In a possible embodiment of the present application, the step of forming a gate-source isolation region and a hole extraction region on the first surface of the N-type single crystal silicon comprises:

[0038] depositing boron phosphorus silicon glass on the first surface of the N-type single crystal silicon, and performing dry etching on the boron phosphorus silicon glass to form the gate-source isolation region and the hole extraction region.

[0039] In a possible embodiment of the present application, the method further comprises:

[0040] forming an N-type electric field cutoff layer region on the second surface of the N-type single crystal silicon;

[0041] forming a P-type collector region on the second surface of the N-type single crystal silicon;

[0042] forming a collector metal region on the P-type collector region.

[0043] In the above structure provided by the embodiments of the present application, to effectively reduce the on-voltage drop, the hole concentration in the N-type charge storage layer will significantly increase, which will result in an exponential increase of the field strength in the N-type charge storage layer when the insulated gate bipolar transistor is in reverse blocking, and finally result in a decrease of the collector-emitter reverse blocking voltage. In the embodiments, a part of the conductive channel is replaced by the first P+ region, and the introduction of the first P+ region can decrease the field strength in the N-type charge storage layer and share the increased field strength with the N-drift region. However, the introduction of the first P+ region will decrease the effect of conductance modulation of the N-type charge storage layer, and therefore the N+ intercepting regions, the trench intercepting regions and the hole extraction regions arranged along the extension direction of the trench in the first P+ region can artificially adjust the extraction rate of the key carrier holes, and can solve the balance problem of the saturation voltage drop, the reverse blocking voltage, the short circuit characteristic and the switching speed (including consistency) of the insulated gate bipolar transistor. BRIEF DESCRIPTION OF DRAWINGS

[0044] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation to the scope, and for those skilled in the art, other related drawings can also be obtained without creative labor on the basis of the drawings.

[0045] Figure 1 A front view of a unit cell structure of the insulated gate bipolar transistor provided by the embodiments of the present application.

[0046] Figure 2 A front view of a unit cell structure of the insulated gate bipolar transistor provided by the embodiments of the present application. Figure 1 A film layer structure schematic diagram of the unit cell structure in the y-axis direction.

[0047] Figure 3 A step schematic diagram of the manufacturing method of the insulated gate bipolar transistor provided by the embodiments of the present application.

[0048] Figure 4 A step schematic diagram of the manufacturing method of the insulated gate bipolar transistor provided by the embodiments of the present application. Figure 5 A step schematic diagram of the manufacturing method of the insulated gate bipolar transistor provided by the embodiments of the present application. Figure 3 A process flow diagram corresponding to the method.

[0049] Figure legend:

[0050] 10 - N-type single crystal silicon; 101 - emitter metal layer; 102 - first P+ region; 103 - source region; 104 - second P+ region; 105 - P-type semiconductor region; 106 - N-type charge storage layer; 107 - N-drift region; 108 - N-type electric field stop layer region; 109 - P-type collector region; 110 - collector metal region; 111 - gate oxide layer; 112 - polysilicon gate; 113 - gate-source isolation region; 114 - N+ intercept region; 115 - trench intercept region; 116 - hole extraction region; 120 - trench. DETAILED DESCRIPTION

[0051] In order to make the objects, technical solutions, and advantages of the embodiments of the present application clearer, the following will be combined with the accompanying drawings for the embodiments of the present application to make a clear and complete description of the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the accompanying drawings can be arranged and designed in various different configurations.

[0052] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without making creative efforts are within the scope of protection of the present application.

[0053] It should be noted that: similar reference numerals and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.

[0054] In the description of the present application, unless explicitly defined and limited, the terms "set", "connected", and "connection" should be understood in a broad sense, for example, can be fixed connection, can also be detachable connection, or integrally connected; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through an intermediate medium, can be the communication inside two elements. For those of ordinary skill in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0055] In order to improve the technical problems mentioned in the background art, the embodiments of the present application provide an insulated gate bipolar transistor, please refer to Figure 1 and Figure 2 , Figure 1 A front view of a unit cell structure of the insulated gate bipolar transistor provided in the present embodiment, Figure 2 A film layer structure schematic diagram of the unit cell structure in the AA' direction provided in the present embodiment. The insulated gate bipolar transistor provided in the present embodiment can include a plurality of three-dimensionally distributed unit cell structures, the following will be combined withFigure 1 and Figure 2 The single cell structure is described in detail.

[0056] The single cell structure can include N-drift region 107, N-type charge storage layer 106, P-type semiconductor region 105, first P+ region 102, second P+ region 104 and emitter metal layer 101 arranged in sequence, wherein the junction depth of first P+ region 102 is greater than that of second P+ region 104 in the vertical direction of N-drift region 107 film layer.

[0057] The single cell structure can also include gate region (not shown in the figure) and source region 103, the gate region can include a plurality of trenches extending from P-type semiconductor region 105 to N-drift region 107 (Z-axis direction in the figure), gate oxide layer 111 on the surface of the trench, polysilicon gate 112 on the surface of gate oxide layer 111, and gate-source isolation region 113, the gate region and source region 102 can be isolated by gate-source isolation region 113, and emitter metal layer 101 covers gate-source isolation region 113 and P-type semiconductor region 105. First P+ region 102 is located between adjacent trenches of the gate region, and second P+ region 104 is located between the gate region and source region 103.

[0058] The single cell structure can also include N+ intercept region 114, trench intercept region 115 and hole extraction region 116 arranged in the first P+ region 102 in the gate region and repeatedly arranged along the extension direction (Z-axis direction in the figure) of the trench on the surface of the single cell structure, wherein the single cell structure includes a plurality of repeated structures of N+ intercept region 114 and trench intercept region 115.

[0059] In the above structure, in order to effectively reduce the on-state voltage drop, the hole concentration in N-type charge storage layer 106 will increase significantly, which will cause the field strength in N-type charge storage layer 106 to increase exponentially when the insulated gate bipolar transistor is in reverse blocking, and finally the collector-emitter reverse blocking voltage will decrease. A part of the conductive channel is replaced by first P+ region 102, and the introduction of first P+ region 102 can reduce the field strength in N-type charge storage layer 106 and share the rising field strength with N-drift region 107. However, the introduction of first P+ region 102 will reduce the effect of conductance modulation of N-type charge storage layer 106, so the repeated arrangement of N+ intercept region 114, trench intercept region 115 and hole extraction region 116 in the extension direction of the trench in first P+ region 102 can artificially adjust the extraction rate of key carrier holes, and can solve the balance problem of the saturation voltage drop, reverse cutoff voltage, short circuit characteristic and switching speed (including consistency) of the insulated gate bipolar transistor.

[0060] Further, in the embodiment, the first P+ region 102 extends from the P-type semiconductor region 105 to the N-drift region 107 (the Z-axis direction in the figure), and the junction depth of the first P+ region 102 is greater than the depth of the trench. The second P+ region 104 extends from the P-type semiconductor region 105 to the N-drift region 107, and the junction depth of the second P+ region 104 is less than the film thickness of the P-type semiconductor region 105.

[0061] Further, in the embodiment, in each unit cell structure, the number of trenches can be at least 3, the number of N+ interception regions 114 can be 2-10, the number of trench interception regions 115 can be 1-5, and the number of hole extraction regions 116 can be 1-2.

[0062] Further, in the embodiment, the unit cell structure can further include: a collector metal region 110, a P-type collector region 109, and an N-type electric field cutoff layer region 108 which are sequentially stacked;

[0063] The N-drift region 107 is located on the side of the N-type electric field cutoff layer region 108 away from the collector metal region 110.

[0064] The embodiment also provides a manufacturing method of an insulated gate bipolar transistor. Please refer to Figures 3-5 , wherein Figure 3 is a step diagram of the manufacturing method of the insulated gate bipolar transistor provided by the embodiment, Figure 4 , and Figure 5 is Figure 3 a corresponding process diagram. The following will introduce in detail the manufacturing method of the insulated gate bipolar transistor provided by the embodiment. Figures 3-5

[0065] Step S11, providing an N-type single crystal silicon.

[0066] In this step, part of the N-type single crystal silicon can be used as the N-drift region 107, and the resistivity of the N-type single crystal silicon can range from 20 to 200 Ω·cm.

[0067] Step S12, forming an N-type charge storage region on a first surface of the N-type single crystal silicon.

[0068] In this step, the N-type charge storage region 106 can be formed on the first surface of the N-type single crystal silicon by phosphorus ion implantation and diffusion.

[0069] Step S13, forming a first P+ region on the first surface of the N-type single crystal silicon.

[0070] In this step, the first P+ region 102 can be formed on the first surface of the N-type single crystal silicon by photolithography, boron ion implantation, and diffusion push junction. ​

[0071] Step S14, forming a trench on the first surface of the N-type single crystal silicon.

[0072] In this embodiment, step S14 can be implemented by the following way:

[0073] First, coating a photoresist layer on the first surface of the N-type single crystal silicon;

[0074] Next, forming a photoresist pattern exposing the region where the trench 120 will be made by exposing and developing the photoresist layer;

[0075] Then, etching the N-type single crystal silicon by dry etching method to form the trench 120 on the first surface of the N-type single crystal silicon;

[0076] Finally, removing the residual photoresist layer.

[0077] In this embodiment, the width of the trench can be 0.3 microns to 2 microns, and the depth of the trench 120 can be 4 microns to 11 microns.

[0078] Step S15, forming a gate oxide layer and a trench intercept region by diffusion oxidation treatment.

[0079] In this step, diffusion oxidation treatment is performed on the surface of the trench to form a gate oxide layer 111, and the thickness of the gate oxide layer 111 can be 800 angstroms to 2000 angstroms. Here, a layer of silicon nitride can also be deposited on the oxide layer to form a composite layer, and the thickness of the silicon nitride can be 100 angstroms to 1000 angstroms. For reference Figure 1 A trench intercept region 115 is formed between adjacent trenches 120.

[0080] Step S16, depositing polysilicon on the surface of the gate oxide layer to obtain a polysilicon gate.

[0081] In this step, polysilicon can be deposited on the surface of the gate oxide layer 111 and subjected to polysilicon photolithography to form a polysilicon gate 112.

[0082] Step S17, forming a P-type semiconductor region on both sides of the trench.

[0083] In this step, a P-type semiconductor region 105 can be formed on both sides of the trench by boron ion implantation and diffusion push joint.

[0084] Step S18, forming a source region and an N+ intercept region on the first surface of the N-type single crystal silicon.

[0085] In combination Figure 1 In this embodiment, step S18 can be implemented by the following way:

[0086] First, coating a photoresist layer on the first surface of the N-type single crystal silicon;

[0087] Next, the photoresist layer is exposed and developed to form a photoresist pattern exposing the region where the source region 103 and the N+ intercept region 114 are to be formed;

[0088] Then, the source region 103 and the N+ intercept region 114 are formed by implanting phosphorus ions or arsenic ions into the first surface of the N-type single crystal silicon;

[0089] Finally, the remaining photoresist layer is removed.

[0090] Step S19, a second P+ region is formed on the first surface of the N-type single crystal silicon.

[0091] In this step, the second P+ region 104 can be formed on the first surface of the N-type single crystal silicon by photolithography, boron ion implantation, and diffusion push bonding.

[0092] Step S20, a gate-source isolation region and a hole extraction region are formed on the first surface of the N-type single crystal silicon.

[0093] The gate oxide layer 111, the polysilicon gate 112, and the gate-source isolation region 113 form a gate region.

[0094] In this step, please refer again to Figure 1 The boron phosphorus silicon glass can be deposited on the first surface of the N-type single crystal silicon, and dry etching is performed on the boron phosphorus silicon glass to form the gate-source isolation region 113 and the hole extraction region 116.

[0095] Step S21, a emitter metal layer is formed on the first surface of the N-type single crystal silicon.

[0096] The metal is deposited on the first surface of the N-type single crystal silicon to form the emitter metal layer 101.

[0097] Step S22, an N-type field stop layer region is formed on the second surface of the N-type single crystal silicon.

[0098] In this step, the second surface of the N-type single crystal silicon opposite to the first surface is thinned, and phosphorus ions are implanted to form the N-type field stop layer region.

[0099] Step S23, a P-type collector region is formed on the second surface of the N-type single crystal silicon.

[0100] Step S24, a collector metal region is formed on the P-type collector region.

[0101] In summary, the insulated gate bipolar transistor and the manufacturing method thereof provided by the embodiments of the present application can effectively reduce the on-state voltage drop, and the hole concentration in the N-type charge storage layer will significantly increase, which will cause the field strength in the N-type charge storage layer to exponentially increase when the insulated gate bipolar transistor is in reverse blocking, and finally the collector-emitter reverse blocking voltage will decrease. The first P+ region is used to replace a part of the conductive channel, and the introduction of the first P+ region can make the field strength in the N-type charge storage layer decrease and share the increased field strength with the N-drift region. However, the introduction of the first P+ region will reduce the conductance modulation effect of the N-type charge storage layer, so the N+ intercepting region, the trench intercepting region and the hole extraction region arranged repeatedly along the extension direction of the trench in the first P+ region can artificially adjust the extraction rate of the key carrier holes, and the balance problem of the saturated voltage drop, the reverse blocking voltage, the short circuit characteristic and the switching speed (including consistency) of the insulated gate bipolar transistor can be solved at the same time.

[0102] The preferred embodiments of the present application have been described above with the preferred embodiments of the present application, but are not intended to limit the present application. Those skilled in the art can make various modifications and changes to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An insulated gate bipolar transistor, characterized by, The insulated gate bipolar transistor comprises a plurality of three-dimensionally distributed unit cell structures, and each unit cell structure comprises: An N-drift region, an N-type charge storage layer, a P-type semiconductor region, a first P+ region, a second P+ region, and an emitter metal layer are sequentially stacked; The unit cell structure further comprises a gate region and a source region, the gate region comprises a plurality of trenches extending from the P-type semiconductor region to the N-drift region, a gate oxide layer on the surface of the trench, a polysilicon gate on the surface of the gate oxide layer, and a gate-source isolation region, the gate region and the source region are isolated by the gate-source isolation region, and the emitter metal layer covers the gate-source isolation region and the P-type semiconductor region; The first P+ region is located between adjacent trenches of the gate region, and the second P+ region is located between the gate region and the source region; The unit cell structure further comprises an N+ interception region, a trench interception region, and a hole extraction region of the first P+ region in the gate region, wherein the unit cell structure comprises a plurality of repeated structures of the N+ interception region and the trench interception region, the first P+ region is used to share the field strength with the N-type charge storage layer and the N-drift region, and the N+ interception region, the trench interception region, and the hole extraction region are used to adjust the extraction rate of holes.

2. The insulated gate bipolar transistor of claim 1, wherein, The first P+ region extends from the P-type semiconductor region to the N-drift region, and the junction depth of the first P+ region is greater than the depth of the trench; The second P+ region extends from the P-type semiconductor region to the N-drift region, and the junction depth of the second P+ region is less than the film thickness of the P-type semiconductor region.

3. The insulated gate bipolar transistor of claim 2, wherein the base region is formed by implanting a dopant of the first conductivity type into the collector region. The N+ interception region, the trench interception region, and the hole extraction region are repeatedly arranged along the extension direction of the trench on the surface of the unit cell structure.

4. The insulated gate bipolar transistor of claim 3, wherein the base region is formed by implanting a dopant of the first conductivity type into the collector region. In each unit cell structure, The number of trenches is at least 3; The number of N+ interception regions is 2-10, the number of trench interception regions is 1-5, and the number of hole extraction regions is 1-2.

5. The insulated gate bipolar transistor of any of claims 1-4, the unit cell structure further comprising: A collector metal region, a P-type collector region, and an N-type electric field cutoff layer region are sequentially stacked; The N-drift region is located on the side of the N-type electric field cutoff layer region away from the collector metal region.

6. A method of fabricating the insulated gate bipolar transistor of claim 1, wherein The method comprises: Providing an N-type single crystal silicon; Forming an N-type charge storage region on a first surface of the N-type single crystal silicon; Forming a first P+ region on the first surface of the N-type single crystal silicon; Forming a trench on the first surface of the N-type single crystal silicon; Forming a gate oxide layer and a trench interception region by diffusion oxidation treatment; Depositing polysilicon on the surface of the gate oxide layer to obtain a polysilicon gate; Forming a P-type semiconductor region in the region on both sides of the trench; Forming a source region and an N+ interception region on the first surface of the N-type single crystal silicon; Forming a second P+ region on the first surface of the N-type single crystal silicon; Forming a gate-source isolation region and a hole extraction region on the first surface of the N-type single crystal silicon, wherein the gate oxide layer, the polysilicon gate, and the gate-source isolation region form a gate region; Forming an emitter metal layer on the first surface of the N-type single crystal silicon.

7. The method of fabricating an insulated gate bipolar transistor of claim 6, wherein, The step of forming a trench on the first surface of the N-type single crystal silicon comprises: Coating a photoresist layer on the first surface of the N-type single crystal silicon; Forming a photoresist pattern by exposing and developing the photoresist layer to expose the area where the trench will be made; Etching the N-type single crystal silicon by dry etching to form a trench on the first surface of the N-type single crystal silicon.

8. The method of fabricating an insulated gate bipolar transistor of claim 6, wherein, The step of forming a source region and an N+intercept region on the first surface of the N-type single crystal silicon comprises: Coating a photoresist layer on the first surface of the N-type single crystal silicon; Forming a photoresist pattern by exposing and developing the photoresist layer to expose the area where the source region and the N+intercept region will be made; Forming the source region and the N+intercept region on the first surface of the N-type single crystal silicon by implanting phosphorus ions or arsenic ions.

9. The method of fabricating an insulated gate bipolar transistor of claim 6, wherein, The step of forming a gate-source isolation region and a hole extraction region on the first surface of the N-type single crystal silicon comprises: Depositing boron phosphorus silicon glass on the first surface of the N-type single crystal silicon and dry etching the boron phosphorus silicon glass to form the gate-source isolation region and the hole extraction region.

10. The method of fabricating an insulated gate bipolar transistor of claim 6, wherein, The method further comprises: Forming an N-type field stop layer region on the second surface of the N-type single crystal silicon; Forming a P-type collector region on the second surface of the N-type single crystal silicon; Making a collector metal region on the P-type collector region.

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