A GPIO and timer-based pwm signal generation method
By using a PWM signal generation method based on GPIO and timers, multiple PWM signals can be generated using the GPIO resources of the microcontroller, solving the problem of insufficient timers and PWM resources, realizing the control requirements of complex systems, and reducing production costs.
Patent Information
- Application Number
- CN202210667577.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-06-14
- Publication Date
- 2026-05-15
- Estimated Expiration
- 2042-06-14
AI Technical Summary
Existing microcontrollers have limited timer and PWM resources, which leads to resource waste and increased production costs, making it difficult to meet the control requirements of complex systems.
A PWM signal generation method based on GPIO and timers is adopted. The PWM signal is generated through the main program and timer interrupt service function, and combined with the PID closed-loop control algorithm for logical judgment and adjustment to realize the adjustment of duty cycle, phase shift angle and frequency.
It effectively utilizes the GPIO resources of the microcontroller to achieve multi-channel PWM output, reducing production costs and expanding the application scenarios of low-end microcontrollers, supporting the control of complex systems.
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Figure CN115133915B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of control, and in particular to a method for generating PWM signals based on GPIO and timers. Background Technology
[0002] Embedded microcontrollers are widely used in industrial fields. As a type of miniature computer, they play a crucial role in the safe and reliable operation of equipment. Embedded control commonly uses PWM modulation technology, which offers flexible and diverse functions. Duty cycle, phase shift angle, and frequency can be adjusted through software programming. It can be used not only as modulation pulses to control equipment but also as ordinary high and low level signals, communication timing signals, etc. As a highly effective technology for controlling analog circuits using the digital output of a microprocessor, it is widely used in many fields, from measurement and communication to power control and conversion.
[0003] Due to cost constraints, microcontrollers offer limited timer and PWM resources, resulting in simpler system structures and fewer parameters. Controlling complex systems requires more advanced microcontrollers, increasing costs. To achieve better system control, additional control parameters are often needed, which ordinary microcontrollers' PWM and timer resources often cannot meet. For example, the TMS320F28335 only has 18 PWM channels and three 32-bit CPU timers, offering limited timer and PWM resources, but it has 88 usable GPIO ports, leading to significant resource waste.
[0004] Currently, most microcontrollers used in my country are imported. Foreign manufacturers intentionally reduce timer and PWM resources to encourage users to choose more advanced microcontrollers, thereby increasing profits. Therefore, developing a PWM generation method that minimizes resource consumption and utilizes excess GPIO resources is of great significance for users to reduce production costs. Summary of the Invention
[0005] In order to overcome the above-mentioned shortcomings and deficiencies of the prior art, the purpose of this invention is to provide a PWM signal generation method based on GPIO and timers, which is suitable for embedded microcontrollers.
[0006] The objective of this invention is achieved through the following technical solution:
[0007] A method for generating PWM signals based on GPIO and timers, characterized by comprising:
[0008] The main program initializes various parameters based on user-defined values, calls the PWM generation subroutine to generate PWM and perform signal stop and judgment, and the parameters include CNT, Period, Duty, and Phase.
[0009] The timer interrupt service routine periodically enters the timer interrupt to perform the increment count function based on the initialized unit clock value, and calls the PWM generation subroutine to generate each PWM signal.
[0010] The PWM generation subroutine includes a single PWM duty cycle adjustment method, a single PWM phase shift angle adjustment method, a single PWM frequency adjustment method, and a hybrid PWM adjustment method. It performs logical judgments based on the CNT, Period, Duty, and Phase values, and sets the corresponding GPIO high or low to complete the PWM generation function. At the same time, when the conditions are met, it calls the PID closed-loop control algorithm to obtain the Period, Duty, and Phase values for the next cycle.
[0011] Furthermore, the main program initializes various parameters according to user-defined values, calls the PWM generation subroutine to generate PWM and perform signal stop and judgment. These parameters include CNT, Period, Duty, and Phase, specifically:
[0012] S1, System power-on, Microcontroller hardware initialization;
[0013] S2, initialization of parameters CNT, Period, Duty, and Phase;
[0014] S3, Timer interrupt clock configuration, the configured unit clock is the clock for CNT increment counting;
[0015] S4, check the switch signal. If the start signal is detected, proceed to the next step S5; otherwise, return to check the switch signal.
[0016] S5, run the timer interrupt service function to generate PWM pulses according to the logical timing sequence;
[0017] S6: Check the switch signal. If no stop signal is detected, return to the previous step S5; otherwise, end the program.
[0018] Furthermore, the timer interrupt service routine, based on the initialized unit clock value, periodically enters the timer interrupt to complete the incrementing count function, and calls the PWM generation subroutine to generate each PWM signal, specifically as follows:
[0019] S1, initialize the unit clock value i to 1;
[0020] S2, call the PWM generation logic subroutine module to generate the i-th PWM signal;
[0021] S3, i is incremented by 1;
[0022] S4: Determine if i is less than or equal to n. If yes, return to step S2; otherwise, end the program.
[0023] Furthermore, the PWM generation logic subroutine is specifically as follows:
[0024] S1, CNT i increments by 1;
[0025] S2, determine if CNT i is less than Period i. If the condition is not met, execute S3; if the condition is met, execute S4.
[0026] S3, call the PID closed-loop algorithm to perform calculations and obtain Period i, Duty i and Phase i for the next cycle to generate PWM for logic operations;
[0027] S4, determine whether CNT i is less than Duty i. If the condition is met, execute S6; otherwise, execute S7.
[0028] S5, CNT i count is cleared to zero, program ends and enters the next cycle;
[0029] S6, determine whether CNT i is less than Phase i. If the condition is met, execute S9; otherwise, execute S8.
[0030] S7, determine whether CNT i is less than Phase i + Duty i. If the condition is met, execute S10; otherwise, execute S11.
[0031] S8 sets GPIO i1 and GPIO i2 high, then terminates the program;
[0032] S9 sets GPIO i1 high and GPIO i2 low, then terminates the program;
[0033] S10: Set GPIO i1 low and GPIO i2 high, then terminate the program;
[0034] S11 sets GPIO i1 and GPIO i2 low, then terminates the program.
[0035] Furthermore, the implementation process of the PWM single duty cycle adjustment method is as follows:
[0036] In each cycle, the period value Period i remains unchanged, the phase shift angle Phase i remains at 0°, and only the duty cycle Duty i is changed. The execution process of its PWM generation subroutine is as follows:
[0037] During the t0–t1 phase: CNT i is less than Duty i, and its PWM generation subroutine runs along S1, S2, S4, S6, S8 in each interrupt cycle, setting GPIO i1 and GPIO i2 high. CNT i is incremented by 1 each time it runs until CNT i equals Duty i at time t1, at which point the program exits the current loop path.
[0038] During the t1–t2 phase: CNT i is greater than Duty i, and its PWM generation subroutine runs along S1, S2, S4, S7, S11 in each interrupt cycle, setting GPIO i1 and GPIO i2 low. CNT i is incremented by 1 each time it runs until CNT i equals Period i at time t2, at which point the program exits the current loop path.
[0039] At time t2, CNT i equals Period i. Its PWM generation subroutine runs along S1, S2, S3, and S5 to obtain Period i, Duty i, and Phase i for the next cycle, and clears CNT i to zero, causing the program to enter the logic execution of the next PWM cycle.
[0040] During the t2–t3 phase: CNT i is less than Duty i, and its PWM generation subroutine runs along S1, S2, S4, S6, S8 in each interrupt cycle, setting GPIO i1 and GPIO i2 high. CNT i is incremented by 1 each time it runs until CNT i equals Duty i at time t3, at which point the program exits the current loop path.
[0041] During the t3–t4 phase: CNT i is greater than Duty i, and its PWM generation subroutine runs along S1, S2, S4, S7, S11 in each interrupt cycle, setting GPIO i1 and GPIO i2 low. CNT i is incremented by 1 each time it runs until CNT i equals Period i at time t4, at which point the program exits the current loop path.
[0042] At time t4, CNT i equals Period i. Its PWM generation subroutine runs along S1, S2, S3, and S5 to obtain Period i, Duty i, and Phase i for the next cycle, and clears CNT i to zero, causing the program to enter the logic execution of the next PWM cycle.
[0043] During the t4–t5 phase: CNT i is less than Duty i, and its PWM generation subroutine runs along S1, S2, S4, S6, S8 in each interrupt cycle, setting GPIO i1 and GPIO i2 high. CNT i is incremented by 1 each time it runs until CNT i equals Duty i at time t5, at which point the program exits the current loop path.
[0044] During the t5–t6 phase: CNT i is greater than Duty i, and its PWM generation subroutine runs along S1, S2, S4, S7, S11 in each interrupt cycle, setting GPIO i1 and GPIO i2 low. CNT i is incremented by 1 each time it runs until CNT i equals Period i at time t6, at which point the program exits the current loop path.
[0045] At time t6, CNT i equals Period i. Its PWM generation subroutine runs along S1, S2, S3, and S5 to obtain Period i, Duty i, and Phase i for the next cycle, and clears CNT i to zero, causing the program to enter the logic execution of the next PWM cycle.
[0046] The program repeats this process, continuously obtaining new duty cycles and entering new PWM adjustment cycles.
[0047] Furthermore, the implementation process of the PWM single phase shift angle adjustment method is as follows:
[0048] In each cycle, the cycle value Period i and the duty cycle Duty i remain constant, only the phase shift angle Phasei is changed. The PWM generation subroutine runs as follows:
[0049] t0–t1 phase: Phase i is 0, CNT i is less than Duty i, and its PWM generation subroutine runs along S1, S2, S4, S6, S8 in each interrupt cycle, setting GPIO i1 and GPIO i2 high, and incrementing CNT i by 1 each time it runs, until CNT i equals Duty i at time t1, and the program exits this loop path.
[0050] t1–t2 phase: Phase i is 0, CNT i is greater than Duty i, and its PWM generation subroutine runs along S1, S2, S4, S7, S11 in each interrupt cycle, setting GPIO i1 and GPIO i2 low, and incrementing CNT i by 1 each time it runs, until CNT i equals Period i at time t2, and the program exits this loop path.
[0051] At time t2, CNT i equals Period i. Its PWM generation subroutine runs along S1, S2, S3, and S5 to obtain Period i, Duty i, and Phase i for the next cycle, and clears CNT i to zero, causing the program to enter the logic execution of the next PWM cycle.
[0052] During the t2–t3 phase: Phase i is not 0, CNT i is less than Duty i, and CNT i is less than Phase i. The PWM generation subroutine runs along S1, S2, S4, S6, and S9 in each interrupt cycle, setting GPIO i1 high and GPIO i2 low. CNT i is incremented by 1 each time the program runs until CNT i equals Phase i at time t3, at which point the program exits the current loop path.
[0053] During the t3–t4 phase: Phase i is not 0, CNT i is less than Duty i, and CNT i is greater than Phase i. The PWM generation subroutine runs along S1, S2, S4, S6, and S8 in each interrupt cycle, setting GPIO i1 and GPIO i2 high. CNTi is incremented by 1 each time the program runs until CNT i equals Duty i at time t4, at which point the program exits the current loop path.
[0054] During the t4–t5 phase: Phase i is not 0, CNT i is greater than Duty i, and CNT i is less than Duty i + Phase i. The PWM generation subroutine runs along S1, S2, S4, S7, and S10 in each interrupt cycle, setting GPIO i1 low and GPIO i2 high. CNT i is incremented by 1 each time the program runs until CNT i equals Duty i + Phase i at time t5, at which point the program exits the current loop path.
[0055] During the t5–t6 phase: Phase i is not 0, CNT i is greater than Duty i, and CNT i is greater than Duty i + Phase i. The PWM generation subroutine runs along S1, S2, S4, S7, and S11 in each interrupt cycle, setting GPIO i1 and GPIO i2 low. CNT i is incremented by 1 each time the program runs until CNT i equals Duty i + Phase i at time t5, at which point the program exits the current loop path.
[0056] At time t6, CNT i equals Period i. Its PWM generation subroutine runs along S1, S2, S3, and S5 to obtain Period i, Duty i, and Phase i for the next cycle, and clears CNT i to zero, causing the program to enter the logic execution of the next PWM cycle.
[0057] During the t6–t7 phase: Phase i is not 0, CNT i is less than Duty i, and CNT i is less than Phase i. The PWM generation subroutine runs along S1, S2, S4, S6, and S9 in each interrupt cycle, setting GPIO i1 high and GPIO i2 low. CNT i is incremented by 1 each time the program runs until CNT i equals Phase i at time t7, at which point the program exits the current loop path.
[0058] During the t7–t8 phase: Phase i is not 0, CNT i is less than Duty i, and CNT i is greater than Phase i. The PWM generation subroutine runs along S1, S2, S4, S6, and S8 in each interrupt cycle, setting GPIO i1 and GPIO i2 high. CNTi is incremented by 1 each time the program runs until CNT i equals Duty i at time t8, at which point the program exits the current loop path.
[0059] During the t8–t9 phase: Phase i is not 0, CNT i is greater than Duty i, and CNT i is less than Duty i + Phase i. The PWM generation subroutine runs along S1, S2, S4, S7, and S10 in each interrupt cycle, setting GPIO i1 low and GPIO i2 high. CNT i is incremented by 1 each time the program runs until CNT i equals Duty i + Phase i at time t9, at which point the program exits the current loop path.
[0060] t9–t 10 Phase: When Phase i is not 0, CNT i is greater than Duty i, and CNT i is greater than Duty i + Phase i, the PWM generation subroutine runs along S1, S2, S4, S7, S11 in each interrupt cycle, setting GPIO i1 and GPIO i2 low, and incrementing CNT i by 1 with each run, until t 10 When CNT i equals Duty i + Phase i, the program exits the current loop path.
[0061] t 10 At time 1, CNT i equals Period i. Its PWM generation subroutine runs along S1, S2, S3, S5 to obtain Period i, Duty i, and Phase i for the next cycle, and clears CNT i to zero, causing the program to enter the logic execution of the next PWM cycle.
[0062] The program repeats this process, continuously obtaining new phase shift angles and entering new PWM adjustment cycles.
[0063] Furthermore, the implementation process of the PWM single frequency adjustment method is as follows:
[0064] In each cycle, the duty cycle (Duty i) remains constant, the phase shift angle (Phase i) is 0, and only the period value (Period i) changes. The execution process of its PWM generation subroutine is as follows:
[0065] During the t0–t1 phase: CNT i is less than Duty i, and its PWM generation subroutine runs along S1, S2, S4, S6, S8 in each interrupt cycle, setting GPIO i1 and GPIO i2 high. CNT i is incremented by 1 each time it runs until CNT i equals Duty i at time t1, at which point the program exits the current loop path.
[0066] During the t1–t2 phase: CNT i is greater than Duty i, and its PWM generation subroutine runs along S1, S2, S4, S7, S11 in each interrupt cycle, setting GPIO i1 and GPIO i2 low. CNT i is incremented by 1 each time it runs until CNT i equals Period i at time t2, at which point the program exits the current loop path.
[0067] At time t2, CNT i equals Period i. Its PWM generation subroutine runs along S1, S2, S3, and S5 to obtain Period i, Duty i, and Phase i for the next cycle, and clears CNT i to zero, causing the program to enter the logic execution of the next PWM cycle.
[0068] During the t2–t3 phase: CNT i is less than Duty i, and its PWM generation subroutine runs along S1, S2, S4, S6, S8 in each interrupt cycle, setting GPIO i1 and GPIO i2 high. CNT i is incremented by 1 each time it runs until CNT i equals Duty i at time t3, at which point the program exits the current loop path.
[0069] During the t3–t4 phase: CNT i is greater than Duty i, and its PWM generation subroutine runs along S1, S2, S4, S7, S11 in each interrupt cycle, setting GPIO i1 and GPIO i2 low. CNT i is incremented by 1 each time it runs until CNT i equals Period i at time t4, at which point the program exits the current loop path.
[0070] At time t4, CNT i equals Period i. Its PWM generation subroutine runs along S1, S2, S3, and S5 to obtain Period i, Duty i, and Phase i for the next cycle, and clears CNT i to zero, causing the program to enter the logic execution of the next PWM cycle.
[0071] During the t4–t5 phase: CNT i is less than Duty i, and its PWM generation subroutine runs along S1, S2, S4, S6, S8 in each interrupt cycle, setting GPIO i1 and GPIO i2 high. CNT i is incremented by 1 each time it runs until CNT i equals Duty i at time t5, at which point the program exits the current loop path.
[0072] During the t5–t6 phase: CNT i is greater than Duty i, and its PWM generation subroutine runs along S1, S2, S4, S7, S11 in each interrupt cycle, setting GPIO i1 and GPIO i2 low. CNT i is incremented by 1 each time it runs until CNT i equals Period i at time t6, at which point the program exits the current loop path.
[0073] At time t6, CNT i equals Period i. Its PWM generation subroutine runs along S1, S2, S3, and S5 to obtain Period i, Duty i, and Phase i for the next cycle, and clears CNT i to zero, causing the program to enter the logic execution of the next PWM cycle.
[0074] The program repeats this process, continuously obtaining new period values and entering a new PWM adjustment cycle.
[0075] Furthermore, the implementation process of the PWM hybrid control method is as follows:
[0076] In each cycle, the duty cycle (Duty i), phase shift angle (Phase i), and period value (Period i) can all be changed. The execution process of its PWM generation subroutine is as follows:
[0077] t0–t1 phase: Phase i is 0, CNT i is less than Duty i, and its PWM generation subroutine runs along S1, S2, S4, S6, S8 in each interrupt cycle, setting GPIO i1 and GPIO i2 high, and incrementing CNT i by 1 each time it runs, until CNT i equals Duty i at time t1, and the program exits this loop path.
[0078] t1–t2 phase: Phase i is 0, CNT i is greater than Duty i, and its PWM generation subroutine runs along S1, S2, S4, S7, S11 in each interrupt cycle, setting GPIO i1 and GPIO i2 low, and incrementing CNT i by 1 each time it runs, until CNT i equals Period i at time t2, and the program exits this loop path.
[0079] At time t2, CNT i equals Period i. Its PWM generation subroutine runs along S1, S2, S3, and S5 to obtain Period i, Duty i, and Phase i for the next cycle, and clears CNT i to zero, causing the program to enter the logic execution of the next PWM cycle.
[0080] During the t2–t3 phase: Phase i is not 0, CNT i is less than Duty i, and CNT i is less than Phase i. The PWM generation subroutine runs along S1, S2, S4, S6, and S9 in each interrupt cycle, setting GPIO i1 high and GPIO i2 low. CNT i is incremented by 1 each time the program runs until CNT i equals Phase i at time t3, at which point the program exits the current loop path.
[0081] During the t3–t4 phase: Phase i is not 0, CNT i is less than Duty i, and CNT i is greater than Phase i. The PWM generation subroutine runs along S1, S2, S4, S6, and S8 in each interrupt cycle, setting GPIO i1 and GPIO i2 high. CNTi is incremented by 1 each time the program runs until CNT i equals Duty i at time t4, at which point the program exits the current loop path.
[0082] During the t4–t5 phase: Phase i is not 0, CNT i is greater than Duty i, and CNT i is less than Duty i + Phase i. The PWM generation subroutine runs along S1, S2, S4, S7, and S10 in each interrupt cycle, setting GPIO i1 low and GPIO i2 high. CNT i is incremented by 1 each time the program runs until CNT i equals Duty i + Phase i at time t5, at which point the program exits the current loop path.
[0083] During the t5–t6 phase: Phase i is not 0, CNT i is greater than Duty i, and CNT i is greater than Duty i + Phase i. The PWM generation subroutine runs along S1, S2, S4, S7, and S11 in each interrupt cycle, setting GPIO i1 and GPIO i2 low. CNT i is incremented by 1 each time the program runs until CNT i equals Duty i + Phase i at time t5, at which point the program exits the current loop path.
[0084] At time t6, CNT i equals Period i. Its PWM generation subroutine runs along S1, S2, S3, and S5 to obtain Period i, Duty i, and Phase i for the next cycle, and clears CNT i to zero, causing the program to enter the logic execution of the next PWM cycle.
[0085] During the t6–t7 phase: Phase i is not 0, CNT i is less than Duty i, and CNT i is less than Phase i. The PWM generation subroutine runs along S1, S2, S4, S6, and S9 in each interrupt cycle, setting GPIO i1 high and GPIO i2 low. CNT i is incremented by 1 each time the program runs until CNT i equals Phase i at time t7, at which point the program exits the current loop path.
[0086] During the t7–t8 phase: Phase i is not 0, CNT i is less than Duty i, and CNT i is greater than Phase i. The PWM generation subroutine runs along S1, S2, S4, S6, and S8 in each interrupt cycle, setting GPIO i1 and GPIO i2 high. CNTi is incremented by 1 each time the program runs until CNT i equals Duty i at time t8, at which point the program exits the current loop path.
[0087] During the t8–t9 phase: Phase i is not 0, CNT i is greater than Duty i, and CNT i is less than Duty i + Phase i. The PWM generation subroutine runs along S1, S2, S4, S7, and S10 in each interrupt cycle, setting GPIO i1 low and GPIO i2 high. CNT i is incremented by 1 each time the program runs until CNT i equals Duty i + Phase i at time t9, at which point the program exits the current loop path.
[0088] t9–t 10 Phase: When Phase i is not 0, CNT i is greater than Duty i, and CNT i is greater than Duty i + Phase i, the PWM generation subroutine runs along S1, S2, S4, S7, S11 in each interrupt cycle, setting GPIO i1 and GPIO i2 low, and incrementing CNT i by 1 with each run, until t 10 When CNT i equals Duty i + Phase i, the program exits the current loop path.
[0089] t 10 At time 1, CNT i equals Period i. Its PWM generation subroutine runs along S1, S2, S3, S5 to obtain Period i, Duty i, and Phase i for the next cycle, and clears CNT i to zero, causing the program to enter the logic execution of the next PWM cycle.
[0090] The program repeats this process, continuously obtaining new cycle values, duty cycles, and phase shift angles, and entering a new PWM adjustment cycle.
[0091] Furthermore, the timer interrupt clock configuration is configured so that the unit clock is the clock for CNT incrementing. The smaller the unit clock period, the higher the PWM regulation accuracy.
[0092] Compared with the prior art, the present invention has the following advantages and beneficial effects:
[0093] (1) This method uses a timer configured in periodic interrupt mode, and with multiple GPIO ports, it can realize the function of simulating multi-channel PWM output, which greatly saves microcontroller resources;
[0094] (2) The system configuration is flexible. By controlling the PWM generation logic timing through software programming, the duty cycle, phase shift angle and frequency of PWM can be adjusted, and multiple control methods can be mixed.
[0095] (3) It broadens the application scenarios of low-end microcontrollers, converts excess GPIO resources into PWM for use, and enables the control of multiple parameters for complex systems. Attached Figure Description
[0096] Figure 1 This is the main program flowchart of the present invention;
[0097] Figure 2 This is a flowchart of the interrupt service function of the present invention;
[0098] Figure 3 This is the logic timing diagram of the PWMV generation subroutine of the present invention;
[0099] Figure 4(a) is a schematic diagram of PWM single duty cycle adjustment of the present invention;
[0100] Figure 4(b) is a schematic diagram of the PWM single phase shift angle adjustment of the present invention;
[0101] Figure 4(c) is a schematic diagram of PWM single frequency adjustment of the present invention;
[0102] Figure 4(d) is a schematic diagram of the PWM hybrid regulation of the present invention. Detailed Implementation
[0103] The present invention will be further described in detail below with reference to the embodiments, but the implementation of the present invention is not limited thereto.
[0104] like Figure 1 As shown, a PWM generation method based on GPIO and timers has the following main program steps:
[0105] S1: System power-on, microcontroller hardware initialization;
[0106] S2: Initialize CNT, Period, Duty, and Phase;
[0107] S3: Timer interrupt clock configuration, the configured unit clock is the clock for CNT increment counting;
[0108] S4: Determine the switch signal. If a start-up signal is detected, proceed to the next step S5; otherwise, return to continue determining the switch signal.
[0109] S5: Run the timer interrupt service function to generate PWM pulse signals according to the logic control timing.
[0110] S6: Check the switch signal. If no stop signal is detected, return to the previous step S5; otherwise, end the program.
[0111] The timer interrupt clock is obtained by dividing the system clock, that is, the timer is configured as a periodic interrupt mode;
[0112] like Figure 2 As shown, the steps of its timer interrupt service function subroutine are as follows:
[0113] S1:i is initialized to 1;
[0114] S2: Call the PWM generation logic subroutine to generate the i-th PWM channel;
[0115] S3:i is incremented by 1;
[0116] S4: Determine if i is less than or equal to n. If yes, return to step S2; otherwise, end the program.
[0117] like Figure 3 As shown, the execution logic of its PWM generation subroutine is as follows:
[0118] S1:CNT i increments by 1;
[0119] S2: Determine if CNT i is less than Period i. If the condition is not met, execute S3; otherwise, execute S4.
[0120] S3: Call the closed-loop algorithm to perform calculations and obtain Period i, Duty i, and Phase i for the next cycle to generate PWM for logic operations.
[0121] S4: Determine if CNT i is less than Duty i. If the condition is met, execute S6; otherwise, execute S7.
[0122] S5: CNT i count is cleared to zero, the program ends and enters the next cycle;
[0123] S6: Determine if CNT i is less than Phase i. If the condition is met, execute S9; otherwise, execute S8.
[0124] S7: Determine whether CNT i is less than Phase i + Duty i. If the condition is met, execute S10; otherwise, execute S11.
[0125] S8: Set GPIO i1 and GPIO i2 high, then terminate the program;
[0126] S9: Set GPIO i1 high and GPIO i2 low, then terminate the program;
[0127] S10: Set GPIO i1 low and GPIO i2 high, then terminate the program;
[0128] S11: Set GPIO i1 and GPIO i2 low, then terminate the program.
[0129] As shown in Figure 4(a), when using the PWM single duty cycle adjustment method, in each cycle, the period value Periodi remains unchanged, the phase shift angle Phasei remains at 0°, and only the duty cycle Dutyi is changed. The PWM generation subroutine operation process is as follows:
[0130] During the t0–t1 phase: CNT i is less than Duty i, and its PWM generation subroutine runs along S1, S2, S4, S6, S8 in each interrupt cycle, setting GPIO i1 and GPIO i2 high. CNT i is incremented by 1 each time it runs until CNT i equals Duty i at time t1, at which point the program exits the current loop path.
[0131] During the t1–t2 phase: CNT i is greater than Duty i, and its PWM generation subroutine runs along S1, S2, S4, S7, S11 in each interrupt cycle, setting GPIO i1 and GPIO i2 low. CNT i is incremented by 1 each time it runs until CNT i equals Period i at time t2, at which point the program exits the current loop path.
[0132] At time t2, CNT i equals Period i. Its PWM generation subroutine runs along S1, S2, S3, and S5 to obtain Period i, Duty i, and Phase i for the next cycle, and clears CNT i to zero, causing the program to enter the logic execution of the next PWM cycle.
[0133] During the t2–t3 phase: CNT i is less than Duty i, and its PWM generation subroutine runs along S1, S2, S4, S6, S8 in each interrupt cycle, setting GPIO i1 and GPIO i2 high. CNT i is incremented by 1 each time it runs until CNT i equals Duty i at time t3, at which point the program exits the current loop path.
[0134] During the t3–t4 phase: CNT i is greater than Duty i, and its PWM generation subroutine runs along S1, S2, S4, S7, S11 in each interrupt cycle, setting GPIO i1 and GPIO i2 low. CNT i is incremented by 1 each time it runs until CNT i equals Period i at time t4, at which point the program exits the current loop path.
[0135] At time t4, CNT i equals Period i. Its PWM generation subroutine runs along S1, S2, S3, and S5 to obtain Period i, Duty i, and Phase i for the next cycle, and clears CNT i to zero, causing the program to enter the logic execution of the next PWM cycle.
[0136] During the t4–t5 phase: CNT i is less than Duty i, and its PWM generation subroutine runs along S1, S2, S4, S6, S8 in each interrupt cycle, setting GPIO i1 and GPIO i2 high. CNT i is incremented by 1 each time it runs until CNT i equals Duty i at time t5, at which point the program exits the current loop path.
[0137] During the t5–t6 phase: CNT i is greater than Duty i, and its PWM generation subroutine runs along S1, S2, S4, S7, S11 in each interrupt cycle, setting GPIO i1 and GPIO i2 low. CNT i is incremented by 1 each time it runs until CNT i equals Period i at time t6, at which point the program exits the current loop path.
[0138] At time t6, CNT i equals Period i. Its PWM generation subroutine runs along S1, S2, S3, and S5 to obtain Period i, Duty i, and Phase i for the next cycle, and clears CNT i to zero, causing the program to enter the logic execution of the next PWM cycle.
[0139] The program repeats this process, continuously obtaining new duty cycles and entering new PWM adjustment cycles.
[0140] As shown in Figure 4(b), when using the PWM single phase shift angle adjustment method, the period value Periodi and the duty cycle Duty i remain unchanged in each cycle, and only the phase shift angle Phase i is changed. The PWM generation subroutine operation process is as follows:
[0141] t0–t1 phase: Phase i is 0, CNT i is less than Duty i, and its PWM generation subroutine runs along S1, S2, S4, S6, S8 in each interrupt cycle, setting GPIO i1 and GPIO i2 high, and incrementing CNT i by 1 each time it runs, until CNT i equals Duty i at time t1, and the program exits this loop path.
[0142] t1–t2 phase: Phase i is 0, CNT i is greater than Duty i, and its PWM generation subroutine runs along S1, S2, S4, S7, S11 in each interrupt cycle, setting GPIO i1 and GPIO i2 low, and incrementing CNT i by 1 each time it runs, until CNT i equals Period i at time t2, and the program exits this loop path.
[0143] At time t2, CNT i equals Period i. Its PWM generation subroutine runs along S1, S2, S3, and S5 to obtain Period i, Duty i, and Phase i for the next cycle, and clears CNT i to zero, causing the program to enter the logic execution of the next PWM cycle.
[0144] During the t2–t3 phase: Phase i is not 0, CNT i is less than Duty i, and CNT i is less than Phase i. The PWM generation subroutine runs along S1, S2, S4, S6, and S9 in each interrupt cycle, setting GPIO i1 high and GPIO i2 low. CNT i is incremented by 1 each time the program runs until CNT i equals Phase i at time t3, at which point the program exits the current loop path.
[0145] During the t3–t4 phase: Phase i is not 0, CNT i is less than Duty i, and CNT i is greater than Phase i. The PWM generation subroutine runs along S1, S2, S4, S6, and S8 in each interrupt cycle, setting GPIO i1 and GPIO i2 high. CNTi is incremented by 1 each time the program runs until CNT i equals Duty i at time t4, at which point the program exits the current loop path.
[0146] During the t4–t5 phase: Phase i is not 0, CNT i is greater than Duty i, and CNT i is less than Duty i + Phase i. The PWM generation subroutine runs along S1, S2, S4, S7, and S10 in each interrupt cycle, setting GPIO i1 low and GPIO i2 high. CNT i is incremented by 1 each time the program runs until CNT i equals Duty i + Phase i at time t5, at which point the program exits the current loop path.
[0147] During the t5–t6 phase: Phase i is not 0, CNT i is greater than Duty i, and CNT i is greater than Duty i + Phase i. The PWM generation subroutine runs along S1, S2, S4, S7, and S11 in each interrupt cycle, setting GPIO i1 and GPIO i2 low. CNT i is incremented by 1 each time the program runs until CNT i equals Duty i + Phase i at time t5, at which point the program exits the current loop path.
[0148] At time t6, CNT i equals Period i. Its PWM generation subroutine runs along S1, S2, S3, and S5 to obtain Period i, Duty i, and Phase i for the next cycle, and clears CNT i to zero, causing the program to enter the logic execution of the next PWM cycle.
[0149] During the t6–t7 phase: Phase i is not 0, CNT i is less than Duty i, and CNT i is less than Phase i. The PWM generation subroutine runs along S1, S2, S4, S6, and S9 in each interrupt cycle, setting GPIO i1 high and GPIO i2 low. CNT i is incremented by 1 each time the program runs until CNT i equals Phase i at time t7, at which point the program exits the current loop path.
[0150] During the t7–t8 phase: Phase i is not 0, CNT i is less than Duty i, and CNT i is greater than Phase i. The PWM generation subroutine runs along S1, S2, S4, S6, and S8 in each interrupt cycle, setting GPIO i1 and GPIO i2 high. CNTi is incremented by 1 each time the program runs until CNT i equals Duty i at time t8, at which point the program exits the current loop path.
[0151] During the t8–t9 phase: Phase i is not 0, CNT i is greater than Duty i, and CNT i is less than Duty i + Phase i. The PWM generation subroutine runs along S1, S2, S4, S7, and S10 in each interrupt cycle, setting GPIO i1 low and GPIO i2 high. CNT i is incremented by 1 each time the program runs until CNT i equals Duty i + Phase i at time t9, at which point the program exits the current loop path.
[0152] t9–t 10 Phase: When Phase i is not 0, CNT i is greater than Duty i, and CNT i is greater than Duty i + Phase i, the PWM generation subroutine runs along S1, S2, S4, S7, S11 in each interrupt cycle, setting GPIO i1 and GPIO i2 low, and incrementing CNT i by 1 with each run, until t10 When CNT i equals Duty i + Phase i, the program exits the current loop path.
[0153] t 10 At time 1, CNT i equals Period i. Its PWM generation subroutine runs along S1, S2, S3, S5 to obtain Period i, Duty i, and Phase i for the next cycle, and clears CNT i to zero, causing the program to enter the logic execution of the next PWM cycle.
[0154] The program repeats this process, continuously obtaining new phase shift angles and entering new PWM adjustment cycles.
[0155] As shown in Figure 4(c), when using the PWM single-frequency regulation method, the duty cycle Duty i remains unchanged in each cycle, the phase shift angle Phase i is 0, and only the period value Period i is changed. The PWM generation subroutine runs as follows:
[0156] During the t0–t1 phase: CNT i is less than Duty i, and its PWM generation subroutine runs along S1, S2, S4, S6, S8 in each interrupt cycle, setting GPIO i1 and GPIO i2 high. CNT i is incremented by 1 each time it runs until CNT i equals Duty i at time t1, at which point the program exits the current loop path.
[0157] During the t1–t2 phase: CNT i is greater than Duty i, and its PWM generation subroutine runs along S1, S2, S4, S7, S11 in each interrupt cycle, setting GPIO i1 and GPIO i2 low. CNT i is incremented by 1 each time it runs until CNT i equals Period i at time t2, at which point the program exits the current loop path.
[0158] At time t2, CNT i equals Period i. Its PWM generation subroutine runs along S1, S2, S3, and S5 to obtain Period i, Duty i, and Phase i for the next cycle, and clears CNT i to zero, causing the program to enter the logic execution of the next PWM cycle.
[0159] During the t2–t3 phase: CNT i is less than Duty i, and its PWM generation subroutine runs along S1, S2, S4, S6, S8 in each interrupt cycle, setting GPIO i1 and GPIO i2 high. CNT i is incremented by 1 each time it runs until CNT i equals Duty i at time t3, at which point the program exits the current loop path.
[0160] During the t3–t4 phase: CNT i is greater than Duty i, and its PWM generation subroutine runs along S1, S2, S4, S7, S11 in each interrupt cycle, setting GPIO i1 and GPIO i2 low. CNT i is incremented by 1 each time it runs until CNT i equals Period i at time t4, at which point the program exits the current loop path.
[0161] At time t4, CNT i equals Period i. Its PWM generation subroutine runs along S1, S2, S3, and S5 to obtain Period i, Duty i, and Phase i for the next cycle, and clears CNT i to zero, causing the program to enter the logic execution of the next PWM cycle.
[0162] During the t4–t5 phase: CNT i is less than Duty i, and its PWM generation subroutine runs along S1, S2, S4, S6, S8 in each interrupt cycle, setting GPIO i1 and GPIO i2 high. CNT i is incremented by 1 each time it runs until CNT i equals Duty i at time t5, at which point the program exits the current loop path.
[0163] During the t5–t6 phase: CNT i is greater than Duty i, and its PWM generation subroutine runs along S1, S2, S4, S7, S11 in each interrupt cycle, setting GPIO i1 and GPIO i2 low. CNT i is incremented by 1 each time it runs until CNT i equals Period i at time t6, at which point the program exits the current loop path.
[0164] At time t6, CNT i equals Period i. Its PWM generation subroutine runs along S1, S2, S3, and S5 to obtain Period i, Duty i, and Phase i for the next cycle, and clears CNT i to zero, causing the program to enter the logic execution of the next PWM cycle.
[0165] The program repeats this process, continuously obtaining new period values and entering a new PWM adjustment cycle.
[0166] As shown in Figure 4(d), when using the PWM hybrid control method, the duty cycle (Duty i), phase shift angle (Phase i), and period value (Period i) can all be changed in each cycle. The PWM generation subroutine operation process is as follows:
[0167] t0–t1 phase: Phase i is 0, CNT i is less than Duty i, and its PWM generation subroutine runs along S1, S2, S4, S6, S8 in each interrupt cycle, setting GPIO i1 and GPIO i2 high, and incrementing CNT i by 1 each time it runs, until CNT i equals Duty i at time t1, and the program exits this loop path.
[0168] t1–t2 phase: Phase i is 0, CNT i is greater than Duty i, and its PWM generation subroutine runs along S1, S2, S4, S7, S11 in each interrupt cycle, setting GPIO i1 and GPIO i2 low, and incrementing CNT i by 1 each time it runs, until CNT i equals Period i at time t2, and the program exits this loop path.
[0169] At time t2, CNT i equals Period i. Its PWM generation subroutine runs along S1, S2, S3, and S5 to obtain Period i, Duty i, and Phase i for the next cycle, and clears CNT i to zero, causing the program to enter the logic execution of the next PWM cycle.
[0170] During the t2–t3 phase: Phase i is not 0, CNT i is less than Duty i, and CNT i is less than Phase i. The PWM generation subroutine runs along S1, S2, S4, S6, and S9 in each interrupt cycle, setting GPIO i1 high and GPIO i2 low. CNT i is incremented by 1 each time the program runs until CNT i equals Phase i at time t3, at which point the program exits the current loop path.
[0171] During the t3–t4 phase: Phase i is not 0, CNT i is less than Duty i, and CNT i is greater than Phase i. The PWM generation subroutine runs along S1, S2, S4, S6, and S8 in each interrupt cycle, setting GPIO i1 and GPIO i2 high. CNTi is incremented by 1 each time the program runs until CNT i equals Duty i at time t4, at which point the program exits the current loop path.
[0172] During the t4–t5 phase: Phase i is not 0, CNT i is greater than Duty i, and CNT i is less than Duty i + Phase i. The PWM generation subroutine runs along S1, S2, S4, S7, and S10 in each interrupt cycle, setting GPIO i1 low and GPIO i2 high. CNT i is incremented by 1 each time the program runs until CNT i equals Duty i + Phase i at time t5, at which point the program exits the current loop path.
[0173] During the t5–t6 phase: Phase i is not 0, CNT i is greater than Duty i, and CNT i is greater than Duty i + Phase i. The PWM generation subroutine runs along S1, S2, S4, S7, and S11 in each interrupt cycle, setting GPIO i1 and GPIO i2 low. CNT i is incremented by 1 each time the program runs until CNT i equals Duty i + Phase i at time t5, at which point the program exits the current loop path.
[0174] At time t6, CNT i equals Period i. Its PWM generation subroutine runs along S1, S2, S3, and S5 to obtain Period i, Duty i, and Phase i for the next cycle, and clears CNT i to zero, causing the program to enter the logic execution of the next PWM cycle.
[0175] During the t6–t7 phase: Phase i is not 0, CNT i is less than Duty i, and CNT i is less than Phase i. The PWM generation subroutine runs along S1, S2, S4, S6, and S9 in each interrupt cycle, setting GPIO i1 high and GPIO i2 low. CNT i is incremented by 1 each time the program runs until CNT i equals Phase i at time t7, at which point the program exits the current loop path.
[0176] During the t7–t8 phase: Phase i is not 0, CNT i is less than Duty i, and CNT i is greater than Phase i. The PWM generation subroutine runs along S1, S2, S4, S6, and S8 in each interrupt cycle, setting GPIO i1 and GPIO i2 high. CNTi is incremented by 1 each time the program runs until CNT i equals Duty i at time t8, at which point the program exits the current loop path.
[0177] During the t8–t9 phase: Phase i is not 0, CNT i is greater than Duty i, and CNT i is less than Duty i + Phase i. The PWM generation subroutine runs along S1, S2, S4, S7, and S10 in each interrupt cycle, setting GPIO i1 low and GPIO i2 high. CNT i is incremented by 1 each time the program runs until CNT i equals Duty i + Phase i at time t9, at which point the program exits the current loop path.
[0178] t9–t 10 Phase: When Phase i is not 0, CNT i is greater than Duty i, and CNT i is greater than Duty i + Phase i, the PWM generation subroutine runs along S1, S2, S4, S7, S11 in each interrupt cycle, setting GPIO i1 and GPIO i2 low, and incrementing CNT i by 1 with each run, until t10 When CNT i equals Duty i + Phase i, the program exits the current loop path.
[0179] t 10 At time 1, CNT i equals Period i. Its PWM generation subroutine runs along S1, S2, S3, S5 to obtain Period i, Duty i, and Phase i for the next cycle, and clears CNT i to zero, causing the program to enter the logic execution of the next PWM cycle.
[0180] The program repeats this process, continuously obtaining new cycle values, duty cycles, and phase shift angles, and entering a new PWM adjustment cycle.
[0181] It should be noted that, in this invention, the microcontroller should include all digital signal processors capable of generating PWM timing signals, such as DSP, FPAG, ARM, etc.
[0182] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the embodiments described above. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.
Claims
1. A method for generating PWM signals based on GPIO and a timer, characterized in that, include: The main program initializes various parameters based on user-defined values, calls the PWM generation subroutine to generate PWM and perform signal stop and judgment, and the parameters include CNT, Period, Duty, and Phase. The timer interrupt service routine periodically enters the timer interrupt to perform the increment count function based on the initialized unit clock value, and calls the PWM generation subroutine to generate each PWM signal. The PWM generation subroutine includes a single PWM duty cycle adjustment method, a single PWM phase angle adjustment method, a single PWM frequency adjustment method, and a hybrid PWM adjustment method. It performs logical judgments based on the CNT, Period, Duty, and Phase values, sets the corresponding GPIO high or low, and completes the PWM generation function. At the same time, when the conditions are met, it calls the PID closed-loop control algorithm to obtain the Period, Duty, and Phase values for the next cycle. The PWM generation subroutine is specifically as follows: S1, CNT i increments by 1; S2, determine if CNT i is less than Period i. If the condition is not met, execute S3; if the condition is met, execute S4. S3, call the PID closed-loop algorithm to perform calculations and obtain Period i, Dutyi and Phase i for the next cycle to generate PWM for logic operations; S4, determine whether CNT i is less than Duty i. If the condition is met, execute S6; otherwise, execute S7. S5, CNT i count is cleared to zero, program ends and enters the next cycle; S6, determine whether CNT i is less than Phase i. If the condition is met, execute S9; otherwise, execute S8. S7, determine whether CNT i is less than Phase i + Duty i. If the condition is met, execute S10; otherwise, execute S11. S8 sets GPIO i1 and GPIO i2 high, then terminates the program; S9 sets GPIO i1 high and GPIO i2 low, then terminates the program; S10: Set GPIO i1 low and GPIO i2 high, then terminate the program; S11 sets GPIO i1 and GPIO i2 low, then terminates the program.
2. The PWM signal generation method according to claim 1, characterized in that, The main program initializes various parameters according to user-defined values, calls the PWM generation subroutine to generate PWM and perform signal stop and judgment. The parameters include CNT, Period, Duty, and Phase, specifically: S1, System power-on, Microcontroller hardware initialization; S2, initialization of parameters CNT, Period, Duty, and Phase; S3, Timer interrupt clock configuration, the configured unit clock is the clock for CNT increment counting; S4, check the switch signal. If the start signal is detected, proceed to the next step S5; otherwise, return to check the switch signal. S5, run the timer interrupt service function to generate PWM pulses according to the logical timing sequence; S6: Check the switch signal. If no stop signal is detected, return to the previous step S5; otherwise, end the program.
3. The PWM signal generation method according to claim 1, characterized in that, The timer interrupt service routine, based on the initialized unit clock value, periodically enters the timer interrupt to perform the incrementing count function, and calls the PWM generation subroutine to generate each PWM signal, specifically: S1, initialize the unit clock value i to 1; S2, call the PWM generation subroutine module to generate the i-th PWM signal; S3, i is incremented by 1; S4: Determine if i is less than or equal to n. If yes, return to step S2; otherwise, end the program.
4. The PWM signal generation method according to claim 1, characterized in that, The implementation process of the PWM single duty cycle adjustment method is as follows: In each cycle, the period value Period i remains unchanged, the phase shift angle Phase i remains at 0°, and only the duty cycle Dutyi is changed. The execution process of its PWM generation subroutine is as follows: t 0– t Phase 1: When CNT i is less than Duty i, its PWM generation subroutine runs along S1, S2, S4, S6, S8 in each interrupt cycle, setting GPIO i1 and GPIO i2 high. CNT i increments by 1 with each run, until... t At time 1, CNT i equals Duty i, and the program exits the current loop path; t 1– t Phase 2: When CNT i is greater than Duty i, its PWM generation subroutine runs along S1, S2, S4, S7, S11 in each interrupt cycle, setting GPIO i1 and GPIO i2 low. CNT i increments by 1 with each run, until... t At time 2, CNT i equals Periodi, and the program exits the current loop path; t At time 2, CNT i equals Period i. Its PWM generation subroutine runs along S1, S2, S3, and S5 to obtain Period i, Duty i, and Phase i for the next cycle, and clears CNT i to zero, causing the program to enter the logic execution of the next PWM cycle. t 2– t Phase 3: When CNT i is less than Duty i, its PWM generation subroutine runs along S1, S2, S4, S6, S8 in each interrupt cycle, setting GPIO i1 and GPIO i2 high. CNT i increments by 1 with each run, until... t At time 3, CNT i equals Duty i, and the program exits the current loop path; t 3– t Phase 4: When CNT i is greater than Duty i, its PWM generation subroutine runs along S1, S2, S4, S7, S11 in each interrupt cycle, setting GPIO i1 and GPIO i2 low. CNT i increments by 1 with each run, until... t At time 4, CNT i equals Periodi, and the program exits the current loop path; t At time 4, CNT i equals Period i. Its PWM generation subroutine runs along S1, S2, S3, and S5 to obtain Period i, Duty i, and Phase i for the next cycle, and clears CNT i to zero, causing the program to enter the logic execution of the next PWM cycle. t 4– t Phase 5: When CNT i is less than Duty i, its PWM generation subroutine runs along S1, S2, S4, S6, S8 in each interrupt cycle, setting GPIO i1 and GPIO i2 high. CNT i increments by 1 with each run, until... t At time 5, CNT i equals Duty i, and the program exits the current loop path; t 5– t Stage 6: When CNT i is greater than Duty i, its PWM generation subroutine runs along S1, S2, S4, S7, S11 in each interrupt cycle, setting GPIO i1 and GPIO i2 low, and incrementing CNT i by 1 with each run, until... t At time 6, CNT i equals Periodi, and the program exits the current loop path; t At time 6, CNT i equals Period i. Its PWM generation subroutine runs along S1, S2, S3, and S5 to obtain Period i, Duty i, and Phase i for the next cycle, and clears CNT i to zero, causing the program to enter the logic execution of the next PWM cycle. The program repeats this process, continuously obtaining new duty cycles and entering new PWM adjustment cycles.
5. The PWM signal generation method according to claim 1, characterized in that, The implementation process of the PWM single phase shift angle adjustment method is as follows: In each cycle, the cycle value Period i and the duty cycle Duty i remain constant, only the phase shift angle Phase i changes. The execution process of its PWM generation subroutine is as follows: t 0– t Phase 1: Phase i is 0, CNT i is less than Duty i, and its PWM generation subroutine runs along S1, S2, S4, S6, S8 in each interrupt cycle, setting GPIO i1 and GPIO i2 high. CNT i increments by 1 with each run, until... t At time 1, CNTi equals Duty i, and the program exits the current loop path; t 1– t Phase 2: Phase i is 0, CNT i is greater than Duty i, and its PWM generation subroutine runs along S1, S2, S4, S7, S11 in each interrupt cycle, setting GPIO i1 and GPIO i2 low, and incrementing CNT i by 1 with each run, until... t At time 2, CNTi equals Period i, and the program exits the current loop path; t At time 2, CNT i equals Period i. Its PWM generation subroutine runs along S1, S2, S3, and S5 to obtain Period i, Duty i, and Phase i for the next cycle, and clears CNT i to zero, causing the program to enter the logic execution of the next PWM cycle. t 2– t Phase 3: When Phase i is not 0, CNT i is less than Duty i, and CNT i is less than Phase i, the PWM generation subroutine runs along S1, S2, S4, S6, and S9 in each interrupt cycle, setting GPIO i1 high and GPIO i2 low. CNTi increments by 1 with each run, until... t At time 3, CNT i equals Phase i, and the program exits the current loop path; t 3– t Phase 4: When Phase i is not 0, CNT i is less than Duty i, and CNT i is greater than Phase i, the PWM generation subroutine runs along S1, S2, S4, S6, and S8 in each interrupt cycle, setting GPIO i1 and GPIO i2 high. CNT i increments by 1 with each execution, until... t At time 4, CNT i equals Duty i, and the program exits the current loop path; t 4– t Phase 5: Phase i is not 0, CNT i is greater than Duty i, and CNT i is less than Duty i + Phase i. The PWM generation subroutine runs along S1, S2, S4, S7, and S10 in each interrupt cycle, setting GPIO i1 low and GPIO i2 high. CNT i increments by 1 with each run, until... t At time 5, CNT i equals Duty i + Phase i, and the program exits the current loop path; t 5– t Phase 6: Phase i is not 0, CNT i is greater than Duty i, and CNT i is greater than Duty i + Phase i. The PWM generation subroutine runs along S1, S2, S4, S7, and S11 in each interrupt cycle, setting GPIO i1 and GPIO i2 low. CNT i increments by 1 with each execution, until... t At time 5, CNT i equals Duty i + Phase i, and the program exits the current loop path; t At time 6, CNT i equals Period i. Its PWM generation subroutine runs along S1, S2, S3, and S5 to obtain Period i, Duty i, and Phase i for the next cycle, and clears CNT i to zero, causing the program to enter the logic execution of the next PWM cycle. t 6– t 7-stage: Phase i is not 0, CNT i is less than Duty i, and CNT i is less than Phase i. The PWM generation subroutine runs along S1, S2, S4, S6, and S9 in each interrupt cycle, setting GPIO i1 high and GPIO i2 low. CNTi increments by 1 with each run, until... t At time 7, CNT i equals Phase i, and the program exits the current loop path; t 7– t 8 stages: When Phase i is not 0, CNT i is less than Duty i, and CNT i is greater than Phase i, the PWM generation subroutine runs along S1, S2, S4, S6, and S8 in each interrupt cycle, setting GPIO i1 and GPIO i2 high. CNT i increments by 1 with each run, until... t At time 8, CNT i equals Duty i, and the program exits the current loop path; t 8– t 9 stages: Phase i is not 0, CNT i is greater than Duty i, and CNT i is less than Duty i + Phase i. The PWM generation subroutine runs along S1, S2, S4, S7, and S10 in each interrupt cycle, setting GPIO i1 low and GPIO i2 high. CNT i increments by 1 with each run, until... t At time 9, CNT i equals Duty i + Phase i, and the program exits the current loop path; t 9– t 10 Phase i is not 0, CNT i is greater than Duty i, and CNT i is greater than Duty i + Phase i. The PWM generation subroutine runs along S1, S2, S4, S7, and S11 in each interrupt cycle, setting GPIO i1 and GPIO i2 low. CNT i increments by 1 with each execution, until... t 10 When CNT i equals Duty i + Phase i, the program exits the current loop path. t 10 At time 1, CNT i equals Period i. Its PWM generation subroutine runs along S1, S2, S3, S5 to obtain Period i, Duty i, and Phase i for the next cycle, and clears CNT i to zero, causing the program to enter the logic execution of the next PWM cycle. The program repeats this process, continuously obtaining new phase shift angles and entering new PWM adjustment cycles.
6. The PWM signal generation method according to claim 1, characterized in that, The implementation process of the PWM single-frequency adjustment method is as follows: In each cycle, the duty cycle (Duty i) remains constant, the phase shift angle (Phase i) is 0, and only the period value (Periodi) is changed. The PWM generation subroutine runs as follows: t 0– t Phase 1: When CNT i is less than Duty i, its PWM generation subroutine runs along S1, S2, S4, S6, S8 in each interrupt cycle, setting GPIO i1 and GPIO i2 high. CNT i increments by 1 with each run, until... t At time 1, CNT i equals Duty i, and the program exits the current loop path; t 1– t Phase 2: When CNT i is greater than Duty i, its PWM generation subroutine runs along S1, S2, S4, S7, S11 in each interrupt cycle, setting GPIO i1 and GPIO i2 low. CNT i increments by 1 with each run, until... t At time 2, CNT i equals Periodi, and the program exits the current loop path; t At time 2, CNT i equals Period i. Its PWM generation subroutine runs along S1, S2, S3, and S5 to obtain Period i, Duty i, and Phase i for the next cycle, and clears CNT i to zero, causing the program to enter the logic execution of the next PWM cycle. t 2– t Phase 3: When CNT i is less than Duty i, its PWM generation subroutine runs along S1, S2, S4, S6, S8 in each interrupt cycle, setting GPIO i1 and GPIO i2 high. CNT i increments by 1 with each run, until... t At time 3, CNT i equals Duty i, and the program exits the current loop path; t 3– t Phase 4: When CNT i is greater than Duty i, its PWM generation subroutine runs along S1, S2, S4, S7, S11 in each interrupt cycle, setting GPIO i1 and GPIO i2 low. CNT i increments by 1 with each run, until... t At time 4, CNT i equals Periodi, and the program exits the current loop path; t At time 4, CNT i equals Period i. Its PWM generation subroutine runs along S1, S2, S3, and S5 to obtain Period i, Duty i, and Phase i for the next cycle, and clears CNT i to zero, causing the program to enter the logic execution of the next PWM cycle. t 4– t Phase 5: When CNT i is less than Duty i, its PWM generation subroutine runs along S1, S2, S4, S6, S8 in each interrupt cycle, setting GPIO i1 and GPIO i2 high. CNT i increments by 1 with each run, until... t At time 5, CNT i equals Duty i, and the program exits the current loop path; t 5– t Stage 6: When CNT i is greater than Duty i, its PWM generation subroutine runs along S1, S2, S4, S7, S11 in each interrupt cycle, setting GPIO i1 and GPIO i2 low, and incrementing CNT i by 1 with each run, until... t At time 6, CNT i equals Periodi, and the program exits the current loop path; t At time 6, CNT i equals Period i. Its PWM generation subroutine runs along S1, S2, S3, and S5 to obtain Period i, Duty i, and Phase i for the next cycle, and clears CNT i to zero, causing the program to enter the logic execution of the next PWM cycle. The program repeats this process, continuously obtaining new period values and entering a new PWM adjustment cycle.
7. The PWM signal generation method according to claim 1, characterized in that, The implementation process of the PWM hybrid regulation method is as follows: In each cycle, the duty cycle (Duty i), phase shift angle (Phase i), and period value (Period i) can all be changed. The execution process of its PWM generation subroutine is as follows: t 0– t Phase 1: Phase i is 0, CNT i is less than Duty i, and its PWM generation subroutine runs along S1, S2, S4, S6, S8 in each interrupt cycle, setting GPIO i1 and GPIO i2 high. CNT i increments by 1 with each run, until... t At time 1, CNTi equals Duty i, and the program exits the current loop path; t 1– t Phase 2: Phase i is 0, CNT i is greater than Duty i, and its PWM generation subroutine runs along S1, S2, S4, S7, S11 in each interrupt cycle, setting GPIO i1 and GPIO i2 low, and incrementing CNT i by 1 with each run, until... t At time 2, CNTi equals Period i, and the program exits the current loop path; t At time 2, CNT i equals Period i. Its PWM generation subroutine runs along S1, S2, S3, and S5 to obtain Period i, Duty i, and Phase i for the next cycle, and clears CNT i to zero, causing the program to enter the logic execution of the next PWM cycle. t 2– t Phase 3: When Phase i is not 0, CNT i is less than Duty i, and CNT i is less than Phase i, the PWM generation subroutine runs along S1, S2, S4, S6, and S9 in each interrupt cycle, setting GPIO i1 high and GPIO i2 low. CNTi increments by 1 with each run, until... t At time 3, CNT i equals Phase i, and the program exits the current loop path; t 3– t Phase 4: When Phase i is not 0, CNT i is less than Duty i, and CNT i is greater than Phase i, the PWM generation subroutine runs along S1, S2, S4, S6, and S8 in each interrupt cycle, setting GPIO i1 and GPIO i2 high. CNT i increments by 1 with each execution, until... t At time 4, CNT i equals Duty i, and the program exits the current loop path; t 4– t Phase 5: Phase i is not 0, CNT i is greater than Duty i, and CNT i is less than Duty i + Phase i. The PWM generation subroutine runs along S1, S2, S4, S7, and S10 in each interrupt cycle, setting GPIO i1 low and GPIO i2 high. CNT i increments by 1 with each run, until... t At time 5, CNT i equals Duty i + Phase i, and the program exits the current loop path; t 5– t Phase 6: Phase i is not 0, CNT i is greater than Duty i, and CNT i is greater than Duty i + Phase i. The PWM generation subroutine runs along S1, S2, S4, S7, and S11 in each interrupt cycle, setting GPIO i1 and GPIO i2 low. CNT i increments by 1 with each execution, until... t At time 5, CNT i equals Duty i + Phase i, and the program exits the current loop path; t At time 6, CNT i equals Period i. Its PWM generation subroutine runs along S1, S2, S3, and S5 to obtain Period i, Duty i, and Phase i for the next cycle, and clears CNT i to zero, causing the program to enter the logic execution of the next PWM cycle. t 6– t 7-stage: Phase i is not 0, CNT i is less than Duty i, and CNT i is less than Phase i. The PWM generation subroutine runs along S1, S2, S4, S6, and S9 in each interrupt cycle, setting GPIO i1 high and GPIO i2 low. CNTi increments by 1 with each run, until... t At time 7, CNT i equals Phase i, and the program exits the current loop path; t 7– t 8 stages: When Phase i is not 0, CNT i is less than Duty i, and CNT i is greater than Phase i, the PWM generation subroutine runs along S1, S2, S4, S6, and S8 in each interrupt cycle, setting GPIO i1 and GPIO i2 high. CNT i increments by 1 with each run, until... t At time 8, CNT i equals Duty i, and the program exits the current loop path; t 8– t 9 stages: Phase i is not 0, CNT i is greater than Duty i, and CNT i is less than Duty i + Phase i. The PWM generation subroutine runs along S1, S2, S4, S7, and S10 in each interrupt cycle, setting GPIO i1 low and GPIO i2 high. CNT i increments by 1 with each run, until... t At time 9, CNT i equals Duty i + Phase i, and the program exits the current loop path; t 9– t 10 Phase i is not 0, CNT i is greater than Duty i, and CNT i is greater than Duty i + Phase i. The PWM generation subroutine runs along S1, S2, S4, S7, and S11 in each interrupt cycle, setting GPIO i1 and GPIO i2 low. CNT i increments by 1 with each execution, until... t 10 When CNT i equals Duty i + Phase i, the program exits the current loop path. t 10 At time 1, CNT i equals Period i. Its PWM generation subroutine runs along S1, S2, S3, S5 to obtain Period i, Duty i, and Phase i for the next cycle, and clears CNT i to zero, causing the program to enter the logic execution of the next PWM cycle. The program repeats this process, continuously obtaining new cycle values, duty cycles, and phase shift angles, and entering a new PWM adjustment cycle.
8. The PWM signal generation method according to claim 1, characterized in that, The timer interrupt clock configuration is configured with a unit clock that increments the CNT count. The smaller the unit clock period, the higher the PWM regulation accuracy.