A design optimization method for high-speed video channel detection and selection device

Abstract

The present invention discloses a design optimization method for a high-speed video channel detection and selection device, including: 1) designing the system of the first-piece detection and selection device, electrically connecting the first-piece detection and selection device to the product to be tested through a standard communication cable to form the entire test system, receiving the detection data of the product to be tested, transmitting it to the host computer control system through a USB, and judging the defective products of the product to be tested through an operation interface; 2) coarsely adjusting the EQ basic parameters of the system of the product to be tested; optimizing the clock parameters of the system of the first-piece detection and selection device; and designing the power-on timing of the entire test system; 3) applying the first-piece optimized detection and selection device to the production line, continuously correcting it according to the product test situation, fine-tuning the EQ basic parameters, and obtaining the final standard parts of the detection and selection device. The present invention can obtain standard parts of the detection and selection device, select them on the production line, intercept unqualified products, and improve product quality.

Description

Technical Field

[0001] The present invention relates to the field of intelligent driving cabins, and in particular to a design optimization method for a high-speed video channel detection and selection device. Background Art

[0002] At present, in the field of intelligent driving cabins, it is a common solution for a single host control box to drive a high-definition large screen. The high resolution of the large screen (such as: 1080P, 60Hz) brings about an increase in the video signal transmission rate (greater than 3Gbit / s), which places extremely high demands on the stability and accuracy of the signal front-end input, the quality of the transmission path, and the terminal decoding accuracy. In actual mass production, it was found that when the output exceeded the thousand level, there were very few problems of snowflakes and screen flashing. After designing and optimizing each key node, the individual error of the chip is also one of the key influencing factors. However, the individual error of the chip cannot be avoided, and the product quality needs to be guaranteed. Under this condition, a production line detection and selection system corresponding to a specific product is required to intercept unqualified products. In actual application, it was found that once the product to be tested is mass-produced, due to the individual differences in the communication data encoding and decoding chips in the system of the detection and selection device and the individual differences in the common-mode inductance of the transmission line, very few products to be tested will have problems of snowflakes and screen flashing. Summary of the invention

[0003] The purpose of the present invention is to overcome the defects of the prior art and provide a design optimization method for a high-speed video channel detection and selection device, which can obtain standard parts for the detection and selection device, select them on the production line, intercept unqualified products, and improve product quality.

[0004] The object of the present invention is achieved by: a design optimization method of a high-speed video path detection and selection device, comprising the following:

[0005] 1) Design the system of the first-article inspection and selection device, electrically connect the first-article inspection and selection device to the product to be tested through a standard communication cable to form the entire test system, receive the test data of the product to be tested, transmit it to the host computer control system through USB, and judge the defective products of the product to be tested through the operation interface;

[0006] 2) Roughly adjust the basic EQ parameters of the system of the product to be tested; optimize the clock parameters of the system of the first-article inspection and selection device; design the power-on timing of the entire test system;

[0007] 3) Apply the first optimized detection and selection device to the production line, carry out small batch selection, make continuous corrections based on product test results, fine-tune the basic EQ parameters, select the encoding chip of the detection and selection device, and obtain the final standard parts of the detection and selection device.

[0008] Furthermore, the system of the detection and selection device in step 1) specifically includes a single-chip microcomputer control module, a core processing module, a communication data encoding and transmission module, a host computer control system and a high-definition display touch module; the core processing module is electrically connected to the single-chip microcomputer control module through an SPI bus, and the core processing module is electrically connected to the communication data encoding and transmission module through an RGB bus; the core processing module is electrically connected to the host computer control system through a USB; the core processing module is electrically connected to the high-definition display touch module through a MIPI bus; the communication data encoding and transmission module is electrically connected to the single-chip microcomputer control module through an I2C bus.

[0009] Furthermore, the system of the product to be tested in step 1) integrates a display touch module, a control system, a communication data decoding module, a common mode inductor and an auxiliary equipment eye diagram measurement device; the display touch module is used to complete the display touch function; the control system is used to control various modules inside the display screen to provide initialization settings for the communication data decoding module and provide timing control for the power supply; the eye diagram measurement device is used to preliminarily find the fault location of the product to be tested and perform preliminary repairs when defective products are found.

[0010] Furthermore, the coarse adjustment of the basic EQ parameters of the system of the product to be tested described in step 2) specifically includes: the decoding chip in the communication data decoding module of the product to be tested generates a basic value through the equalizer, and then allows the clock data recovery circuit to maintain a valid lock condition. For each EQ setting, the circuit waits for a program re-lock time period, and then checks whether the result is a valid lock; if a valid lock is detected, the circuit will stop at the current EQ setting and maintain a constant value as long as the lock state continues; if the deserializer loses the lock, the adaptive equalizer will restore the lock algorithm, and the EQ setting will increase to the next valid state; once the lock is lost, the circuit will continue to search for the EQ setting to find a valid setting to regain the serial data stream sent by the serializer that maintains the lock; at this time, this valid setting is the coarse adjustment of the basic EQ parameters.

[0011] Furthermore, the optimization of the clock parameters of the system of the first piece detection and selection device in step 2) specifically includes:

[0012] First, the system display specifications: HPW=16, HBP=16, HFP=52, horizontal effective pixels=1920; VBW=8, VBP=8, VFP=54 vertical effective pixels=720; after calculation, the clock is 94.9896MHz;

[0013] Total horizontal points = HPW + HBP + 1920 + HFP = 16 + 16 + 1920 + 52 = 2004;

[0014] Total vertical points = VBW + VBP + 720 + VFP = 8 + 8 + 720 + 54 = 790;

[0015] Clock = total horizontal dots * total vertical dots * 60HZ = 2004 * 790 * 60 = 94989600;

[0016] The core processing module of the detection and selection system sets the main clock deviation to less than 1%, and continuously modifies the frequency division and multiplication parameters based on this. The SOC PCLK jitter coefficient is measured using a high-speed oscilloscope and is ultimately adjusted to 94.8MHz with a clock deviation of 0.2%, meeting the requirement of less than 1%, and a jitter coefficient of less than 0.3UI.

[0017] Furthermore, the design of the power-on timing of the entire test system described in step 2) specifically includes: after the communication data encoding IC is powered on and before the detection system SOC PCLK is issued, the channel transmission basic frequency is automatically generated by the encoding chip of the communication data encoding and transmission module in the detection and selection system, and after the decoding chip of the product to be tested is reset, a fixed EQ value is forcibly written to keep the channel EQ compensation constant to avoid channel fluctuations.

[0018] The present invention adopts the above technical scheme, and compared with the prior art, the beneficial effects are as follows: by coarsely adjusting the EQ basic parameters of the system of the product to be tested, a preliminary compensation coefficient is determined for the high-speed communication channel of the entire system; the clock parameters of the first-piece detection and selection system are optimized to reduce the clock jitter coefficient and ensure a stable reference clock for the high-speed communication channel of the system; the power-on timing sequence of the entire test system is designed to ensure that the channel instability that occurs at the initial stage of system startup is suppressed in the early stage and will not affect the normal communication of subsequent channels; the above three measures ensure stable high-speed channel communication and improve the product qualification rate; the first-piece optimized detection and selection system is applied to the production line for small-batch selection, and continuous corrections are made according to the product test results, and the EQ basic parameters are fine-tuned to obtain the standard parts of the final detection and selection system, and the standard parts are applied to the production line to select problematic display screens, intercept unqualified products, and improve product quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Flowchart of the present invention.

[0020] Figure 2 System block diagram of the detection and selection device of the present invention.

[0021] Figure 3 System block diagram of the product to be tested of the present invention.

[0022] Figure 4 The present invention is a flow chart for setting basic system EQ parameters of the product to be tested. DETAILED DESCRIPTION

[0023] like Figure 1 A design optimization method for a high-speed video channel detection and selection device is shown, comprising the following steps:

[0024] 1) Design the system of the first-article inspection and selection device, electrically connect the first-article inspection and selection device to the product to be tested through a standard communication cable to form the entire test system, receive the test data of the product to be tested, transmit it to the host computer control system through USB, and judge the defective products of the product to be tested through the operation interface;

[0025] like Figure 2 As shown, the system of the detection and selection device specifically includes a single-chip control module, a core processing module, a communication data encoding and transmission module, a host computer control system and a high-definition display touch module; the core processing module is electrically connected to the single-chip control module through the SPI bus, and the core processing module is electrically connected to the communication data encoding and transmission module through the RGB bus; the core processing module is electrically connected to the host computer control system through USB; the core processing module is electrically connected to the high-definition display touch module through the MIPI bus; the communication data encoding and transmission module is electrically connected to the single-chip control module through the I2C bus. The standard encoding chip is selected as the encoding chip in the communication data encoding module of the first-piece detection and selection device.

[0026] The single-chip control module is responsible for controlling the entire system of the selection device: completing the power-on and power-off timing control of each module in the whole system, providing initialization settings for the communication data encoding module, and providing underlying drive information for the core processing module;

[0027] After the core processing module is started, it drives the high-definition display touch module through the MIPI channel, initializes the display and touch drivers, loads the control interface program, and confirms the handshake protocol with the product under test through the communication data encoding transmission module and communication cable. It exchanges data information to confirm whether the product under test is working normally, extracts the test data part of the interactive information, and transmits it to the host control system through the USB channel.

[0028] The host control system analyzes the data (EQ tolerance measurement, data communication bit error rate, etc.) obtained from the core processing module to determine whether the product meets the requirements and select defective products to be tested.

[0029] The data communication bit error rate is set to 2.62 milliseconds for the pause time while the EQ waits for lock or error-free status. When checking each EQ setting, the AEQ will wait for a time interval before incrementing to the next allowed EQ gain setting; once the maximum setting is reached, if lock is not obtained within the programmed re-lock time, an error is reported, providing bit error information.

[0030] like Figure 3As shown in the figure, the product to be tested is a large-screen high-definition vehicle-mounted product. The system integrates a display touch module, a control system, a communication data decoding module, a common-mode inductor and an auxiliary equipment eye diagram measurement device. The display touch module is used to complete the display touch function. The control system is used to control each module inside the display screen to provide initialization settings for the communication data decoding module and provide timing control for the power supply. The eye diagram measurement device is used to find the fault location of the product to be tested and perform preliminary repairs when defective products are found.

[0031] 2) Roughly adjust the basic EQ parameters of the system of the product to be tested; optimize the clock parameters of the first-article inspection and selection system; and design the power-on timing of the entire test system;

[0032] Determine the preliminary compensation coefficients for the entire system communication high-speed channel, such as Figure 4 As shown, the coarse adjustment of the basic EQ parameters of the system of the product to be tested specifically includes: the decoding chip in the communication data decoding module of the product to be tested generates a basic value through the equalizer, and then allows the clock data recovery circuit to maintain a valid lock condition. For each EQ setting, the circuit waits for a program re-lock time period, and then checks whether the result is a valid lock; if a valid lock is detected, the circuit will stop at the current EQ setting and maintain a constant value as long as the lock state continues; if the deserializer loses the lock, the adaptive equalizer will restore the lock algorithm, and the EQ setting will increase to the next valid state; once the lock is lost, the circuit will continue to search for the EQ setting to find a valid setting to regain the serial data stream sent by the serializer that maintains the lock; at this time, this valid setting is the coarse adjustment of the basic EQ parameters; after the coarse adjustment of the basic EQ parameters, the qualified rate of the mass-produced products to be tested exceeds 99%.

[0033] In systems above 3GHz, time jitter will cause inter-symbol interference (ISI), resulting in an increase in the transmission bit error rate; the video signal clock jitter parameter design plays one of the main factors in the snow and flicker problems; in order to avoid the above problems, the clock parameters of the first-article inspection and selection system are optimized, including: first, the system display specifications: HPW=16, HBP=16, HFP=52, horizontal effective pixels=1920; VBW=8, VBP=8, VFP=54 vertical effective pixels=720; the calculated clock is 94.9896MHz;

[0034] Total horizontal points = HPW + HBP + 1920 + HFP = 16 + 16 + 1920 + 52 = 2004;

[0035] Total vertical points = VBW + VBP + 720 + VFP = 8 + 8 + 720 + 54 = 790;

[0036] Clock = total horizontal dots * total vertical dots * 60HZ = 2004 * 790 * 60 = 94989600;

[0037] The core processing module of the detection and selection system sets the main clock deviation to less than 1%, and based on this, continuously modifies the frequency division and multiplication parameters, and uses a high-speed oscilloscope to measure the SOC PCLK jitter coefficient, and finally adjusts it to 94.8MHz, with a clock deviation of 0.2%, meeting the requirement of less than 1%, and a jitter coefficient of less than 0.3UI. After a large amount of mass production data, it can be proved that 99.7% of the products to be tested can be qualified.

[0038] After the communication data encoding IC is powered on and before the detection system SOC PCLK is issued, the basic frequency of the channel (communication cable between the product to be tested and the detection and selection device) transmission is automatically generated by the encoding chip of the communication data encoding and transmission module in the selection and detection device. Therefore, since there is no PCLK output at this time, it will affect the channel state, causing confusion in the EQ adaptive compensation of the decoding chip in the communication data decoding module of the product to be tested, resulting in screen jitter and snow. In order to solve this problem, after the decoding chip of the product to be tested is reset, a fixed EQ value is forced to be written to keep the channel EQ compensation constant and avoid channel fluctuations.

[0039] 3) Apply the first optimized detection and selection device to the production line, carry out small batch selection, make continuous corrections based on product test results, fine-tune the EQ basic parameters, select the encoding chip of the detection and selection device, and obtain the final standard parts of the detection and selection device;

[0040] Since the encoding chip and decoding chip are a pair of transmission chips; the encoding chip in the detection and selection device still has an extremely low probability (a few thousandths) of causing snow and screen flickering problems due to its own design errors; therefore, by detecting the EQ tolerance parameters of the product to be tested, data communication bit error rate and other data, the standard deviation and average value are calculated according to Six Sigma, and the correlation and deviation between the statistical average and the median value are determined to perform routine trend management; the detection and selection device is used to select the product to be tested. If the selected failure rate is too large, it means that the encoding chip in the detection and selection device has a large deviation. At this time, the encoding chip of the selection device should be replaced; continuous corrections are made according to the product test results, and the basic EQ parameters are fine-tuned to make standard parts.

[0041] The present invention provides a design optimization method for a high-speed video path detection and selection device. By roughly adjusting the EQ basic parameters of the system of the product to be tested; optimizing the clock parameters of the first-piece detection and selection system; and designing the power-on timing of the entire test system, standard parts of the detection and selection device can be obtained, and the problems of snowflakes and screen flashing when the detection and selection device is connected to the product to be tested can be avoided. The selection can be performed on the production line, unqualified products can be intercepted, and product quality can be improved.

[0042] The present invention is not limited to the above-mentioned embodiments. On the basis of the technical solution disclosed in the present invention, technicians in this field can make some substitutions and deformations to some technical features therein according to the disclosed technical content without creative labor, and these substitutions and deformations are all within the protection scope of the present invention.

Claims

1. A design optimization method for a high-speed video channel detection and selection device, characterized in that: Includes the following: 1) Design the system of the first-article inspection and selection device, electrically connect the first-article inspection and selection device to the product to be tested through a standard communication cable to form the entire test system, receive the test data of the product to be tested, transmit it to the host computer control system through USB, and judge the defective products of the product to be tested through the operation interface; 2) Roughly adjust the basic EQ parameters of the system of the product to be tested; Optimize the clock parameters of the system of the first-article inspection and selection device; design the power-on timing of the entire test system; 3) Apply the first optimized detection and selection device to the production line for selection, make continuous corrections based on product test results, fine-tune the EQ basic parameters, select the encoding chip of the detection and selection device, and obtain the final standard parts of the detection and selection device; The video signal transmission rate of the high-speed video channel is greater than 3 Gbit / s; The step 2) of coarsely adjusting the basic EQ parameters of the system of the product under test specifically includes: the decoding chip in the communication data decoding module of the product under test generates a basic value through the equalizer, and then allows the clock data recovery circuit to maintain a valid lock condition. For each EQ setting, the circuit waits for a program re-lock time period, and then checks whether the result is a valid lock; if a valid lock is detected, the circuit will stop at the current EQ setting and maintain a constant value as long as the lock state continues; if the deserializer loses the lock, the adaptive equalizer will restore the lock algorithm, and the EQ setting will increase to the next valid state; once the lock is lost, the circuit will continue to search for the EQ setting to find a valid setting to regain the serial data stream sent by the serializer that maintains the lock; at this time, this valid setting is the coarse adjustment of the basic EQ parameters; The optimization of the clock parameters of the system of the first piece detection and selection device described in step 2) specifically includes: First, the system display specifications: HPW=16, HBP=16, HFP=52, horizontal effective pixels=1920; VPW=8, VBP=8, VFP=54 vertical effective pixels=720; after calculation, the clock is 94.9896MHz; Total horizontal points = HPW + HBP + 1920 + HFP = 16 + 16 + 1920 + 52 = 2004; Total vertical points = VPW + VBP + 720 + VFP = 8 + 8 + 720 + 54 = 790; Clock = total horizontal dots * total vertical dots * 60HZ = 2004 * 790 * 60 = 94989600; The core processing module of the system of the first-article inspection and selection device sets the main clock deviation to less than 1%, and based on this, continuously modifies the frequency division and multiplication parameters, and uses a high-speed oscilloscope to measure the SOC PCLK jitter coefficient, which is finally adjusted to 94.8MHz, with a clock deviation of 0.2%, meeting the requirement of less than 1%, and a jitter coefficient of less than 0.3UI; The design of the power-on timing of the entire test system described in step 2) specifically includes: after the communication data encoding IC is powered on, before the system SOC PCLK of the first-article inspection and selection device is issued, the channel transmission basic frequency is automatically generated by the encoding chip of the communication data encoding and transmission module in the system of the first-article inspection and selection device, and after the decoding chip of the product to be tested is reset, a fixed EQ value is forcibly written to keep the channel EQ compensation constant.

2. The design optimization method of a high-speed video path detection and selection device according to claim 1, characterized in that: The system of the first-piece detection and selection device described in step 1) specifically includes a single-chip microcomputer control module, a core processing module, a communication data encoding and transmission module, a host computer control system and a high-definition display touch module; the core processing module is electrically connected to the single-chip microcomputer control module through an SPI bus, and the core processing module is electrically connected to the communication data encoding and transmission module through an RGB bus; the core processing module is electrically connected to the host computer control system through a USB; the core processing module is electrically connected to the high-definition display touch module through a MIPI bus; the communication data encoding and transmission module is electrically connected to the single-chip microcomputer control module through an I2C bus.

3. The design optimization method of a high-speed video path detection and selection device according to claim 1, characterized in that: The system of the product to be tested in step 1) integrates a display touch module, a control system, a communication data decoding module, a common mode inductor and an auxiliary equipment eye diagram measurement device; the display touch module is used to complete the display touch function; the control system is used to control various modules inside the display screen to provide initialization settings for the communication data decoding module and provide timing control for the power supply; the eye diagram measurement device is used to preliminarily find the fault location of the product to be tested and perform preliminary repairs when defective products are found.

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