Wafer image chip cutting lane automatic positioning method

Abstract

The present application relates to a wafer image chip cutting path automatic positioning method, a wafer is fixed in a full-automatic wafer cutting system, and the chip shape in the wafer is a rounded square. The method first coarsely positions the inner region edge position of each chip in the wafer through a template matching algorithm and an image region growing algorithm, then finely positions the inner region edge position of the chip through a gray value threshold algorithm based on the distribution difference of the gray value of the pixel points in the inner and outer regions of the chip to obtain the inner region edge point coordinates of the chip, and then the inner region edge line of each column of chips in the wafer is obtained by straight line fitting from the edge points, so as to position the wafer cutting path. For the wafer, the method can effectively solve the problem of large positioning error of the wafer cutting path, and effectively improve the positioning accuracy.

Description

Technical Field

[0001] This invention belongs to the field of automated wafer dicing, specifically relating to a method for automatically locating chip dicing tracks in wafer images. It particularly addresses wafers where there is a significant difference in grayscale values ​​between the inner and outer regions of the chip, locating the dicing tracks by detecting the edge pixels of the inner region and the corresponding straight lines. Background Technology

[0002] A wafer is made of silicon and densely packed with tiny chips. The units within a wafer are chips, which are arranged in a regular, dense pattern. Before packaging, the chips need to be separated from the array by dicing equipment along the blocks between the chips.

[0003] In the integrated circuit manufacturing process, to improve wafer utilization, chip density is increasing, and the width of the dicing blocks (the area between adjacent chips) is decreasing, reaching tens of micrometers or even smaller. Therefore, ensuring wafer dicing precision is crucial. Before dicing wafers or separating chips, the dicing path must be predicted and calculated with high accuracy to ensure that the chips are not damaged during dicing and to improve the yield rate after dicing.

[0004] Currently, wafer dicing is mainly performed by combining machine vision and laser cutting technology. First, a microscopic vision system and image processing are used to identify and locate the dicing zones on the wafer, and then laser dicing is performed. The microscopic vision system typically consists of a low-magnification coarse positioning vision system and a high-magnification fine positioning vision system used to acquire wafer images of the chip array. Image processing technology is used to obtain the dicing tracks from the acquired wafer images. Most existing image processing methods for obtaining wafer dicing tracks fall into the categories of template matching and edge detection. Cao Chengbing, in his paper "Automatic Wafer Dicing System for Visual Inspection," proposed using Hough transform to detect the straight edges or circular features of the chips in the wafer image to determine the location of the wafer dicing tracks. Du Mingze, in his paper "Development of a Wafer Positioning and Dicing System Based on Machine Vision," proposed first using template matching for coarse positioning, and then using Hough transform to extract the center coordinates of the cross-shaped center region of the wafer dicing track to locate the dicing track. The methods mentioned above are more suitable for wafers with regular chip shapes, smooth edges, and uniform grayscale distribution of the dicing zones. However, the wafer has a relatively random chip shape and the chip edges are also relatively rough. Conventional edge detection and positioning of chip edge contours will produce large errors. Furthermore, since the size and gray value distribution of each chip in the wafer are also different, template matching will also produce large positioning deviations.

[0005] For the aforementioned wafer, this invention introduces an automatic chip dicing track positioning method in wafer images. It proposes a coarse-to-fine positioning method based on the difference in grayscale value distribution between the inner and outer regions of the chip, locating the edge lines of the inner region of the chip and thus the wafer dicing track. Compared to other positioning methods, this invention is effective in processing high-quality wafer images with regular shapes and uniform exposure. Simultaneously, it maintains positioning accuracy even for wafer images with irregular chip shapes and rough edges, as well as for wafer images of poor quality acquired due to overexposure or underexposure. Its method has a wider range of applications and superior accuracy. Summary of the Invention

[0006] The chip in the wafer is a rounded square with relatively rough edges. In the chip image, the outer ring is dark and is defined as the outer area of ​​the chip, while the inner ring is light and is defined as the inner area of ​​the chip.

[0007] Based on the shape and grayscale distribution characteristics of chips in a wafer, this invention introduces an automatic chip dicing track positioning method in a wafer image. Since the grayscale value distribution of the inner and outer regions of the chip in the wafer differs significantly, and the inner regions of chips in the same row and column have the same shape and aligned edges, this method performs coarse and fine positioning of the inner regions of chips in the same column to locate the left and right edge lines of the inner regions of chips in the same column. The wafer dicing track is then located using the inner region edge lines of two adjacent columns of chips in the wafer.

[0008] To achieve the above objectives, the present invention adopts the following technical solution:

[0009] The automatic chip dicing track positioning method in the wafer image involves fixing the wafer to the dicing motion platform of a fully automated wafer dicing machine's CNC system. It employs template matching and region growing algorithms for coarse positioning of the chip and its internal regions, and then uses a grayscale threshold algorithm based on the grayscale value distribution differences between the chip's internal and external regions to finely position the edges of the chip's internal regions, thereby locating the wafer dicing track. The method includes the following steps:

[0010] 1. Align the wafer.

[0011] The wafer image is acquired by a wafer dicing system, and the obtained wafer image is processed by frequency domain transformation. The angle between the wafer image coordinate system and the wafer dicing system coordinate system is determined by the obtained frequency domain information, and then the wafer is aligned.

[0012] 2. Create multi-level matching templates

[0013] Based on the shape and grayscale distribution characteristics of the chips in the wafer, a multi-level matching template is made for the chips. The coarse positioning of the wafer chips is achieved by matching the multi-level templates. The following are the steps for making the multi-level matching template.

[0014] (1) Create a Level 1 template

[0015] Wafer images are acquired using a wafer dicing system, and a complete chip is cropped from the wafer image using a rectangular frame as a primary template. The light-colored portion in the center of the primary template is the chip's internal region (including the light-colored seams at its edges), and the dark-colored portion around it is the chip's external region.

[0016] (2) Create a secondary template

[0017] The primary template obtained in the first step is subjected to a second cut, shrinking the maximum range of the rectangular frame to within the chip edge and controlling the minimum range to outside the edge of the chip area, thus obtaining the secondary template of the chip.

[0018] 3. Coarse and fine combined positioning of the chip's inner edge area

[0019] (1) Extracting the location of the chip's internal region from the primary template.

[0020] The center point of the primary template obtained in the first step is selected as the seed point. A binary image is obtained by growing the region outwards from the seed point. The area within the chip is the white region of the binary image. The length u0 and width v0 of the area within the chip are obtained by summing the gray values ​​of the horizontal and vertical pixels passing through the seed point. To prevent excessive growth beyond the edge of the area within the chip, a threshold is set to reduce the size of the obtained area within the chip.

[0021] (2) Coarse positioning of edge points in the chip region

[0022] The first-level template image is obtained from the first step. Template matching algorithms are then used to perform template matching on the acquired wafer image to locate the coordinates of each complete chip within the wafer image, and the center point coordinates of each complete chip are obtained. The secondary positioning region of the chip can be obtained from the chip's position coordinates in the wafer image and the cropped position of the second-level template obtained in the previous step within the first-level template.

[0023] (3) Extract the coarse positioning area at the edge of the chip's internal region.

[0024] The edge position of the chip is initially coarsely located by the secondary positioning region of the chip and the chip region position extracted by region growing, resulting in the coarse positioning region of the chip region edge.

[0025] (4) Precise positioning of the chip's internal region edges

[0026] The light-colored gaps at the edge of the chip's internal region have a significant difference in grayscale values ​​between the inside and the sides. Based on this grayscale value distribution characteristic, a grayscale value threshold method is proposed to accurately locate the edge of the chip's internal region.

[0027] Because the internal region of the chip is approximately a rounded square with curvature at its four corners, thresholds are set to further reduce the positioning error of the inner region's edges to minimize this error. Within the reduced left and right coarse positioning regions, the area is further segmented along the y-axis into n layers. In each layer, the ratio of the cumulative grayscale values ​​of adjacent columns of pixels is calculated, resulting in a ratio array for each layer. Based on the grayscale distribution characteristics of the light-colored gaps at the chip's inner region edges, multiple extreme value searches are performed on the ratio array. The position of the final extreme value in the array determines the x-coordinate of the edge point of that layer, and its y-coordinate is the center coordinate of that layer along the y-axis. Thus, each layer can obtain one edge point coordinate; that is, the left and right inner regions of the chip can each have n inner region edge point coordinates located.

[0028] 4. Detection and correction of abnormal edge points

[0029] (1) Detection of abnormal edge points in the chip region

[0030] Due to limitations in wafer fabrication precision, light-colored seams at the edges of chip regions within some wafers are not always clearly visible, which can lead to abnormal edge point localization. Therefore, an anomaly detection algorithm is proposed to detect abnormal edge points.

[0031] Taking the coordinates of the edge point as the center point, take a pixel region block to the left and right of the center point respectively, and calculate the ratio of the sum of the gray values ​​of the left and right regions. Set a ratio threshold. For abnormal edge points on the left side of the chip region, if the ratio is less than this threshold, it is an abnormal point. For abnormal edge points on the right side of the chip region, if the ratio is greater than this threshold, it is an abnormal point.

[0032] (2) Correction of abnormal edge points in the chip region

[0033] After detecting anomalies in the first step, the location of these anomalies is corrected. Since the edge point location is abnormal due to the indistinct light-colored gaps at the chip's inner edge, based on the chip's inner edge characteristics, the ratio of the cumulative grayscale values ​​of the inner and outer columns of pixels in the layer containing the anomaly is the minimum value in the layer's ratio array. By finding the extreme value of this layer, the abscissa of the edge point within the chip's inner edge is repositioned, and the ordinate is the center coordinate of the y-axis of this layer.

[0034] 5. Fitting and positioning the cutting path at the edge points of the chip's internal region

[0035] Linear fitting is performed on the inner region edge points of the same column of chips in the wafer image to locate the left and right edge lines of the inner region of this column of chips. The right edge line of the first column of chips and the left edge line of the second column of chips are taken to determine the midline of these two lines. The slope and intercept of the midline are output to determine the dicing position.

[0036] The automatic chip dicing track localization method in wafer images disclosed in this invention is based on template matching algorithms and region growing algorithms for coarse chip localization, and then uses a grayscale thresholding algorithm to finely locate the edges of the chip regions, thereby locating the wafer dicing track. For the wafer in question, this invention starts from the grayscale distribution characteristics and chip shape characteristics of the chips in the wafer. Compared with traditional template matching and edge detection methods, it is not only effective in processing high-quality wafer images with regular shapes and uniform exposure, but also ensures positioning accuracy for wafer images with irregular chip shapes and rough edges, as well as for wafer images of poor quality acquired due to overexposure or underexposure. Its method has a wider range of applications and superior accuracy. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of the fully automated wafer dicing system involved in the present invention.

[0038] Figure 2 The wafer image outline diagram involved in this invention

[0039] Figure 3 This invention relates to a single complete chip template image cropped from a wafer image.

[0040] Figure 4 This is a binary image of a single chip template in a wafer after region growth, as per the present invention.

[0041] Figure 5 This is a schematic diagram illustrating the coarse positioning of the edge of a region within a single chip, as described in this invention.

[0042] Figure 6 This is a schematic diagram of the edge line and positioning dicing channel within the wafer positioning chip involved in the present invention.

[0043] Figure 7 This invention relates to an automatic chip dicing track positioning method in wafer images.

[0044] Figure 8 This invention relates to a method for coarse-fine edge positioning within a chip region.

[0045] Figure 9 The present invention relates to a method for detecting abnormal points at the edge of a region within a chip.

[0046] Figure 10The present invention relates to a method for correcting abnormal points at the edges of regions within a chip.

[0047] Explanation of markings in the attached diagram

[0048] A1-Rotating Control Console

[0049] A2-CCD camera

[0050] A3-Transparent Stage

[0051] A4-Wafer

[0052] A5 Laser Cutting Blade

[0053] A6-2 axis translation stage

[0054] u0: The length of the inner region in the chip

[0055] v0: Width of the inner region in the chip

[0056] K0(x0, y0): Position of the chip positioning center point

[0057] K1(x t1 y t1 ): Coordinates of the upper left corner of the chip's secondary positioning area

[0058] K2(x r1 y t1 ): Coordinates of the upper right corner of the chip's secondary positioning area

[0059] K3(x t1 y l1 ): Coordinates of the lower left corner of the chip's secondary positioning area

[0060] K4(x t2 y t2 ): Location of the upper right corner of the chip's internal region.

[0061] K5(x r2 y t2 ): The coordinates of the top left corner point within the chip's internal region.

[0062] K6(x t2 y l2 ): Location of the lower left corner of the chip's internal region.

[0063] H d1 Long coarse positioning area

[0064] L d1 : Wide coarse positioning area

[0065] B1: The straight line of the cutting track obtained from positioning

[0066] B2: Edge line of the chip's internal region obtained from positioning. Detailed Implementation

[0067] The present invention will now be described in further detail with reference to the accompanying drawings. As shown in the figures, the method for automatically locating chip dicing tracks in a wafer image includes the following steps:

[0068] 1. Wafer alignment

[0069] pass Figure 1 The wafer dicing system shown acquires wafer images and performs a Fourier transform on the images to obtain a spectrum. Due to the regular arrangement of the chips, two mutually perpendicular discrete point regions appear in the spectrum after the Fourier transform. According to the properties of the Fourier transform, the determined straight line will pass through the center of the image. The line detection method using Hough linear transform and principal component analysis is used to determine the straight line in the spectrum and obtain its angle in the image. This gives the angle between the wafer image coordinate system and the wafer dicing system coordinate system. Then, the wafer is aligned using the rotating control console A1.

[0070] 2. Create multi-level matching templates

[0071] (1) Create a Level 1 template

[0072] Wafer images are acquired using the CCD camera A2 to obtain wafer images. Figure 2 A complete chip is cropped from the wafer image using a rectangular frame as a template to obtain the chip's primary template. Figure 3 . Figure 3 The light-colored portion in the middle is defined as the internal chip region (including the light-colored seams at its edges), and the dark-colored portion around it is defined as the external chip region. Due to wafer fabrication precision issues, the light-colored seams at the edges of the internal chip region are not obvious in some wafers.

[0073] (2) Create a secondary template

[0074] Level 1 template Figure 3 A second cropping process is performed, shrinking the maximum cropping range of the rectangle to within the chip edge and controlling the minimum cropping range outside the chip's inner region edge, thus obtaining the chip's secondary template.

[0075] 3. Coarse and fine combined positioning of the edge points within the chip area

[0076] (1) Extracting the location of the chip's internal region from the primary template.

[0077] Select the first-level template obtained in the first step. Figure 3 The center point is used as the seed point, and a binary region is obtained by growing outwards from the seed point. Figure 5 .exist Figure 5The length u0 and width v0 of the region within the chip are obtained by calculating the cumulative sum of the gray values ​​of the horizontal and vertical pixels past the center point. To prevent the region from growing excessively beyond its inner edge, a threshold is set to reduce the size of the obtained inner region, with the length u = 0.8 * u0 and the width v = 0.8 * v0.

[0078] (2) Coarse positioning of the chip's internal region edges

[0079] From the first-level template Figure 3 Based on the NCC template matching algorithm, the acquired wafer images are analyzed. Figure 2 Template matching is performed to locate the coordinates of each complete chip in the wafer image, and the center point coordinates K0(x0, y0) of each complete chip are obtained. The obtained positions of the complete chips in the wafer image and the secondary templates within the primary template are then used to determine their positions. Figure 2 The intercepted position can be used to obtain the secondary positioning region S32 of the chip. The chip internal region position S33 obtained by the secondary positioning region of the chip and the region growth extraction is used to perform preliminary coarse positioning of the chip internal region edge.

[0080] (3) Extract the coarse positioning area at the edge of the chip's internal region.

[0081] Figure 5 The area selected by the large rectangle is the secondary positioning area of ​​the chip, and the area selected by the small rectangle is the extracted location of the chip's internal region. This allows for preliminary coarse positioning of the chip's internal region edge.

[0082] The coarse positioning area on the left edge of the chip's internal region: its horizontal coordinate direction is the horizontal coordinate x of point K1. t1 x-coordinate of point K4 t2 The ordinate of point K4 is y. t2 The y-coordinate of point K6 l2 The obtained coarse positioning area on the left edge of the chip's internal region has a horizontal length L. d1 Longitude H d1 .

[0083] Coarse positioning area on the right edge of the chip's internal region: the horizontal coordinate direction is the horizontal coordinate x of point K5. r2 x-coordinate of point K2 r1 ; Vertical coordinate direction: the vertical coordinate of point K5 (y) t2 The y-coordinate of point K6 l2 The coarse positioning area on the right edge of the chip's internal region has the same length and width as the left edge.

[0084] (4) Precise positioning of the chip's internal region edges

[0085] As in the template Figure 3As shown, the grayscale values ​​inside the light-colored gaps at the edge of the chip's internal region differ significantly from those on either side. This grayscale distribution characteristic is used to precisely locate the edge of the chip's internal region.

[0086] Because the inner region of the chip is approximately a rounded square (see...) Figure 7 The chip contains a coarse positioning region S35, which has a certain curvature at its four corners. To reduce the positioning error of the edge points, a threshold is set for the coarse positioning region at the chip's edge to further reduce its size. Within the coarse positioning region S35, the region is layered along the y-axis, resulting in 10 layers. In the left coarse positioning region, the ratio of the sum of gray values ​​of adjacent columns of pixels is calculated from left to right within each layer, resulting in a ratio array S39. In the right coarse positioning region, the ratio of the sum of gray values ​​of adjacent columns of pixels is calculated from right to left within each layer, resulting in a ratio array S310. Based on the gray value distribution characteristics of the light-colored gaps at the chip's edge, the ratio of the sum of gray values ​​of the inner and outer columns of pixels on the right edge of the light-colored gap is the maximum value in ratio arrays S39 and S310, yielding the position S311 of the maximum value in the array. By using a peak detection function to find the minimum value position S312 between the initial value position and the maximum value position S311 in the array, the horizontal coordinates S313 of the left and right edge points of the chip's region can be obtained. Its ordinate is the center coordinate of this layer's region along the y-axis. Thus, each layer can obtain the coordinates of an edge point, meaning that 10 edge points can be located on the left and right edges of each region within the chip.

[0087] 4. Detection and correction of abnormal points in the edge points of the chip region

[0088] (1) Detection of abnormal points at the edge of the chip region

[0089] Due to wafer fabrication precision limitations, some light-colored seams at the edges of chip regions within wafers are not obvious, leading to abnormal edge point positioning. To eliminate this type of edge point positioning anomaly, an anomaly detection algorithm is proposed to detect abnormal edge points.

[0090] Centered on the coordinates of an edge point, take two regions S41, one horizontally 1 pixel long and one vertically 20 pixels long, to the left and right of the edge point. Calculate the ratio S42 of the sum of the grayscale values ​​of the left and right regions, setting a threshold of 0.9. Within the left edge point of the chip region, if the ratio is greater than this threshold, it is considered an abnormal point S48; if it is less than this threshold, it is considered a normal point S47. Within the right edge point of the chip region, if the ratio is less than this threshold, it is considered an abnormal point S49; if it is greater than this threshold, it is considered a normal point S410.

[0091] (2) Correction of abnormal points at the edge of the chip region

[0092] After identifying the anomaly in the first step, the anomaly is relocated. The anomaly is caused by the indistinct light-colored gaps at the edges of the chip's internal regions. Based on the grayscale distribution characteristics, the ratio of the sum of the grayscale values ​​of the inner and outer columns of pixels within the region where the anomaly is located is the minimum value in the region ratio array S54 for this layer. By finding the position S56 of the minimum value in the region ratio array S54, the horizontal coordinate S57 of the edge point in this layer is relocated, and the vertical coordinate is the center point coordinate of the y-axis direction of this layer.

[0093] 5. Edge point fitting and positioning of cutting path

[0094] In a wafer image, the edge points of the inner regions located within the same column of chips are fitted with a straight line using the least squares method, such as... Figure 6 As shown. For chip regions located in the same column, processing is performed. Within these regions, the coordinates of the left and right edge points are fitted using the least squares method to obtain the left and right edge lines. The right edge line of the first column of chips and the left edge line of the second column of chips are taken, and the midline B1 of the two lines is calculated. The slope and intercept of the midline are output to the computer, which then determines the dicing path based on the distance between adjacent chips in the wafer, and adjusts... Figure 1 The 2-axis translation stage A6 performs dicing and cutting operations on the wafer using the laser cutting blade A5.

[0095] For the aforementioned wafer type, the image detection and positioning of the cutting path using this invention results in fast cutting path positioning speed and high accuracy, which can effectively improve wafer processing efficiency.

Claims

1. An automatic positioning method for chip dicing tracks in a wafer image, characterized in that... The process includes the following steps: Aligning the wafer using a fully automated wafer dicing system and capturing wafer images; extracting a single complete chip template from the wafer image; using multi-level templates and region growth to coarsely locate the edges of the chip's internal regions; proposing a grayscale threshold method based on the difference in grayscale values ​​between pixels inside and outside the chip to finely locate the edges of the chip's internal regions; detecting and adjusting anomalies in the located edge points; obtaining the edge lines of the chip's internal regions through straight line fitting from the final edge points; and locating the wafer dicing track positions using the adjacent internal region edge lines of two rows of chips. Template matching algorithms are used to match the acquired wafer image with a primary template image to locate the coordinates of each chip in the wafer image and the center point coordinates K0(x0, y0) of each complete chip. A region growing algorithm is used to grow a region outward from the center point of the primary template image, resulting in a binary image of the grown chip image. The sum of the gray values ​​of the horizontal and vertical pixels passing through the center point in the binary image is used to obtain the length u0 and width v0 of the chip's inner region. To prevent the region from growing excessively beyond its inner region edge, a threshold is set to reduce the size of the inner region, with the length u = 0.8 * u0 and the width v = 0.8 * v0. The edges of the chip's inner region are coarsely located using the chip positions located by template matching, the cut-off position of the secondary template relative to the primary template, and the size of the chip's inner region obtained by region growing. The above positioning method yields a coarse localization region for the chip's internal edge. Based on the difference in grayscale value distribution between the inner and outer regions of the chip within the wafer, a grayscale threshold algorithm is proposed to locate the chip's internal edge points. The coarse localization region is then layered into 10 layers. A ratio array is calculated by summing the grayscale values ​​of adjacent columns of pixels in each layer. A secondary extreme value search is performed on this ratio array: first, the maximum value is searched; second, the minimum value is searched within the array between the initial and maximum values. This yields the coordinates of the chip's internal edge points in each layer. After locating the chip's edge point coordinates, anomaly detection and correction are performed to improve edge positioning. Using the center point as the coordinate location, take two regions, one with a horizontal length of 1 pixel and a vertical length of 20 pixels, to the left and right of the center point. Calculate the ratio of the sum of the gray values ​​of the left and right regions. Set a ratio threshold of 0.

9. Points on the left edge of the chip region with values ​​greater than this threshold are defined as outliers, and points on the right edge of the chip region with values ​​less than this threshold are defined as outliers. After obtaining the outliers, perform an extreme value search again on the ratio array of the region layer containing the outliers to locate the minimum value in the ratio array and obtain the coordinates of the edge points of this region layer. In this way, the coordinates of 10 edge points on the left and right edges of each chip region are located.

2. The method for automatic positioning of chip dicing tracks in a wafer image according to claim 1, characterized in that: The wafer image is acquired by a fully automated wafer dicing system. A complete chip in the wafer image is cut out with a rectangular frame as a template to obtain the first-level template image. In the first-level template image, the maximum range of the rectangular frame is shrunk to inside the chip edge, and the minimum range is controlled to outside the edge of the chip area to obtain the second-level template image of the wafer chip.

3. The method for automatic positioning of chip dicing tracks in a wafer image according to claim 1, characterized in that: The edge points of the inner regions of chips in the same column within the wafer are obtained by straight line fitting using a fitting algorithm; the wafer dicing channel is located by taking the midline of the adjacent edge lines of two adjacent columns of chips.

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