A Comprehensive Radiation-Resistant Design Method for Load Hardware Modules

Abstract

The present invention discloses a radiation-resistant design method for an integrated payload hardware module, belonging to the field of radiation-resistant design of hardware modules, which includes the steps: following the requirements of the general function framework of the module, each digital module is composed of units such as MSU, PU, RU, CMU, and PSE, and the module root devices of all model modules are MSU, CMU, and PSE. Space-grade devices are selected, integrated circuits of other units of the module use non-space-grade devices, and passive devices use space-grade devices; the radiation resistance of the DSP of PU, the FPGA of PU, and the SRIO switching chip of RU is realized relying on MSU; the operation of the space-grade FPGA of MSU is monitored by a space-grade watchdog. When single-event upset effects cause abnormal firmware loading, program operation errors, or even crashes, the watchdog will perform firmware reloading on it, etc. The present invention has the advantages of standardization, generalization, high performance, and low cost.

Description

Technical Field

[0001] The present invention relates to the field of anti-radiation design of hardware modules, and more specifically, to an anti-radiation design method for an integrated payload hardware module. Background Art

[0002] The characteristics of an integrated electronic system are that most functions in the system are realized by adding different software to general hardware modules. By adopting an open system architecture and modular general design standards, the research and development and production costs are reduced, the development cycle is shortened, and the maintenance and support costs of the system are reduced. In the integrated electronic system, the hardware modules follow the requirements of the general function framework in terms of function unit division and design. The general function framework requirements for digital hardware modules are as follows: each digital module consists of a module support unit (MSU), a processing unit (PU), a routing unit (RU), a setting management unit (CMU), a power supply support component (PSE), etc., to realize the standardized, generalized and integrated design of the module hardware circuit.

[0003] Traditional spaceborne payloads are mainly based on combined system designs, with each independent device as the basic unit to build the system. Such a system independently designs the corresponding apertures, channels and processing devices to implement functions such as radar, electronic reconnaissance, communication and fusion recognition. Due to the separation of functions, the relevant apertures, channels and processing resources are solidified, the system is closed, it is difficult to expand functions, the general resources cannot be multiplexed in time, the resource utilization rate is low, resulting in problems such as large volume, high weight, high power consumption, poor operability, many fault links, and high price. The system has weak expansion, upgrade and growth capabilities. At the same time, because both the "combined" system and the previous "separated" system bind the sensor functions and devices, the failure of a device or module in a physical device will cause the sensor function to be unable to be completed. Summary of the Invention

[0004] The purpose of the present invention is to overcome the deficiencies of the prior art, and provides an anti-radiation design method for an integrated payload hardware module, which overcomes the shortcomings of traditional methods and has the advantages of standardization, generalization, high performance and low cost.

[0005] The purpose of the present invention is achieved through the following solutions:

[0006] An anti-radiation design method for an integrated payload hardware module, comprising the following steps:

[0007] S1, the root devices of the module are MSU, CMU and PSE, and all the root devices are selected as aerospace-grade devices. The integrated circuits of other units of the module adopt non-aerospace-grade devices, and the passive devices adopt aerospace-grade devices;

[0008] S2, the anti-radiation of the DSP of the PU, the FPGA of the PU, and the SRIO switching chip of the RU relies on the MSU to achieve;

[0009] S3, the operation of the space-grade FPGA of the MSU is monitored by a space-grade watchdog. When a single event upset causes abnormal firmware loading, program operation errors, or even crashes, the watchdog will perform firmware reloading on it;

[0010] S4, the single event upset of the DSP of the PU is hardened through operation status monitoring and program reloading. The space-grade FPGA of the MSU forms a watchdog to monitor it, and when a single event upset causes program operation errors or even crashes in the DSP of the PU, it resets and reloads the program;

[0011] S5, the single event upset of the FPGA of the PU is hardened by the SRAM blind refresh method. The space-grade FPGA of the MSU reads the firmware of the FPGA of the PU from the space-grade parallel FLASH and periodically writes it into its SRAM;

[0012] S6, the single event upset of the SRIO switch chip of the RU is hardened by blindly refreshing its internal control registers. The space-grade FPGA of the MSU periodically refreshes the register data through the I2C interface.

[0013] Further, in step S3, it includes sub-steps:

[0014] After the module is powered on, after the space-grade watchdog chip detects that the power supply voltage rises above the threshold level, the reset signal outputs a low-level pulse;

[0015] The space-grade FPGA chip of the MSU receives this low-level pulse and starts the firmware loading process at the rising edge of the pulse, reading the firmware code from the space-grade serial FLASH chip through the SPI interface; at the same time, the watchdog counter of the space-grade watchdog chip is initialized and starts counting;

[0016] If the loading process is normal, the space-grade FPGA chip of the MSU constructs a MicroBlaze soft-core processor, and clears the watchdog counter of the space-grade watchdog chip by periodically outputting a dog-feeding signal to keep the circuit running normally; when a single event upset affects the normal operation of the MicroBlaze processor and it is unable to feed the dog, the space-grade FPGA chip of the MSU will reload.

[0017] Further, in step S4, it includes sub-steps:

[0018] The program loading of the DSP chip of the PU is read by the space-grade FPGA chip of the MSU from the space-grade parallel FLASH chip. After continuously reading the set number of times and the data is consistent, it is sent into the memory of the DSP chip of the PU.

[0019] Further, in step S5, it includes sub-steps:

[0020] The program loading of the FPGA chip of the PU is read by the MSU aerospace-grade FPGA chip from the aerospace-grade parallel FLASH chip. After continuously reading the set number of times with consistent data, it is then written into the SRAM of the FPGA chip of the PU.

[0021] Further, the aerospace-grade watchdog chip is selected as JSR706RD or its replacement model; the aerospace-grade FPGA chip of the MSU is selected as the domestic aerospace-grade V5 series FPGA chip JXCSX95T or its replacement model; the aerospace-grade serial FLASH chip is selected as the domestic JFM25FL032RH or its replacement model.

[0022] Further, the DSP chip of the PU is selected as the domestic FT-M6678H.

[0023] Further, the set number of times is 3 times.

[0024] Further, the FPGA chip of the PU is selected as the domestic JFM7VX690T36.

[0025] Further, the aerospace-grade parallel FLASH chip is selected as the domestic VDRF512M16RS56SS8V90 or its replacement model.

[0026] Further, the SRIO switching chip of the RU is selected as the domestic NMS1800.

[0027] The beneficial effects of the present invention include:

[0028] (1) The present invention has the technical effects of standardization and generalization: One of the differences between the method of the present invention and the traditional methods in this field is that it follows the requirements of the module general function framework. Each digital module is composed of units such as MSU, PU, RU, CMU, and PSE, and the module root devices of all model modules are MSU, CMU, and PSE. Aerospace-grade devices are selected, and the integrated circuits of other units of the module use non-aerospace-grade devices, while passive devices use aerospace-grade devices. The anti-radiation of the DSP of the PU, the FPGA of the PU, and the SRIO switching chip of the RU relies on the MSU to achieve, ensuring the standardization and generalization of the module hardware circuit. The method of the present invention breaks the traditional idea of mainly using combined system design for spaceborne payloads and overcomes a series of disadvantages existing in the traditional methods in this field recorded in the background.

[0029] (2) The present invention has the technical effects of high performance and low cost: By determining that the root devices of the module are MSU, CMU, and PSE, and selecting aerospace-grade devices, non-aerospace-grade integrated circuits are used for other units of the module, and aerospace-grade passive devices are used. The anti-radiation of the DSP of the PU, the FPGA of the PU, and the SRIO switching chip of the RU relies on the MSU to achieve, solving the problem of difficult selection of aerospace-grade devices for high-performance DSP, FPGA of the PU, and SRIO switching chips, and avoiding the problem of increased cost caused by the traditional hardware multi-mode redundancy or the selection of aerospace-grade devices. A high-performance hardware module with anti-radiation is realized at a relatively low cost. Description of the Drawings

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0031] Figure 1 It is a flowchart of the method steps of the embodiment of the present invention. Detailed Embodiments

[0032] All the features disclosed in all the embodiments in this specification, or all the steps in any disclosed method or process, except for mutually exclusive features and / or steps, can be combined and / or extended and replaced in any way.

[0033] In order to solve the technical problems in the background, after creative thinking, the inventor of the present invention applied the idea of integration to aerospace payloads, which is an integrated payload. The integrated payload changes the traditional "one-arrow-for-life" mode in which the mission function of the aerospace payload is bound to physical equipment and has no reconfiguration ability. In terms of design, an open structure of modularization, integration, and intelligence is adopted. The integrated payload integrates multiple system functions such as communication relay, electronic reconnaissance, electronic jamming, active detection of the ground / sea, global navigation and positioning, information distribution and broadcasting, space network switching, and multi-source information fusion, and can complete function reconfiguration through software loading, thus realizing a new concept of integrated electronic system with capabilities such as resource sharing and dynamic reconfiguration.

[0034] In the integrated payload, a large number of general hardware modules adopt large-scale digital integrated circuit devices using CMOS technology, such as FPGA, DSP, SRIO switching chips, etc. Taking such chips as the core, a large number of power supplies (DC / DC, LDO), clocks (crystal oscillators, clock buffers), memories (DDR3, FLASH), and interfaces (LVDS, MLVDS, RS422, CAN, etc.) also need to be configured in the circuit design. Unradiation-hardened CMOS circuits have low radiation resistance. Due to the existence of various high-energy particles in the space environment, radiation effects such as single-event upsets, lockups, burnouts, and gate breakdowns will occur. It is necessary to perform radiation-hardening design on the hardware module to improve reliability.

[0035] In the specific implementation process, as Figure 1 shown, an embodiment of the present invention provides a radiation-hardening design method for an integrated payload hardware module, including the following steps:

[0036] S1, the root devices of the module are MSU, CMU, and PSE. Select space-grade devices, and use non-space-grade devices for the integrated circuits of other units of the module and space-grade devices for passive devices;

[0037] S2, the radiation hardening of the DSP of the PU, the FPGA of the PU, and the SRIO switching chip of the RU relies on the MSU to achieve;

[0038] S3, the operation of the space-grade FPGA of the MSU is monitored by a space-grade watchdog. When the single-event upset effect causes abnormal firmware loading, program running errors, or even crashes, the watchdog will perform firmware reloading on it;

[0039] S4, the single-event upset effect of the DSP of the PU is hardened by monitoring the running state and program reloading. The space-grade FPGA of the MSU is used to form a watchdog to monitor it, and when the single-event upset effect causes the program of the DSP of the PU to run incorrectly or even crash, it will be reset and the program will be reloaded;

[0040] S5, the single-event upset effect of the FPGA of the PU is hardened by the SRAM blind refresh method. The space-grade FPGA of the MSU reads the firmware of the FPGA of the PU from the space-grade parallel FLASH and writes it into its SRAM regularly;

[0041] S6, the single-event upset effect of the SRIO switching chip of the RU is hardened by blindly refreshing its internal control registers. The space-grade FPGA of the MSU regularly refreshes the register data through the I2C interface.

[0042] In a further embodiment, the space-grade watchdog chip is selected as JSR706RD or its replacement model, the space-grade FPGA of the MSU is selected as the domestic space-grade V5 series FPGA chip JXCSX95T or its replacement model, the space-grade serial FLASH chip is selected as the domestic JFM25FL032RH or its replacement model, the space-grade parallel FLASH is selected as the domestic VDRF512M16RS56SS8V90 or its replacement model, the DSP of the PU is selected as the domestic FT-M6678H, the FPGA of the PU is selected as the domestic JFM7VX690T36, and the SRIO switch chip of the RU is selected as the domestic NMS1800.

[0043] In a further embodiment, after the module is powered on, when the space-grade watchdog chip JSR706RD monitors that the power supply voltage rises above the threshold level, it outputs a low-level pulse with a width of 200 ms for the reset signal. The space-grade FPGA chip JXCSX95T of the MSU receives this low-level pulse and starts the firmware loading process at the rising edge of the pulse, and reads the firmware code from the space-grade serial FLASH chip JFM25FL032RH through the SPI interface. At the same time, the watchdog counter of the space-grade watchdog chip JSR706RD is initialized and starts counting. The counter overflow time is 1.6 s. The maximum firmware of the space-grade FPGA chip JXCSX95T of the MSU is 35716096 bit, the loading rate can be set to 45 MHz, and the loading process takes about 0.8 s. If the loading process is normal, the space-grade FPGA chip JXCSX95T of the MSU constructs a MicroBlaze soft-core processor, and clears the watchdog counter of the space-grade watchdog chip JSR706RD by periodically outputting a dog-feeding signal to keep the circuit running normally. When a single-event upset affects the normal operation of the MicroBlaze processor and it is unable to feed the dog, the space-grade FPGA chip JXCSX95T of the MSU will be reloaded.

[0044] In a further embodiment, the program loading of the DSP chip FT-M6678H of the PU is read by the space-grade FPGA chip JXCSX95T of the MSU from the space-grade parallel FLASH chip VDRF512M16RS56SS8V90. After reading the data three times continuously and the data is consistent, it is sent to the memory of the DSP chip FT-M6678H of the PU.

[0045] In a further embodiment, the program loading of the FPGA chip JFM7VX690T36 of the PU is read by the MSU space-grade FPGA chip JXCSX95T from the space-grade parallel FLASH chip VDRF512M16RS56SS8V90. When the data read continuously three times is consistent, it is then written into the SRAM of the FPGA chip JFM7VX690T36 of the PU.

[0046] The embodiment of the present invention has the following improved effects compared with the prior art:

[0047] The present invention has the technical effects of standardization and generalization: Existing spaceborne payloads are mainly designed with combined systems, and the hardware circuits are mostly custom-designed. The anti-radiation design method for the integrated payload hardware module follows the requirements of the module general function framework. Each digital module consists of units such as MSU, PU, RU, CMU, and PSE, and the module root devices of all model modules are MSU, CMU, and PSE. Space-grade devices are selected, and the integrated circuits of other units of the module use non-space-grade devices, while the passive devices use space-grade devices. The anti-radiation of the DSP of the PU, the FPGA of the PU, and the SRIO switch chip of the RU relies on the MSU to achieve, ensuring the standardization and generalization of the module hardware circuit.

[0048] The present invention has the technical effects of high performance and low cost: The anti-radiation design method for the integrated payload hardware module determines that the module root devices are MSU, CMU, and PSE, and space-grade devices are selected. The integrated circuits of other units of the module use non-space-grade devices, while the passive devices use space-grade devices. The anti-radiation of the DSP of the PU, the FPGA of the PU, and the SRIO switch chip of the RU relies on the MSU to achieve, solving the problem of difficult selection of space-grade devices for high-performance DSP, FPGA of the PU, and SRIO switch chips, and avoiding the cost increase caused by the traditional hardware multi-mode redundancy or the selection of space-grade devices, and achieving a high-performance hardware module with anti-radiation at a low cost.

[0049] Embodiment 1

[0050] An anti-radiation design method for an integrated payload hardware module includes the following steps:

[0051] S1, the module root devices are MSU, CMU, and PSE, and all root devices are selected as space-grade devices. The integrated circuits of other units of the module use non-space-grade devices, and the passive devices use space-grade devices;

[0052] S2, the anti-radiation of the DSP of the PU, the FPGA of the PU, and the SRIO switch chip of the RU relies on the MSU to achieve;

[0053] S3. The operation of the space-grade FPGA of the MSU is monitored by a space-grade watchdog. When a single-event upset causes abnormal firmware loading, program running errors or even crashes, the watchdog will reload the firmware.

[0054] S4. The single-event upset of the DSP of the PU is fortified through running state monitoring and program reloading. The space-grade FPGA of the MSU constitutes a watchdog to monitor it, and when a single-event upset causes program running errors or even crashes of the DSP of the PU, it will reset and reload the program.

[0055] S5. The single-event upset of the FPGA of the PU is fortified through the SRAM blind refresh method. The space-grade FPGA of the MSU reads the firmware of the FPGA of the PU from the space-grade parallel FLASH and writes it into its SRAM regularly.

[0056] S6. The single-event upset of the SRIO switch chip of the RU is fortified through the blind refresh method of its internal control register. The space-grade FPGA of the MSU refreshes the register data regularly through the I2C interface.

[0057] Embodiment 2

[0058] Based on Embodiment 1, in step S3, it includes sub-steps:

[0059] After the module is powered on, after the space-grade watchdog chip monitors that the power supply voltage rises above the threshold level, the reset signal outputs a low-level pulse.

[0060] The space-grade FPGA chip of the MSU receives this low-level pulse and starts the firmware loading process at the rising edge of the pulse, reads the firmware code from the space-grade serial FLASH chip through the SPI interface; at the same time, the watchdog counter of the space-grade watchdog chip is initialized and starts counting.

[0061] If the loading process is normal, the space-grade FPGA chip of the MSU constructs a MicroBlaze soft-core processor, clears the watchdog counter of the space-grade watchdog chip by periodically outputting a dog-feeding signal to keep the circuit running normally; when a single-event upset affects the normal operation of the MicroBlaze processor and it is unable to feed the dog, the space-grade FPGA chip of the MSU will reload.

[0062] Embodiment 3

[0063] Based on Embodiment 1, in step S4, it includes sub-steps:

[0064] The program loading of the DSP chip of the PU is read by the MSU space-grade FPGA chip from the space-grade parallel FLASH chip. After continuously reading the set number of times and the data being consistent, it is then sent to the memory of the DSP chip of the PU.

[0065] Example 4

[0066] Based on Example 1, in step S5, it includes sub-steps:

[0067] The program loading of the FPGA chip of the PU is read by the MSU space-grade FPGA chip from the space-grade parallel FLASH chip. After continuously reading the set number of times and the data being consistent, it is then written into the SRAM of the FPGA chip of the PU.

[0068] Example 5

[0069] Based on Example 2, the space-grade watchdog chip selects JSR706RD or its replacement model; the space-grade FPGA chip of the MSU selects the domestic space-grade V5 series FPGA chip JXCSX95T or its replacement model; the space-grade serial FLASH chip selects the domestic JFM25FL032RH or its replacement model.

[0070] Example 6

[0071] Based on Example 3, the DSP chip of the PU selects the domestic FT-M6678H.

[0072] Example 7

[0073] Based on Example 3, the set number of times is 3 times.

[0074] Example 8

[0075] Based on Example 4, the FPGA chip of the PU selects the domestic JFM7VX690T36.

[0076] Example 9

[0077] Based on Example 4, the space-grade parallel FLASH chip selects the domestic VDRF512M16RS56SS8V90 or its replacement model.

[0078] Example 10

[0079] Based on any one of Examples 1 to 9, the SRIO switching chip of the RU selects the domestic NMS1800.

[0080] The units involved in the embodiments of the present invention can be implemented in software or in hardware, and the described units can also be provided in a processor. Among them, the names of these units do not constitute a limitation to the unit itself in some cases.

[0081] According to one aspect of the present application, there is provided a computer program product or a computer program, the computer program product or the computer program including computer instructions, the computer instructions being stored in a computer-readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the methods provided in the above various alternative implementation manners.

[0082] As another aspect, the present application further provides a computer-readable medium, which may be included in the electronic device described in the above embodiments; or may exist alone without being assembled into the electronic device. The above computer-readable medium carries one or more programs, and when the one or more programs are executed by an electronic device, the electronic device implements the methods described in the above embodiments.

[0083] The parts not involved in the present invention are the same as the prior art or can be implemented by the prior art.

[0084] The above technical solution is only one implementation manner of the present invention. For those skilled in the art, based on the disclosed application methods and principles of the present invention, it is easy to make various types of improvements or deformations, not limited to the methods described in the above specific implementation manners of the present invention. Therefore, the above-described manner is only preferred and does not have a limiting meaning.

[0085] Except for the above examples, those skilled in the art can obtain inspiration according to the above disclosure or make modifications using the knowledge or technology in related fields to obtain other embodiments. The features of each embodiment can be interchanged or replaced. As long as the modifications and changes made by those skilled in the art do not depart from the spirit and scope of the present invention, they should all be within the protection scope of the claims attached to the present invention.

Claims

1. A radiation-resistant design method for an integrated payload hardware module, characterized in that, It includes the following steps: S1. The module root devices are MSU, CMU, and PSE, and all root devices are selected as aerospace-grade devices. The integrated circuits of other units of the module use non-aerospace-grade devices, and the passive devices use aerospace-grade devices; S2. The radiation resistance of the DSP of the PU, the FPGA of the PU, and the SRIO switching chip of the RU is realized relying on the MSU; S3. The operation of the aerospace-grade FPGA of the MSU is monitored by an aerospace-grade watchdog. When the single-event upset effect causes abnormal firmware loading, program running errors, or even crashes, the watchdog will perform firmware reloading on it; S4. The single-event upset effect of the DSP of the PU is strengthened through running state monitoring and program reloading. The aerospace-grade FPGA of the MSU is configured as a watchdog to monitor it, and when the single-event upset effect causes program running errors or even crashes of the DSP of the PU, it will be reset and the program will be reloaded; S5. The single-event upset effect of the FPGA of the PU is strengthened through the SRAM blind refresh method. The aerospace-grade FPGA of the MSU reads the firmware of the FPGA of the PU from the aerospace-grade parallel FLASH and writes it into its SRAM regularly; S6. The single-event upset effect of the SRIO switching chip of the RU is strengthened through the blind refresh method of its internal control register. The aerospace-grade FPGA of the MSU refreshes the register data regularly through the I2C interface.

2. The anti-irradiation design method of the integrated load hardware module according to claim 1, wherein In step S3, it includes sub-steps: After the module is powered on, when the aerospace-grade watchdog chip detects that the power supply voltage rises above the threshold level, it outputs a low-level pulse for the reset signal; The aerospace-grade FPGA chip of the MSU receives this low-level pulse and starts the firmware loading process at the rising edge of the pulse, reading the firmware code from the aerospace-grade serial FLASH chip through the SPI interface; at the same time, the watchdog counter of the aerospace-grade watchdog chip is initialized and starts counting; If the loading process is normal, the aerospace-grade FPGA chip of the MSU constructs a MicroBlaze soft-core processor, and clears the watchdog counter of the aerospace-grade watchdog chip by periodically outputting a dog-feeding signal to keep the circuit running normally; when a single-event upset affects the normal operation of the MicroBlaze processor and it is unable to feed the dog, the aerospace-grade FPGA chip of the MSU will reload.

3. The anti-irradiation design method of the integrated payload hardware module according to claim 1, wherein In step S4, it includes sub-steps: The program loading of the DSP chip of the PU is read from the aerospace-grade parallel FLASH chip by the aerospace-grade FPGA chip of the MSU. After continuously reading the set number of times and the data is consistent, it is sent into the memory of the DSP chip of the PU.

4. The anti-irradiation design method of the integrated payload hardware module according to claim 1, characterized in that In step S5, it includes sub-steps: The program loading of the FPGA chip of the PU is read from the aerospace-grade parallel FLASH chip by the aerospace-grade FPGA chip of the MSU. After continuously reading the set number of times and the data is consistent, it is written into the SRAM of the FPGA chip of the PU.

5. The anti-irradiation design method of the integrated payload hardware module according to claim 2, wherein The aerospace-grade watchdog chip is selected as JSR706RD or its replacement model; the aerospace-grade FPGA chip of the MSU is selected as the domestic aerospace-grade V5 series FPGA chip JXCSX95T or its replacement model; the aerospace-grade serial FLASH chip is selected as the domestic JFM25FL032RH or its replacement model.

6. The anti-irradiation design method of the integrated load hardware module according to claim 3, characterized in that The DSP chip of the PU is selected as the domestic FT-M6678H.

7. The anti-irradiation design method of the integrated load hardware module according to claim 3, characterized in that The set number of times is 3 times.

8. The anti-radiation design method for the integrated payload hardware module according to claim 4, characterized in that The FPGA chip of the PU is selected as the domestic JFM7VX690T36.

9. The anti-irradiation design method of the integrated payload hardware module according to claim 4, characterized in that The aerospace-grade parallel FLASH chip is selected as the domestic VDRF512M16RS56SS8V90 or its replacement model.

10. The anti - radiation design method of the integrated load hardware module according to any one of claims 1 to 9, characterized in that, The SRIO switching chip of the RU is selected as the domestic NMS1800.

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