Chip-compatible three-dimensional integrated system and manufacturing method thereof

Abstract

The present invention provides a three-dimensional integrated system of compatible chips and a manufacturing method thereof, wherein at least one functional chip is expanded to form an extended chip including the functional chip and a peripheral pad, and the pad of the functional chip is electrically led out to the peripheral pad by rewiring. Based on the alignment and bonding of the two extended chips corresponding to the peripheral pads, or based on the alignment and bonding of a functional chip and an extended chip, the electrical connection and three-dimensional integration between the two functional chips are simply and efficiently completed, and the integrated connection between the two independent functional chips is realized based on the peripheral extended pad. Each functional chip can be manufactured using its own independent process system, and each functional chip can work independently to ensure optimal performance. The process compatibility with the functional chip is strong and the usage scenarios are wide. At the same time, the three-dimensional integration and electrical connection are realized based on the peripheral extended pad. Compared with the complex silicon through-silicon via integrated interconnection technology, the manufacturing process is relatively simple, the technical difficulty is low, and the yield rate is high.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a chip-compatible three-dimensional integrated system and a manufacturing method thereof. Background Art

[0002] Optoelectronic components such as photoelectric detectors and image sensors are limited in their large-scale application in airborne and aerospace applications due to complex peripheral drivers and low integration. Three-dimensional integration (3D integration) of optoelectronic components and other electronic components is the trend toward achieving high-level chip-level integration. To achieve 3D integration of chips with varying structures and types, top-level architecture design is crucial. The rationality of this architecture directly determines the direction and path of 3D integration, as well as the performance of the 3D integrated chip.

[0003] However, the current three-dimensional integration technology solutions for multiple functional chips have at least the following defects: First, in the monolithic three-dimensional integration based on CMOS technology, each functional chip is not independent, the performance of the functional chip cannot be optimized, and the types of integrated functional chips are subject to certain restrictions. Different functional chips produced by different process routines cannot be integrated with each other; Second, using through-silicon via (TSV) technology as a carrier to achieve three-dimensional integration or three-dimensional stacking of chips of different structures and types, it is necessary to perform multiple etching and deposition of through-silicon vias based on the stacking connection between multiple different functional chips. The manufacturing process is relatively complex, the technical difficulty is high, and the yield is low.

[0004] Therefore, there is an urgent need for a three-dimensional integrated architecture technology solution that is compatible with a variety of chips of different process types, has a simple manufacturing process and a high yield. Summary of the Invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a three-dimensional integrated architecture technical solution for multiple functional chips to solve the above-mentioned technical problems.

[0006] To achieve the above-mentioned objectives and other related objectives, the present invention provides the following technical solutions.

[0007] A chip-compatible three-dimensional integrated system, comprising at least:

[0008] A first chip has a front side and a back side that are opposite to each other, the front side including a first area and a second area, the second area being arranged around the first area, a first function chip being arranged on the first area, M first pads being arranged on the second area, the first function chip having N pads, the N pads of the first function chip being electrically connected to the N first pads in a one-to-one correspondence, and the K pads of the first function chip need to be interconnected with the second function chip;

[0009] The second chip has a front side and a back side that are opposite to each other, the front side including a third area and a fourth area, the fourth area being arranged around the third area, the second function chip being arranged on the third area, and M second pads being arranged on the fourth area, the second function chip having P pads, the P pads of the second function chip being electrically connected to the P second pads in a one-to-one correspondence, and the K pads of the second function chip need to be interconnected with the first function chip;

[0010] The first chip and the second chip are aligned and bonded by bonding the M first pads to the M second pads in a one-to-one correspondence, and the K pads of the first function chip are electrically connected to the K pads of the second function chip in a one-to-one correspondence;

[0011] M, N, P, and K are integers greater than or equal to 2, respectively, and N<M<N+P, P<M<N+P, K<N, K<P, and M=N+PK.

[0012] Optionally, M first pads are arranged around the first functional chip, M second pads are arranged around the second functional chip, and the M first pads on the second area are aligned one by one with the M second pads on the fourth area.

[0013] Optionally, M through holes are provided on the back surface of the first chip, and the M through holes expose the M first pads in a one-to-one correspondence.

[0014] A chip-compatible three-dimensional integrated system, comprising at least:

[0015] A first chip having a front side and a back side arranged opposite to each other, wherein the front side includes a first area, a second area, and a third area, the second area being arranged around the first area, and the third area being arranged around the second area, a first function chip being arranged on the first area, p first pads being arranged on the second area, and m second pads being arranged on the third area, the first function chip having n pads, the n pads of the first function chip being electrically connected to the n second pads in a one-to-one correspondence, the p first pads being electrically connected to the p second pads in a one-to-one correspondence, and the k pads of the first function chip need to be interconnected with the second function chip;

[0016] The second function chip has a front side and a back side that are opposite to each other, and p pads are electrically connected to the front side of the chip, and k pads of the second function chip need to be interconnected with the first function chip;

[0017] The p pads of the second function chip are connected to the p first pads in a one-to-one correspondence, so that the second function chip is arranged on the second area of ​​the first chip, and the k pads of the first function chip are electrically connected to the k pads of the second function chip in a one-to-one correspondence;

[0018] m, n, p, and k are integers greater than or equal to 2, respectively, and n<m<n+p, p<m<n+p, k<n, k<p, and m=n+pk.

[0019] Optionally, the m second pads are arranged around the first function chip and the p first pads, and the p first pads on the second area are aligned one-to-one with the p second pads on the second function chip.

[0020] Optionally, m through holes are provided on the back surface of the first chip, and the m through holes expose m second pads in a one-to-one correspondence.

[0021] A method for manufacturing a chip-compatible three-dimensional integrated system, comprising:

[0022] Obtaining a layout design of a first function chip and a layout design of a second function chip;

[0023] Determine, based on the layout design of the first function chip and the layout design of the second function chip, the number N of pads of the first function chip, the number P of pads of the second function chip, and the number K of pads required to be electrically connected between the first function chip and the second function chip;

[0024] Expanding the layout design of the first function chip, disposing M first pads around the periphery of the first function chip, wherein N of the first pads are electrically connected to the N pads of the first function chip in a one-to-one correspondence, to obtain a layout design of the first chip;

[0025] The layout design of the second function chip is expanded, and M second pads are arranged around the periphery of the second function chip, and P of the second pads are electrically connected to the P pads of the second function chip in a one-to-one correspondence, to obtain a layout design of the second chip;

[0026] manufacturing the first chip with reference to the layout design of the first chip;

[0027] manufacturing the second chip with reference to the layout design of the second chip;

[0028] The first chip and the second chip are aligned and bonded by bonding the M first pads to the M second pads in a one-to-one correspondence, and the K pads of the first function chip are electrically connected to the K pads of the second function chip in a one-to-one correspondence;

[0029] Among them, M, N, P, and K are integers greater than or equal to 2, and N<M<N+P, P<M<N+P, K<N, K<P, and M=N+PK.

[0030] Optionally, the first chip has a front side and a back side that are opposite to each other, the first functional chip and M first pads are formed on the front side of the first chip, and the method for manufacturing the three-dimensional integrated system of compatible chips further includes:

[0031] performing a thinning process on the back side of the first chip;

[0032] Etching the back surface of the first chip to form M through holes on the back surface of the first chip, wherein the M through holes expose the M first pads in a one-to-one correspondence;

[0033] Slicing, packaging and testing are performed in sequence to obtain the three-dimensional integrated system.

[0034] A method for manufacturing a chip-compatible three-dimensional integrated system, comprising:

[0035] Obtaining a layout design of a first function chip and a layout design of a second function chip;

[0036] Determine, based on the layout design of the first function chip and the layout design of the second function chip, the number n of pads of the first function chip, the number p of pads of the second function chip, and the number k of pads that need to be electrically connected between the first function chip and the second function chip;

[0037] The layout design of the first function chip is expanded, and a chip connection area is designed outside the first function chip, wherein p first pads are provided on the chip connection area, and m second pads are provided around the first function chip and the p first pads. The first function chip has n pads, and the n pads of the first function chip are electrically connected to the n second pads in a one-to-one correspondence, and the p first pads are electrically connected to the p second pads in a one-to-one correspondence, thereby obtaining a layout design for the first chip.

[0038] manufacturing the first chip with reference to the layout design of the first chip;

[0039] Referring to the layout design of the second function chip, the second function chip is manufactured, and p pads are electrically connected to the front side of the second function chip;

[0040] The second function chip is disposed on the chip connection area of ​​the first chip by connecting the p pads of the second function chip to the p first pads in a one-to-one correspondence, and the k pads of the first function chip are electrically connected to the k pads of the second function chip in a one-to-one correspondence;

[0041] Wherein, m, n, p, and k are integers greater than or equal to 2, respectively, and n<m<n+p, p<m<n+p, k<n, k<p, and m=n+pk.

[0042] Optionally, the first chip has a front side and a back side that are opposite to each other, the first functional chip, p first pads, and m second pads are formed on the front side of the first chip, and the method for manufacturing the three-dimensional integrated system of compatible chips further includes:

[0043] performing a thinning process on the back side of the first chip;

[0044] Etching the back surface of the first chip to form m through holes on the back surface of the first chip, wherein the m through holes expose the m second pads in a one-to-one correspondence;

[0045] Slicing, packaging and testing are performed in sequence to obtain the three-dimensional integrated system.

[0046] Optionally, the first chip has a front side and a back side that are opposite to each other, the first functional chip, p first pads, and m second pads are formed on the front side of the first chip, and the method for manufacturing the three-dimensional integrated system of compatible chips further includes:

[0047] performing a thinning process on the back side of the first chip;

[0048] Etching the back surface of the first chip to form m through holes on the back surface of the first chip, wherein the m through holes expose the m second pads in a one-to-one correspondence;

[0049] Slicing, packaging and testing are performed in sequence to obtain the three-dimensional integrated system.

[0050] As described above, the three-dimensional integrated system with compatible chips and the manufacturing method thereof provided by the present invention have at least the following beneficial effects:

[0051] At least one functional chip is expanded to form an extended chip that includes the functional chip and peripheral pads, and the pads of the functional chip are electrically led out to the peripheral pads. Based on the one-to-one alignment and bonding of the two extended chips corresponding to the peripheral pads, the bonding between the two extended chips can be quickly and effectively achieved, and the three-dimensional stacking integration and electrical connection between the functional chips inside the two extended chips are simply and efficiently completed. Or based on the alignment connection between a functional chip and an extended chip, the integrated connection between a functional chip and an extended chip can be quickly and effectively achieved, and the three-dimensional stacking integration and electrical connection between a functional chip and the functional chips inside an extended chip are simply and efficiently completed. The stacking connection of two independent chips is achieved based on the peripheral extended pads. The functional chips involved in each independent chip can adopt their own independent process system and be independently manufactured. Their types are not restricted. Each functional chip can work independently to ensure optimal performance. The three-dimensional integrated system has high process compatibility with the integrated functional chips. At the same time, the three-dimensional stacking integration and electrical connection between chips are achieved based on the peripheral extended pads. Compared with the complex silicon through-silicon via integrated interconnection technology, the manufacturing process is relatively simple, the technical difficulty is low, and the yield rate is high. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1-Figure 3 Shown is a schematic structural diagram of a three-dimensional integrated system of compatible chips in an optional embodiment of the present invention.

[0053] Figure 4-Figure 6 It is a schematic structural diagram of a three-dimensional integrated system of compatible chips in another optional embodiment of the present invention.

[0054] Figure 7 It is a schematic diagram showing the steps of a method for manufacturing a three-dimensional integrated system compatible with chips in an optional embodiment of the present invention.

[0055] Figures 8-14 Shown is a process flow chart of a method for manufacturing a three-dimensional integrated system compatible with chips in an optional embodiment of the present invention.

[0056] Figures 15-19 It is a process flow chart showing a method for manufacturing a three-dimensional integrated system compatible with chips in another optional embodiment of the present invention. DETAILED DESCRIPTION

[0057] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0058] See also Figures 1 to 19 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner, so the diagrams only show the components related to the present invention rather than being drawn according to the number, shape and size of the components during actual implementation. During actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated. The structure, proportion, size, etc. shown in the diagrams attached to this specification are only used to match the content disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the conditions under which the present invention can be implemented. Therefore, they have no technical significance. Any modification of the structure, change in the proportional relationship or adjustment of the size should still fall within the scope of the technical content disclosed in the present invention without affecting the efficacy and purpose that can be achieved by the present invention.

[0059] As mentioned above in the background technology, the inventors have found that the current three-dimensional integration technology solutions for multifunctional chips generally include the following two technical solutions: one is a monolithic three-dimensional integration solution based on CMOS process. In the monolithic three-dimensional integration solution, based on the unified limitations of CMOS process, the types of integrated functional chips are limited. They can only be functional chips based on CMOS process and are not compatible with functional chips manufactured by other processes. Moreover, the functional chips are not independent of each other, and the performance of a single functional chip cannot reach the optimal level; the other is a three-dimensional integration solution based on silicon via technology. Although it can realize three-dimensional integration between multiple functional chips of different structures and different process types, it requires multiple implementations of silicon via process based on stacked connections between multiple different functional chips. The manufacturing process is relatively complex, the technical difficulty is high, and the yield is low.

[0060] Based on this, the present invention proposes a three-dimensional integration technology solution that is compatible with chips of different process types and chips of different functional modules: for two functional chips that need to be integrated, at least one functional chip is expanded, and a solder pad is set on the periphery of the functional chip, and then the integrated connection of the two independent chips is realized based on the solder pad expanded on the periphery of the functional chip, so that the functional chips involved in each independent chip are not restricted, and can be manufactured using their own independent process systems. Each functional chip can work independently to improve the process compatibility of the integrated functional chip; at the same time, based on the solder pad expanded on the periphery of the functional chip, three-dimensional integration and electrical connection between chips are realized to simplify the integration process, reduce the difficulty of process technology, and improve the yield.

[0061] First, if Figure 1-Figure 3 As shown, in an optional embodiment of the present invention, a three-dimensional integrated system compatible with chips is provided, which at least includes:

[0062] A first chip 1 has a front side and a back side that are oppositely arranged. The front side includes a first area A and a second area B. The second area B is arranged around the first area A. A first function chip 10 is arranged on the first area A. M first pads 11 are arranged on the second area B. The first function chip 10 has N pads 101. The N pads 101 of the first function chip 10 are electrically connected to the N first pads 11 in a one-to-one correspondence via a wiring layer 12. The K pads 101 of the first function chip 10 need to be interconnected with the second function chip 20.

[0063] The second chip 2 has a front side and a back side that are opposite to each other. The front side includes a third area C and a fourth area D. The fourth area D is arranged around the third area C. The second function chip 20 is arranged on the third area C. M second pads 21 are arranged on the fourth area D. The second function chip 20 has P pads 201. The P pads 201 of the second function chip 20 are electrically connected to the P second pads 21 in a one-to-one correspondence through the wiring layer 22. The K pads 201 of the second function chip 20 need to be interconnected with the first function chip 10.

[0064] Among them, the first chip 1 and the second chip 2 are aligned and bonded by one-to-one bonding of M first pads 11 and M second pads 21, and bonding by wafer-level or die-level three-dimensional integration. The K pads 101 of the first functional chip 10 (as input and output interfaces) and the K pads 201 of the second functional chip 20 (as input and output interfaces) are electrically connected one-to-one; M, N, P, and K are integers greater than or equal to 2, and N<M<N+P, P<M<N+P, K<N, K<P, and M=N+PK.

[0065] In detail, Figure 1 The first function chip 10 shown has 18 pads 101. Figure 2 The second function chip 20 shown has 18 pads 201. Figure 1 32 first pads 11 are provided on the second area B shown in FIG. Figure 2 The second region D shown in FIG. 1 is provided with 32 second pads 21. The number of pads required to be electrically connected between the first function chip 10 and the second function chip 20 is 4. Figure 1-Figure 3 In the illustrated embodiment, the value of M is 32, the value of N is 18, the value of P is 18, and the value of K is 4. It is understood that the values ​​of M, N, P, and K are not limited to these values. As long as M, N, P, and K are integers greater than or equal to 2, and N<M<N+P, P<M<N+P, K<N, K<P, and M=N+PK, the value of M is slightly smaller than N+P, and the number of pads K required to electrically connect the first function chip 10 and the second function chip 20 needs to be deducted.

[0066] In detail, such as Figure 1-Figure 3 As shown, M first pads 11 are arranged around the first functional chip 10, and M second pads 21 are arranged around the second functional chip 20, which is convenient for the dispersed support connection when the first chip 1 and the second chip 2 are subsequently bonded; the size of the first chip 1 is the same as the size of the second chip 2, and the M first pads 11 on the second area B are aligned one by one with the M second pads 21 on the fourth area D, which is convenient for the rapid alignment when the first chip 1 and the second chip 2 are subsequently bonded.

[0067] In addition, the backside of the first chip 1 is thinned and provided with M through-holes (not shown in the figure). The M through-holes expose M first pads 11 in a one-to-one correspondence, facilitating the electrical lead-out and subsequent packaging of each functional chip in the three-dimensional integrated system. It is understood that the M through-holes can also be provided on the backside of the second chip 2, with the M through-holes on the backside of the second chip 2 exposing M second pads 21 in a one-to-one correspondence. This will not be further described here.

[0068] In more detail, Figure 1-Figure 3 In the embodiment shown, the first chip 1 is formed by expanding the first functional chip 10, and the second chip 2 is formed by expanding the second functional chip 20. The size specifications of the first functional chip 10 and the second functional chip 20 are inconsistent, and the distribution of the corresponding pads is quite different. The first functional chip 10 and the second functional chip 20 are expanded at the same time to obtain a first chip 1 and a second chip 2 with exactly the same size specifications. All the pads 101 of the first functional chip 10 are electrically led out to the first pads 11, and all the pads 201 of the second functional chip 20 are electrically led out to the second pads 21. The number of first pads 11 on the first chip 1 is the same as the number of second pads 21 on the second chip 2, and the distribution position of the first pads 11 on the first chip 1 is the same as the distribution position of the second pads 21 on the second chip 2. Based on this, the alignment connection between the first chip 1 and the second chip 2 can be quickly achieved, completing the three-dimensional integration and electrical connection between the first functional chip 10 and the second functional chip 20.

[0069] Among them, the first functional chip 10 and the second functional chip 20 can be functional chips of the same type, such as photodetectors arranged in series and parallel, or they can be functional chips of different types, such as one is a photodetector and the other is a drive control circuit. There is an electrical connection relationship between the first functional chip 10 and the second functional chip 20, forming a system-level integrated functional module, and the specific chip types of the first functional chip 10 and the second functional chip 20 are not limited.

[0070] It should be noted that in Figure 1-Figure 3In the embodiment shown, the first function chip 10 and the second function chip 20 are expanded respectively, and the process is relatively complicated. To further reduce the difficulty of process implementation, only one of the function chips can be expanded.

[0071] Therefore, in another optional embodiment of the present invention, a three-dimensional integrated system compatible with chips is provided, such as Figure 4-Figure 6 As shown, it at least includes:

[0072] The first chip 1' has a front side and a back side that are arranged opposite to each other. The front side includes a first area A1, a second area B1 and a third area C1. The second area B1 is arranged around the first area A1, and the third area C1 is arranged around the second area B1. The first functional chip 10' is arranged on the first area A1, p first pads 11' are arranged on the second area B1, and m second pads 12' are arranged on the third area C1. The first functional chip 10' has n pads 101'. The n pads of the first functional chip 10' are 101' is electrically connected to the n second pads 12' in one-to-one correspondence through the wiring layer 13', and the p first pads 11' are electrically connected to the p second pads 12' in one-to-one correspondence through the wiring layer 14', and the k pads 101' of the first function chip 10' need to be interconnected with the second function chip 20'; the second function chip 20' has a front and a back surface arranged opposite to each other, and p pads 201' are electrically led out of the front surface, and the k pads 201' of the second function chip 20' need to be interconnected with the first function chip 10';

[0073] Among them, the p pads 201' of the second function chip 20' are connected one-to-one with the p first 11', so that the second function chip 20' is set on the second area B1 of the first chip 1', and the k pads 101' of the first function chip 10' are electrically connected one-to-one with the k pads 201' of the second function chip 20'; m, n, p, k are respectively integers greater than or equal to 2, and n<m<n+p, p<m<n+p, k<n, k<p, m=n+pk.

[0074] In detail, Figure 4 The first function chip 10' shown has 10 pads 101'. Figure 5 The second function chip 20' shown has eight pads 201'. Figure 4 The second area B1 shown is provided with eight first pads 11'. Figure 4 The third area C1 shown in FIG. 1 is provided with 16 second pads 12'. The number of pads required for electrical connection between the first function chip 10' and the second function chip 20' is 2. Figure 4-Figure 6In the illustrated embodiment, the value of m is 16, the value of n is 10, the value of p is 8, and the value of k is 2. It is understood that the values ​​of m, n, p, and k are not limited to these values, as long as m, n, p, and k are integers greater than or equal to 2, and n<m<n+p, p<m<n+p, k<n, k<p, and m=n+pk, the value of m is slightly smaller than n+p, and the number of pads required to electrically connect the first function chip 10' and the second function chip 20' needs to be deducted.

[0075] In detail, such as Figure 4-Figure 6 As shown, m second pads 12' are arranged around the first functional chip 10' and the p first pads 11', which is convenient for the dispersed electrical lead-out of the pads of the first functional chip 10' and the pads of the second functional chip 20'; the size of the second functional chip 20' is the same as the size of the second area B1, and the p first pads 11' on the second area B1 are aligned one by one with the p second pads 12' of the second functional chip 20', which is convenient for the subsequent rapid alignment of the first chip 1' and the second functional chip 20' during integrated connection.

[0076] In addition, the back side of the first chip 1' is thinned, and M through holes (not shown in the figure) are provided on the back side of the first chip 1'. The M through holes expose M second pads 12' one by one, which facilitates the electrical lead-out and subsequent packaging of each functional chip in the three-dimensional integrated system.

[0077] It is understandable that, similar to the above embodiment, more functional chips can be integrated on the expanded first chip 1'. It is only necessary to reserve a functional chip setting area and corresponding electrical connection pads on the first chip 1'. For details, please refer to the above embodiment and will not be repeated here.

[0078] Secondly, with Figure 1-Figure 3 Corresponding to the embodiment shown, the present invention also provides a method for manufacturing a three-dimensional integrated system compatible with chips, such as Figure 7 As shown, it includes the steps of:

[0079] S1. Obtaining a layout design of a first function chip and a layout design of a second function chip;

[0080] S2. Determine the number N of pads of the first function chip, the number P of pads of the second function chip, and the number K of pads required to be electrically connected between the first function chip and the second function chip based on the layout design of the first function chip and the layout design of the second function chip;

[0081] S3. Expanding the layout design of the first function chip, disposing M first pads around the periphery of the first function chip, wherein N of the first pads are electrically connected to the N pads of the first function chip in a one-to-one correspondence, to obtain a layout design of the first chip;

[0082] S4. Expand the layout design of the second function chip, disposing M second pads around the periphery of the second function chip, wherein the P second pads are electrically connected to the P pads of the second function chip in a one-to-one correspondence, to obtain a layout design of the second chip;

[0083] S5. Manufacturing the first chip with reference to the layout design of the first chip;

[0084] S6. Manufacturing the second chip with reference to the layout design of the second chip;

[0085] S7. Align and bond the first chip and the second chip by bonding the M first pads to the M second pads in a one-to-one correspondence manner through wafer-level or die-level three-dimensional integration, and electrically connect the K pads of the first function chip to the K pads of the second function chip in a one-to-one correspondence;

[0086] Among them, M, N, P, and K are integers greater than or equal to 2, and N<M<N+P, P<M<N+P, K<N, K<P, and M=N+PK.

[0087] Specifically, in step S1, in an optional embodiment of the present invention, the obtained layout design of the first function chip 10 is as follows: Figure 8 As shown, Figure 8 As shown, the first function chip 10 has 18 pads 101, and the obtained layout design of the second function chip 20 Figure 9 As shown, Figure 9 As shown, the second function chip 20 has 18 pads 201 .

[0088] Among them, the values ​​of M and N are not limited to this. As long as M and N are integers greater than or equal to 2, the values ​​of M and N can be the same or different; and the size specifications of the first function chip 10 and the second function chip 20 are inconsistent, the distribution of the corresponding pads is quite different, the number of pads and the distribution position of the pads are different, and the first function chip 10 and the second function chip 20 cannot be directly aligned and electrically connected.

[0089] In detail, in step S2, based on the layout design of the first function chip and the layout design of the second function chip, the number N of solder pads of the first function chip, the number P of solder pads of the second function chip, and the number K of solder pads that need to be electrically connected between the first function chip and the second function chip are determined, and based on the above three parameters, the number M of first solder pads that need to be set around the first function chip or the number M of second solder pads that need to be set around the second function chip when the layout design is expanded are determined, M=N+PK, the value of M is slightly smaller than N+P, and the number K of solder pads that need to be electrically connected between the first function chip and the second function chip needs to be deducted.

[0090] In detail, in steps S3 to S4, based on the layout design of the first functional chip, the layout design of the second functional chip, and the number M of first pads and the number M of second pads obtained in step S2, the layout design of the first functional chip and the layout design of the second functional chip are expanded respectively, and M first pads are arranged around the periphery of the first functional chip, and M second pads are arranged around the periphery of the second functional chip, and the M first pads and the M second pads are aligned one by one. At the same time, through the redesigned wiring layer, the N first pads are electrically connected one by one to the N pads of the first functional chip, and the P second pads are electrically connected one by one to the P pads of the second functional chip, so as to obtain the layout design of the first chip and the second chip.

[0091] In more detail, in steps S3 to S4, to further facilitate alignment of the subsequent first chip and the second chip during bonding, the size of the first chip expanded based on the first functional chip is the same as the size of the second chip expanded based on the second functional chip.

[0092] In an optional embodiment of the present invention, Figure 8 The layout of the first functional chip 10 shown in FIG. 1 is expanded to obtain the following Figure 10 The layout design of the first chip 1 shown in FIG. Figure 9 The layout of the second function chip 20 shown in FIG. 2 is expanded to obtain the following Figure 11 The layout design of the second chip 2 is shown in FIG. Figure 10-11 As shown, the size of the first chip 1 is the same as the size of the second chip 2 .

[0093] Specifically, in steps S5-S6, the first chip and the second chip are independently manufactured with reference to the layout design of the first chip and the layout design of the second chip, thereby obtaining the first chip and the second chip. The first function chip within the first chip and the second function chip within the second chip can be manufactured using different process routines and are compatible with function chips manufactured using different process routines.

[0094] In an optional embodiment of the present invention, the first chip 1 manufactured by referring to the layout design of the first chip 1 is as follows: Figure 10 As shown, the second chip 2 manufactured by referring to the layout design of the second chip 2 is as shown in FIG. Figure 11 shown.

[0095] In detail, in step S7, wafer-level hybrid bonding or die-level bump bonding are used to bond the M first pads to the M second pads in a one-to-one correspondence, so that the first chip and the second chip are aligned and bonded, and the K pads of the first functional chip and the K pads of the second functional chip are electrically connected in a one-to-one correspondence, completing the three-dimensional integration of the first chip and the second chip.

[0096] In an optional embodiment of the present invention, Figure 10 The first chip 1 shown and Figure 11 The second chip 2 shown is bonded and integrated to obtain Figure 12 and Figure 13 The structure shown in FIG. Figure 12 is a side view, Figure 13 A partial perspective view of the bonding interface.

[0097] Optionally, the first chip has a front side and a back side that are arranged opposite to each other, and a first functional chip and a first pad are formed on the front side of the first chip, that is, the functional structure on the first chip is arranged on the front side thereof, such as Figure 7 As shown, the method for manufacturing the three-dimensional integrated system of compatible chips further includes the steps of:

[0098] S8, such as Figure 14 As shown, the back surface of the first chip 1 is thinned by surface flattening.

[0099] S9. Etching the back surface of the first chip 1 to form M through holes on the back surface of the first chip 1. The M through holes expose M first bonding pads in a one-to-one correspondence to facilitate packaging and pressure bonding of the first chip 1 and the second chip 2.

[0100] S10, performing dicing, packaging and testing in sequence to obtain a three-dimensional integrated system. For details, please refer to the existing technology and will not be repeated here.

[0101] It is understandable that, in step S9 , the M through holes may also be provided on the back side of the second chip, and the M through holes on the back side of the second chip expose the M second pads in a one-to-one correspondence.

[0102] It should be noted that in the above method embodiment, the first function chip and the second function chip are expanded separately, and the process is relatively complicated. In order to further reduce the difficulty of process implementation, only one of the function chips can be expanded.

[0103] Therefore, in another optional embodiment of the present invention, Figure 4-Figure 6 Corresponding to the embodiment shown, a method for manufacturing a three-dimensional integrated system compatible with chips is also provided, which includes the steps of:

[0104] Step 1: Obtaining a layout design of a first function chip and a layout design of a second function chip;

[0105] Step 2: Determine the number n of pads of the first function chip, the number p of pads of the second function chip, and the number k of pads required to be electrically connected between the first function chip and the second function chip based on the layout design of the first function chip and the layout design of the second function chip;

[0106] Step 3. Expand the layout design of the first function chip, design a chip connection area outside the first function chip, provide p first pads on the chip connection area, and provide m second pads surrounding the first function chip and the p first pads. The first function chip has n pads, and the n pads of the first function chip are electrically connected to the n second pads in a one-to-one correspondence, and the p first pads are electrically connected to the p second pads in a one-to-one correspondence, thereby obtaining the layout design of the first chip.

[0107] Step 4: Manufacturing the first chip based on the layout design of the first chip;

[0108] Step 5: Refer to the layout design of the second function chip to manufacture the second function chip, and electrically lead out p pads on the front side of the second function chip;

[0109] Stp6. The second function chip is set on the chip connection area of ​​the first chip by connecting the p pads of the second function chip with the p first pads in a one-to-one correspondence, and the k pads of the first function chip are electrically connected with the k pads of the second function chip in a one-to-one correspondence; wherein, m, n, p, and k are integers greater than or equal to 2, and n<m<n+p, p<m<n+p, k<n, k<p, and m=n+pk.

[0110] In detail, in step Stp2, based on the layout design of the first function chip and the layout design of the second function chip, the number n of solder pads of the first function chip, the number p of solder pads of the second function chip, and the number k of solder pads that need to be electrically connected between the first function chip and the second function chip are determined, and based on the above three parameters, the number m of first solder pads that need to be set around the first function chip when the layout design is expanded is determined, m=n+pk, the value of m is slightly smaller than n+p, and the number k of solder pads that need to be electrically connected between the first function chip and the second function chip needs to be deducted.

[0111] In an optional embodiment of the present invention, the obtained layout design of the first function chip 10' is as follows: Figure 15 As shown, Figure 15 As shown, the first function chip 10' has 10 pads 101', and the obtained layout design of the second function chip 20' Figure 16 As shown, Figure 16 As shown, the second function chip 20 ′ has eight pads 201 ′, and the number of pads required to be electrically connected between the first function chip 10 ′ and the second function chip 20 ′ is two.

[0112] In detail, in step Stp3, based on the layout design of the first functional chip, and the number m of first pads and the number p of pads of the second functional chip obtained in step Stp2, the layout design of the first functional chip is expanded, and a chip connection area is designed outside the first functional chip. P first pads are set on the chip connection area. The connection area is used to set up an independent second functional chip for connection. M second pads are set around the first functional chip and the p first pads. The first functional chip has n pads. Through the internally arranged wiring layer, the n pads of the first functional chip are electrically connected to the n second pads one by one, and the p first pads are electrically connected to the p second pads one by one, thereby completing the layout design of the first chip.

[0113] In an optional embodiment of the present invention, Figure 15 The layout design of the first functional chip 10' shown in FIG. 1 is expanded to obtain the following Figure 17 The layout design of the first chip 1' is shown.

[0114] Specifically, in steps Stp4 to Stp5, the first chip and the second chip are independently manufactured with reference to the layout design of the first chip and the layout design of the second chip. The first chip and the second chip can be manufactured using different process routines and are compatible with function chips manufactured using different processes.

[0115] In an optional embodiment of the present invention, the first chip 1' is manufactured by referring to the layout design of the first chip 1'. Figure 17 As shown, the second function chip 20' manufactured by referring to the layout design of the second function chip 20' is as shown in FIG. Figure 16 shown.

[0116] In detail, in step Stp6, wafer-level hot pressing and other methods are used to connect the p pads of the second functional chip to the p first pads one-to-one, so that the second functional chip is set on the chip connection area of ​​the first chip, and the k pads of the first functional chip are electrically connected to the k pads of the second functional chip one-to-one, completing the three-dimensional integration of the first chip and the second functional chip.

[0117] In an optional embodiment of the present invention, Figure 16 The first functional chip 20' shown and Figure 17 The first chip 1' shown is connected and integrated to obtain Figure 18-19The structure shown in FIG. Figure 18 is a side view, Figure 19 A partial perspective view of the bonding interface.

[0118] Optionally, the first chip has a front side and a back side that are opposite to each other, and a first functional chip, p first pads, and m second pads are formed on the front side of the first chip. The method for manufacturing the three-dimensional integrated system of compatible chips further includes the steps of:

[0119] Step 7: Thinning the back surface of the first chip by surface planarization.

[0120] Step 8: Etch the back surface of the first chip to form m through holes on the back surface of the first chip, where the m through holes expose m second pads in a one-to-one correspondence to facilitate subsequent packaging and pressure welding;

[0121] Stp9, perform dicing, packaging and testing in sequence to obtain a three-dimensional integrated system. For details, please refer to the existing technology and will not be repeated here.

[0122] It should be noted that many conventional process steps are omitted in the above embodiment, which is well known to those skilled in the art and will not be described in detail here. At the same time, the above embodiment only introduces the system-level three-dimensional integration of two functional chips. The system-level three-dimensional integration of three or more functional chips can be similar to this and will not be described in detail here.

[0123] In summary, in the three-dimensional integrated system of compatible chips and its manufacturing method provided by the present invention, at least one functional chip is expanded to form an extended chip that includes the functional chip and the peripheral pads, and the pads of the functional chip are electrically led out to the peripheral pads. Based on the one-to-one alignment and bonding of the two extended chips corresponding to the peripheral pads, the bonding integration between the two extended chips can be quickly and effectively achieved, and the three-dimensional stacking integration and electrical connection between the functional chips inside the two extended chips are simply and efficiently completed, or based on the alignment connection between a functional chip and an extended chip, the integrated connection between a functional chip and an extended chip can be quickly and effectively achieved. The three-dimensional stacking integration and electrical connection between a functional chip and the functional chip inside an extended chip are simply and efficiently completed. The stacking connection of two independent chips is realized based on the peripheral extended pads. The functional chips involved in each independent chip can adopt their own independent process system and be independently manufactured. Their types are not restricted. Each functional chip can work independently to ensure the best performance. The three-dimensional integrated system has high process compatibility for the integrated functional chips. At the same time, the three-dimensional stacking integration and electrical connection between chips are realized based on the peripheral extended pads. Compared with the complex silicon through-silicon via integrated interconnection technology, the manufacturing process is relatively simple, the technical difficulty is low, and the yield rate is high.

[0124] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A three-dimensional integrated system compatible with chips, characterized in that: At least: A first chip has a front side and a back side that are opposite to each other, the front side including a first area and a second area, the second area being arranged around the first area, a first function chip being arranged on the first area, M first pads being arranged on the second area, the first function chip having N pads, the N pads of the first function chip being electrically connected to the N first pads in a one-to-one correspondence, and the K pads of the first function chip need to be interconnected with the second function chip; The second chip has a front side and a back side that are opposite to each other, the front side including a third area and a fourth area, the fourth area being arranged around the third area, the second function chip being arranged on the third area, and M second pads being arranged on the fourth area, the second function chip having P pads, the P pads of the second function chip being electrically connected to the P second pads in a one-to-one correspondence, and the K pads of the second function chip need to be interconnected with the first function chip; The first chip and the second chip are aligned and bonded by bonding the M first pads to the M second pads in a one-to-one correspondence, and the K pads of the first function chip are electrically connected to the K pads of the second function chip in a one-to-one correspondence; M, N, P, and K are integers greater than or equal to 2, and N<M<N+P, P<M<N+P, K<N, K<P, and M=N+PK; The M first pads are arranged around the first function chip, the M second pads are arranged around the second function chip, and the M first pads on the second area are aligned one-to-one with the M second pads on the fourth area; M through holes are provided on the back surface of the first chip, and the M through holes expose the M first pads in a one-to-one correspondence.

2. A three-dimensional integrated system compatible with chips, characterized in that: At least: A first chip having a front side and a back side arranged opposite to each other, wherein the front side includes a first area, a second area, and a third area, the second area being arranged around the first area, and the third area being arranged around the second area, a first function chip being arranged on the first area, p first pads being arranged on the second area, and m second pads being arranged on the third area, the first function chip having n pads, the n pads of the first function chip being electrically connected to the n second pads in a one-to-one correspondence, the p first pads being electrically connected to the p second pads in a one-to-one correspondence, and the k pads of the first function chip need to be interconnected with the second function chip; The second function chip has a front side and a back side that are opposite to each other, and p pads are electrically connected to the front side of the chip, and k pads of the second function chip need to be interconnected with the first function chip; The p pads of the second function chip are connected to the p first pads in a one-to-one correspondence, so that the second function chip is arranged on the second area of ​​the first chip, and the k pads of the first function chip are electrically connected to the k pads of the second function chip in a one-to-one correspondence; m, n, p, k are integers greater than or equal to 2, and n<m<n+p, p<m<n+p, k<n, k<p, m=n+pk; The m second pads are arranged around the first function chip and the p first pads, and the p first pads on the second area are aligned one-to-one with the p second pads on the second function chip; M through holes are provided on the back surface of the first chip, and the m through holes expose m second pads in a one-to-one correspondence.

3. A method for manufacturing a three-dimensional integrated system compatible with chips, characterized in that: include: Obtaining a layout design of a first function chip and a layout design of a second function chip; Determine, based on the layout design of the first function chip and the layout design of the second function chip, the number N of pads of the first function chip, the number P of pads of the second function chip, and the number K of pads required to be electrically connected between the first function chip and the second function chip; The layout design of the first function chip is expanded, and M first pads are arranged around the periphery of the first function chip, and N of the first pads are electrically connected to the N pads of the first function chip in a one-to-one correspondence, to obtain a layout design of the first chip; The layout design of the second function chip is expanded, and M second pads are arranged around the periphery of the second function chip, and P of the second pads are electrically connected to the P pads of the second function chip in a one-to-one correspondence, to obtain a layout design of the second chip; manufacturing the first chip with reference to the layout design of the first chip; manufacturing the second chip with reference to the layout design of the second chip; The first chip and the second chip are aligned and bonded by bonding the M first pads to the M second pads in a one-to-one correspondence, and the K pads of the first function chip are electrically connected to the K pads of the second function chip in a one-to-one correspondence; Wherein, M, N, P, and K are integers greater than or equal to 2, respectively, and N<M<N+P, P<M<N+P, K<N, K<P, and M=N+PK; The first chip has a front side and a back side that are opposite to each other, and the first functional chip and M first pads are formed on the front side of the first chip. The method for manufacturing the three-dimensional integrated system of compatible chips further includes: performing a thinning process on the back side of the first chip; Etching the back surface of the first chip to form M through holes on the back surface of the first chip, wherein the M through holes expose the M first pads in a one-to-one correspondence; Slicing, packaging and testing are performed in sequence to obtain the three-dimensional integrated system.

4. A method for manufacturing a three-dimensional integrated system compatible with chips, characterized in that: include: Obtaining a layout design of a first function chip and a layout design of a second function chip; Determine, based on the layout design of the first function chip and the layout design of the second function chip, the number n of pads of the first function chip, the number p of pads of the second function chip, and the number k of pads that need to be electrically connected between the first function chip and the second function chip; The layout design of the first function chip is expanded, and a chip connection area is designed outside the first function chip, wherein p first pads are provided on the chip connection area, and m second pads are provided around the first function chip and the p first pads. The first function chip has n pads, and the n pads of the first function chip are electrically connected to the n second pads in a one-to-one correspondence, and the p first pads are electrically connected to the p second pads in a one-to-one correspondence, thereby obtaining a layout design for the first chip. manufacturing the first chip with reference to the layout design of the first chip; Referring to the layout design of the second function chip, the second function chip is manufactured, and p pads are electrically connected to the front side of the second function chip; The second function chip is disposed on the chip connection area of ​​the first chip by connecting the p pads of the second function chip to the p first pads in a one-to-one correspondence, and the k pads of the first function chip are electrically connected to the k pads of the second function chip in a one-to-one correspondence; Wherein, m, n, p, and k are integers greater than or equal to 2, respectively, and n<m<n+p, p<m<n+p, k<n, k<p, and m=n+pk; The first chip has a front side and a back side that are opposite to each other, and the first functional chip, p first pads, and m second pads are formed on the front side of the first chip. The method for manufacturing the three-dimensional integrated system of compatible chips further includes: performing a thinning process on the back side of the first chip; Etching the back surface of the first chip to form m through holes on the back surface of the first chip, wherein the m through holes expose the m second pads in a one-to-one correspondence; Slicing, packaging and testing are performed in sequence to obtain the three-dimensional integrated system.

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