Display substrate and display device

Abstract

The display substrate and display device provided by the present disclosure belong to the technical field of display technology, and can at least partially solve one of the existing technical problems. The display substrate of the present disclosure comprises a substrate substrate, and a plurality of sub-pixels arranged in an array on the substrate substrate; the adjacent sub-pixels have a spacing area; the spacing area comprises a first spacing area having a functional site and a second spacing area without a functional site; at least part of the functional site is provided with a functional part; the width of the first spacing area between adjacent two sub-pixels arranged in a first direction or a second direction is greater than the width of the second spacing area between adjacent two sub-pixels arranged in the same direction; wherein the width of the spacing area is equal to the shortest distance between the boundaries of the two sub-pixels corresponding to the spacing area.

Description

TECHNICAL FIELD

[0001] The present disclosure belongs to the technical field of display, and particularly relates to a display substrate and a display device. BACKGROUND

[0002] Organic light emitting diode (OLED) display is an important display mode. Compared with liquid crystal display (LCD), OLED display has the advantages of low energy consumption, low cost, self-luminous, wide viewing angle, fast response speed, etc., and is widely used in mobile phones, tablet computers, digital cameras and other fields.

[0003] An OLED display substrate mainly includes a substrate and a plurality of sub-pixels (or pixel units) arranged in an array (such as a matrix) on the substrate. Each sub-pixel includes an OLED device. The OLED device is formed by a vapor deposition process, that is, organic material is controlled to pass through an opening on a fine metal mask (FMM) to form a light-emitting layer (EML) and other structures of the OLED device. SUMMARY

[0004] The present disclosure at least partially solves one of the existing technical problems, and provides a display substrate and a display device.

[0005] In a first aspect, the present disclosure provides a display substrate, comprising a substrate, and a plurality of sub-pixels arranged in an array on the substrate.

[0006] The sub-pixels are arranged with a spacing area between adjacent sub-pixels; the spacing area includes a first spacing area with a functional site and a second spacing area without a functional site.

[0007] A functional element is arranged at least partially on the functional site.

[0008] The width of the first spacing area between two adjacent sub-pixels arranged in the same direction is greater than the width of the second spacing area between two adjacent sub-pixels arranged in the same direction. The width of the spacing area is equal to the shortest distance between the boundaries of the two sub-pixels corresponding to the spacing area.

[0009] In some embodiments, the width of the first spacing area is greater than or equal to 20 microns.

[0010] In some embodiments, the distance between the boundary of the functional element and the boundary of the closest sub-pixel is greater than or equal to 3 microns.

[0011] In some embodiments, the second spacing region has a width less than or equal to 19 μm.

[0012] In some embodiments, a shortest line between boundaries of two sub-pixels corresponding to the first spacing region passes through the functional element in the first spacing region.

[0013] In some embodiments, in a cross section passing through the shortest line and perpendicular to the substrate, a distance between boundaries of two sub-pixels corresponding to the first spacing region is greater than or equal to 20 μm, and a distance between the functional element in the first spacing region and the sub-pixels is greater than or equal to 3 μm.

[0014] In some embodiments, a line between geometric centers of two sub-pixels corresponding to the first spacing region passes through the functional element in the first spacing region.

[0015] In some embodiments, a line between geometric centers of two sub-pixels corresponding to the first spacing region passes through a geometric center of the functional element in the first spacing region.

[0016] In some embodiments, the first spacing region extends along a third direction at least in part;

[0017] The first spacing region extends along a fourth direction at least in part; the fourth direction intersects the third direction.

[0018] The first spacing region extending along the third direction at least in part and the first spacing region extending along the fourth direction at least in part have an overlapping region, and the functional element at least partially overlaps the overlapping region.

[0019] In some embodiments, a distance between adjacent functional elements is between 100 μm and 300 μm.

[0020] In some embodiments, a number of functional positions provided with the functional element accounts for at least 15% of a total number of the functional elements.

[0021] In some embodiments, the display substrate further comprises a pixel definition layer.

[0022] The pixel definition layer comprises pixel definition layer openings and pixel definition portions between the pixel definition layer openings.

[0023] The pixel definition layer openings define light emitting regions of the sub-pixels.

[0024] The functional element is disposed on a side of the pixel definition portion away from the substrate.

[0025] In some embodiments, the functional element and the pixel definition portion are in an integrated structure.

[0026] In some embodiments, among the plurality of sub-pixels adjacent to at least part of the functional element, the geometric center of at least one sub-pixel deviates from a straight line extending along the first direction, and the geometric centers of at least two sub-pixels in the same row as the sub-pixel in the first direction are located on the straight line;

[0027] and / or,

[0028] Among the plurality of sub-pixels adjacent to at least part of the functional element, the geometric center of at least one sub-pixel deviates from a straight line extending along the second direction, and the geometric centers of at least two sub-pixels in the same row as the sub-pixel in the second direction are located on the straight line; the second direction intersects the first direction.

[0029] In some embodiments, the sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel;

[0030] The first sub-pixel and the third sub-pixel are alternately arranged along the first direction to form a first pixel group, and are alternately arranged along the second direction to form a third pixel group; the second direction intersects the first direction;

[0031] The second sub-pixel is arranged along the first direction to form a second pixel group, and is arranged along the second direction to form a fourth pixel group;

[0032] Among them, the first pixel group and the second pixel group are alternately arranged along the second direction; the third pixel group and the fourth pixel group are alternately arranged along the first direction.

[0033] In some embodiments, among the spacing regions between the first sub-pixel and the third sub-pixel adjacent in the third pixel group, at least part of the spacing regions are the first spacing regions;

[0034] Among the spacing regions between the first sub-pixel and the third sub-pixel adjacent in the first pixel group, the spacing regions are the second spacing regions.

[0035] In some embodiments, among the spacing regions between the first sub-pixel and the third sub-pixel adjacent in the third pixel group, the spacing regions are alternately the first spacing regions and the second spacing regions along the second direction;

[0036] Among two adjacent third pixel groups, a first spacing region in one of the third pixel groups and a second spacing region in the other third pixel group are located between the same two rows of sub-pixels arranged along the first direction.

[0037] In some embodiments, the geometric centers of two first sub-pixels and two third sub-pixels arranged in an array successively connected form a virtual trapezoid.

[0038] The interval region between the first sub-pixel and the third sub-pixel corresponding to the bottom side of the virtual trapezoid is the first interval region, and the interval region between the first sub-pixel and the third sub-pixel corresponding to the top side of the virtual trapezoid is the second interval region.

[0039] In some embodiments, the bottom side of the virtual trapezoid is parallel to the second direction.

[0040] In some embodiments, the virtual trapezoid is a virtual isosceles trapezoid.

[0041] In some embodiments, in the first interval region at least partially located between the adjacent first sub-pixel and third sub-pixel, the geometric center of the functional element is located on the line connecting the geometric center of the first sub-pixel and the geometric center of the third sub-pixel corresponding to the first interval region.

[0042] In some embodiments, in the first interval region at least partially located between the adjacent first sub-pixel and third sub-pixel, along the second direction, the distance between the geometric center of the functional element and the geometric center of the first sub-pixel corresponding to the first interval region is less than the distance between the geometric center of the functional element and the geometric center of the third sub-pixel corresponding to the first interval region.

[0043] In some embodiments, in the first interval region at least partially located between the adjacent first sub-pixel and third sub-pixel, along the second direction, the geometric center of the functional element is located on the reference line corresponding thereto close to the side of the first sub-pixel corresponding to the first interval region; wherein the reference line of the functional element is the line connecting the geometric centers of the two second sub-pixels located on both sides of the functional element in the first direction.

[0044] In some embodiments, the shape of the first sub-pixel includes a square or a rounded square, one diagonal of the square or rounded square is parallel to the first direction, and the other diagonal is parallel to the second direction.

[0045] The shape of the third sub-pixel includes a square or a rounded square, one diagonal of the square or rounded square is parallel to the first direction, and the other diagonal is parallel to the second direction.

[0046] In some embodiments, at least part of the third sub-pixel is divided into an asymmetric first part and a second part along a straight line passing through the geometric center of the third sub-pixel and parallel to the first direction, and along the second direction, the maximum size of the first part is less than that of the second part.

[0047] In the first interval region between the first sub-pixel and the third sub-pixel adjacent along the second direction, at least part of the first interval region is an interval region between a first part of the third sub-pixel and the adjacent first sub-pixel.

[0048] In some embodiments, the sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel.

[0049] The first sub-pixel pair and the third sub-pixel are alternately arranged along a first direction to form a fifth pixel group; the first sub-pixel pair includes one first sub-pixel and one second sub-pixel arranged along a second direction; the second direction intersects the first direction.

[0050] The first sub-pixel and the second sub-pixel are alternately arranged along a second direction to form a sixth pixel group.

[0051] The third sub-pixel is arranged along the second direction to form a seventh pixel group.

[0052] The sixth pixel group and the seventh pixel group are alternately arranged along the first direction; and a plurality of the fifth pixel groups are arranged along the second direction.

[0053] In some embodiments, in the interval region between the third sub-pixels adjacent in the seventh pixel group, at least part of the interval region is the first interval region.

[0054] In the interval region between the first sub-pixel and the third sub-pixel adjacent in the fifth pixel group, and the interval region between the second sub-pixel and the third sub-pixel adjacent, is the second interval region.

[0055] In the interval region between the first sub-pixel and the second sub-pixel adjacent in the fifth pixel group, is the second interval region.

[0056] In some embodiments, at least part of the interval region between the third sub-pixels adjacent in the seventh pixel group is alternately the first interval region and the second interval region along the second direction.

[0057] In some embodiments, at least part of the third sub-pixel is divided into an asymmetric first part and a second part along a straight line passing through the geometric center of the third sub-pixel and parallel to the first direction; along the second direction, the maximum dimension of the first part is smaller than that of the second part.

[0058] In the first interval region between the third sub-pixels adjacent along the second direction, at least part of the first interval region is an interval region between the first parts of the third sub-pixels.

[0059] In some embodiments, the sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel.

[0060] The second sub-pixel pair, the first sub-pixel, and the third sub-pixel are alternately arranged along a first direction to form an eighth pixel group; the second sub-pixel pair includes two second sub-pixels arranged along a second direction; the second direction intersects the first direction.

[0061] A plurality of the eighth pixel groups are arranged along the second direction.

[0062] In two adjacent eighth pixel groups, one second sub-pixel pair of one eighth pixel group is located between one first sub-pixel and one third sub-pixel of another eighth pixel group along the first direction.

[0063] In some embodiments, at least part of the interval region between the adjacent first sub-pixel and the third sub-pixel in the interval region respectively located in two adjacent eighth pixel groups is the first interval region.

[0064] In some embodiments, at least part of the interval region between the adjacent first sub-pixel and the second sub-pixel in the interval region respectively located in two adjacent eighth pixel groups is the first interval region.

[0065] In some embodiments, the two second sub-pixels in the second sub-pixel pair are symmetrically distributed with respect to a line parallel to the first direction.

[0066] In some embodiments, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel.

[0067] In some embodiments, the function includes a spacer position, and the functional element includes a spacer.

[0068] In a second aspect, the embodiments of the present disclosure further provide a display device including any one of the display substrates described above. BRIEF DESCRIPTION OF DRAWINGS

[0069] Figure 1 A cross-sectional structure schematic diagram of a display substrate in some related technologies when supporting a high-fineness metal mask plate in an evaporation process;

[0070] Figure 2 A cross-sectional structure schematic diagram of a display substrate in some related technologies when separating from a high-fineness metal mask plate in an evaporation process;

[0071] Figure 3A circuit diagram of a pixel circuit in a sub-pixel of a display substrate provided in an embodiment of this disclosure;

[0072] Figure 4 This is a partial cross-sectional structural diagram of a display substrate provided in an embodiment of the present disclosure;

[0073] Figure 5 This is a schematic diagram illustrating the relationship between a sub-pixel and its light-emitting area in a display substrate, provided by an embodiment of the present disclosure.

[0074] Figure 6 This is a schematic diagram showing the partial distribution of a portion of a structure in a display substrate according to an embodiment of the present disclosure;

[0075] Figure 7 for Figure 6 A schematic diagram showing the location of a portion of the structure in a cross-section along line XX' in a display substrate;

[0076] Figure 8 This is a schematic diagram showing the partial distribution of a portion of a structure in a display substrate according to an embodiment of the present disclosure;

[0077] Figure 9 for Figure 8 A partially enlarged structural diagram;

[0078] Figure 10 for Figure 8 Another form of locally enlarged structural diagram;

[0079] Figure 11 A schematic diagram showing the distribution of some structures in another display substrate provided in an embodiment of this disclosure;

[0080] Figure 12 A schematic diagram showing the partial distribution of a portion of a structure in another display substrate provided in an embodiment of this disclosure;

[0081] Figure 13 for Figure 12 A partially enlarged structural diagram;

[0082] Figure 14 A schematic diagram showing the partial distribution of a portion of a structure in another display substrate provided in an embodiment of this disclosure;

[0083] Figure 15 A schematic diagram showing the partial distribution of a structure in a display substrate according to an embodiment of this disclosure;

[0084] Figure 16 for Figure 15 A schematic diagram of a partially enlarged structure;

[0085] Figure 17 forFigure 15 Another form of locally enlarged structural diagram;

[0086] Figure 18 This is a block diagram of a display device provided in an embodiment of the present disclosure. Detailed Implementation

[0087] To enable those skilled in the art to better understand the technical solutions of this disclosure, the disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0088] It is understood that the specific embodiments and accompanying drawings described herein are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0089] It is understood that, without conflict, the various embodiments of this disclosure and the features thereof can be combined with each other.

[0090] It is understood that, for ease of description, only the parts related to the embodiments of this disclosure are shown in the accompanying drawings, while the parts unrelated to the embodiments of this disclosure are not shown in the drawings.

[0091] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms do not indicate any order, quantity, or importance, but are merely used to distinguish different components; similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one; the terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the element or object listed following the word and its equivalents, without excluding other elements or objects; the terms “connected,” “linked,” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect; “upper,” “lower,” “left,” “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0092] Before describing the solutions of the embodiments of this disclosure in detail, some of the concepts involved will be explained by way of example below.

[0093] In the embodiments disclosed herein, a display substrate refers to a plate-like structure with a display structure used in a display device, more specifically an array substrate with a thin-film transistor array, and further specifically an array substrate for organic light-emitting diode (OLED) displays.

[0094] In the embodiments of the present disclosure, the display substrate includes a substrate (or base), which is a basis for carrying other display structures in the display substrate, i.e., other display structures of the display substrate are "provided on" the substrate. The substrate can be rigid, such as including a rigid material such as glass; or the substrate can be flexible, such as including a flexible material such as a polymer, so as to be used in a bendable display device (such as a flexible display device, a folding display device, etc.).

[0095] In the embodiments of the present disclosure, each "sub-pixel (or pixel unit)" refers to a minimum structure capable of being independently controlled to emit light of a required brightness. Specifically, the sub-pixel can be an organic electroluminescent device (OLED). The organic electroluminescent device is a device composed of a cathode, a light-emitting layer, and an anode, and the light-emitting layer can emit light of different brightnesses according to the size of the current flowing therethrough. The light-emitting layer can specifically include a hole injection layer (HIL), a hole transport layer (HTL), an organic light-emitting layer (EML), an electron transport layer (ETL), an electron injection layer (EIL), and the like.

[0096] In the embodiments of the present disclosure, the first sub-pixel, the second sub-pixel, and the third sub-pixel represent three different color sub-pixels, i.e., three sub-pixels capable of emitting light of different colors. The three colors of the first sub-pixel, the second sub-pixel, and the third sub-pixel can be three colors of a "three-primary color combination", and can further be a red sub-pixel, a green sub-pixel, and a blue sub-pixel. In part of the embodiments of the present disclosure, the first sub-pixel is taken as a red sub-pixel, the second sub-pixel is taken as a green sub-pixel, and the third sub-pixel is taken as a blue sub-pixel as an example for description; however, it should be understood that the above description of the first sub-pixel as a red sub-pixel, the second sub-pixel as a green sub-pixel, and the third sub-pixel as a blue sub-pixel does not constitute a limitation on the protection scope of the embodiments of the present disclosure. The specific manner of causing different types of sub-pixels to emit light of different colors is various, for example, the materials of the light-emitting layers of the organic electroluminescent devices of different types of sub-pixels can be different, or different types of sub-pixels are provided with color filters (CFs) of different colors, and the like, which will not be described in detail herein.

[0097] In the embodiments of the present disclosure, the structures of the sub-pixels are all provided on the substrate, and the positions of different sub-pixels are spaced apart. The above spacing is used to arrange pixel circuits for driving the sub-pixels, and various leads, electrodes, and the like for providing driving signals to the pixel circuits. For example, with reference to Figure 3The pixel circuit can include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst, and drive the organic electroluminescent device (OLED) corresponding to the sub-pixel to emit light of a required brightness under the control of driving signals such as a positive electrode driving signal (VDD), a negative electrode driving signal (VSS), a gate driving signal (Gtae), a data driving signal (Data), a reset driving signal (Reset'), an initialization driving signal (Vinit), a switch driving signal (EM), and the like. Since the pixel circuit has seven transistors and one capacitor, it is referred to as a 7T1C pixel circuit. However, it should be understood that the pixel circuit can also be in other specific forms, such as a 2T1C pixel circuit, a 3T1C pixel circuit, and the like.

[0098] In the embodiments of the present disclosure, part of the layers of the organic electroluminescent device of the sub-pixel can be beyond the range of the sub-pixel, for example, the cathodes of all the sub-pixels in the entire display substrate can form an integral cathode layer, and the range covered by the light-emitting layer of each sub-pixel can also be beyond the range of the sub-pixel. Therefore, in the embodiments of the present disclosure, the range of the sub-pixel is defined as the area where the cathode, the light-emitting layer, and the anode are in direct contact and stacked, thereby forming an area capable of emitting light.

[0099] In the embodiments of the present disclosure, the pixel definition layer (PDL) is used to define the range of the above sub-pixel. The pixel definition layer includes a plurality of pixel definition layer openings, and the pixel definition layer openings are pixel definition portions. The cathode, the light-emitting layer, and the anode can only contact to form the organic electroluminescent device at the pixel definition layer openings, and even if the cathode, the light-emitting layer, and the anode are present at the same time at the pixel definition portion, one of them (such as the anode) will be separated from the other two (such as the light-emitting layer and the cathode) by the pixel definition portion, so as to be unable to contact to form the organic electroluminescent device. Therefore, each sub-pixel is located in the pixel definition layer opening of the pixel definition layer, that is, the range of the pixel definition layer opening is the range of the sub-pixel, and the pixel definition portion corresponds to the interval between the sub-pixels.

[0100] In the embodiments of the present disclosure, the first direction and the second direction are two mutually intersecting directions parallel to the substrate base plate, i.e., the included angle between the first direction and the second direction can be any angle other than 0. Among them, as one of the modes of the embodiments of the present disclosure, the first direction and the second direction can further be perpendicular to each other, for example, one of the first direction and the second direction is a row direction, and the other is a column direction. In part of the embodiments of the present disclosure, the first direction is taken as the row direction, and the second direction is taken as the column direction. It should be understood that the above row direction and column direction are only two opposite directions in the display substrate, and have nothing to do with the shape, placement mode, etc. of the display substrate.

[0101] To further illustrate the structure of the display substrate of the embodiments of the present disclosure, the partial film layer structure in the display substrate of the embodiments of the present disclosure is exemplarily introduced below in combination with the preparation method of the display substrate, wherein, Figure 1 FIG. 1 is a partial cross-sectional structure schematic diagram of a display substrate according to an embodiment of the present disclosure.

[0102] As shown in FIG. 1, the display substrate according to the embodiments of the present disclosure can include a substrate base plate 010, a first flexible material layer 020, a first inorganic material layer 030, a semiconductor layer 040, a second flexible material layer 050, and a second inorganic material layer 060. Figures 1 to 17 The preparation method of the display substrate according to the embodiments of the present disclosure can specifically include the following steps:

[0103] S001, preparing a substrate base plate on a glass carrier plate.

[0104] As one of the modes of the embodiments of the present disclosure, the substrate base plate 010 of the display substrate can be a flexible substrate base plate.

[0105] For example, the substrate base plate 010 can include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer which are sequentially stacked. Among them, the material of the first flexible material layer and the second flexible material layer can adopt polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, etc. The material of the first inorganic material layer and the second inorganic material layer can adopt silicon nitride (SiNx) or silicon oxide (SiOx), etc., which is used to improve the water and oxygen resistance of the substrate base plate 010, so the first inorganic material layer and the second inorganic material layer are called barrier layers. The material of the semiconductor layer can adopt amorphous silicon (a-si).

[0106] For example, taking the material of each layer structure of the substrate 010 as PI1 / Barrier1 / a-si / PI2 / Barrier2, the preparation process can include: first, coating a layer of polyimide on a glass carrier plate, and after curing into a film, forming a first material layer (PI1); then, depositing a layer of inorganic material on the first flexible material layer, forming a first barrier (Barrier1) layer covering the first material layer; then, depositing a layer of amorphous silicon on the first barrier layer, forming an amorphous silicon layer (a-si) covering the first barrier layer; then, coating a layer of polyimide on the amorphous silicon layer, and after curing into a film, forming a second material layer (PI2); then, depositing a layer of inorganic material on the second flexible material layer, forming a second barrier layer (Barrier2) covering the second flexible material layer; finally, separating the first flexible material layer from the glass carrier plate by laser stripping or the like, to obtain the substrate 010.

[0107] S002、In the substrate 010 of the foregoing structure, a driving structure layer is prepared.

[0108] The driving structure layer includes a plurality of pixel circuits, and lead lines or the like for providing various driving signals to the pixel circuits. Each pixel circuit can include a plurality of transistors and at least one storage capacitor Cst, such as the 7T1C pixel circuit, 2T1C pixel circuit, 3T1C pixel circuit, etc. described above.

[0109] Figure 1 In the following description, only the structure of one transistor (such as the sixth transistor T6 in Figure 3 ) of the pixel circuit of each sub-pixel P is described as an example, but it should be understood that it does not represent the entire structure in the pixel circuit. Accordingly, the preparation process of the driving structure layer can include:

[0110] A first insulating film and a semiconductor film are sequentially deposited on the substrate 010, the semiconductor film is patterned by a patterning process, to form a first insulating layer 011 covering the entire substrate 010, and an active layer pattern disposed on the first insulating layer 011. The active layer pattern includes active regions of each transistor, and can also have partially conductive semiconductor structures as lead lines connecting different active regions, etc.

[0111] Then, a second insulating film and a first metal film are sequentially deposited, the first metal film is patterned by a patterning process, to form a second insulating layer 012 covering the active layer pattern, and a first gate metal layer pattern disposed on the second insulating layer 012. The first gate metal layer pattern includes gate electrodes of some transistors, and a first electrode of the storage capacitor Cst.

[0112] Subsequently, a third insulating thin film and a second metal thin film are sequentially deposited, the second metal thin film is patterned by a patterning process, a third insulating layer 013 covering the first gate metal layer is formed, and a second gate metal layer pattern is arranged on the third insulating layer 013. The second gate metal layer pattern includes a second electrode of a storage capacitor Cst and the like, which is opposite to a first electrode of the storage capacitor Cst.

[0113] Subsequently, a fourth insulating thin film is deposited, the fourth insulating thin film is patterned by a patterning process, a fourth insulating layer 014 covering the second gate metal layer is formed, at least two first vias are formed on the fourth insulating layer 014, and the fourth insulating layer 014, the third insulating layer 013 and the second insulating layer 012 in the two first vias are etched to expose the surface of the active region.

[0114] Subsequently, a third metal thin film is deposited, the third metal thin film is patterned by a patterning process, a source-drain metal layer pattern is formed on the fourth insulating layer 014, and the source-drain metal layer includes source electrodes and drain electrodes of part of the transistors (for example, the sixth transistor T6 in FIG. 6). Figure 3 The source electrodes and the drain electrodes can be connected to the corresponding active regions through the first vias, respectively.

[0115] As one of the embodiments of the present disclosure, the first insulating layer 011, the second insulating layer 012, the third insulating layer 013 and the fourth insulating layer 014 can be made of inorganic insulating materials, such as any one or a combination of more than one of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON). Each of the insulating layers can be a single-layer structure or a multi-layer composite structure and the like.

[0116] The first insulating layer 011 is also called a buffer layer (Buffer) for improving the water-oxygen resistance of the substrate 010 and improving the adhesion of the subsequent structure to the substrate 010. The second insulating layer 012 and the third insulating layer 013 are also called gate insulating layers (GI, Gate Insulator) for insulating the gate electrodes of the transistors and the active regions. The fourth insulating layer 014 is also called an interlayer dielectric layer (ILD, Interlayer Dielectric) for insulating part of the conductive structures arranged in different layers.

[0117] The first metal thin film, the second metal thin film and the third metal thin film are made of conductive metal materials, such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or a combination (alloy) of multiple metals, such as aluminum-neodymium alloy (AlNd), molybdenum-niobium alloy (MoNb) and the like. Each of the metal thin films can be a single-layer structure or a multi-layer composite structure, such as a Ti / Al / Ti multi-layer composite structure and the like.

[0118] The active layer thin film adopts a semiconductor material, such as an amorphous indium gallium zinc oxide material (a-IGZO), a zinc oxide nitride (ZnON), an indium zinc tin oxide (IZTO), or a metal oxide semiconductor material, or an amorphous silicon (a-Si), a polycrystalline silicon (p-Si), or a silicon-based semiconductor material, or a hexathienyl, a polythiophene, or an organic semiconductor material, that is, the present disclosure is applicable to a transistor manufactured based on oxide technology, silicon technology, and organic technology.

[0119] S003, forming a planarization layer (PLN) on the substrate 010 of the foregoing structure.

[0120] As one of the embodiments of the present disclosure, a planar thin film of an organic material is coated on the substrate 010 of the foregoing structure to form a planarization layer 015 covering the entire substrate 010, and a plurality of second vias are formed on the planar layer 015 by a mask, exposure, development, and other processes to respectively expose the surface of the drain electrode of the transistor (such as the sixth transistor T6 in FIG. 1) of each sub-pixel P. Figure 3

[0121] The planar layer 015 has a large thickness and good flow leveling to eliminate the step difference of the underlying structure, so that the subsequent organic electroluminescent device (OLED) can be formed on a relatively flat basis to improve its light emitting effect.

[0122] S004, forming a first electrode pattern on the substrate 010 of the foregoing structure.

[0123] As one of the embodiments of the present disclosure, a conductive thin film is deposited on the substrate 010 of the foregoing structure, and the conductive thin film is patterned by a patterning process to form a first electrode pattern, which includes the first electrode of the organic electroluminescent device of each sub-pixel P, and each first electrode is connected to the drain electrode of the transistor (such as the sixth transistor T6 in FIG. 1) through the second via. Figure 3

[0124] In some examples, the first electrode is an anode 213, and further a reflective anode.

[0125] ​​In some examples, the anode 213 can be a metallic material, such as any one or more combinations (alloys) of magnesium (Mg), silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb); the anode 213 can be a single-layer structure or a multi-layer composite structure, such as a Ti / Al / Ti multi-layer composite structure; or, the anode 213 can also be a stacked structure formed by a reflective metal and a transparent conductive material, such as an ITO / Ag / ITO, Mo / AlNd / ITO, etc. stacked structures.

[0126] S005. A pixel definition layer pattern is formed on the substrate 010 on which the aforementioned structure is formed.

[0127] As one embodiment of this disclosure, a pixel definition film is coated on the substrate 010 forming the aforementioned structure, and a pixel definition layer (PDL) is formed by removing a portion of the pixel definition film through a masking, exposure, and development process.

[0128] The pixel definition layer 30 includes a plurality of pixel definition layer openings 301 corresponding to the locations where the pixel definition films are removed, and pixel definition portions 302 located between the pixel definition layer openings 301; the pixel definition layer openings 301 expose at least a portion of the surface of the anode 213 of each sub-pixel P. Therefore, the subsequently formed light-emitting layer 216 can only contact the anode 213 of the corresponding sub-pixel P at the pixel definition layer openings 301, thus the pixel definition layer openings 301 define the position of the sub-pixel P, while the pixel definition portions 302 are the intervals between the sub-pixels P.

[0129] In some examples, the pixel definition layer 30 may be made of materials such as polyimide, acrylic, or polyethylene terephthalate.

[0130] As one embodiment of this disclosure, spacers 34 (PS, Post Spacer, or Pixel Subport) may also be formed while forming the pixel definition layer 30.

[0131] The spacer 34 is located at the pixel definition section 302, that is, at the interval between sub-pixels P. It "protrudes" relative to the pixel definition section 302, so as to support the fine metal mask (FMM) in the subsequent vapor deposition process.

[0132] In the masking and exposure process of the pixel definition film, a "halftone mask" or a "grayscale mask" can be used to expose different positions of the pixel definition film to different degrees. After the development process, the pixel definition film at some positions (corresponding to the pixel definition layer opening 301) is removed, a thinner pixel definition film is retained at some positions (corresponding to the individual pixel definition part 302), and a thicker pixel definition film is retained at some positions (corresponding to the pixel definition part 302 with spacer 34). In other words, spacer 34 is obtained as an "integral structure" with pixel definition part 302, and the material of spacer 34 is the same as that of pixel definition layer 30.

[0133] The spacers 34 may be distributed only in the gaps between some sub-pixels P, for example, refer to Figure 1 The three sub-pixels P in the image have only one spacer 34.

[0134] Of course, it should be understood that it is also feasible to form spacers 34, which are independent of the pixel definition layer 30, through a separate process.

[0135] Among them, reference Figure 7 Due to limitations in the manufacturing process, the edges of various physical structures (such as spacers 34 and pixel definition parts 302) that are actually formed are usually structures that gradually thicken from their boundaries inward, or have a "slope angle".

[0136] Therefore, in this embodiment, the boundary of various physical structures refers to the maximum position occupied by the structure, including the "slope angle" portion, or in other words, the boundary of the orthographic projection of the structure "as a whole" onto the substrate 010. For example, the area of ​​the pixel definition portion 302 is... Figure 7 The area that won the bid is d1, and the area of ​​spacer 34 is... Figure 7 The region between the two regions marked d2.

[0137] Correspondingly, the boundaries of non-physical regions are defined by the boundaries of the corresponding physical structures. For example, the region of pixel definition layer opening 301 (i.e., sub-pixel P) is the region of pixel definition part 302. Figure 7 The area outside of the area marked d1.

[0138] When the spacer 34 and the pixel defining part 302 are integrally formed, they are made of the same material and there is no obvious dividing interface between them. Since the upper side of the pixel defining part 302 has a basically flat surface, and the spacer 34 is disposed on this basically flat surface, it can be referred to... Figure 7The portion of the spacer 34 where the angle between the surface and the flat surface begins to exceed a threshold (e.g., the threshold could be 20 degrees, 25 degrees, 30 degrees, etc.) is used as the boundary (i.e., the "slope angle" portion).

[0139] S006. On the substrate 010 on which the aforementioned structure is formed, the light-emitting layer of the organic electroluminescent device and the second electrode are sequentially formed.

[0140] In some examples, the first electrode is a cathode 218, and more specifically, a transparent cathode.

[0141] Organic electroluminescent devices can emit light from the side away from the substrate 010 via a transparent cathode, achieving top emission. Therefore, the cathode 218 can be made of a transparent material such as indium tin oxide (ITO).

[0142] In some examples, the light-emitting layer of the organic electroluminescent device comprises multiple stacked sublayers, such as the following layers in sequence, in a direction gradually moving away from the substrate 010: hole injection layer (HIL) 214, hole transport layer (HTL) 215, organic light-emitting layer (EML) 216, and electron transport layer (ETL) 217.

[0143] Among them, the hole injection layer 214, hole transport layer 215, electron transport layer 217, and cathode 218 of the organic electroluminescent device of each sub-pixel P can be an integral structure, so they can be formed by sequential evaporation on the substrate 010 that forms the aforementioned structure using an open mask.

[0144] Among them, reference Figure 1 The organic light-emitting layer 216 corresponding to different sub-pixels P can be made of different materials, so the organic light-emitting layer 216 of different sub-pixels P (such as the first sub-pixel P01, the second sub-pixel P02, and the third sub-pixel P03) can be prepared sequentially on the substrate 010 forming the aforementioned structure using a patterning process.

[0145] Among them, reference Figure 1 The organic light-emitting layer 216 corresponding to each sub-pixel P can extend beyond the range of the sub-pixel P (organic electroluminescent device) itself. Thus, a sub-pixel P (or multiple adjacent sub-pixels P of the same color) can correspond to a larger organic light-emitting layer 216, and the area where the organic light-emitting layer 216 is located is called the "light-emitting area P99" of the sub-pixel P.

[0146] For example, refer to Figure 5The actual areas of the first sub-pixel P01, the second sub-pixel P02, and the third sub-pixel P03 can be relatively small, and the areas of the light-emitting regions P99 corresponding to the sub-pixels P01, P02, and P03 are larger than the actual areas of the sub-pixels P01, P02, and P03. For example, the ratio of the actual area of the sub-pixel P to the area of the light-emitting region P99 corresponding to the sub-pixel P can be 1: (1.01-10.5), and further can be 1: (1.1-1.3).

[0147] The shape and size of the light-emitting region P99 correspond to the opening on the high-precision metal mask used to form the organic light-emitting layer.

[0148] From the process point of view, the opening positions on the high-precision metal mask used to form the organic light-emitting layer can be connected or overlapped, that is, although the different sub-pixels P are arranged at intervals, the light-emitting regions P99 of the different sub-pixels P can be connected or overlapped. Figure 5

[0149] In some examples, the cathode 218 can be a semi-reflective semi-transmissive cathode, so that a "resonant microcavity" can be formed between the semi-reflective semi-transmissive cathode and the reflective anode to enhance the purity and brightness of light emission.

[0150] Therefore, the light-emitting layer can further include a microcavity adjusting layer between the hole transport layer 215 and the organic light-emitting layer 216 to adjust the thickness of the "resonant microcavity" between the different sub-pixels P.

[0151] In some example embodiments, the cathode 218 can be a combination (alloy) of any one or more of magnesium (Mg), silver (Ag), and aluminum (Al), or the cathode 218 can be a transparent conductive material, for example, indium tin oxide (ITO), or the cathode 218 can be a multi-layer composite structure of a metal and a transparent conductive material.

[0152] In some examples, a light coupling layer can be further formed on the side of the cathode 244 away from the substrate 010, and the light coupling layer can be a common layer for the plurality of sub-pixels P. The light coupling layer can cooperate with the transparent cathode to increase light output. For example, the material of the light coupling layer can be a semiconductor material.

[0153] S007, a packaging layer is formed on the substrate 010 having the foregoing structure.

[0154] As one of the embodiments of the present disclosure, a packaging layer can be further formed on the substrate 010 having the foregoing structure, so as to enclose the various structures thereunder and avoid the corrosion of the structures (especially the light-emitting layer) by water vapor and oxygen in the environment.

[0155] ​In some examples, the encapsulation layer can include a first encapsulation layer 41, a second encapsulation layer 42 and a third encapsulation layer 43 which are sequentially stacked, the first encapsulation layer 41 can adopt an inorganic material, the second encapsulation layer 42 adopts an organic material, and the third encapsulation layer 43 adopts an inorganic material, that is, the encapsulation layer can adopt a three-layer stacked structure of inorganic layer / organic layer / inorganic layer. Of course, the specific form of the encapsulation layer is not limited thereto, for example, in other examples, the encapsulation layer can also adopt a five-layer stacked structure of inorganic layer / organic layer / inorganic layer / organic layer / inorganic layer.

[0156] In some related technologies, with reference to Figure 1 After the formation of the spacers 34, when the subsequent structures are continuously formed by the evaporation process, the high-precision metal mask FMM needs to be in contact with the spacers 34 to be supported by the spacers 34.

[0157] Due to the double effects of gravity and adsorption magnetic force (Gauss force) for the high-precision metal mask FMM, the substrate substrate 010 will be deformed and stressed, and the transmission of stress will cause a slight friction between the spacers 34 and the high-precision metal mask FMM, thereby causing the material (such as the material of the hole injection layer 214) on the spacers 34 in contact with the high-precision metal mask FMM to fall off and generate particles PT.

[0158] And with reference to Figure 2 When the high-precision metal mask FMM is separated from the display substrate, the above particles PT can be adhered to the high-precision metal mask FMM, or fall into the area where the sub-pixel P of the display substrate is located, thereby causing dark spots, dead spots and other defects, reducing the display effect, and causing reliability and yield problems.

[0159] In a first aspect, with reference to Figures 1 to 17 The display substrate provided by the embodiments of the present disclosure.

[0160] The display substrate provided by the embodiments of the present disclosure can be an array substrate, and further can be an array substrate for organic electroluminescence (OLED, Organic Light Emitting Diode) display.

[0161] The display substrate provided by the embodiments of the present disclosure includes a substrate substrate 010, and a plurality of sub-pixels P arranged in an array on the substrate substrate 010; wherein

[0162] The adjacent sub-pixels P have a spacing area therebetween; the spacing area includes a first spacing area 91 having a functional site, and a second spacing area 92 without a functional site;

[0163] A functional member is arranged at at least part of the functional site;

[0164] The width of the first interval region 91 is greater than the width of the second interval region 92; wherein the width of an interval region is equal to the shortest distance between the boundaries of the two sub-pixels P corresponding to the interval region.

[0165] Wherein each interval region (such as the first interval region 91 and the second interval region 92) is located between two sub-pixels P, and thus the width of an interval region is the distance between the two sub-pixels P on its two sides (i.e. the interval between the two sub-pixels P in the arrangement direction), for example, the distance between the closest boundaries of the two sub-pixels P on the line connecting the geometric centers of the two sub-pixels P, and thus the extension direction of the above line (or the arrangement direction of the two sub-pixels P) is the width direction of the interval region.

[0166] Further, the two sub-pixels P on the two sides of each interval region must be arranged in a certain direction (such as the row direction or the column direction), and thus the comparison of the widths of different interval regions (the first interval region 91 and the second interval region 92) should be the comparison of the widths of interval regions located between sub-pixels P arranged in the same direction (or substantially the same direction), or in other words, the widths of two interval regions can be compared only when the width directions of the two interval regions are the same (or substantially the same) (i.e. when the two interval regions are located between sub-pixels P arranged in the same direction).

[0167] Wherein the "functional position" refers to a position in the interval region between sub-pixels P, which can be used to set a functional structure. And the "functional structure" refers to a structure set in the above interval region, which is used to realize a certain function.

[0168] For example, the above functional structure can be a sensor such as an infrared sensor, a fingerprint sensor, etc.; or the functional structure can be an auxiliary conductive column used to connect with the cathode to play an auxiliary conductive role; or the functional structure can be a blocking structure used to realize an optical or electrical blocking role, for example, a blocking structure used to separate certain film layers such as a common layer (an electron transport layer, a hole transport layer, a cathode, etc.) to reduce cross talk; or the functional structure can be a lens structure, a reflective structure, etc. used to enhance the light extraction efficiency.

[0169] In some embodiments, although the projection of the functional position on the substrate is located between two sub-pixels P (such as a pixel defining layer opening), the functional structure does not necessarily lie in the same layer as at least some film layers of the sub-pixel P, for example, it can be located above the pixel defining layer; or the functional structure can be located in the same layer as the pixel defining layer (for example, the pixel defining layer has a functional opening in addition to the sub-pixel opening used for display, and the functional structure is located in the functional opening of the pixel defining layer); or the functional structure can also be located on the side of the pixel defining layer close to the substrate (for example, it is located in the anode interval of the sub-pixel, or in the flat layer opening on the side of the anode close to the substrate, etc.).

[0170] In some embodiments, the function bit is a spacer bit 911 for setting a spacer, and the function piece is the spacer 34 (PS).

[0171] As one of the embodiments of the present disclosure, the function piece is the spacer 34 which plays a supporting role, and the corresponding function bit is the spacer bit 911 for setting the above spacer. Of course, even for the spacer bit 911 for setting the spacer 34, other function pieces (such as the above sensors, auxiliary conductive columns, partition structures, lens structures, etc.) can also be set.

[0172] In the following part of the embodiments of the present disclosure, the spacer bit 911 is taken as an example of the function bit, and the spacer 34 is taken as an example of the function piece. It should be understood that the spacer bit 911 in the following description can be replaced by a function bit, and the spacer 34 can be replaced by a function piece, but the function bit and the function piece are not limited to the above spacer bit 911 and the spacer 34.

[0173] In the embodiments of the present disclosure, with reference to Figure 6 , the interval between the sub-pixels P is divided into two categories, one of which has a larger width (the interval is relatively increased compared to the related art), which is the first interval region 91, and the other of which has a smaller width (the interval is not changed compared to the related art), which is the second interval region 92, and the spacer 34 (PS) is only set in the spacer bit 911 (but not all spacer bits 911 must be provided with the spacer 34).

[0174] That is, in the embodiments of the present disclosure, the spacer 34 is only set in the first interval region 91 with a larger width, and it is impossible to set the spacer in the second interval region 92.

[0175] Therefore, in the display substrate of the embodiments of the present disclosure, the interval between part of the sub-pixels P (the first interval region 91) is “enlarged”, and the spacer 34 is set in the “enlarged” interval, thereby increasing the distance between the spacer 34 and the sub-pixel P, reducing the generation of particles PT in the evaporation process, and further reducing the dark spots, dead spots and other defects caused by the particles PT, improving the product yield and reliability, increasing the passing rate of the display substrate product in the 8585 test (test under 85°C and 85% relative humidity) for 500h (hours), 1000h, and improving the display quality.

[0176] Meanwhile, in the display substrate of this embodiment, only the first spacing region 91 where the spacer 34 may be provided is "enlarged", while the size of the second spacing region 92 between other sub-pixels P remains unchanged. Thus, the overall distribution of the sub-pixels P remains unchanged, that is, the resolution (PI, Pixels Per Inch) of the display substrate does not change (although the aperture ratio may be reduced to some extent), and it will not have a significant impact on the display effect, but can meet the requirements of high resolution.

[0177] In some embodiments, the width of the first interval region 91 is greater than or equal to 20 μm.

[0178] In some embodiments, the distance between the boundary of the spacer 34 (spacer position 911) and the boundary of the nearest sub-pixel P is greater than or equal to 3 μm.

[0179] In some embodiments, the width of the second spacing region 92 is less than or equal to 19 μm.

[0180] The applicant's creative discovery, based on research, and with reference to Figure 6 , Figure 7 When the width of the first spacing region 91 with spacer 34 (that is, the overall width of the pixel definition section 302) d1 is greater than or equal to 20 μm, and the distance between the spacer 34 and the boundary of the nearest sub-pixel P (that is, the distance between the boundary of the spacer 34 and the boundary of the pixel definition section 302) d2 is greater than or equal to 3 μm, it can effectively avoid the generation of particles PT.

[0181] Wherein, if a pixel definition part 302 is provided in the interval region, then the location of the pixel definition part 302 is the interval region. However, due to process limitations, refer to Figure 7 The edge portion of the pixel definition section 302 is usually a structure that gradually thickens from its boundary inward, or has a "slope angle". Therefore, the cross-section of the pixel definition section 302 is approximately trapezoidal. Thus, the interval area should correspond to the area where the pixel definition section 302 is located, that is, the size of the "widest" part of the trapezoidal base of the pixel definition section 302. For example, the interval area usually covers the edge of the anode 213.

[0182] In this context, a spacer 34 (that is, it may be adjacent to multiple sub-pixels P, and at this time, there will also be multiple distances between the spacer 34 and the multiple adjacent sub-pixels P. These distances can be all the same, all different (i.e. any two distances are different), or partially the same and partially different.

[0183] Conversely, the width of the second spacing region 92 without spacers (or the width of the spacing between sub-pixels P in the related art) can be less than or equal to 19 μm.

[0184] The width dl of the first spacing region 91 with the spacers 34 can be further greater than or equal to 21 pm, greater than or equal to 22 pm, greater than or equal to 24 pm, greater than or equal to 26 pm, greater than or equal to 28 pm, greater than or equal to 30 pm, etc.

[0185] The distance d2 between the spacer 911 and the boundary of the closest sub-pixel P can be further greater than or equal to 4 pm, greater than or equal to 5 pm, greater than or equal to 6 pm, greater than or equal to 7 pm, greater than or equal to 8 pm, etc.

[0186] The width dl of the second spacing region 92 without the spacers can be further less than or equal to 18 pm, less than or equal to 16 pm, etc.

[0187] For example, as shown in Table 1 below, when the size of the spacers 34 and the size of the spacing between two sub-pixels P are different, the corresponding spacer profile determination is also different. The size of the embodiment of the present disclosure that meets the above requirements can ensure that the spacer profile determination is qualified.

[0188] Table 1. Spacer profile under different sizes

[0189]

[0190]

[0191] In some embodiments, the shortest line between the boundaries of the two sub-pixels P corresponding to the first spacing region 91 passes through the spacers 34 in the first spacing region 91.

[0192] In some embodiments, in the cross section passing through the shortest line and perpendicular to the substrate 010, the distance between the boundaries of the two sub-pixels P corresponding to the first spacing region 91 is greater than or equal to 20 pm, and the distance between the spacer 911 in the first spacing region 91 and the sub-pixel P is greater than or equal to 3 pm.

[0193] As an embodiment of the present disclosure, referring to Figure 6 , at least part of the spacers 911 can pass through the shortest position between the adjacent sub-pixels P, so that if the spacers 34 are provided on these spacers 911, the shortest line between the boundaries of the two sub-pixels P corresponding to the spacers 34 on the spacers 911 also passes through the spacers 34 on the spacers 911, and referring to Figure 7 , at this time, in the cross section at the shortest position, the size of the spacer 911 and the spacing also meets the above requirements.

[0194] In some embodiments, a line between geometric centers of two sub-pixels P corresponding to at least part of the first spacing region 91 passes through the spacer 34 in the first spacing region 91.

[0195] In some embodiments, a line between geometric centers of two sub-pixels P corresponding to at least part of the first spacing region 91 passes through a geometric center of the spacer 34 in the first spacing region 91.

[0196] As another way of implementing the embodiments of the present disclosure, referring to Figure 6 , at least part of the spacer site 911 (and the spacer 34 thereon) can also pass through a line between geometric centers of adjacent sub-pixels P, and further, a geometric center of the spacer site 911 (and the spacer 34 thereon) can be located on the line between the geometric centers of the adjacent sub-pixels P.

[0197] Wherein, the pattern of the spacer 34 in the cross section passing through any of the lines and perpendicular to the substrate 010 can also be left-right symmetrical, for example, a trapezoid as shown in Figure 7 .

[0198] In some embodiments, at least part of the first spacing region 91 extends in a third direction; at least part of the first spacing region 91 extends in a fourth direction; the fourth direction intersects the third direction; at least part of the first spacing region 91 extending in the third direction and the first spacing region 91 extending in the fourth direction have an overlapping region, and at least part of the spacer 34 at least partially overlaps the overlapping region.

[0199] Referring to Figure 6 , a spacing region can be provided between any adjacent sub-pixels P, and the sub-pixels P can be adjacent in different directions, so that the sub-pixels P adjacent in different directions will have spacing regions extending in different directions, for example, Figure 6 , a “laterally extending” spacing region is provided between “laterally adjacent” sub-pixels P, and a “vertically extending” spacing region is provided between “vertically adjacent” sub-pixels P. Moreover, the above different spacing regions can also have overlapping regions.

[0200] Therefore, if two first spacing regions 91 extending in different directions have an overlapping region, then the spacer 34 (spacer site 911) can be at least partially located in the overlapping region, or completely located in the above overlapping region. That is, referring to Figure 6 , the above spacer 34 (spacer site 911) is located between multiple “pairs” of different adjacent sub-pixels P, so it can also “belong to” multiple first spacing regions 91.

[0201] It should be understood that when the spacer 34 (the spacer position 911) is located in a plurality of intervals at the same time, any one of the interval should be the first interval 91 above, and should meet the width requirement above.

[0202] Among them, the third direction and the fourth direction only represent two different directions, and do not necessarily mean that they are perpendicular.

[0203] Among them, the extension direction of the interval can also be the direction of its width, such as the extension direction of the connecting line of the geometric centers of the two sub-pixels P on its two sides.

[0204] Among them, the specific shape of the interval is various, which is determined according to the shape of the area between the two sub-pixels P, for example, the interval can be bar-shaped (or rectangular), or circular, elliptical, etc.; for example, the interval can be a relatively regular symmetrical shape with a symmetrical axis, or other irregular shapes, etc.

[0205] It should be understood that no matter the specific shape of the interval, as long as its size in the width direction meets the above requirements, it belongs to the first interval 91 above, that is, the spacer 34 (the spacer position 911) can be provided.

[0206] In some embodiments, the distance between adjacent spacers 34 is between 100 μm and 300 μm.

[0207] As before, the spacer position 911 is a position where the spacer 34 can be provided, but it does not mean that each spacer position 911 actually has a spacer 34 provided, but as long as the setting density of the spacer 34 meets the requirement of supporting the high-fineness metal mask FMM. The distance between the spacers 34 that meet the above support requirements can be between 100 μm and 300 μm, and further can be between 120 μm and 280 μm, or between 150 μm and 250 μm.

[0208] In some embodiments, the number of spacer positions 911 provided with the spacer 34 accounts for at least 15% of the total number of spacers 34.

[0209] In the embodiments of the present disclosure, at least 15% of the spacer positions 911 can be provided with the spacer 34. Of course, the proportion of the spacer positions 911 provided with the spacer 34 is at least 25%, 50%, 75%, etc., or all the spacer positions 911 are provided with the spacer 34, which is also feasible.

[0210] Therefore, if the interval between adjacent first intervals 91 is smaller than the above range, it can be referred to Figure 6 , and only one of the spacer positions 911 of the plurality of first intervals 91 actually has a spacer 34 provided.

[0211] In some embodiments, the display substrate further comprises a pixel definition layer 30;

[0212] The pixel definition layer 30 comprises pixel definition layer openings 301 and pixel definition portions 302 between the pixel definition layer openings 301;

[0213] The pixel definition layer openings 301 define the light emitting areas of the sub-pixels P;

[0214] The spacers 34 are disposed on the side of the pixel definition portions 302 away from the substrate 010.

[0215] In some embodiments, the spacers 34 and the pixel definition portions 302 are in an integral structure.

[0216] As one of the embodiments of the present disclosure, the area where the sub-pixels P can actually emit light (i.e., the sub-pixels P) can correspond to the pixel definition layer openings 301 of the pixel definition layer (PDL) 30, so the intervals between the sub-pixels P correspond to the pixel definition portions 302 of the pixel definition layer 30, and the spacers 34 are disposed above the pixel definition portions 302.

[0217] As one of the embodiments of the present disclosure, the spacers 34 can be in an integral structure with the pixel definition portions 302, i.e., formed by a material layer in one patterning process.

[0218] Of course, if the spacers 34 are independent structures formed on the pixel definition portions 302 by a separate patterning process using a separate material layer, it is also feasible.

[0219] Of course, if the functional member is not the spacer 34 but other structures, it can be formed by a separate patterning process, or can be disposed in the same layer as other structures (e.g., formed in one patterning process), and the functional member and the other structures disposed in the same layer can be connected to form an integral structure, or can be independent of each other.

[0220] The following exemplary introduces some specific sub-pixel P arrangement modes adopted by the display substrate, and the corresponding setting modes of the first interval region 91 (and the spacers 911 therein) and the second interval region 92.

[0221] In some embodiments, among the plurality of sub-pixels P adjacent to at least part of the spacers 34, the geometric center of at least one sub-pixel P deviates from a straight line extending in the first direction, and the geometric centers of at least two sub-pixels P in the same row as the sub-pixel P in the first direction are located on the straight line;

[0222] and / or,

[0223] Of the plurality of sub-pixels P adjacent to at least a portion of the spacer 34, at least one sub-pixel P has its geometric center deviated from a straight line extending along the second direction, and the geometric centers of at least two sub-pixels P located in the same row as the sub-pixel P in the second direction are located on the straight line; the second direction intersects the first direction.

[0224] In the following description, the first direction is the row direction and the second direction is the column direction, as an example. However, it should be understood that the above directions are not a limitation on the scope of protection of this disclosure.

[0225] In other words, each sub-pixel P1 can be arranged in multiple rows and columns according to the row direction (first direction) and column direction (second direction). Among the multiple sub-pixels P1 in the same row, those sub-pixels P1 adjacent to the spacer 34 (spacer position 911) can be other sub-pixels P1 "offset" from that row (in terms of the position of the geometric center), for example, offset from the direction away from the adjacent spacer 34; and among the multiple sub-pixels P1 in the same column, the sub-pixels P1 adjacent to the spacer 34 (spacer position 911) can also be other sub-pixels P1 "offset" from that column (in terms of the position of the geometric center), for example, offset from the direction away from the adjacent spacer 34.

[0226] Therefore, sufficient space can be provided for the interval area with spacer 34 (spacer position 911) so that it can meet the width requirements of the first interval area 91.

[0227] In some embodiments, the first sub-pixel P01 is a red sub-pixel, the second sub-pixel P02 is a green sub-pixel, and the third sub-pixel P03 is a blue sub-pixel.

[0228] As one embodiment of this disclosure, taking into account the luminous efficiency of organic light-emitting diodes (OLEDs) of different colors and the sensitivity of the human eye to different colors of light, the colors of different sub-pixels P can be as described above. However, it should be understood that the above color correspondence of sub-pixels P is not a limitation on the scope of protection of this disclosure.

[0229] For example, you can refer to Figure 8The sub-pixels P are arranged in an array, which includes multiple rows of first pixel rows and multiple rows of second pixel rows, with the first and second pixel rows alternating. The first pixel rows are formed by alternating red and blue sub-pixels, and red and blue sub-pixels in the same column within the multiple rows of first pixel rows are also alternating. The second pixel rows are formed by multiple green sub-pixels arranged side-by-side, with the green sub-pixels interleaved with the red and blue sub-pixels in adjacent rows. For this pixel arrangement, the pixel array can be divided into repeating units arranged in an array. Each repeating unit includes two rows and four columns of sub-pixels, that is, each repeating unit includes one red sub-pixel, one blue sub-pixel, and two green sub-pixels. The red and blue sub-pixels are shared sub-pixels. Through a virtual algorithm, four sub-pixels can achieve the display of two virtual pixel units. For example, the red sub-pixel in the second repeating unit of the first row, together with the blue sub-pixel in the first repeating unit of the first row and its nearest green sub-pixel, forms a virtual pixel unit. At the same time, the red sub-pixel in the second repeating unit of the first row, together with the blue sub-pixel in the same repeating unit and its nearest green sub-pixel, forms another virtual pixel unit. In addition, the blue sub-pixel in the second repeating unit of the first row, together with another green sub-pixel in the same repeating unit and its nearest red sub-pixel in the third repeating unit of the first row, forms another virtual pixel unit. This can effectively improve the resolution of the display panel using this pixel array.

[0230] In some embodiments, the sub-pixel P includes a first sub-pixel P01, a second sub-pixel P02, and a third sub-pixel P03;

[0231] The first sub-pixel P01 and the third sub-pixel P03 are alternately arranged along a first direction to form a first pixel group A01, and alternately arranged along a second direction to form a third pixel group A03; the second direction intersects with the first direction;

[0232] The second sub-pixel P02 is arranged along the first direction to form the second pixel group A02, and arranged along the second direction to form the fourth pixel group A04;

[0233] The first pixel group A01 and the second pixel group A02 are arranged alternately along the second direction; the third pixel group A03 and the fourth pixel group A04 are arranged alternately along the first direction.

[0234] Reference Figure 8 , Figure 9As one embodiment of this disclosure, in the display substrate, the first sub-pixel P01 and the third sub-pixel P03 can be alternately arranged into multiple rows of first pixel groups A01, and the second sub-pixel P02 can be arranged into multiple rows of second pixel groups A02. In the column direction, the first pixel groups A01 and the second pixel groups A02 are alternately arranged. At the same time, the first sub-pixel P01 and the third sub-pixel P03 can be alternately arranged into multiple columns of third pixel groups A03, and the second sub-pixel P02 can be arranged into multiple columns of fourth pixel groups A04. In the row direction, the third pixel groups A03 and the fourth pixel groups A04 are alternately arranged.

[0235] In some embodiments, in the interval region between the first sub-pixel P01 and the third sub-pixel P03 adjacent to each other in the third pixel group A03, at least a portion of the interval region is the first interval region 91;

[0236] The interval between the first sub-pixel P01 and the third sub-pixel P03, which are adjacent in the first pixel group A01, is the second interval 92.

[0237] As one embodiment of this disclosure, refer to Figure 8 , Figure 9 The gap between adjacent first sub-pixel P01 and third sub-pixel P03 in the row direction is a second gap 92 without spacers; while the gap between adjacent first sub-pixel P01 and third sub-pixel P03 in the column direction is at least partly a first gap 91 with spacers 911 (spacers 34).

[0238] Specifically, the widths of multiple second interval regions 92 located in the same row (that is, multiple second interval regions 92 located between two adjacent row sub-pixels P) should be the same or substantially equivalent. For example, if the width of the second interval region 92 with the smallest width among the multiple second interval regions 92 in the same row is 0.8, then the relative width of the second interval region 92 with the largest width should not exceed 1.2.

[0239] In some embodiments, the spacing between adjacent first sub-pixels P01 and third sub-pixels P03 in the third pixel group A03 alternates between the first spacing region 91 and the second spacing region 92 along the second direction;

[0240] In two adjacent third pixel groups A03, a first spacing region 91 in one third pixel group A03 and a second spacing region 92 in the other third pixel group A03 are located between the same two rows of sub-pixels P arranged along the first direction.

[0241] As one embodiment of this disclosure, refer to Figure 8 ,Figure 9 In the interval between the first sub-pixel P01 and the third sub-pixel P03 in each column, the first interval 91 and the second interval 92 are alternately arranged; and in the multiple intervals located between two adjacent third pixel groups A03, the first interval 91 and the second interval 92 are also alternately arranged. For example, refer to Figure 8 , Figure 9 In the interval between the first sub-pixel P01 and the third sub-pixel P03 located in any column, the interval where the third sub-pixel P03 is above and the first sub-pixel P01 is below is the first interval 91. Correspondingly, the interval where the third sub-pixel P03 is below and the first sub-pixel P01 is above is the second interval 92. Therefore, in two adjacent third pixel groups A03, those located in the same row of the first interval 91 and the second interval 92 (and these two intervals are necessarily adjacent) are both located between two adjacent rows of sub-pixels P, for example, those located in... Figure 8 Between the two rows of sub-pixels P marked with H.

[0242] Therefore, the spacers 911 (spacers 34) are relatively evenly distributed in the display substrate, which is beneficial for the setting of spacers 911 (spacers 34).

[0243] The widths of multiple first interval regions 91 located in the same row (that is, multiple first interval regions 91 located between two adjacent rows of sub-pixels P) can be equal, and the widths of multiple second interval regions 92 located in the same row (that is, multiple second interval regions 92 located between two adjacent rows of sub-pixels P) can also be equal, thereby achieving a regular arrangement of sub-pixels P.

[0244] In some embodiments, the geometric centers of two first sub-pixels P01 and two third sub-pixels P03 arranged in an array are connected sequentially to form a virtual trapezoid.

[0245] The interval between the first sub-pixel P01 and the third sub-pixel P03 corresponding to the bottom edge of the virtual trapezoid is the first interval 91, and the interval between the first sub-pixel P01 and the third sub-pixel P03 corresponding to the top edge of the virtual trapezoid is the second interval 92.

[0246] As one embodiment of this disclosure, reference is made to... Figure 9 The virtual "quadrilateral" formed by connecting the geometric centers of four first sub-pixels P01 and third sub-pixels P03 is a "trapezoidal shape", and the spacer 911 (first interval 91) is located at the bottom edge (longer side) of the corresponding virtual trapezoid, while the top edge (shorter side) of the virtual trapezoid corresponds to the second interval 92.

[0247] Alternatively, for each column of first sub-pixel P01 and third sub-pixel P03, the distance between some of the first sub-pixel P01 and third sub-pixel P03 can be "enlarged" (the distance between other first sub-pixel P01 and third sub-pixel P03 is obviously reduced accordingly), and the spacer position 911 (first interval area 91) is set at the position where the interval is "enlarged", thereby increasing the distance between the spacer 34 and the sub-pixel P, reducing the generation of particles PT, and improving reliability and yield.

[0248] In some embodiments, the base of the virtual trapezoid is parallel to the second direction.

[0249] In some embodiments, the virtual trapezoid is a virtual isosceles trapezoid.

[0250] Furthermore, the base of the virtual trapezoid can be parallel to the column direction, and can further be a virtual isosceles trapezoid (i.e., the first sub-pixel P01 and the third sub-pixel P03 move equal distances).

[0251] In some embodiments, in the first interval region 91 located at least partially between the adjacent first sub-pixel P01 and the third sub-pixel P03, the geometric center of the spacer 34 is located on the line connecting the geometric center of the first sub-pixel P01 and the geometric center of the third sub-pixel P03 corresponding to the first interval region 91.

[0252] As one embodiment of this disclosure, reference is made to... Figure 9 The geometric center of at least part of the spacer 911 and the spacer 34 located thereon may be located on the line connecting the geometric centers of the corresponding first sub-pixel P01 and the third sub-pixel P03 (e.g., the bottom edge of the virtual trapezoid above).

[0253] In some embodiments, in the first interval region 91 located at least partially between adjacent first sub-pixels P01 and third sub-pixels P03, along the second direction, the distance between the geometric center of the spacer 34 and the geometric center of the first sub-pixel P01 corresponding to the first interval region 91 is less than the distance between the geometric center of the spacer 911 and the geometric center of the third sub-pixel P03 corresponding to the first interval region 91.

[0254] As one embodiment of this disclosure, reference is made to... Figure 9 For at least a portion of the spacers 911 in the first interval 91, the spacers 34 are not located "between" their corresponding first sub-pixel P01 and third sub-pixel P03 in the column direction, but are "closer" to their corresponding first sub-pixel P01 and "far away" from their corresponding third sub-pixel P03; or, the spacers 911 are located "lower".

[0255] In some embodiments, in the first interval region 91 located at least partially between adjacent first sub-pixels P01 and third sub-pixels P03, along the second direction, the geometric center of the spacer 34 is located on the side of its corresponding reference line 9111 close to the first sub-pixel P01 corresponding to the first interval region 91; wherein, the reference line 9111 of the spacer position 911 is a line connecting the geometric centers of two second sub-pixels P02 located on both sides of the spacer position 911 in the first direction.

[0256] As one embodiment of this disclosure, reference is made to... Figure 9 For the spacer 34 disposed on the spacer position 911 in at least the first interval region 91, in the column direction, it can be "closer" to its corresponding first sub-pixel P01 relative to the second sub-pixel P2 in the same row. For example, it can be the geometric center (reference line 9111) of the second sub-pixel P2 in the same row, located on the line connecting the midpoint of the fixed side and the midpoint of the bottom side of the corresponding virtual trapezoid. That is, the second sub-pixel P2 can be located in the middle of the first sub-pixel P01 and the third sub-pixel P03, while the second sub-pixel P2 is relatively closer to the first sub-pixel P01 (lower).

[0257] In some embodiments, the shape of the first sub-pixel P01 includes a square or a rounded square, wherein one diagonal of the square or rounded square is parallel to the first direction and the other diagonal is parallel to the second direction;

[0258] The shape of the third sub-pixel P03 includes a square or a rounded square, wherein one diagonal of the square or rounded square is parallel to the first direction and the other diagonal is parallel to the second direction.

[0259] As one embodiment of this disclosure, reference is made to... Figure 8 , Figure 9 The shapes of the first sub-pixel P01 and the third sub-pixel P03 can be squares or rounded squares (that is, the shape obtained by rounding each corner of a square), and the two diagonals of the square (or rounded square) are set along the row direction and the column direction, respectively.

[0260] Of course, the second sub-pixel P02 can also be a square or a rounded square, or a non-square rectangle or a rounded rectangle, or a shape obtained by "missing" a part of a rectangle or a rounded rectangle, which will not be described in detail here.

[0261] In some embodiments, at least a portion of the third sub-pixel P03 is divided into an asymmetrical first portion and a second portion along a straight line passing through its geometric center and parallel to the first direction, wherein the maximum size of the first portion is smaller than the maximum size of the second portion along the second direction; in the first interval region 91 located between the first sub-pixel P01 and the third sub-pixel P03 adjacent along the second direction, at least a portion of the first interval region 91 is the interval region between the first portion of the third sub-pixel P03 and the adjacent first sub-pixel P01.

[0262] As another form of the embodiment of this disclosure, it may also be referred to Figure 10 , Figure 11 At least part of the third sub-pixel P03 can be an "asymmetric" shape relative to an axis parallel to the first direction, with one side (the first part, such as...) having a more asymmetric shape. Figure 10 The lower side of the middle) is opposite the other side (the second part). Figure 10 The upper side of the third sub-pixel P03 is "missing" a portion, thus making its first portion "shorter" in the second direction. Therefore, the first interval 91 can be positioned between the side containing the "shorter" first portion of the third sub-pixel P03 and the first sub-pixel P01. In other words, the third sub-pixel P03 does not need to "move," but can meet the width requirement of the first interval 91 through a change in its shape (of course, it is also feasible if one side of the third sub-pixel P03 is also "missing" a portion while the third sub-pixel P03 is "moving").

[0263] Furthermore, refer to Figure 11 When the spacer 34 is provided only in some locations, the first part of each third sub-pixel P03 faces different directions to form the location where the spacer 34 is provided.

[0264] In some embodiments, the area of ​​the second sub-pixel P02 is smaller than the area of ​​the first sub-pixel P01;

[0265] The area of ​​the second sub-pixel P02 is smaller than the area of ​​the third sub-pixel P03.

[0266] As one embodiment of this disclosure, reference is made to... Figure 8 , Figure 9 The area of ​​the second sub-pixel P02 (e.g., the green sub-pixel) can be the smallest, for example, the area of ​​the third sub-pixel P03 (e.g., the blue sub-pixel) can be the largest, the area of ​​the second sub-pixel P02 (e.g., the green sub-pixel) can be the smallest, and the area of ​​the first sub-pixel P01 (e.g., the red sub-pixel) can be medium.

[0267] In some embodiments, the sub-pixel P includes a first sub-pixel P01, a second sub-pixel P02, and a third sub-pixel P03;

[0268] The first sub-pixel pair P91 and the third sub-pixel P03 are alternately arranged along the first direction to form the fifth pixel group A05; the first sub-pixel pair P91 includes a first sub-pixel P01 and a second sub-pixel P02 arranged along the second direction; the second direction intersects the first direction;

[0269] The first sub-pixel P01 and the second sub-pixel P02 are alternately arranged along the second direction to form the sixth pixel group A06;

[0270] The third sub-pixel P03 is arranged along the second direction to form the seventh pixel group A07;

[0271] The sixth pixel group A06 and the seventh pixel group A07 are arranged alternately along the first direction; and a plurality of fifth pixel groups A05 are arranged along the second direction.

[0272] As another embodiment of this disclosure, refer to Figure 12 , Figure 13 It can be that a first sub-pixel P01 and a second sub-pixel P02 adjacent in the column direction form a "first sub-pixel pair P91". The first sub-pixel pair P91 is arranged alternately with the third sub-pixel P03 to form multiple rows of fifth pixel groups A05. The first sub-pixel pair P91 is also arranged into multiple columns of sixth pixel groups A06, and the third sub-pixel P03 is arranged into multiple columns of seventh pixel groups A07. The seventh pixel group A07 and the sixth pixel group A06 are arranged alternately in the row direction.

[0273] In some embodiments, at least a portion of the interval between adjacent third sub-pixels P03 in the seventh pixel group A07 is the first interval 91;

[0274] The interval between the first sub-pixel P01 and the third sub-pixel P03 adjacent to each other in the fifth pixel group A05, and the interval between the second sub-pixel P02 and the third sub-pixel P03 adjacent to each other, is the second interval 92.

[0275] The interval between the first sub-pixel P01 and the second sub-pixel P02 adjacent to each other in the fifth pixel group A05 is the second interval 92.

[0276] As another embodiment of this disclosure, refer to Figure 12 , Figure 13The first interval 91 is located between adjacent third sub-pixels P03 in the column direction; while the interval between adjacent third sub-pixels P03 and first sub-pixels P01 in the row direction, the interval between adjacent third sub-pixels P03 and second sub-pixels P02 in the row direction, and the interval between adjacent first sub-pixels P01 and second sub-pixels P02 in the column direction are all the second interval 92.

[0277] That is, the spacing between at least some of the third sub-pixels P03 in the same column can be "enlarged" to increase the distance between the spacer 911 and the sub-pixel P (e.g., increasing the spacing between the spacer 911 and the sub-pixel P). Figure 13 The d3 in the sample increases from 5 μm to 10 μm.

[0278] In some embodiments, at least a portion of the spacing regions between adjacent third sub-pixels P03 in the seventh pixel group A07 alternately form the first spacing region 91 and the second spacing region 92 along the second direction.

[0279] Reference Figure 12 , Figure 13 In at least part of the seventh pixel group A07, the interval area can also be alternately divided into the first interval area 91 and the second interval area 92, so that the distribution of the spacer 911 is more uniform.

[0280] In some embodiments, the area of ​​the third sub-pixel P03 is larger than the area of ​​the first sub-pixel P01;

[0281] The area of ​​the third sub-pixel P03 is larger than the area of ​​the second sub-pixel P02.

[0282] As one embodiment of this disclosure, reference is made to... Figure 12 , Figure 13 The area of ​​the third sub-pixel P03 (e.g., the blue sub-pixel) can be the largest. For example, the area of ​​the third sub-pixel P03 (e.g., the blue sub-pixel) is the largest, the area of ​​the second sub-pixel P02 (e.g., the green sub-pixel) is medium, and the area of ​​the first sub-pixel P01 (e.g., the red sub-pixel) is the smallest.

[0283] The shapes of the first sub-pixel P01, the second sub-pixel P02, and the third sub-pixel P02 can also be varied, for example, see reference. Figure 12 , Figure 13 The shapes of the first sub-pixel P01, the second sub-pixel P02, and the third sub-pixel P02 are all rectangles or rounded rectangles, and the two sides of the rectangle (or rounded rectangle) are parallel to the row direction and the column direction, respectively.

[0284] In some embodiments, at least a portion of the third sub-pixel P03 is divided into an asymmetrical first part and a second part along a straight line passing through its geometric center and parallel to the first direction, and along the second direction, the maximum size of the first part is smaller than the maximum size of the second part.

[0285] In the first interval region 91 located between adjacent third sub-pixels P03 along the second direction, at least a portion of the first interval region 91 is an interval region between first portions of the third sub-pixels P03.

[0286] As another form of the embodiment of this disclosure, it may also be referred to Figure 14 At least part of the third sub-pixel P03 can be an "asymmetrical" shape relative to an axis parallel to the first direction, with one side "missing" a portion relative to the other side. Figure 14 The first portion of the third sub-pixel P03 is positioned below the upper third sub-pixel P03 and above the lower third sub-pixel P03, thus making its first portion "shorter" in the second direction. Therefore, the first spacing region 91 can be positioned between the two "shorter" first portions of the second third sub-pixel P03 to meet the width requirements of the first spacing region 91.

[0287] It should be understood that the above scheme, in which a portion is "missing" on one side of the third sub-pixel P03 and the first interval area 91 is set on the "missing" side of the third sub-pixel P03, is a setting of the specific shape of the sub-pixel P. Therefore, it is not necessary to have any relation to the position of each sub-pixel P itself or the position of each interval area. Thus, the above scheme is "compatible" with other various arrangements of sub-pixels P and interval areas.

[0288] It should be understood that, except for the third sub-pixel P03, which can be "missing" a portion, the positions of other sub-pixels P corresponding to the first interval 91 can also be "missing" a portion to meet the width requirements of the first interval 91.

[0289] In some embodiments, the sub-pixel P includes a first sub-pixel P01, a second sub-pixel P02, and a third sub-pixel P03;

[0290] The second sub-pixel pair P92, the first sub-pixel P01, and the third sub-pixel P03 are alternately arranged along the first direction to form the eighth pixel group A08; the second sub-pixel pair P92 includes two second sub-pixels P02 arranged along the second direction; the second direction intersects the first direction;

[0291] Multiple eighth pixel groups A08 are arranged along the second direction;

[0292] In two adjacent eighth pixel groups A08, a second sub-pixel pair P92 of one eighth pixel group A08 is located along the first direction between a first sub-pixel P01 and a third sub-pixel P03 of the other eighth pixel group A08.

[0293] As one embodiment of this disclosure, reference is made to... Figure 15 , Figure 16 , Figure 17 Alternatively, two adjacent second sub-pixels P02 in the column direction can form a second sub-pixel pair P92, and the second sub-pixel pair P92, the first sub-pixel P01, and the third sub-pixel P03 can be arranged alternately to form multiple rows of eighth pixel groups A08, and the eighth pixel groups A08 in adjacent rows are staggered by "one and a half columns".

[0294] In some embodiments, at least a portion of the interval regions located between two adjacent eighth pixel groups A08 and between adjacent first sub-pixel P01 and third sub-pixel P03 are the first interval regions 91.

[0295] As one embodiment of this disclosure, reference is made to... Figure 16 This can be achieved by "bringing" the distance between two second sub-pixels P02 in the second sub-pixel pair P92, thereby increasing the distance between the diagonally adjacent second sub-pixels P02 and third sub-pixels P03 in the adjacent eighth pixel group A08 (adjacent row). Therefore, a spacer 911 (first spacer area 91) can be located between these two sub-pixels P02 and P03. Of course, this spacer 911 is also located between two diagonally adjacent first sub-pixels P01 in the adjacent eighth pixel group A08.

[0296] In some embodiments, at least a portion of the interval regions located between two adjacent eighth pixel groups A08 and between adjacent first sub-pixels P01 and second sub-pixels P02 are the first interval regions 91.

[0297] As another embodiment of this disclosure, refer to Figure 17 Alternatively, the first sub-pixel P01 and the third sub-pixel P03 can be "compressed" along the column direction, thereby increasing the distance between the diagonally adjacent first sub-pixel P01 and third sub-pixel P03 in the adjacent eighth pixel group A08 (adjacent row). Thus, a spacer 911 (first spacer area 91) can be provided between the first sub-pixel P01 and the third sub-pixel P03. Of course, this spacer 911 is also located between two diagonally adjacent second sub-pixels P02 in the adjacent eighth pixel group A08.

[0298] In this way, the first sub-pixel P01, located in the adjacent eighth pixel group A08, is positioned closer to the "same row" on both the upper and lower sides, thus achieving a better display effect.

[0299] In some embodiments, the two second sub-pixels P02 in the second sub-pixel pair P92 are symmetrically distributed relative to a line parallel to the first direction.

[0300] Reference Figure 15 , Figure 16 , Figure 17 In each second sub-pixel pair P92, the two second sub-pixels P02 can be symmetrical vertically to improve the uniformity of the distribution of the second sub-pixel pair P92.

[0301] The shapes of the first sub-pixel P01, the second sub-pixel P02, and the third sub-pixel P02 can also be diverse. For example, refer to... Figure 15 , Figure 16 , Figure 17 The first sub-pixel P01 and the third sub-pixel P02 can both be hexagons, and each hexagon can be divided into two symmetrical parts; while each second sub-pixel P02 can be a pentagon, that is, each second sub-pixel is a hexagon after splicing two second sub-pixels P02 in P92.

[0302] In some embodiments, the area of ​​the second sub-pixel P02 is smaller than the area of ​​the first sub-pixel P01;

[0303] The area of ​​the second sub-pixel P02 is smaller than the area of ​​the third sub-pixel P03.

[0304] As one embodiment of this disclosure, reference is made to... Figure 18 , ​ , ​ The area of ​​the second sub-pixel P02 (e.g., the green sub-pixel) can be the smallest, for example, the area of ​​the third sub-pixel P03 (e.g., the blue sub-pixel) can be the largest, the area of ​​the second sub-pixel P02 (e.g., the green sub-pixel) can be the smallest, and the area of ​​the first sub-pixel P01 (e.g., the red sub-pixel) can be medium.

[0305] In some embodiments, the resolution of the display substrate is less than or equal to 1000 PPI.

[0306] The display substrate of this disclosure is suitable for applications with lower resolutions, such as resolutions not exceeding 1000 PPI (pixels per inch), further not exceeding 800 PPI, and further not exceeding 600 PPI. When the resolution of the display substrate is too high, the theoretically possible spacing between its sub-pixels P is too small, making it difficult to achieve the above spacing conditions.

[0307] Secondly, referring to ​ This disclosure also provides a display device comprising any of the above-described display substrates.

[0308] The above display substrate can be assembled with other structures (such as cell substrate, driving device, power supply component, housing, etc.) to form an independent product with display function, namely a display device.

[0309] Specifically, the display device can be any product or component with display function, such as an organic light-emitting diode (OLED) display panel, electronic paper, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, etc.

[0310] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A display substrate, comprising a substrate substrate, and a plurality of sub-pixels arranged in an array on the substrate substrate; characterized in that, The sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel; The adjacent sub-pixels have a spacing region therebetween; the spacing region includes a first spacing region having a functional site and a second spacing region without a functional site; A functional element is disposed at least partially on the functional site; The width of the first spacing region between two adjacent sub-pixels arranged in the same direction is greater than the width of the second spacing region between two adjacent sub-pixels arranged in the same direction; the width of the spacing region is equal to the shortest distance between the boundaries of the two sub-pixels corresponding to the spacing region; The first sub-pixels and the third sub-pixels are alternately arranged in a first direction to form a first pixel group and are alternately arranged in a second direction to form a third pixel group; the second direction intersects the first direction; The second sub-pixels are arranged in the first direction to form a second pixel group and are arranged in the second direction to form a fourth pixel group; The first pixel group and the second pixel group are alternately arranged in the second direction; the third pixel group and the fourth pixel group are alternately arranged in the first direction; At least part of the third sub-pixel is divided into an asymmetric first part and a second part along a straight line passing through the geometric center of the third sub-pixel and parallel to the first direction; in the second direction, the maximum size of the first part is smaller than that of the second part; In the first spacing region between the first sub-pixel and the third sub-pixel adjacent in the second direction, at least part of the first spacing region is the spacing region between the first part of the third sub-pixel and the adjacent first sub-pixel; Or A first sub-pixel pair and the third sub-pixel are alternately arranged in the first direction to form a fifth pixel group; the first sub-pixel pair includes one first sub-pixel and one second sub-pixel arranged in the second direction; the second direction intersects the first direction; The first sub-pixel and the second sub-pixel are alternately arranged in the second direction to form a sixth pixel group; The third sub-pixel is arranged in the second direction to form a seventh pixel group; The sixth pixel group and the seventh pixel group are alternately arranged in the first direction; a plurality of fifth pixel groups are arranged in the second direction; At least part of the third sub-pixel is divided into an asymmetric first part and a second part along a straight line passing through the geometric center of the third sub-pixel and parallel to the first direction; in the second direction, the maximum size of the first part is smaller than that of the second part; In the first spacing region between the third sub-pixels adjacent in the second direction, at least part of the first spacing region is the spacing region between the first parts of the third sub-pixels; The display substrate further includes a driving structure layer between the substrate and the plurality of sub-pixels.

2. The display substrate of claim 1, wherein The width of the first spacing region is greater than or equal to 20 μm.

3. The display substrate of claim 1, wherein The distance between the boundary of the functional element and the boundary of the closest sub-pixel is greater than or equal to 3 μm. 4.The display substrate of claim 1, wherein a width of the second interval region is less than or equal to 19 μm. 5.The display substrate of claim 1, wherein a shortest line connecting boundaries of two sub-pixels corresponding to at least part of the first interval region passes through the functional element in the first interval region. 6.The display substrate of claim 5, wherein in a cross section passing through the shortest line and perpendicular to the substrate, a distance between the boundaries of the two sub-pixels corresponding to the first interval region is greater than or equal to 20 μm, and a distance between the functional element in the first interval region and the sub-pixels is greater than or equal to 3 μm. 7.The display substrate of claim 1, wherein a line connecting geometric centers of two sub-pixels corresponding to at least part of the first interval region passes through the functional element in the first interval region. 8.The display substrate of claim 7, wherein the line connecting the geometric centers of the two sub-pixels corresponding to at least part of the first interval region passes through a geometric center of the functional element in the first interval region. 9.The display substrate of claim 1, wherein at least part of the first interval region extends along a third direction; at least part of the first interval region extends along a fourth direction; the fourth direction intersects the third direction; at least part of the first interval region extending along the third direction and at least part of the first interval region extending along the fourth direction have an overlapping region, and at least part of the functional element overlaps the overlapping region. 10.The display substrate of claim 1, wherein a distance between adjacent functional elements is between 100 μm and 300 μm. 11.The display substrate of claim 1, wherein a proportion of a number of functional positions provided with the functional elements to a total number of the functional elements is at least 15%. 12.The display substrate of claim 1, further comprising a pixel definition layer; the pixel definition layer comprises pixel definition layer openings and pixel definition portions between the pixel definition layer openings; the pixel definition layer openings define light emitting regions of the sub-pixels; and the functional elements are disposed on a side of the pixel definition portions away from the substrate. 13.The display substrate of claim 12, wherein the functional elements and the pixel definition portions are in an integrated structure. 14.The display substrate of claim 1, wherein among a plurality of sub-pixels adjacent to at least part of the functional elements, a geometric center of at least one sub-pixel deviates from a straight line extending along a first direction, and geometric centers of at least two sub-pixels in a same row as the sub-pixel in the first direction are on the straight line; and / or, among the plurality of sub-pixels adjacent to at least part of the functional elements, a geometric center of at least one sub-pixel deviates from a straight line extending along a second direction, and geometric centers of at least two sub-pixels in a same row as the sub-pixel in the second direction are on the straight line; the second direction intersects the first direction. 15.The display substrate of claim 1, wherein ​ ​ ​ ​ ​ ​ 12.The display substrate of claim 1, wherein, ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The interval region between the first sub-pixel and the third sub-pixel in the third pixel group is the first interval region. The interval region between the first sub-pixel and the third sub-pixel in the first pixel group is the second interval region. 16.The display substrate of claim 15, wherein, The interval region between the first sub-pixel and the third sub-pixel in the third pixel group is alternately the first interval region and the second interval region along the second direction. In two adjacent third pixel groups, one first interval region in one third pixel group and one second interval region in the other third pixel group are located between two rows of sub-pixels arranged along the first direction. 17.The display substrate of claim 16, wherein, The connecting line of the geometric centers of two first sub-pixels and two third sub-pixels arranged in an array forms a virtual trapezoid. The interval region between the first sub-pixel and the third sub-pixel corresponding to the bottom side of the virtual trapezoid is the first interval region, and the interval region between the first sub-pixel and the third sub-pixel corresponding to the top side of the virtual trapezoid is the second interval region. 18.The display substrate of claim 17, wherein, The bottom side of the virtual trapezoid is parallel to the second direction. 19.The display substrate of claim 17, wherein, The virtual trapezoid is a virtual isosceles trapezoid. 20.The display substrate of claim 15, wherein, In the first interval region located at least partially between the first sub-pixel and the third sub-pixel, the geometric center of the functional element is located on the connecting line between the geometric center of the first sub-pixel and the geometric center of the third sub-pixel corresponding to the first interval region. 21.The display substrate of claim 15, wherein, In the first interval region located at least partially between the first sub-pixel and the third sub-pixel, along the second direction, the distance between the geometric center of the functional element and the geometric center of the first sub-pixel corresponding to the first interval region is less than the distance between the geometric center of the functional element and the geometric center of the third sub-pixel corresponding to the first interval region. 22.The display substrate of claim 21, wherein, In the first interval region located at least partially between the first sub-pixel and the third sub-pixel, along the second direction, the geometric center of the functional element is located on the side of the reference line corresponding to the first interval region close to the first sub-pixel; wherein the reference line of the functional element is the connecting line between the geometric centers of two second sub-pixels located on the two sides of the functional element in the first direction. 23.The display substrate of claim 1, wherein, A shape of the first sub-pixel comprises a square or a rounded square, one diagonal of the square or the rounded square is parallel to the first direction, and the other diagonal is parallel to the second direction. A shape of the third sub-pixel comprises a square or a rounded square, one diagonal of the square or the rounded square is parallel to the first direction, and the other diagonal is parallel to the second direction. 24.The display substrate of claim 1, wherein, In the interval regions between the third sub-pixels adjacent to each other in the seventh pixel group, at least part of the interval regions are the first interval regions. The interval regions between the first sub-pixels and the third sub-pixels adjacent to each other in the fifth pixel group, and the interval regions between the second sub-pixels and the third sub-pixels adjacent to each other, are the second interval regions. The interval regions between the first sub-pixels and the second sub-pixels adjacent to each other in the fifth pixel group are the second interval regions. 25.The display substrate of claim 24, wherein, In the interval regions between the third sub-pixels adjacent to each other in at least part of the seventh pixel group, the interval regions are alternately the first interval regions and the second interval regions along the second direction. 26.The display substrate of any one of claims 1 to 25, wherein, The first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel. 27.The display substrate of claim 1, wherein, The function comprises a spacer position, and the functional element comprises a spacer.

28. A display device comprising: comprising: The display substrate of any one of claims 1 to 27.

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