A method for preparing a low-leakage surface-structured SiC phototransistor
By forming a P+ or N+ region at the edge of the SiC phototransistor and using a passivation layer, the interface defect problem introduced by mesa etching is solved, the leakage current is reduced, and the sensitivity and gain of the detector are improved.
Patent Information
- Application Number
- CN202211485532.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-11-24
- Publication Date
- 2025-10-14
- Estimated Expiration
- 2042-11-24
AI Technical Summary
During the preparation process of traditional SiC phototransistors, mesa etching introduces interface defects at the edge of the device, resulting in increased leakage current and affecting detection efficiency and sensitivity.
Ion implantation is used to form a P+ or N+ region at the edge of the SiC phototransistor, and a passivation layer is combined to reduce edge gain and leakage current. The specific steps include ion implantation, photolithography, etching, passivation, and electrode fabrication.
It effectively reduces the device edge leakage current, improves the sensitivity and gain of the detector, and enhances the detection efficiency of the device.
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Figure CN115763627B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application belongs to the technical field of integrated circuits, and particularly relates to a preparation method of a low-leakage mesa structure SiC phototransistor. BACKGROUND
[0002] Ultraviolet (UV) photodetectors have attracted extensive attention due to their applications in industrial, environmental, biological and deep space detection fields. Compared with traditional Si-based UV detectors, 4H-SiC UV detectors have low current, natural visible light blindness, high quantum efficiency in the solar blind band, and high-temperature radiation resistance, and are ideal materials for preparing high-performance detectors. The research on traditional 4H-SiC PIN photodiodes has been relatively mature, but compared with SiC photodiodes, SiC npn phototransistors have the advantages of high responsivity, good linearity, low working bias and easy integration with detection systems, and have more development prospects. In the traditional SIC preparation process, the mesa etching step inevitably introduces interface defects at the edges of the device, and these interface defects become the main factor of the leakage current of the device. At the same time, due to the gain inside the device, the leakage current and the photocurrent are amplified together, which leads to the decrease of the detection efficiency of the device, so suppressing the leakage at the edge of the device is one of the most effective ways to reduce the dark current of the device and improve the gain and detection sensitivity of the device. SUMMARY
[0003] To solve the existing problems, the application provides a preparation method of a low-leakage mesa structure SiC phototransistor.
[0004] The application adopts the following technical scheme to realize the application:
[0005] A preparation method of a low-leakage mesa structure SiC phototransistor, which uses ion implantation at the edge of the device to form a P + region, reduces the edge gain and edge leakage, and specifically includes the following steps:
[0006] 1) standard cleaning of a SiC epitaxial wafer sample;
[0007] 2) alignment mark etching of the epitaxial wafer, then photoetching to form a mask film, ion implantation, and thermal annealing to form a P + region;
[0008] 3) photoetching to form a mask etching film, and using inductively coupled plasma technology to etch to form a mesa;
[0009] 4) passivation of the SiC epitaxial wafer obtained in step 3);
[0010] 5) fabrication of a back electrode, electron beam evaporation of a metal Ni electrode to form an n-type ohmic contact;
[0011] 6) Fabricating front electrode, electron beam evaporation Ni / Ti / Al / ni / Au to form ohmic contact, and finally evaporating Al to form a lead zone, obtaining a new type of SiC photoelectric NPN transistor.
[0012] The further improvement of the present application is that in step 1), the size of the SiC epitaxial wafer is 1*1 cm, and the device diameter is 200 μm.
[0013] The further improvement of the present application is that in step 2), step 3), step 5), and step 6), the photoresist used in the photoetching process is AZ5214, the spin coating speed is 500-1000 rpm at low speed, the spin coating time is 10-20 s, the spin coating speed is 3000-4000 rpm at high speed, and the spin coating time is 30-60 s.
[0014] The further improvement of the present application is that the mask etching film used is metal nickel.
[0015] The further improvement of the present application is that the thickness of the mask etching film is 50-100 nm.
[0016] The further improvement of the present application is that in step 1), the standard cleaning process conditions are as follows: ① the sample is sequentially placed in acetone, ethanol, and deionized water, and ultrasonic cleaning is performed for 10-20 min at a power of 80-100 W, and the deionized water is cleaned; ② a solution with a volume ratio of concentrated H2SO4:H2O2=3:1 is used for 80℃ water bath for 10-20 min, and the deionized water is cleaned; ③ a solution with a volume ratio of ammonia water:H2O2:H2O=0.25:1:5 is used for 80℃ water bath for 10-20 min, and the deionized water is cleaned; ④ a solution with a volume ratio of HCl:H2O2:H2O=1:1:6 is used for 80℃ water bath for 10-20 min, and the deionized water is cleaned; ⑤ a BOE solution is soaked for 3-5 min, and the deionized water is cleaned; and ⑥ the sample is dried by nitrogen blowing, and is placed on a heating table and baked at 120℃ for 3-5 min.
[0017] The further improvement of the present application is that in step 3), the inductively coupled plasma etching ion source power is 100-800 W, the substrate bias power is 20-100 W, a mixed gas of CF4 and O2 or a mixed gas of SF6 and O2 is used to etch the device, and a gas C4F8 is used to protect the sidewall of the device.
[0018] The further improvement of the present application is that in step 4), it specifically comprises growing a sacrificial oxide layer, removing the sacrificial oxide layer with a BOE solution, then growing a thermal oxide layer, and then PECVD 1 μm of an oxide layer.
[0019] The further improvement of the present application is that, in step 4), before high-temperature thermal oxidation, high-purity oxygen is introduced into the oxidation furnace for 10-20 min, the oxidation temperature is 1100-1500 DEG C, the temperature rising time is 2-3 h, and the single oxidation time is 1-3 h.
[0020] The present application has at least the following beneficial technical effects:
[0021] In the traditional SiC preparation process, mesa etching inevitably introduces interface defects at the edge of the device, and these interface defects become the main factor of the device leakage current. Meanwhile, due to the gain inside the device, these leakage currents and photocurrents are amplified together, resulting in the decrease of the detection efficiency of the device. Therefore, suppressing the leakage at the edge of the device is one of the most effective ways to reduce the dark current of the device and improve the gain and detection sensitivity of the device. The present application provides a preparation method of a low-leakage mesa structure SiC phototransistor, which ionizes P + at the edge of the mesa SiC NPN device, so that the gain value at the edge of the device is greatly reduced (about 1), thereby achieving the purpose of reducing the leakage of the device. BRIEF DESCRIPTION OF DRAWINGS
[0022] Figure 1 It is a structure diagram of a SiC photodiode.
[0023] Figure 2 It is a structure diagram of a SiC phototransistor.
[0024] Figure 3 It is a structure diagram of a new SiC phototransistor with low leakage current provided by the embodiment of the present application.
[0025] Figures 4-19 It is a preparation method flowchart of a new phototransistor junction provided by the embodiment 1 of the present application.
[0026] Figures 20-29 It is a preparation method flowchart of a new phototransistor junction provided by the embodiment 2 of the present application. DETAILED DESCRIPTION
[0027] The present application will be further described in detail below in combination with specific embodiments, but the embodiments of the present application are not limited thereto.
[0028] Compared with the SiC photodiode, the SiC npn phototransistor has the advantages of high responsivity, good linearity, low working bias and easy integration with the detection system.
[0029] As shown in Figure 1 , it is a structure diagram of a photodiode. Figure 1
[0030] AsFigure 2 As shown, Figure 2 It is a schematic diagram of the structure of an npn phototransistor. Figure 1 The difference between the structures shown is that the phototransistor is a device with internal gain, which has a higher response and the output current is much greater than that of the photodiode.
[0031] After years of research in the industry, some manufacturers have taken the lead in launching commercial products of npn phototransistors.
[0032] However, there are still several problems in the actual process manufacturing and application of SiC npn phototransistors:
[0033] 1. In order to form the terminal of the npn phototransistor prepared with an epitaxial structure, the preparation of the mesa structure becomes a very important process in the device preparation.
[0034] 2. The dark current level of the npn phototransistor determines the minimum light signal intensity that the detector can detect and determines the sensitivity of the device. Since the preparation process will inevitably introduce some defects, the surface leakage current of the detector cannot be ignored.
[0035] In order to solve the above problems, the technical solution of the present invention provides a new SiC photoelectric NPN transistor with low leakage current and a preparation method thereof. Ion implantation is used at the edge of the device to form a P + , reducing the edge gain and thus reducing the contribution of edge leakage.
[0036] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to examples.
[0037] Example 1
[0038] like Figure 3 As shown, Figure 3 A schematic diagram of the structure of a silicon carbide npn phototransistor provided in an embodiment of the present invention. The silicon carbide semiconductor device shown includes a substrate 1. The substrate of the epitaxial wafer is mostly a medium-doped n-type substrate with a concentration of 3E18cm -3 Collector region 2, parameter is 5μm(1E16cm -3 ), base region 3, parameter is 0.5μm(1E17cm -3 ). Emission zone 4, parameter is 0.3μm (2E19cm -3 ).
[0039] In order to solve the problem of edge leakage of phototransistor, ion implantation is used to form P + Region 7, reduces leakage current at the edge.
[0040] In order to reduce the leakage current, a passivation layer is used, which includes a thermal oxide layer 11 and a PECVD oxide layer 12. There are also a backside metal Ni electrode 13, a frontside electrode 15 and a wire bonding area 17.
[0041] In the present application, the P region at the edge is formed by ion implantation + , which reduces the amplification of the edge leakage current, reduces the dark current of the device and improves the sensitivity of the detector.
[0042] The manufacturing method can be as shown in Figures 1-19 .
[0043] Step 1: as shown in Figure 4 , an epitaxial wafer is provided, which includes a silicon carbide substrate 1, an npn phototransistor collector region 2, an npn phototransistor base region 3 and an npn phototransistor emitter region 4.
[0044] Step 2: first, the epitaxial wafer is etched with alignment marks. Then, as shown in Figure 5 , Figure 6 , Figure 7 , a P region 7 at the edge is formed by ion implantation. Photolithography is performed using a mask plate 5 and photoresist 6, and then ion implantation is performed. For silicon carbide material, ion implantation is generally performed at 500-600°C by a high-temperature ion implantation device to reduce damage to the silicon carbide lattice. For P + ion implantation, the typical implantation ion is Al ion; the ion implantation energy can be in the range of hundreds of KeV to several MeV, and the dose is 1E12 cm + -1E16 cm -2 -1E16 cm -2 ; the implantation depth is several hundred nm to several μm.
[0045] Step 3: In order to achieve electrical isolation between devices, the active region of the device needs to be isolated. As shown in Figure 8 , Figure 9 , photolithography is performed using a photomask plate 8 and photoresist 9 to form a mask etching film, and inductively coupled plasma (ICP) etching is used to form a mesa. Here, CF4 / O2 is used as the gas source for etching. Figure 9 to form a vertical mesa as shown.
[0046] Step 4: The device is passivated, and the damage to the surface etching can be reduced by passivation to reduce the etching damage in the material and reduce the leakage current of the device.
[0047] 4.1 First, thermal oxidation is performed in a high-temperature oxidation furnace (1300°C) for 60 minutes to obtain a sacrificial oxide layer 10, as shown in Figure 10 . Then, the thermal oxide layer is removed by buffer oxide etching (BOE). The purpose of this step is to remove the etching damage.
[0048] 4.2 The device is then re-oxidized for 5h by the same oxidation process to obtain a thermal oxide layer 11 as shown in Figure 12 .
[0049] 4.3 Then 1 μm of SiO2 is grown by plasma enhanced chemical vapor deposition (PECVD) to increase the thickness of the passivation layer as shown in Figure 13 .
[0050] 4.4 The SiO2 grown by PECVD contains a lot of hydrogen, so it is first annealed in N2 atmosphere at 400°C for 40 min to remove the hydrogen, and then annealed at 1000°C for 1 h to increase the density of the SiO2.
[0051] Step 5: Fabrication of back electrode
[0052] As shown in Figures 14-15 , the passivation layer on the front side is first covered with photoresist, then the SiO2 on the back side is removed, and then a layer of metal Ni 13 is formed by electron beam evaporation, followed by rapid annealing (first at 500°C for 10 min, then at 950°C for 5 min) to form an n-type ohmic contact electrode 13 to form the back electrode.
[0053] Step 6: Fabrication of front electrode.
[0054] As shown in Figures 16-17 , a mask plate 14 and photoresist are used, and then the SiO2 at the places where the metal contact needs to be prepared is etched clean using the BOE etching method, and then a Ni / Ti / Al / ni / Au (25nm / 35nm / 200nm / 20nm / 100nm) metal layer 15 is generated by electron beam evaporation, then acetone is used for stripping, and then deionized water is used for cleaning, and then nitrogen is used for drying;
[0055] Step 7: As shown in Figures 18-19 , a photomask 16 is used to prepare the soldering area by photolithography. Negative photoresist AZ5214 is used, and then a 1 μm thick Ti / Au / Ti / Al 17 is evaporated on the surface of the sample by electron beam evaporation, and then the photoresist is stripped using a stripping solution, and then the sample is cleaned with deionized water, and then dried with nitrogen.
[0056] Example 2
[0057] As shown in Figure 20 , Figure 20 is a structural diagram of a silicon carbide pnp phototransistor provided by an embodiment of the present application. The silicon carbide semiconductor device shown includes a substrate 18, and the substrate of the epitaxial wafer is a p-type substrate with a concentration of 3E18 cm -3 . A collector region 19 with parameters of 5 μm (1E16 cm -3), base region 20, parameter 0.5um (1E17cm -3 ), emitter region 21, parameter 0.3um (2E19cm -3 ).
[0058] In order to solve the problem of edge leakage of phototransistor, N+ region 22 is formed by ion implantation to reduce the edge leakage current.
[0059] In order to reduce the leakage current, passivation layer is used, and the passivation layer structure includes thermal oxide layer 24 and PECVD oxide layer 25. There are also back metal electrode 26, front electrode 27 and lead bonding area 28.
[0060] In the example of the present application, N+ is formed at the edge by ion implantation to reduce the amplification of edge leakage current, reduce the dark current of the device, and improve the sensitivity of the detector.
[0061] The manufacturing method can be as shown in Figures 20-29 .
[0062] Step 1: as shown in Figure 20 , an epitaxial wafer is provided, which includes silicon carbide substrate 18, npn phototransistor collector region 19, PNP phototransistor base region 20, and npn phototransistor emitter region 21.
[0063] Step 2: first, the epitaxial wafer is etched with alignment marks. Then, as shown in Figure 21 , edge N+ region 22 is formed by ion implantation. For silicon carbide material, ion implantation is generally carried out at 500-600°C by high-temperature ion implantation equipment to reduce the damage to the silicon carbide material lattice. For N+ ion implantation, the typical implantation ion is P ion; the ion implantation energy can be in the range of hundreds of KeV to several MeV, the dose is 1E12cm -2 -1E16cm -2 , and the implantation depth is several hundred nm to several μm.
[0064] Step 3: In order to achieve electrical isolation between devices, the active region of the device needs to be isolated. As shown in Figure 22 , first, photoetching is carried out to form a mask etching film, and inductive coupling plasma technology (ICP) is used to etch to form a mesa, and CF4 / O2 is used as the gas source for etching. The vertical mesa shown in Figure 22 is formed.
[0065] Step 4: The device is passivated, and the damage of surface etching can be reduced by passivation to reduce the etching damage in the material and reduce the leakage current of the device.
[0066] 4.1 First, a sacrificial oxide layer 23 is formed by thermal oxidation at high temperature (1300 °C) for 60 min, as shown in Fig. 4.1. Then the thermal oxide layer is removed by buffered oxide etching (BOE). The purpose of this step is to remove etching damage. Figure 23
[0067] 4.2 Next, the device is oxidized again by the same oxidation process for 5 h to form a thermal oxide layer 24, as shown in Fig. 4.2. Figure 24
[0068] 4.3 Then, 1 μm of SiO2 25 is grown by plasma chemical vapor deposition (PECVD) to increase the thickness of the passivation layer, as shown in Fig. 4.3. Figure 25
[0069] 4.4 The SiO2 grown by PECVD contains a large amount of hydrogen. First, it is annealed at 400 °C for 40 min in N2 atmosphere to remove hydrogen, and then annealed at 1000 °C for 1 h to increase the density of the SiO2.
[0070] Step 5: Fabrication of back electrode
[0071] As shown in Fig. 4.4, first, the passivation layer on the front side is covered with photoresist, then the SiO2 on the back side is removed, and then Ni / Ti / Al / ni / Au (25 nm / 35 nm / 200 nm / 20 nm / 100 nm) is formed by electron beam evaporation, followed by rapid annealing (first 500 °C for 10 min, then 950 °C for 5 min) to form a P-type ohmic contact electrode 26, and then acetone is used to strip the photoresist, and the sample is cleaned with deionized water and dried with nitrogen. Figures 26-27 Step 6: Fabrication of front electrode.
[0072] As shown in Fig. 4.5, first, a mask film is formed by photolithography, then the SiO2 at the places where the metal contact is to be prepared is etched clean using the BOE etching method, then a Ni / Ti / Al / ni / Au (25 nm / 35 nm / 200 nm / 20 nm / 100 nm) metal layer is formed by electron beam evaporation, followed by rapid annealing (first 500 °C for 10 min, then 950 °C for 5 min) to form a P-type ohmic contact electrode 27, then acetone is used to strip the photoresist, and the sample is cleaned with deionized water and dried with nitrogen.
[0073] Figure 28 Step 7: As shown in Fig. 4.6, a soldering area is prepared by photolithography. Negative resist AZ5214 is used, then a 1 μm thick Ti / Au / Ti / Al 28 is evaporated on the surface of the sample by electron beam evaporation, then the resist is stripped with a stripping solution, and the sample is cleaned with deionized water and dried with nitrogen.
[0074] Figure 29
[0075] While the application has been described in detail and with reference to specific embodiments thereof, it will be apparent to one skilled in the art that various modifications or changes can be made therein without departing from the spirit and scope thereof. Accordingly, it is intended that all such modifications and changes be included within the scope of the application as claimed.
Claims
1. A method for preparing a low-leakage field-structure SiC phototransistor, characterized in that: This method uses ion implantation at the edge of the device to form P + The following steps are specifically included to reduce edge gain and edge leakage: 1) Perform standard cleaning on SiC epitaxial wafer samples; 2) Etch the alignment mark of the epitaxial wafer, then photolithography to form a mask film, perform ion implantation, thermal annealing, and form P + district; 3) Photolithography forms a mask film, and inductively coupled plasma technology is used to etch the mesa. The inductively coupled plasma etching ion source power is 100 to 800 W, the substrate bias power is 20 to 100 W, and a mixed gas of CF4 and O2 or a mixed gas of SF6 and O2 is used to etch the device. The sidewalls of the device are protected by gas C4F8. 4) passivating the SiC epitaxial wafer obtained in step 3); specifically, growing a sacrificial oxide layer, removing it with a BOE solution, growing a thermal oxide layer by high-temperature thermal oxidation, and then growing a 1 μm oxide layer by PECVD; before the high-temperature thermal oxidation, passing high-purity oxygen into the oxidation furnace for 10 to 20 minutes, the oxidation temperature is 1100 to 1500° C., the heating time is 2 to 3 hours, and the single oxidation time is 1 to 3 hours; 5) Fabricate the back electrode and form an n-type ohmic contact by electron beam evaporation of a metal Ni electrode; 6) Fabricate the front electrode, electron beam evaporate Ni / Ti / Al / Ni / Au to form an ohmic contact, and finally evaporate Al to form a lead pad to obtain a new SiC NPN phototransistor.
2. The method for preparing a low-leakage surface structure SiC phototransistor according to claim 1, characterized in that: In step 1), the size of the SiC epitaxial wafer is 1×1 cm, and the device diameter is 200 μm.
3. The method for preparing a low leakage ground-structure SiC phototransistor according to claim 1, characterized in that: In step 2), step 3), step 5), and step 6), the photoresist used in the photolithography process is AZ5214, the spin coating speed is 500-1000 rpm at a low speed, the spin coating time is 10-20 s, and the spin coating speed is 3000-4000 rpm at a high speed, and the spin coating time is 30-60 s.
4. The method for preparing a low-leakage surface-structure SiC phototransistor according to claim 3, characterized in that: The mask film used is nickel.
5. The method for preparing a low-leakage surface-structure SiC phototransistor according to claim 3, characterized in that: The thickness of the mask film is 50 to 100 nm.
6. The method for preparing a low-leakage surface-structure SiC phototransistor according to claim 1, characterized in that: In step 1), the standard cleaning process conditions are as follows: ① the sample is placed in acetone, ethanol, and deionized water in turn, ultrasonically cleaned for 10 to 20 minutes at a power of 80 to 100 W, and cleaned with deionized water; ② in a solution of concentrated H2SO4:H2O2=3:1 by volume, in a water bath at 80°C for 10 to 20 minutes, and cleaned with deionized water; ③ in a solution of ammonia:H2O2:H2O=0.25:1:5 by volume, in a water bath at 80°C for 10 to 20 minutes, and cleaned with deionized water; ④ in a solution of HCl:H2O2:H2O=1:1:6 by volume, in a water bath at 80°C for 10 to 20 minutes, and cleaned with deionized water; ⑤ soaked in BOE solution for 3 to 5 minutes, and cleaned with deionized water; ⑥ blown dry with nitrogen, the sample is placed on a heating table, and baked at 120°C for 3 to 5 minutes.