N-type crystalline silicon TOPCon battery

Abstract

The utility model discloses an N-type crystalline silicon TOPCon cell, which comprises a silicon substrate, a front metal electrode, a back metal electrode, a front selective emitter and a front anti-reflection passivation layer which are sequentially arranged along the front direction of the silicon substrate, and a TOPCon passivation contact structure, a back selective emitter and a back anti-reflection passivation layer which are sequentially arranged along the back direction of the silicon substrate. The double advantages of the selective emitter and the TOPCon cell are utilized, the front face of the silicon substrate is provided with the selective emitter structure, the back face of the silicon substrate is provided with the TOPCon passivation contact structure and the selective emitter structure, the TOPCon passivation contact structure and the double selective emitter structures are combined, and the selective emitter structure and the TOPCon passivation contact structure are combined. Metal contact resistance of the front and back surfaces and recombination loss of photon-generated carriers on the front and back surfaces of the cell can be obviously reduced, open-circuit voltage and filling factors are improved, and the conversion efficiency of the cell is effectively improved.

Description

TECHNICAL FIELD

[0001] The utility model belongs to the technical field of solar cell manufacturing, concretely relates to an N type crystalline silicon cell, and particularly relates to an N type crystalline silicon TOPCon cell. BACKGROUND

[0002] Crystalline silicon solar cells have been widely applied in recent years, conversion efficiency is continuously improved, and production cost continuously decreases. At present, crystalline silicon solar cells account for more than 80% of the total solar cell market. In the crystalline silicon solar cells, the TOPCon passivation contact cell is a new type of high conversion efficiency cell, the conversion efficiency can reach 24%, and the cell has good compatibility with conventional production lines. The passivation contact layer provides good surface passivation for the n+ surface, greatly reduces the metal contact recombination, and improves the open circuit voltage and short circuit current of the cell. The selective emitter structure (SE) can also effectively reduce the contact resistance between the N type crystalline silicon cell front and back metal and the silicon matrix, reduce the J0,met of the P+ area under the metal grid, improve the open circuit voltage and fill factor of the cell, and thus improve the conversion efficiency of the N type crystalline silicon cell.

[0003] The current industry problem is that the existing technology of mass production of N type crystalline silicon TOPCon cell structure has a large contact resistance (Rs) between the backside phosphorus diffusion metal grid and the N+ layer, a low fill factor (FF), a low backside passivation, and a low cell open circuit voltage (Uoc), and a series of bottlenecks. The selective emitter structure is one of the ideas to solve the above problems. In summary, it is an important industry problem to design an efficient N type crystalline silicon TOPCon cell structure to overcome the above defects. SUMMARY

[0004] The utility model discloses in order to effectively solve above technical problem, provides an N type crystalline silicon TOPCon cell, including silicon substrate, along the front surface direction of the silicon substrate and set front surface selective emitter, front surface antireflection passivation layer in proper order, along the back surface direction of the silicon substrate and set TOPCon passivation contact structure, back surface selective emitter, back surface antireflection passivation layer in proper order, still include, with the ohmic contact of the front surface selective emitter of stereoscopic front surface metal electrode, and with the ohmic contact of the back surface selective emitter of stereoscopic back surface metal electrode.

[0005] Preferably, the front surface selective emitter includes a P+ layer and a P++ layer located in the metallization area of the P+ layer, the P++ layer is a patterned P++ layer of laser SE structure, the pattern of the P++ layer corresponds to the printing pattern of the front surface metal electrode, and the P++ layer and the P+ layer are a heavily doped region and a lightly doped region of the front surface selective emitter.

[0006] Preferably, the back surface selective emitter includes an N+ layer and the N++ layer located in the N+ layer metallization area, the N++ layer is a patterned N++ layer of a laser SE structure, the pattern of the N++ layer corresponds to the printed pattern of the back surface metal electrode, and the N++ layer and the N+ layer are a heavily doped region and a lightly doped region of the back surface selective emitter.

[0007] Preferably, the TOPCon passivation contact structure is a tunnel oxide layer plus a doped polysilicon layer, and the TOPCon passivation contact structure is the N+ layer.

[0008] Preferably, the front surface anti-reflection passivation layer is an aluminum oxide layer and a front surface silicon nitride layer, and the aluminum oxide layer and the front surface silicon nitride layer are sequentially formed along the direction of the silicon substrate; and the back surface anti-reflection passivation layer is a back surface silicon nitride layer.

[0009] Preferably, the doped polysilicon layer is a doped thin film polysilicon layer with a thickness controlled in a range of 120-180 nm.

[0010] Preferably, the P+ layer is a boron diffusion layer formed by a boron doping source.

[0011] Preferably, the P+ layer is a high surface concentration P+ layer.

[0012] Preferably, the tunnel oxide layer is an ultrathin silicon oxide layer.

[0013] Preferably, the doped polysilicon layer is a phosphorus-doped polysilicon layer.

[0014] The utility model discloses the beneficial effect is:

[0015] (1) the utility model provides a kind of N-type crystalline silicon TOPCon battery, and its selective emitter structure can effectively reduce metal gate line and heavily doped region (P++ area, N++ area) contact resistance, effectively reduce the metal J0 of heavily doped region, improve the fill factor (FF) of battery;Lightly doped region and heavily doped region can constitute obvious potential difference, effectively improve the open-circuit voltage (Uoc) of battery.

[0016] (2) the utility model discloses N-type crystalline silicon Topcon (Tunnel Oxide Passivated Contact) battery, contact performance is good, battery efficiency limit 28.7%, most close to crystalline silicon solar cell theoretical limit efficiency 29.43%. Its back surface tunnel oxide layer+doped polysilicon layer jointly forms good passivation contact structure, can effectively reduce the recombination of metal and silicon contact surface to 10fA / cm 2 Following.

[0017] (3) The utility model discloses a combination of front and back double selective emitter and TOPCon passivation contact structure, effectively improve the carrier collection ability, improve open-circuit voltage (Uoc), improve the short-circuit current (Isc) of battery. Among them, the tunneling oxide layer reduces the recombination loss, and improves the minority carrier lifetime; The doped polysilicon layer reduces the metal contact recombination, and the good contact effectively improves the open-circuit voltage and the fill factor, thereby improving the conversion efficiency; The light doping area of selective emitter can be well passivated, the surface recombination probability of carrier is reduced, thereby reducing the reverse saturation current of battery, and the closer to the surface of battery, the higher the generation rate of photo-generated carrier is, so that the light doping area can obtain high collection rate in the area of high carrier generation rate, thereby improving the short-circuit current (Isc) of battery; The heavy doping area formed under the electrode in this area is easy to form ohmic contact, thereby reducing the series resistance of battery and improving the fill factor (FF) of battery. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to better express the technical scheme of the utility model, the following will be described in the utility model:

[0019] Figure 1 N-type crystalline silicon TOPCon battery structure schematic diagram;

[0020] Figure 2 Performance comparison chart of example one;

[0021] Brief description of the drawings: 1, silicon substrate, 2, front metal electrode, 3, P+ layer, 4, aluminum oxide layer, 5, front silicon nitride layer, 6, P++ layer, 7, tunneling oxide layer, 8, doped polysilicon layer, 9, back silicon nitride layer, 10, back metal electrode, 11, N++ layer. DETAILED DESCRIPTION

[0022] The preferred embodiments of the utility model will be described below with reference to the drawings. Those skilled in the art should understand that these embodiments are only used to explain the technical principles of the utility model, and are not intended to limit the protection scope of the utility model.

[0023] It should be noted that in the description of the utility model, the terms "up", "down", "left", "right", "inside", "outside", "front", "back" and the like indicate the direction or positional relationship of the terms based on the direction or positional relationship shown in the drawings, which is only for the convenience of description, and does not indicate or imply that the device or element must have a specific orientation, be constructed and operated in a specific orientation, therefore it cannot be understood as a limitation on the utility model.

[0024] Example one is referred to Figure 1A N-type crystalline silicon TOPCon cell, comprising a silicon substrate 1, a front selective emitter, a front anti-reflective passivation layer arranged in sequence along the front direction of the silicon substrate 1, a TOPCon passivation contact structure, a back selective emitter, a back anti-reflective passivation layer arranged in sequence along the back direction of the silicon substrate 1; further comprising a stereoscopic front metal electrode 2 forming an ohmic contact with the front selective emitter, and a stereoscopic back metal electrode 10 forming an ohmic contact with the back selective emitter. The anti-reflective passivation layer can be one or more of a silicon nitride (SiN x ), silicon dioxide (SiO2), silicon oxynitride (SiO X N y ), and aluminum oxide (Al2O3) thin film stacked together. In this embodiment, the front anti-reflective passivation layer is a stack of an aluminum oxide layer 4 and a front silicon nitride layer 5, i.e. the aluminum oxide layer 4 and the front silicon nitride layer 5 are formed in sequence along the direction of the silicon substrate 1; the back anti-reflective passivation layer is a back silicon nitride layer 9.

[0025] The front selective emitter comprises a P+ layer 3 and a P++ layer 6 located in the metallization area of the P+ layer 3, the P++ layer 6 is a patterned P++ layer of laser SE structure, in this embodiment, the P++ layer 6 is located directly below the front metal electrode 2, i.e. the P++ layer 6 is closer to the silicon substrate 1, the pattern of the P++ layer 6 corresponds to the printed pattern of the front metal electrode 2, the P++ layer 6 and the P+ layer 3 are the heavily doped region and the lightly doped region of the front selective emitter. In this embodiment, the P+ layer 3 is a high surface concentration P+ layer, and the P+ layer 3 is a boron diffusion layer formed by a boron doping source.

[0026] The back selective emitter comprises an N+ layer and an N++ layer 11 located in the metallization area of the N+ layer, and the TOPCon passivation contact structure is a N+ layer, which is a doped polysilicon layer 8 and a tunnel oxide layer 7. In this embodiment, the doped polysilicon layer 8 is a doped thin film polysilicon layer with a thickness of 120-180 nm. The doped polysilicon layer 8 is a phosphorus-doped polysilicon layer. The N++ layer 11 is a patterned N++ layer of laser SE structure, in this embodiment, the N++ layer 11 is located directly below the back metal electrode 10, i.e. the N++ layer 11 is closer to the silicon substrate 1, the pattern of the N++ layer 11 corresponds to the printed pattern of the back metal electrode 10, and the N++ layer 11 and the N+ layer are the heavily doped region and the lightly doped region of the back selective emitter. In this embodiment, the printed patterns of the front metal electrode 2 and the back metal electrode 10 can adopt an equal-width grid line shape. The front metal electrode 2 adopts silver-aluminum paste, and the back metal electrode 10 adopts silver paste.

[0027] The N-type crystalline silicon TOPCon cell of this utility model has a TOPCon passivated contact structure and is equipped with a selective emitter on both the front and back sides. This structure can significantly reduce the metal contact resistance on the front and back sides and the recombination loss of photogenerated carriers on the front and back sides of the cell, increase the open circuit voltage and fill factor, and effectively improve the cell conversion efficiency. Figure 2 The experimental group is the performance of the TOPCon battery of the utility model, and the comparison group is the performance of the Topcon battery commonly used at present. Figure 2 It can be seen that the open circuit voltage and fill factor of the N-type crystalline silicon TOPCon battery of the present invention are significantly improved.

[0028] The preparation method of an N-type crystalline silicon TOPCon battery of the present invention is carried out according to the following steps:

[0029] Step 1: Select an N-type single crystal silicon wafer as the silicon substrate 1 for texturing and cleaning. The specifications and dimensions of the N-type single crystal silicon wafer may depend on the actual application scenario. In Example 1, an N-type single crystal silicon wafer with a resistivity of 0.5-1.1 Ohm.cm, a thickness of 160-170um, and a specification size of 182mm*182mm may be selected. The conventional method of texturing with alkaline solution is used for texturing and cleaning to prepare a pyramid velvet surface. The alkaline solution may be sodium hydroxide or potassium hydroxide solution.

[0030] Step 2: The front side of the textured silicon substrate 1 is doped with a boron-containing doping source to form a boron diffusion layer to prepare a P+ layer 3.

[0031] Step three: Patterned laser doping is performed on the metallized area of ​​the P+ layer 3 to form a P++ layer 6, which may include an etching process. The pattern of the patterned P++ layer 6 corresponds to the printed pattern of the front metal electrode 2, forming a heavily doped area and a lightly doped area of ​​the front selective emitter. At this time, borosilicate glass is generated at the edge of the surface of the silicon substrate 1 due to boron diffusion, and a lightly doped layer is formed in the area outside the P++ layer 6 that is not covered by the boron-containing doping source due to boron volatilization. Then, the borosilicate glass located at the edge of the silicon substrate 1 and the lightly doped layer formed on the surface due to the volatilization of boron in the boron-containing doping source are removed to form a front selective emitter.

[0032] Step 4: In this embodiment, the passivation contact structure is prepared on the back side of the silicon substrate 1; that is, a tunneling oxide layer 7 and a doped polysilicon layer 8 are prepared. The tunneling oxide layer 7 is an ultra-thin silicon oxide layer formed on the back side of the silicon substrate 1 using nitric acid oxidation, high-temperature thermal oxidation, ozone oxidation, or low-pressure chemical vapor deposition (LPCVD). The doped polysilicon layer 8 is formed on the surface of the tunneling oxide layer 7. The doped polysilicon layer 8 can be prepared using PECVD, LPCVD, or other methods known in the industry. The passivation contact structure formed serves as the N+ layer.

[0033] Step five: coating the N+ layer with a phosphorus-containing diffusion source, and performing patterned laser doping on the N+ layer coated with the phosphorus-containing diffusion source to prepare a patterned N++ layer 11, the pattern of the N++ layer corresponding to the printed pattern of the back metal electrode 10 to form the heavily doped region and the lightly doped region of the back selective emitter, and step five is specifically divided into the following three steps:

[0034] First step: coating the N+ layer with the phosphorus-containing diffusion source, and the phosphorus-containing diffusion source is coated by simple spin coating, roll coating, spraying, etc., or by other methods;

[0035] Second step: performing patterned laser doping on the N+ layer coated with the phosphorus-containing diffusion source, and the laser wavelength used in embodiment one for the patterned laser doping is 355nm-1064nm, the laser pattern used for the patterned laser doping is consistent with the pattern of the back metal electrode 10, and the laser fine grid line width is 50-80um; a picosecond laser is used in this embodiment, the power is controlled at 25-35W, the spot size is 30-45um, and the laser doping method using the phosphorus-containing diffusion source is more convenient, controllable and safe than the conventional high-temperature tube diffusion;

[0036] Third step: putting the laser-doped N+ layer into a chain-type high-temperature diffusion furnace, injecting oxygen into the chain-type high-temperature diffusion furnace, and performing high-temperature pushing and oxidation treatment to complete the doping and form the N++ layer 11, and the purpose of the chain-type high-temperature pushing is to prepare the surface concentration and junction depth required by the N++ layer 11, and at this time, phosphosilicate glass is generated at the edge of the surface of the silicon substrate 1. The combination of laser doping treatment and chain-type high-temperature pushing can more easily and controllably obtain the surface concentration and junction depth required by the N++ layer 11, thereby preparing a high-quality selective emitter structure.

[0037] Step six: removing the phosphosilicate glass (PSG) formed at the edge of the surface of the silicon substrate 1 and the phosphorus-containing diffusion source on the front surface by etching to form the back selective emitter. The front surface wrap plating includes borosilicate glass, doped polysilicon layer, and phosphosilicate glass, and can be removed by acid washing combined with alkali washing.

[0038] Step seven: coating films on the front surface and the back surface of the N-type crystalline silicon wafer to form the front anti-reflective passivation layer and the back anti-reflective passivation layer, and the specific method of this embodiment is to deposit aluminum oxide (Al2O3) on the surface of the P+ layer 3 to form an aluminum oxide layer 4, then deposit silicon nitride (SiN x ) on the surface of the aluminum oxide layer 4 to form a front silicon nitride layer 5, and deposit silicon nitride (SiN x ) on the surface of the N+ layer to form a back silicon nitride layer 9. The anti-reflective passivation film can also be silicon nitride (SiN x ), silicon dioxide (SiO2), silicon oxynitride (SiOX N y ), one or more of the aluminum oxide (Al2O3) films are superimposed.

[0039] Step 8: Screen printing the front metal electrode 2 and the back metal electrode 10, and sintering.

[0040] The above-described embodiments merely represent several implementation methods of the present invention. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the concept of the present invention, and all such variations and improvements fall within the scope of protection of the present invention.

Claims

1. An N-type crystalline silicon TOPCon cell, characterized in that: The device comprises a silicon substrate, a front selective emitter and a front anti-reflection passivation layer arranged in sequence along the front direction of the silicon substrate, and a TOPCon passivation contact structure, a back selective emitter and a back anti-reflection passivation layer arranged in sequence along the back direction of the silicon substrate; It also includes a three-dimensional front metal electrode forming an ohmic contact with the front selective emitter, and a three-dimensional back metal electrode forming an ohmic contact with the back selective emitter; the TOPCon passivation contact structure is a tunneling oxide layer plus a doped polysilicon layer, the TOPCon passivation contact structure serves as the N+ layer, and the doped polysilicon layer is a doped thin-film polysilicon layer with a thickness of 120-180nm; the back selective emitter includes an N+ layer and a patterned N++ layer located in the metallization area of ​​the N+ layer, and the pattern of the N++ layer corresponds to the printed pattern of the back metal electrode; The front selective emitter includes a P+ layer and a patterned P++ layer located in a metallization region of the P+ layer, wherein a pattern of the P++ layer corresponds to a printed pattern of the front metal electrode.

2. The N-type crystalline silicon TOPCon cell according to claim 1, characterized in that: The front anti-reflection passivation layer is an aluminum oxide layer and a front silicon nitride layer stacked together, and the aluminum oxide layer and the front silicon nitride layer are sequentially formed along the direction of the silicon substrate; the back anti-reflection passivation layer is a back silicon nitride layer.

3. The N-type crystalline silicon TOPCon cell according to claim 1, characterized in that: The P+ layer is a boron diffusion layer.

4. The N-type crystalline silicon TOPCon cell according to claim 1, characterized in that: The tunneling oxide layer is an ultra-thin silicon oxide layer.

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