Image data transmission method and device based on FPGA and computer equipment

Abstract

The application relates to the technical field of image data processing, in particular to an image data transmission method and device based on FPGA and computer equipment, which can solve the problem of waste of block RAM resources caused by insufficient utilization of the width of the block RAM in the storage mode of separately buffering image data of each channel in each block RAM. The method comprises the following steps: determining the number of block RAMs based on the channel width and the number of channels of each channel; in each channel, splicing image data received in a continuous preset number of moments to obtain spliced image data; in the preset number of moments, spliced image data of all channels is sequentially written into different addresses of corresponding block RAMs, wherein the image data of the same spliced image data is written into the same address of the same block RAM; after one line of image data is written into the block RAM, the image data is sequentially read from the same address of all block RAMs.

Description

Technical Field

[0001] This application relates to the field of image data processing technology, and more specifically, to an image data transmission method, apparatus, and computer device based on FPGA. Background Technology

[0002] As image sensors achieve higher resolutions and higher frame rates, the bandwidth of image data also increases. To achieve higher image data throughput, image data is transmitted through multi-channel parallel transmission based on high-speed interface technology.

[0003] Typically, image sensors use parallel data in a non-continuous format. Figure 1A This is a schematic diagram illustrating a non-continuous arrangement of image data. Figure 1A As shown, the image is divided into multiple channels horizontally (e.g., channels 1-4), and image data at the same position in each channel (small squares in the figure) are transmitted simultaneously. This non-contiguous format of image data is unsuitable for backend image processing algorithms. To address this issue, a method is proposed to transmit parallel data in a contiguous format, and to cache the image data of each channel in a separate RAM block, such as... Figure 1B This is a schematic diagram showing image data arranged in a continuous format.

[0004] Typically, the width of image data for each channel is 8 bits, 10 bits, or 12 bits. The width of the block RAM is greater than the width of the image data. Therefore, this storage method of caching the image data of each channel separately in each block RAM has the problem of wasting block RAM resources due to insufficient utilization of the block RAM width. Since the block RAM resources on the FPGA are limited and the image algorithm has a large demand for block RAM, the block RAM space occupied should be minimized when storing image data. Summary of the Invention

[0005] To address the problem of wasted RAM resources caused by insufficient utilization of the RAM width when storing image data for each channel separately in each RAM block, this application provides an FPGA-based image data transmission method, apparatus, and computer device.

[0006] The embodiments of this application are implemented as follows:

[0007] This application provides an FPGA-based image data transmission method, the method comprising:

[0008] The number of block RAMs is determined based on the channel width and the number of channels for each channel, and the channel width for each channel is determined based on the channel width and the number of channels;

[0009] In each channel, image data received within a consecutive preset number of time intervals are stitched together to obtain stitched image data, wherein the image is composed of multiple rows of image data arranged in an array, and the preset number is determined according to the number of channels and the number of blocks of RAM;

[0010] Within a preset number of time intervals, the stitched image data of all channels are sequentially written to different addresses of the corresponding block RAM. The image data of the same stitched image data is written to the same address of the same block RAM. The address of the corresponding block RAM where the image data is written is determined according to the column index of each image data in the stitched image data and the number of channels. The index of the corresponding block RAM where the image data is written is determined according to the column index of each image data in the stitched image data, the number of channels, and the preset number. At the same time, the column indices of the image data of all channels are not consecutive.

[0011] After all the image data in a row has been written to the block RAM, the image data is read sequentially from the same address in all the block RAMs.

[0012] In some embodiments, determining the number of block RAMs based on the channel width and the number of channels for each channel further includes:

[0013] Calculate the greatest common divisor of the channel width and the number of channels;

[0014] Calculate the quotient of the number of channels and the greatest common divisor, where the quotient is the number of RAM blocks.

[0015] In some embodiments, the preset number is determined based on the number of channels and the number of block RAMs, and further includes:

[0016] Calculate the quotient of the number of channels and the number of RAM blocks, where the quotient is the value of the preset number.

[0017] In some embodiments, the width of each block RAM is equal to the product of the image data width and the preset number, and the depth of each block RAM is equal to the channel width of the channel.

[0018] In some embodiments, the address of the corresponding block RAM where the image data is written is determined based on the column index of each image data in the stitched image data and the number of channels, further including:

[0019] Obtain the column index of each image data, where the column index represents the number of columns in the image where the image data is located;

[0020] Calculate the first quotient and the first remainder between the column index and the number of channels. The first quotient is the address where the image data corresponding to the column index is stored in the corresponding block of RAM. The address is {0, 1, 2, ..., N-1, where N = channel width}.

[0021] In some embodiments, the index of the corresponding block RAM where the image data is written is determined based on the column index of each image data in the stitched image data, the number of channels, and the preset number, further including:

[0022] Obtain the column index of each image data, where the column index represents the number of columns in the image where the image data is located;

[0023] Calculate the second quotient and the second remainder of the first remainder and the preset number of values. The second quotient is the index of the image data corresponding to the column index stored in the corresponding block RAM. The index of the block RAM is {0, 1, 2, ..., M-1, where M = number of blocks RAM}.

[0024] In some embodiments, after all the image data in a row has been written to the block RAM, the image data is read sequentially from the same address in all the block RAMs, further comprising:

[0025] After all the image data in a row is written to the block RAM, the image data is read from all the block RAMs in the order of the addresses. During the reading, the image data with the same address in all the block RAMs are read sequentially to obtain continuously arranged image data.

[0026] Another aspect of this application provides an FPGA-based image data transmission device, comprising:

[0027] A determination module is used to determine the number of block RAMs based on the channel width and the number of channels for each channel, wherein the width of each channel is determined based on the image width and the number of channels;

[0028] The stitching module is used to stitch together image data received within a preset number of consecutive time intervals in each channel to obtain stitched image data, wherein the image is composed of multiple rows of image data arranged in an array, and the preset number is determined according to the number of channels and the number of blocks of RAM;

[0029] The writing module is used to sequentially write the stitched image data of all channels to different addresses of the corresponding block RAM within a preset number of time intervals. The image data of the stitched image data is written to the same address in the same block RAM. The address of the corresponding block RAM where the image data is written is determined based on the column index of each image data in the stitched image data and the number of channels. The index of the corresponding block RAM where the image data is written is determined based on the column index of each image data in the stitched image data, the number of channels, and the preset number. At the same time, the column indices of the image data of all channels are not consecutive.

[0030] The reading module is used to read the image data sequentially from the same address of all the image data blocks after all the image data in a row has been written into the block RAM.

[0031] Another aspect of this application provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the above-described FPGA-based image data transmission method.

[0032] Another aspect of this application provides a computer-readable storage medium storing instructions that, when executed on a computer, cause the computer to perform the FPGA-based image data transmission method described above.

[0033] The beneficial effects of this application are as follows: While converting the arrangement format of image data from non-continuous data to continuous data, this application stitches together the image data received within a preset number of time intervals to obtain stitched image data. The stitched image data of all channels is written to the corresponding block RAM address. The width of the stitched image data written to the block RAM address at each time interval is equal to the data width of the block RAM, thereby achieving the purpose of making full use of the data width of the BRAM and reducing the waste of BRAM resources. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1A This is a schematic diagram showing image data arranged in a non-continuous format.

[0036] Figure 1B A schematic diagram showing image data arranged in a continuous format;

[0037] Figure 2 An exemplary flowchart of an image data transmission method based on PFGA is shown in one embodiment of this application;

[0038] Figure 3 An exemplary flowchart illustrating the process of determining the number of block RAMs is shown;

[0039] Figure 4 An exemplary schematic diagram illustrates the process of calculating the index and address of each image data to be written to the corresponding block RAM in another embodiment of this application;

[0040] Figure 5 An example is shown illustrating the arrangement of column indexes for non-continuous data;

[0041] Figure 6 An example diagram illustrates the arrangement of column indexes for continuous data;

[0042] Figure 7 A schematic diagram of the index of each image data in the block RAM is shown;

[0043] Figure 8 A schematic diagram of the addresses of each image data in the block RAM is shown;

[0044] Figure 9 An exemplary block diagram of an FPGA-based image data transmission device is shown, according to yet another embodiment of this application. Detailed Implementation

[0045] To make the objectives, implementation methods and advantages of this application clearer, the exemplary implementation methods of this application will be clearly and completely described below with reference to the accompanying drawings of the exemplary embodiments of this application. Obviously, the described exemplary embodiments are only some embodiments of this application, and not all embodiments.

[0046] It should be noted that the brief descriptions of terms in this application are only for the convenience of understanding the embodiments described below, and are not intended to limit the embodiments of this application. Unless otherwise stated, these terms should be understood in their ordinary and common meaning.

[0047] The terms "first," "second," "third," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar or related objects or entities, and do not necessarily imply a specific order or sequence, unless otherwise specified. It should be understood that such terms are interchangeable where appropriate.

[0048] The terms “include” and “have”, and any variations thereof, are intended to cover but not exclusively include, for example, a product or device that includes a range of components is not necessarily limited to all of the components that are clearly listed, but may include other components that are not clearly listed or that are inherent to such product or device.

[0049] The terms "setup" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0050] FPGA, or Field-Programmable Gate Array, is a further development based on programmable devices such as PAL, GAL, and CPLD. It emerged as a semi-custom circuit in the field of Application-Specific Integrated Circuits (ASICs), addressing the shortcomings of custom circuits while overcoming the limited gate count of earlier programmable devices. It is the primary hardware platform for modern digital system design, characterized by its complete user-configurable and programmable functionality via software, allowing for repeated erasing and rewriting. Modifications and upgrades do not require additional changes to the PCB; only program updates on the computer are performed, transforming hardware design into software development, shortening system design cycles, increasing implementation flexibility, and reducing costs.

[0051] FPGA chips have two types of memory resources: one is called Block RAM (BRAM for short), and the other is internal memory (distributed RAM) configured by LUTs. Block RAM consists of a certain number of fixed-size storage blocks. Using block RAM does not consume additional logic resources and is fast.

[0052] Image sensors employ multiple channels for imaging and outputting image data, such as two or four channels for parallel transmission of discontinuous image data. Typically, image data is 8-bit, 10-bit, or 12-bit wide. Existing methods, which cache image data for each channel separately in a single RAM block, do not fully utilize the RAM's width. Therefore, this application proposes an FPGA-based image data transmission method and apparatus.

[0053] Figure 2 An exemplary flowchart of a data transmission method based on PFGA in one embodiment of this application is shown, such as... Figure 2 As shown, the data transmission method based on PFGA in this application is implemented through the following steps:

[0054] In step 210, the number of block RAMs is determined based on the channel width and the number of channels for each channel. The channel width for each channel is determined based on the image width and the number of channels, and the number of channels is set according to the configuration of the image sensor.

[0055] Assuming the image width is Img_W, the image width represents the number of pixels in an image in the X direction. Each pixel corresponds to image data that can be 1 bit or multiple bytes. The image is divided into Tap_Num channels along the image width direction (X direction). The number of channels is determined according to the configuration of the image sensor. Then, the channel width of each channel is expressed as Tap_W = Img_W / Tap_Num, where the channel width represents the number of pixels in the image in the X direction within a channel.

[0056] Figure 3 An exemplary flowchart illustrating the process of determining the number of block RAMs is shown, such as... Figure 3 As shown, the determination of the number of RAM blocks in this application is achieved through the following steps:

[0057] In step 310, the greatest common divisor of the channel width and the number of channels is calculated;

[0058] In step 320, the quotient of the number of channels and the greatest common divisor is calculated, and the quotient is the number of block RAMs.

[0059] The greatest common divisor is the width of a BRAM. The width of all BRAMs must be the same. The numerator (channel width) before reduction is the depth of the BRAM. The depth of each BRAM is also the same because the channel width of each channel is the same. The denominator (number of channels) after reduction by the greatest common divisor is the number of BRAMs.

[0060] Therefore, by reducing Tap_W / Tap_Num until the numerator and denominator are coprime, the number of channels Tap_Num is reduced to a prime number (denoted as Tap_Num′), which is the number of RAM blocks, denoted as Ram_Num.

[0061] In step 220, in each channel, the image data received within a consecutive preset number of time intervals are stitched together to obtain stitched image data. The image consists of multiple rows of image data arranged in an array, and the preset number is determined according to the number of channels and the number of RAM blocks.

[0062] In some embodiments, the quotient of the number of channels and the number of RAM blocks is calculated, and the quotient is a preset number of values; the preset number is represented as Combin_Num, where Combin_Num = Tap_Num / Ram_Num.

[0063] By stitching together a preset number of image data, the width of the stitched image data is equal to the width of the block RAM, thus achieving the goal of fully utilizing the data width of the block RAM.

[0064] The width of each RAM block is equal to the product of the image data width and the preset number, and the depth of each RAM block is equal to the channel width.

[0065] In step 230, within a preset number of time intervals, the stitched image data of all channels are sequentially written to different addresses of the corresponding block RAM. The image data of the same stitched image data is written to the same address of the same block RAM. The address of the corresponding block RAM where the image data is written is determined according to the column index of each image data in the stitched image data and the number of channels. The index of the corresponding block RAM where the image data is written is determined according to the column index of each image data in the stitched image data, the number of channels, and the preset number. At the same time, the column indices of the image data of all channels are not consecutive.

[0066] In some embodiments, the address of the corresponding block RAM where the image data is written is determined based on the column index and the number of channels of each image data in the stitched image data, and further includes:

[0067] Obtain the column index of each image data point. The column index is used to represent the number of columns in the image where the image data is located.

[0068] Calculate the first quotient and the first remainder between the column index and the number of channels. The first quotient is the address where the image data corresponding to the column index is stored in the corresponding block of RAM, and the address is {0, 1, 2, ..., N, where N = channel width}.

[0069] In some embodiments, the index of the corresponding block RAM where the image data is written is determined based on the column index, number of channels, and preset number of each image data in the stitched image data, and further includes:

[0070] Obtain the column index of each image data point. The column index is used to represent the number of columns in the image where the image data is located.

[0071] Calculate the second quotient and the second remainder of the first remainder and the preset number of values. The second quotient is the index of the image data corresponding to the column index to be stored in the corresponding block RAM. The index of the block RAM is {0, 1, 2, ..., M, where M = the number of blocks RAM}.

[0072] Figure 4 An exemplary schematic diagram illustrates the process of calculating the index and address of each image data entry for writing to the corresponding RAM block, as shown in another embodiment of this application. Figure 4As shown, the index and address of the corresponding RAM block to be written are determined based on the column index, number of channels, and preset number of each image data in the stitched image data, and this is achieved through the following steps:

[0073] In step 410, the column index of each image data is obtained. The column index is used to represent the number of columns in the image data. The column index of the image data in each image is represented as Col_Index.

[0074] In step 420, the first quotient and the first remainder between the column index and the number of channels are calculated. The first quotient is the address when the image data corresponding to the column index is stored in the corresponding block of RAM, and the address is {0, 1, 2, ..., N, where N = channel width}.

[0075] In some embodiments, the quotient of Col_Index / Tap_Num is calculated as a first quotient Q1 and a first remainder R1, where the first quotient is the address Ram_Addr where the target image data (i.e., the image data corresponding to the column index) is stored in the corresponding block RAM.

[0076] In step 430, the second quotient and the second remainder are calculated by the first remainder and the value of the preset number. The second quotient is the index of the image data corresponding to the column index that is stored in the corresponding block RAM. The index of the block RAM is {0, 1, 2, ..., M, where M = number of blocks RAM}.

[0077] In some embodiments, the second quotient Q2 of the first remainder R1 / Combin_Num and the second remainder R2 are calculated. The second quotient Q2 is the index Ram_Index of the target image data (i.e. the image data corresponding to the column index) stored in the corresponding block RAM.

[0078] The image data corresponding to the column index is written to the address of the corresponding block RAM according to the index Ram_Index and the address Ram_Addr. The image data in the stitched image data is written to the same address of the same block RAM.

[0079] In step 240, after a row of image data is written to the block RAM, the image data is read sequentially from the same address in all the block RAMs.

[0080] In some embodiments, after a row of image data is written to the block RAM, image data is read from all the block RAMs in address order. During reading, image data with the same address in all the block RAMs are read sequentially to obtain continuously arranged image data.

[0081] In some embodiments, the method of this application is illustrated using an image width of 800 (i.e., 800 image data are arranged in each row of the image), a number of channels of 8, and a channel width of 100 as an example.

[0082] Figure 5 An example is shown illustrating the arrangement of column indexes for non-continuous data, such as... Figure 5 As shown, image data is received from 8 channels in each clock cycle. The image data received by the 8 channels in each clock cycle is not continuous (e.g., the column index of the image data received by the 8 channels at clock 1 is 0, 100, 200, ..., 800).

[0083] Figure 6 An example diagram illustrates the arrangement of column indexes for continuous data, such as... Figure 6 As shown, image data is received from 8 channels (Tap1-Tap8) in each clock cycle. At the same time, the column indices of the image data from all channels are consecutive (e.g., the column indices of the image data received by clock 1 (Clk1) are 0, 1, 2, ..., 7).

[0084] Based on the transmission of continuous data, the number of RAM blocks (Ram_Num) required for image data with an image width (Img_W) of 800 is calculated. Since the greatest common divisor between the channel width and the number of channels is 4, the number of RAM blocks is 2.

[0085] Next, the preset number of image data in the stitched image data is calculated, Combin_Num, which is 4. That is, the image data obtained at 4 consecutive time points are stitched together and written into the block RAM. Then, the address and index of the image data written into the block RAM are calculated.

[0086] In some embodiments, if the column index of the image data is 0, then the first quotient is 0, the first remainder is 0, and the second quotient is 0. Then, the image data with column index 1 should be written to the 0th address of the first block RAM. Similarly, the image data with column indices 1, 2, and 3 are also written to the 0th address of the first block RAM.

[0087] Specifically, when writing image data, the four image data points received by the first channel during four consecutive clock cycles from clock 1 to clock 4 are stitched together and written to the same address in the same RAM block. The width of the stitched image data is equal to the width of the RAM block.

[0088] In some embodiments, if the column index of the image data is 4, then the first quotient is 0, the first remainder is 4, and the second quotient is 1. The image data with column index 4 should be written to the 0th address of the second storage block. Similarly, the image data with column indices 5, 6, and 7 are also written to the 0th address of the second block RAM.

[0089] Specifically, when writing image data, the four image data points received by the first channel during four consecutive clock cycles from clock 5 to clock 8 are spliced ​​together and written to the same address in the same RAM block. The width of the spliced ​​image data is equal to the width of the RAM block.

[0090] In some embodiments, if the column index of the image data is 408, then the first quotient is 51, the first remainder is 0, and the second quotient is 0. The image data with column index 408 should be written to the 51st address of the first storage block. Similarly, the image data with column indices 409, 410, and 411 are also written to the 51st address of the first block RAM.

[0091] Specifically, when writing image data, the four image data points received by the 8th channel during four consecutive clock cycles from clock 9 to clock 12 are spliced ​​together and written to the same address in the same RAM block. The width of the spliced ​​image data is equal to the width of the RAM block.

[0092] In some embodiments, if the column index of the image data is 412, then the first quotient is 51, the first remainder is 4, and the second quotient is 1. The image data with column index 412 should be written to the 51st address of the second storage block. Similarly, the image data with column indices 413, 414, and 415 are also written to the 51st address of the second block RAM.

[0093] Specifically, when writing image data, the four image data points received by the 5th channel during four consecutive clock cycles from clock 13 to clock 16 are stitched together and written to the same address in the same RAM block. The width of the stitched image data is equal to the width of the RAM block.

[0094] In some embodiments, if the column index of the image data is 792, then the first quotient is 99, the first remainder is 0, and the second quotient is 0. The image data with column index 792 should be written to the 99th address of the first storage block. Similarly, the image data with column indices 793, 794, and 795 are also written to the 99th address of the first block RAM.

[0095] Specifically, when writing image data, the four image data points received by the 8th channel during four consecutive clock cycles from clock 93 to clock 96 are spliced ​​together and written to the same address in the same RAM block. The width of the spliced ​​image data is equal to the width of the RAM block.

[0096] In some embodiments, if the column index of the image data is 796, then the first quotient is 99, the first remainder is 4, and the second quotient is 1. The image data with column index 796 should be written to the 99th address of the second storage block. Similarly, the image data with column indices 797, 798, and 799 are also written to the 99th address of the second block RAM.

[0097] Specifically, when writing image data, the four image data points received by the 8th channel during four consecutive clock cycles from clock 97 to clock 100 are spliced ​​together and written to the same address in the same RAM block. The width of the spliced ​​image data is equal to the width of the RAM block.

[0098] Figure 7 and Figure 8 The index and address of the response block RAM for which image data is written are calculated using the method of this application, wherein, Figure 7 This diagram illustrates the indexing of each image data point in the block RAM. Figure 8 The diagram shows the address of each image data in the block RAM. Figure 7 In this context, 0 represents the first storage block, and 1 represents the second storage block. Figure 8 The numbers in the representation indicate the addresses in the block of RAM.

[0099] Once a row of image data (referring to 800 image data) is written in the above manner, it can be read out. When reading out, the data at address 0 of two BRAMs are read simultaneously, that is, the image data stored in address 0 of the first RAM and the second memory unit, which is the image data with column indices 0 to 7. Then, the data is read out sequentially according to the address order, thus completing the data format conversion.

[0100] This application converts the image data arrangement format from discontinuous data to continuous data, while stitching together the image data received within a preset number of time intervals to obtain stitched image data. The stitched image data of all channels is written to the corresponding block RAM address. The width of the stitched image data written to the block RAM address at each time interval is equal to the data width of the block RAM, thereby achieving the goal of making full use of the data width of the BRAM and reducing the waste of BRAM resources.

[0101] Figure 9 An exemplary structural block diagram of an FPGA-based image data transmission device according to another embodiment of this application is shown, such as... Figure 9 As shown, the FPGA-based image data transmission device 900 includes: a determining module 910, a stitching module 920, a writing module 930, and a reading module 940, wherein:

[0102] The determination module is used to determine the number of block RAMs based on the channel width and the number of channels for each channel, where the width of each channel is determined based on the image width and the number of channels;

[0103] The stitching module is used to stitch together image data received within a preset number of consecutive time intervals in each channel to obtain stitched image data. The image consists of multiple rows of image data arranged in an array. The preset number is determined based on the number of channels and the number of RAM blocks.

[0104] The writing module is used to sequentially write the stitched image data of all channels to different addresses of the corresponding RAM blocks at every preset number of time intervals. The image data of the stitched image data is written to the same address of the same RAM block. The address of the corresponding RAM block where the image data is written is determined according to the column index of each image data in the stitched image data and the number of channels. The index of the corresponding RAM block where the image data is written is determined according to the column index of each image data in the stitched image data, the number of channels, and the preset number. At the same time, the column indices of the image data of all channels are not consecutive.

[0105] The read module is used to read image data sequentially from the same address in all block RAMs after a row of image data has been written to the block RAM.

[0106] In some embodiments, the determining module is also used for

[0107] Calculate the greatest common divisor of the channel width and the number of channels;

[0108] Calculate the quotient of the number of channels and the greatest common divisor. The quotient is the number of RAM blocks.

[0109] In some embodiments, the determining module is further configured to: calculate the quotient of the number of channels and the number of block RAMs, wherein the quotient is a preset number of values.

[0110] In some embodiments, the width of each block RAM is equal to the product of the image data width and a preset number, and the depth of each block RAM is equal to the channel width.

[0111] In some embodiments, the write module is further configured to: obtain the column index of each image data, the column index being used to characterize the number of columns in the image where the image data is located; calculate the first quotient and the first remainder between the column index and the number of channels, the first quotient being the address when the image data corresponding to the column index is stored in the corresponding block RAM, the address being {0, 1, 2, ..., N, where N = channel width}.

[0112] In some embodiments, the writing module is further configured to: obtain the column index of each image data, the column index being used to characterize the number of columns in the image where the image data is located; calculate the second quotient and the second remainder of the first remainder and a preset number of values, the second quotient being the index of the image data corresponding to the column index stored in the corresponding block RAM, the index of the block RAM being {0, 1, 2, ..., M, where M = number of blocks RAM}.

[0113] In some embodiments, the reading module is configured to: after a row of image data is written into the block RAM, read image data from all the block RAMs in order of address, wherein, during reading, image data with the same address in all the block RAMs are read sequentially to obtain continuously arranged image data.

[0114] In some embodiments, a computer device is provided, including a memory and a processor, which executes a computer program to implement the steps of the above-described FPGA-based image data transmission method. Its implementation principle and technical effects are similar to those of the above-described method embodiments, and will not be repeated here.

[0115] In some embodiments, a computer-readable storage medium is provided, storing instructions that, when executed on a computer, cause the computer to perform the steps of the FPGA-based image data transmission method described above. Its implementation principle and technical effects are similar to the methods described in the embodiments above, and will not be repeated here.

[0116] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.

[0117] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0118] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0119] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. An image data transmission method based on FPGA, characterized in that, The method includes: The number of RAM blocks is determined based on the channel width and the number of channels for each channel. The channel width of each channel is determined based on the image width and the number of channels. The width of each RAM block is equal to the product of the image data width and a preset number of channels. The depth of each RAM block is equal to the channel width. In each channel, image data received within a consecutive preset number of time intervals are stitched together to obtain stitched image data, wherein the image is composed of multiple rows of image data arranged in an array, and the preset number is determined according to the number of channels and the number of blocks of RAM; Within a preset number of time intervals, the stitched image data of all channels are sequentially written to different addresses of the corresponding block RAM. The image data of the same stitched image data is written to the same address of the same block RAM. The address of the corresponding block RAM where the image data is written is determined according to the column index of each image data in the stitched image data and the number of channels. The index of the corresponding block RAM where the image data is written is determined according to the column index of each image data in the stitched image data, the number of channels, and the preset number. At the same time, the column indices of the image data of all channels are not consecutive. After all the image data in a row is written to the block RAM, the image data is read sequentially from the same address in all the block RAMs; The number of block RAMs is determined based on the channel width and number of channels for each channel, further including: Calculate the greatest common divisor of the width of the channel image and the number of channels; Calculate the quotient of the number of channels and the greatest common divisor, where the quotient is the number of RAM blocks; The preset number is determined based on the number of channels and the number of block RAMs, and further includes: Calculate the quotient of the number of channels and the number of RAM blocks, where the quotient is the preset number; The address of the corresponding RAM block where the image data is written is determined based on the column index of each image data in the stitched image data and the number of channels, and further includes: Obtain the column index of each image data, where the column index represents the number of columns in the image where the image data is located; Calculate the first quotient and the first remainder between the column index and the number of channels. The first quotient is the address where the image data corresponding to the column index is stored in the corresponding block of RAM. The address is {0, 1, 2, ..., N-1, where N = channel width}.

2. The FPGA-based image data transmission method as described in claim 1, characterized in that, The index of the corresponding RAM block where the image data is written is determined based on the column index of each image data in the stitched image data, the number of channels, and the preset number, and further includes: Obtain the column index of each image data, where the column index represents the number of columns in the image where the image data is located; Calculate the second quotient and the second remainder of the first remainder and the preset number of values. The second quotient is the index of the image data corresponding to the column index stored in the corresponding block RAM. The index of the block RAM is {0, 1, 2, ..., M-1, where M = number of blocks RAM}.

3. The FPGA-based image data transmission method as described in claim 1, characterized in that, After all the image data in a row is written to the block RAM, the image data is read sequentially from the same address in all the block RAMs, further including: After all the image data in a row is written to the block RAM, the image data is read from all the block RAMs in the order of the addresses. During the reading, the image data with the same address in all the block RAMs are read sequentially to obtain continuously arranged image data.

4. An FPGA-based image data transmission device, the device being applicable to the method described in any one of claims 1 to 3, characterized in that, include: A determination module is used to determine the number of block RAMs based on the channel width and the number of channels for each channel, wherein the channel width of each channel is determined based on the image width and the number of channels; The stitching module is used to stitch together image data received within a preset number of consecutive time intervals in each channel to obtain stitched image data, wherein the image is composed of image data arranged in an array, and the preset number is determined according to the number of channels and the number of blocks of RAM; The writing module is used to sequentially write the stitched image data of all channels to different addresses of the corresponding block RAM within a preset number of time intervals. The image data of the stitched image data is written to the same address in the same block RAM. The address of the corresponding block RAM where the image data is written is determined based on the column index of each image data in the stitched image data and the number of channels. The index of the corresponding block RAM where the image data is written is determined based on the column index of each image data in the stitched image data, the number of channels, and the preset number. At the same time, the column indices of the image data of all channels are not consecutive. The reading module is used to read the image data sequentially from the same address of all the image data blocks after all the image data in a row has been written into the block RAM.

5. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the FPGA-based image data transmission method according to any one of claims 1 to 3.

6. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores instructions that, when executed on a computer, cause the computer to perform the FPGA-based image data transmission method as described in any one of claims 1 to 3.

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