Signal triggering output method and device

Abstract

The application discloses a signal trigger output method and device, and the method comprises the following steps: acquiring a current edge phase value of a first trigger signal; judging whether the current edge phase value of the first trigger signal is stable; calculating a dynamic phase decision threshold which makes the stable edge phase value of the first trigger signal between phase decision thresholds according to the stable edge phase value of the first trigger signal; acquiring a real-time edge phase value of the first trigger signal, and judging whether the real-time edge phase value is between the dynamic phase decision thresholds; if the real-time edge phase value is between the dynamic phase decision thresholds, the real-time edge phase value is taken as a trigger phase value of waveform generation to control predetermined waveform generation. By adjusting the phase decision threshold to make the edge phase value of the first trigger signal between the phase decision thresholds according to the stable edge phase value of the first trigger signal in the synchronous trigger mode, the jitter of the signal trigger output is greatly reduced.

Description

Technical Field

[0001] This application relates to the field of signal generation technology, and in particular to a signal triggering output method and apparatus. Background Technology

[0002] In signal source measurement applications, to reduce jitter in external trigger output signals, most current methods aim to achieve high-precision trigger output by improving the phase detection accuracy of the external trigger signal edge. However, limited by the phase detection accuracy of the trigger signal and the sampling clock accuracy of the digital-to-analog converter, the jitter of the trigger output using this technique can only reach the nanosecond level.

[0003] In some specialized applications, there are strict requirements regarding the timing of the signal source's output signal. It is desirable to control the signal source to output a specific signal needed by the user at a specific moment, requiring the jitter of the trigger output signal relative to the trigger signal to be on the order of picoseconds. Current techniques that improve the phase detection accuracy of the trigger input signal are insufficient to meet this requirement. How to further reduce the jitter of the trigger output signal is a crucial technical problem that has been continuously addressed in this field. Summary of the Invention

[0004] In view of this, the present application provides a signal trigger output method and a signal trigger output device to solve at least one problem existing in the background art.

[0005] In a first aspect, one embodiment of this application provides a signal-triggered output method, comprising the following steps:

[0006] Obtain the current edge phase value of the first trigger signal;

[0007] Determine whether the current edge phase value of the first trigger signal is stable;

[0008] If the judgment result is stable, a dynamic phase decision threshold is determined based on the edge phase value of the first trigger signal to keep the edge phase value of the first trigger signal between the phase decision thresholds.

[0009] Obtain the real-time edge phase value of the first trigger signal, and determine whether the real-time edge phase value is within the range of the dynamic phase decision threshold;

[0010] If the real-time edge phase value is within the range of the dynamic phase decision threshold, then the real-time edge phase value is determined as the trigger phase value for waveform generation;

[0011] The predetermined signal waveform is output according to the trigger phase value.

[0012] In conjunction with the first aspect of this application, in an optional embodiment, determining the dynamic phase decision threshold that causes the edge phase value of the first trigger signal to be between phase decision thresholds includes:

[0013] Obtain the edge phase value of the first trigger signal relative to the working clock for waveform generation;

[0014] Determine the amount of phase change;

[0015] Based on the edge phase value, a dynamic phase decision threshold is determined according to the phase change.

[0016] In conjunction with the first aspect of this application, in an optional embodiment, the dynamic phase decision threshold includes a high dynamic phase decision threshold and a low dynamic phase decision threshold; wherein, the high dynamic phase decision threshold is equal to the edge phase value plus the phase change amount, and the low dynamic phase decision threshold is equal to the edge phase value minus the phase change amount.

[0017] Secondly, one embodiment of this application provides a signal-triggered output method, comprising the following steps:

[0018] Obtain the current edge phase value of the first trigger signal;

[0019] Determine whether the current edge phase value of the first trigger signal is stable;

[0020] If the judgment result is stable, determine the time delay adjustment level that makes the edge phase value of the first trigger signal between the fixed phase decision thresholds;

[0021] The edge phase of the first trigger signal is adjusted according to the delay adjustment level to obtain the second trigger signal;

[0022] Obtain the real-time edge phase value of the second trigger signal, and determine whether the real-time edge phase value is within the range of the fixed phase decision threshold;

[0023] If the real-time edge phase value is within the range of the fixed phase decision threshold, then the real-time edge phase value is determined as the trigger phase value for waveform generation;

[0024] The predetermined signal waveform is output according to the trigger phase value.

[0025] In conjunction with a second aspect of this application, in an optional embodiment, determining the time delay level that causes the edge phase value of the first trigger signal to be within a fixed phase decision threshold range includes:

[0026] The delay adjustment level is calculated based on the fixed phase decision threshold.

[0027] Based on the time delay adjustment level, the current edge phase of the first trigger signal is adjusted to obtain the second trigger signal;

[0028] Detect the current edge phase of the second trigger signal and determine whether the current edge phase of the second trigger signal is within the fixed phase decision threshold range;

[0029] If the judgment result is negative, the delay adjustment level is redefined, and the delay of the first trigger signal edge phase is adjusted according to the redefined delay adjustment level.

[0030] In conjunction with a second aspect of this application, in an optional embodiment, the step of calculating the delay adjustment level based on the fixed phase decision threshold includes:

[0031] The phase change is determined based on the fixed phase decision threshold.

[0032] The delay adjustment level is determined based on the phase change.

[0033] In conjunction with the second aspect of this application, in an optional embodiment, before obtaining the current phase value of the first trigger signal, the method further includes the following steps: obtaining the trigger mode of the trigger signal; if the trigger mode is an asynchronous trigger mode, then performing the following steps:

[0034] Calculate the phase decision threshold based on the sampling rate during digital-to-analog conversion;

[0035] Obtain the edge phase information of the first trigger signal, and obtain the edge phase value of the first trigger signal according to the phase decision threshold;

[0036] The edge phase value is used as the trigger phase value for waveform generation;

[0037] The predetermined signal waveform is output according to the trigger phase value.

[0038] In conjunction with the second aspect of this application, in an optional embodiment, the step of calculating the phase decision threshold based on the sampling rate during digital-to-analog conversion includes: dividing the working clock period used for waveform generation into N segments according to the working clock period used for digital-to-analog conversion, to obtain N phase decision thresholds, where N is a positive integer.

[0039] In conjunction with the first or second aspect of this application, in an optional embodiment, after the step of controlling the predetermined signal waveform output according to the trigger phase value, the method further includes:

[0040] Repeat the steps of acquiring the real-time edge phase value of the first trigger signal, determining whether the real-time edge phase value is within the dynamic phase decision threshold range, and determining the real-time edge phase value as the trigger phase value for waveform generation if the real-time edge phase value is within the dynamic phase decision threshold range.

[0041] Repeat the steps of acquiring the real-time edge phase value of the second trigger signal, determining whether the real-time edge phase value is within the fixed phase decision threshold range, and determining the real-time edge phase value as the trigger phase value for waveform generation if the real-time edge phase value is within the fixed phase decision threshold range.

[0042] The predetermined signal waveform is continuously controlled and output according to the trigger phase value.

[0043] Thirdly, embodiments of this application provide a signal-triggered output device for executing the above-described signal-triggered output method.

[0044] The signal triggering output method and apparatus provided in this application, by adjusting the phase decision threshold or the delay level of the trigger signal according to the edge phase value of the stable first trigger signal in synchronous triggering mode, so that the edge phase value of the first trigger signal is within the phase decision threshold, greatly improves the accuracy of phase decision, avoids misjudgment, thereby reducing signal output jitter and realizing high-precision signal triggering output.

[0045] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0046] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0047] Figure 1 A schematic diagram illustrating the causes of jitter error in the trigger output signal;

[0048] Figure 2 This is a schematic diagram of a signal triggering output method according to an embodiment of this application;

[0049] Figure 3 This diagram illustrates the phase relationship between the trigger signal and the operating clock of the waveform generation module in synchronous trigger mode. Figure 1 ;

[0050] Figure 4 This is a schematic diagram illustrating the calculation of the dynamic phase decision threshold in one embodiment of this application;

[0051] Figure 5 This is a schematic diagram of a signal triggering output method according to another embodiment of this application;

[0052] Figure 6 This diagram illustrates the phase relationship between the trigger signal and the operating clock of the waveform generation module in synchronous trigger mode. Figure 2 ;

[0053] Figure 7 This is a schematic diagram of the calculation delay adjustment level in one embodiment of this application;

[0054] Figure 8a , Figure 8b This is a schematic diagram of the synchronous trigger mode signal triggering output result according to an embodiment of this application;

[0055] Figure 9 This is a schematic diagram of the asynchronous triggering mode phase decision threshold calculation in one embodiment of this application;

[0056] Figure 10 This is a schematic diagram of the asynchronous trigger mode signal triggering output result according to an embodiment of this application;

[0057] Figure 11 This is a flowchart of a trigger output method according to an embodiment of this application;

[0058] Figure 12 This is a schematic diagram of a trigger output device according to an embodiment of this application;

[0059] Figure 13 This is a schematic diagram of a trigger output device according to another embodiment of this application;

[0060] Figure 14 This is a schematic diagram of a trigger output device according to another embodiment of this application;

[0061] Figure 15 This is a schematic diagram of a trigger output device according to another embodiment of this application;

[0062] Figure 16 This is a schematic diagram of an electronic device in one embodiment of this application. Detailed Implementation

[0063] To make the technical solutions and beneficial effects of this application more apparent and understandable, the technical solutions in the embodiments of this application are clearly and completely described below by listing specific examples. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0064] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0065] It is understood that the terms “first,” “second,” etc., as used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor. When “first” is described, it does not imply the necessary presence of a “second”; and when “second” is discussed, it does not imply the necessary presence of a first element, component, region, layer, or portion. As used herein, the singular forms “a,” “an,” and “the” may also be intended to include the plural forms unless the context clearly indicates otherwise. “A plurality” means two or more, unless otherwise explicitly specified. It should also be understood that the term “comprising,” when used in this specification, identifies the presence of the stated feature but does not exclude the presence or addition of one or more other features. As used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0066] It is understood that in the context of this application, "connection" means that there is an electrical signal or data transmission between the connected end and the connected end, which can be understood as "electrical connection", "communication connection", etc. In the context of this application, "A and B are directly connected" means that there are no other components between A and B except for wires.

[0067] Instruments with waveform generation capabilities include various signal sources such as function generators, arbitrary waveform generators, radio frequency and microwave signal generators, analog signal generators, vector signal generators, and digital code generators. Common waveform generation technologies include Direct Digital Synthesis (DDS), programmable output, Direct Memory Access (DMA) output, and variable clock counter addressing. These instruments consist of a waveform generation module and a digital-to-analog converter (DAC) module. Both modules have their own operating clocks, which are generated based on the same reference clock. The DAC module's operating clock is equal to the reference clock, while the waveform generation module's clock is obtained after frequency division. The waveform generation module outputs a signal waveform under the control of a trigger signal.

[0068] Trigger modes include synchronous trigger mode (SYNC) and asynchronous trigger mode (ASYNC). In synchronous trigger mode, the trigger signal generation unit / device and the waveform generation unit / device share the same reference clock, and the clock generating the trigger signal and the operating clock of the waveform generation module are integer multiples of each other. In this case, the generated trigger signal and the operating clock of the waveform generation module have a stable phase relationship. After the test system is set up and powered on, the trigger signal edge will stably appear at a fixed phase within the operating clock cycle of the waveform generation module. If the test system undergoes hardware changes, such as replacing the trigger signal cable or the reference clock cable, and then powering on and restarting, the trigger signal may stably appear at a different phase within the operating clock cycle of the waveform generation module. In asynchronous trigger mode, the clock of the trigger signal unit / device and the operating clock of the waveform generation unit / device are unrelated. Therefore, the rising edge of the trigger signal may fall at any point on the operating clock of the waveform generation unit / device.

[0069] The inventors discovered that the main reason for the large jitter error in the trigger output signal is that the input trigger signal may fall into any position of the operating clock (sampling clock) of the digital-to-analog converter module. When the edge of the trigger signal is at the critical point of the decision threshold, the jitter of the trigger signal, superimposed on the jitter, can easily cause a phase decision error, that is, at least one sampling period of hard decision error. This decision error will cause the output signal to have jitter of at least one sampling period. Figure 1 As shown, the rising edge of the trigger signal and the phase decision threshold are perfectly aligned, so it is possible for the signal to be judged as either Sample n or Sample n+1. If we add the jitter of the trigger signal itself and the jitter introduced by the hardware comparator circuit, the jitter may even exceed two sampling periods.

[0070] For scenarios where a synchronous clock system can be constructed, the Synchronous Trigger Mode (SYNC) is employed. This mode dynamically adjusts the phase decision threshold or the delay level of the high-precision delay circuit to stably identify the phase edge information of the trigger signal, reducing the jitter of the SYNC trigger output to within 30ps. Furthermore, this mode can adapt to external trigger phase changes; for example, if the user replaces the trigger signal line, the SYNC detection mode will automatically recognize the external phase change to readjust and lock the phase decision threshold.

[0071] This application provides a signal trigger output method to reduce trigger jitter in a synchronous triggering environment. See also... Figure 2 The method includes the following steps:

[0072] S110, Obtain the current edge phase value of the first trigger signal. The first trigger signal is a timing signal, and its edge phase value changes with changes in hardware status or operating environment. The first trigger signal can be the initial trigger signal or a signal obtained by sampling or processing the initial trigger signal. A phase detection module is used to obtain the current edge phase information of the first trigger signal and the operating clock of the waveform generator, thereby obtaining the edge phase value of the first trigger signal relative to the operating clock of the waveform generator. A high-precision phase detection module is preferred, with a detection accuracy of up to 10 ps.

[0073] S120: Determine whether the current edge phase value of the first trigger signal is stable. Based on the determination result, select whether to calculate the dynamic phase threshold. The phase detection module continuously detects the edge phase value of the first trigger signal, obtaining multiple edge phase values ​​over a period of time. Statistical analysis is performed on the detected edge phase values ​​to determine their stability. When the changes in multiple edge phase values ​​are very small and all within a predetermined range, the phase value of the first trigger signal is considered stable. When the changes in multiple edge phase values ​​are large and exceed the predetermined range, the phase value of the first trigger signal is considered unstable. If the first trigger signal phase is determined to be unstable, the phase value can be stabilized by adjusting the hardware or setting hardware parameters, and the process returns to step S110. If the first trigger signal phase is determined to be stable, proceed to step S130.

[0074] S130, if the judgment result is stable, a dynamic phase decision threshold is calculated based on the edge phase value of the stable first trigger signal to keep the edge phase value of the stable first trigger signal within the phase decision threshold range. By keeping the edge phase of the first trigger signal within the phase decision threshold range, the phase decision error is reduced, thereby reducing trigger jitter.

[0075] See Figures 3-4 The step of calculating the dynamic phase decision threshold that keeps the edge phase value of the stable first trigger signal within the phase decision threshold range based on the edge phase value of the stable first trigger signal further includes the following steps:

[0076] S131: Obtain the stable edge phase value of the first trigger signal relative to the waveform generation clock. For synchronous triggering, the clock generating the input trigger signal has a fixed phase difference with the operating clock of the waveform generation module. Due to transmission distance, impedance, and other factors, the edge phase of the input trigger signal has a certain time delay relative to the operating clock that generates the input trigger signal. Knowing the clock that generates the first trigger signal and the edge phase value of the trigger signal detected by the phase detection module, the edge phase value of the first trigger signal relative to the operating clock of the waveform generation module can be obtained.

[0077] S132, determine the phase change. Based on the phase change, obtain the dynamic phase decision threshold range. The dynamic phase decision threshold includes a high phase decision threshold and a low phase decision threshold. The difference between the two is the dynamic phase decision threshold range. High phase decision threshold T 12 This refers to the rising edge phase decision threshold. The low-phase decision threshold T... 11 This refers to the falling edge phase decision threshold. Different phase changes Δt1' and Δt1" are selected above and below the phase value of the first trigger signal edge, respectively. The dynamic phase decision threshold range is then Δt1' + Δt1". This ensures that the stable trigger signal edge phase is always between the high and low phase decision thresholds. The phase change amount is determined based on the specific application.

[0078] Optionally, the same phase change amount Δt1 can be selected above and below the edge phase value, resulting in a dynamic phase decision threshold range of 2Δt1. The phase change amount Δt1 is selected based on the actual application. This ensures that the stable trigger signal edge phase is always located between the high and low phase decision thresholds. The "middle" refers to the median value of the difference between the high and low phase decision thresholds.

[0079] S133, using the phase value of the first trigger signal edge as a reference, determine the high / low dynamic phase decision threshold based on the phase change. Optionally, the high / low phase decision threshold can be a single value. The high / low phase decision threshold is obtained after determining the range of the high / low phase decision threshold. When different phase change amounts Δt1' and Δt1” are selected above and below the edge phase value, respectively, the high phase decision threshold T... 12 =t0 + Δt1'. Low-phase decision threshold T 11 =t0-Δt1”. When the same phase change Δt1 is selected above and below the edge phase value, the high phase decision threshold T 12 = t0 + Δt1. Low-phase decision threshold T 11 = t0 - Δt1.

[0080] To improve the robustness of phase decision, preferably, both the high and low dynamic phase decision thresholds are ranges, rather than single values. When the edge phase value of the trigger signal falls within the range of the high and low dynamic phase decision thresholds, it indicates that the edge of the trigger signal is about to approach the critical point of the phase decision threshold. At this time, the phase decision threshold can be adjusted immediately to avoid phase decision errors and reduce trigger signal jitter.

[0081] Optionally, the high / low dynamic phase decision threshold range is determined based on the operating clock cycle of the waveform generation module. For example... Figure 3 As shown, the low-phase decision threshold T 11 Let T1 / 2, where T1 is the operating clock period of the waveform generation module. Then the high-phase decision threshold T... 12 =T1 / 2-2Δt1. High-phase decision threshold T12 and low phase decision threshold T 11 This is an absolute value relative to the operating clock cycle of the waveform generation module.

[0082] Optionally, the high / low dynamic phase decision threshold range is determined based on the sampling period during digital-to-analog conversion and the operating clock of the waveform generation module. The operating clock period of the waveform generation module is divided into N segments according to the operating clock period (sampling period) of the digital-to-analog conversion module. For example, ... Figure 3 As shown, N = 16. Low-phase decision threshold T 11 =T1 / N. High-phase decision threshold T 12 =2Δt1+T1 / N.

[0083] S134, Lock the high and low dynamic phase decision thresholds. After ensuring that the current stable trigger signal edge phase is in the middle of the high and low phase decision thresholds by calculating the high and low dynamic phase decision thresholds, lock the calculated phase decision thresholds and enter the synchronous trigger signal detection mode to detect whether a trigger signal has been acquired.

[0084] S140: Obtain the real-time edge phase value of the first trigger signal and determine whether the real-time edge phase value is within the dynamic phase decision threshold range. After the phase decision threshold is determined, formally enter the synchronous trigger signal detection mode. Continue to receive the edge phase information of the first trigger signal to obtain the real-time edge phase value of the first trigger signal. Determine whether the real-time edge phase value is within the dynamic phase decision threshold range, and select whether to send the edge phase value of the trigger signal to the waveform generation module based on the determination result. By comparing the real-time edge phase value with the dynamic phase decision threshold, it can be determined whether the real-time edge phase value is within the phase decision threshold range. If the real-time edge phase value is within the phase decision threshold range, proceed to step S150. If the real-time edge phase value is not within the phase decision threshold range, re-enter step S110.

[0085] S150, if the real-time edge phase value of the first trigger signal is within the phase decision threshold, then the real-time edge phase value is determined as the trigger phase value for waveform generation.

[0086] S160 controls the generation of a predetermined waveform based on the trigger phase value. When the real-time edge phase value of the first trigger signal is between the high and low phase decision thresholds, it is considered that the trigger signal has been correctly acquired. At this time, the real-time edge phase value of the first trigger signal is sent to the waveform generator to control the generation of the predetermined waveform. When the acquired real-time edge phase value of the first trigger signal is not between the dynamic phase decision thresholds, it is considered that the external trigger signal may have changed, such as the user changing the trigger cable, causing a large change in the phase delay of the trigger signal. At this time, it is necessary to pause the transmission of the trigger signal phase information to the waveform generator and re-enter step S110.

[0087] S170, repeat steps S140 to S160 to continuously control waveform generation.

[0088] If the instrument does not integrate a high-precision delay adjustment circuit, or the delay adjustment range of the high-precision delay adjustment circuit is insufficient, then the dynamic adjustment of the phase decision threshold should be selected. Based on the phase relationship between the edge phase of the trigger signal and the phase of the operating clock of the waveform generation module, the high and low phase decision thresholds are dynamically calculated, which can accurately acquire the trigger signal and reduce the jitter of the signal source trigger output.

[0089] If the instrument integrates a high-precision delay adjustment circuit, the trigger signal edge phase delay can be adjusted. In this case, the phase decision threshold is a fixed, known quantity, called the fixed phase decision threshold. By adjusting the setting of the high-precision delay circuit, the trigger signal edge phase is adjusted to the middle of the high and low fixed phase decision thresholds, allowing for stable acquisition of external trigger signals. Simultaneously, it is necessary to continuously monitor whether the trigger signal edge phase exceeds the high and low fixed phase decision thresholds. If it falls outside these thresholds, the high-precision delay module setting should be readjusted to bring the trigger signal edge back within the high and low fixed phase decision threshold range.

[0090] Another embodiment of this application provides a signal trigger output method for reducing trigger jitter in a synchronous triggering environment. See also Figure 5 The method includes the following steps:

[0091] S210, Obtain the current edge phase value of the first trigger signal. The first trigger signal is a timing signal, and its edge phase value changes with changes in hardware status or operating environment. The first trigger signal can be the initial trigger signal or a signal obtained by sampling or converting the initial trigger signal. A phase detection module is used to obtain the current edge phase information of the first trigger signal and the operating clock of the waveform generator, thereby obtaining the edge phase value of the first trigger signal relative to the operating clock of the waveform generator. A high-precision phase detection module is preferred, with a detection accuracy of up to 10 ps.

[0092] S220: Determine whether the current edge phase value of the first trigger signal is stable. Based on the determination result, select whether to calculate the delay adjustment level. The phase detection module continuously detects the edge phase value of the first trigger signal, obtaining multiple edge phase values ​​over a period of time. Statistical analysis is performed on the detected edge phase values ​​to determine their stability. When the changes in multiple edge phase values ​​are very small and all within a predetermined range, the phase value of the first trigger signal is considered stable. When the changes in multiple edge phase values ​​are large and exceed the predetermined range, the phase value of the first trigger signal is considered unstable. If the first trigger signal phase is determined to be unstable, the phase value of the first trigger signal can be stabilized by adjusting hardware or setting hardware parameters, and the process returns to step S210. If the first trigger signal phase is determined to be stable, proceed to step S230.

[0093] S230, if the judgment result is stable, determine the time delay adjustment level so that the edge phase value of the stable first trigger signal is within the fixed phase decision threshold. By keeping the edge phase of the first trigger signal within the fixed phase decision threshold, the phase decision error is reduced, thereby reducing trigger jitter.

[0094] See Figures 6-7 The step of determining the delay adjustment level that makes the edge phase value of the stable first trigger signal fall within the fixed phase decision threshold further includes the following steps:

[0095] S231, calculate the delay adjustment level based on the high and low fixed phase decision thresholds, so that the current edge phase of the first trigger signal is between the high and low phase decision thresholds. When the delay adjustment level is used to ensure that the edge phase value of the first trigger signal is between the phase decision thresholds, the phase decision thresholds are fixed and known quantities, called high and low fixed phase decision thresholds. High and low fixed phase decision thresholds include the high fixed phase decision threshold and the low fixed phase decision threshold. Figure 6This diagram illustrates the phase relationship between the input trigger signal and the operating clock of the waveform generation module. For synchronous triggering, the clock generating the trigger signal and the operating clock of the waveform generation module have a fixed phase difference. Due to transmission distance, impedance, and other factors, the edge phase of the input trigger signal has a certain time delay relative to the clock generating the trigger signal. Therefore, the edge phase of the input trigger signal also has a definite time delay relative to the operating clock of the waveform generation module. The phase detection module can detect the edge phase value of the input trigger signal relative to the operating clock of the waveform generation module.

[0096] like Figure 7 As shown, based on the high fixed phase decision threshold T 22 and low fixed phase decision threshold T 21 The difference determines the phase change Δt2, Δt2=(T 21 -T 22 ) / 2. High fixed-phase decision threshold T 21 and low fixed phase decision threshold T 22 This is an absolute value relative to the operating clock cycle of the waveform generation module. The phase value t0 of the input trigger signal's edge is detected by the phase detection module. Therefore, the delay adjustment amount ΔT of the input trigger signal is ΔT = t0 + Δt - T. 22 -Δt2, where Δt is the phase difference between the edge phase of the input trigger signal and the operating clock of the waveform generation module. The time delay adjustment ΔT calculated above ensures that the stable edge phase of the first trigger signal is always located in the middle of the high and low fixed phase decision thresholds. The middle refers to the median value of the difference between the edge phase values ​​and the high and low fixed phase decision thresholds.

[0097] Optionally, the phase change Δt2 is the high / low fixed phase decision threshold T. 21 T 22 A value between the differences, rather than T 21 T 22 The median of the difference is used to obtain the time delay adjustment ΔT, which ensures that the stable trigger signal edge phase time is within the fixed phase decision threshold range.

[0098] The delay adjustment level is determined based on the delay adjustment amount. Optionally, the delay adjustment level is equal to the delay adjustment amount. A delay adjustment circuit is used to adjust the phase of the trigger signal edge. A high-precision delay adjustment circuit with a delay adjustment accuracy of 3ps is preferred. Optionally, the delay adjustment level is a series of adjustment steps. The adjustment step size is determined based on the numerical range of the calculated delay adjustment amount. For example, if the delay adjustment levels are 5ps, 10ps, and 15ps, and the calculated delay adjustment amount is 3ps, then since the minimum adjustment level is 5ps, the delay adjustment level of 5ps is selected. If the calculated delay adjustment amount is 7ps, 7ps is greater than 5ps and less than 10ps, then the delay adjustment level of 10ps is selected. Optionally, when determining the delay adjustment level, starting with the minimum adjustment step size, a series of adjustment steps are selected sequentially to adjust the phase of the first trigger signal edge until a suitable delay adjustment level is found.

[0099] S232 adjusts the delay of the current edge phase of the first trigger signal according to the calculated delay adjustment level to obtain the second trigger signal. The delay adjustment circuit adjusts the edge phase of the first trigger signal to obtain the second trigger signal after edge phase adjustment. The delay adjustment circuit uses a high-precision hardware delay adjustment circuit with a delay adjustment accuracy of 3ps.

[0100] S233: Detect the current edge phase of the second trigger signal and determine whether its current edge phase is within the fixed phase decision threshold. Based on the determination result, determine whether to recalculate the delay adjustment level and adjust the edge phase of the first trigger signal. If the current edge phase of the second trigger signal is within the fixed phase decision threshold, it indicates that the delay adjustment of the first trigger signal is correct, and proceed to step S240. If the edge phase of the second trigger signal is not within the fixed phase decision threshold, it indicates that the edge phase of the input first trigger signal has changed, causing the calculated delay adjustment level to be inapplicable to the first trigger signal with a changed edge phase. The edge phase of the second trigger signal after delay adjustment is outside the fixed phase decision threshold. The delay adjustment level needs to be recalculated for the changed first trigger signal so that the adjusted edge phase of the second trigger signal falls back within the high / low phase decision threshold range. Repeat steps S231 to S233 until the current trigger signal edge phase is in the middle or between the fixed phase decision thresholds.

[0101] S240, the first trigger signal is adjusted according to the time delay adjustment level to obtain the second trigger signal. The phase of the edge of the first trigger signal is adjusted using a time delay adjustment circuit to obtain the second trigger signal. A high-precision time delay adjustment circuit is preferred, with a time delay adjustment accuracy of 3ps.

[0102] S250: Obtain the real-time edge phase value of the second trigger signal and determine whether the real-time edge phase value is within the fixed phase decision threshold. After the phase decision threshold is determined, the synchronous trigger signal detection mode is officially entered. Continue to obtain the real-time edge phase information of the second trigger signal to obtain the real-time edge phase value of the first trigger signal. Determine whether the real-time edge phase value is within the high and low phase decision thresholds, and select whether to send the edge phase value of the trigger signal to the waveform generation module based on the determination result. By comparing the real-time edge phase value with the high and low phase decision thresholds, it can be determined whether the real-time edge phase value is within the fixed phase decision threshold range. If the real-time edge phase value is not within the fixed phase decision threshold range, proceed to step S210. If the phase value is within the dynamic phase decision threshold range, proceed to step S260.

[0103] S260, if the real-time edge phase value is within the fixed phase decision threshold, then the real-time edge phase value is used as the trigger phase value for waveform generation.

[0104] S270: Control the predetermined waveform generation based on the trigger phase value. When the real-time edge phase value of the first trigger signal is between the high and low phase decision thresholds, it is considered that the trigger signal has been correctly acquired. At this time, the real-time edge phase value of the first trigger signal is sent to the waveform generation module to control the predetermined waveform generation. When the acquired real-time edge phase value of the first trigger signal is not between the dynamic phase decision thresholds, it is considered that the external trigger signal may have changed, such as the user changing the trigger cable, causing a large change in the trigger signal phase delay. At this time, it is necessary to pause the transmission of the trigger signal phase information to the waveform generation module and re-enter step S210.

[0105] Optionally, the waveform generation module is implemented using a Field Programmable Gate Array (FPGA). The operating clock of the waveform generation module is the same as that of the FPGA. Optionally, the waveform generation module is implemented using technologies such as Direct Digital Synthesis (DDS), programmable output, Direct Memory Access (DMA) output, and variable clock counter addressing.

[0106] S280, repeat steps S250 to 270 to continuously control waveform generation.

[0107] The signal output results of the synchronous trigger mode in the embodiments of this application are as follows: Figure 8a , Figure 8b As shown. Figure 8a The signal includes two waveforms, ① and ②. Waveform ① is the input trigger signal, and waveform ② is the trigger output signal. Figure 8b The waveform includes two waveforms, ③ and ④. Waveform ③ is the input trigger signal, and waveform ④ is the trigger output signal. Figure 8a , Figure 8b The horizontal axis represents time, in microseconds (μs), and the vertical axis represents amplitude, in millivolts (mV).

[0108] As can be seen from the figure, the above-mentioned synchronous trigger mode (SYNC) of this application effectively reduces the jitter of the signal trigger output, and the jitter of the trigger output is reduced to less than 30ps.

[0109] Optionally, before step S110, step S010 is included to obtain the trigger mode of the trigger signal. The trigger mode includes synchronous trigger mode (SYNC) and asynchronous trigger mode (ASYNC). The method of obtaining the trigger mode can be determined by receiving a trigger mode selection signal input by the user. If the trigger mode is synchronous trigger mode (SYNC), then proceed to step S110 or step S210. Synchronous trigger mode is suitable for synchronous trigger environments and situations where high trigger jitter accuracy is required. The jitter of the trigger output signal can be reduced to within 30ps. If the trigger mode is asynchronous trigger mode (ASYNC), then proceed to step S310. Asynchronous trigger mode (ASYNC) is suitable for any trigger environment and situations where trigger jitter accuracy is relatively low. The jitter of the trigger output signal can be reduced to 500ps.

[0110] S310 calculates the phase decision threshold based on the sampling rate during digital-to-analog conversion (DAC). The sampling rate during DAC is the reciprocal of the DAC module's operating clock. Both the waveform generation module and the DAC module's operating clocks are generated based on the same reference clock. The DAC module's operating clock is equal to the reference clock, while the waveform generation module's operating clock is obtained by dividing the reference clock. The operating clock period used for waveform generation is divided into N equal segments according to the DAC's operating clock period (sampling period), resulting in N phase decision thresholds, where N is a positive integer. These thresholds are used to further refine the determination of the sampling time corresponding to the rising edge of the trigger signal, so as to trigger the DAC signal output based on the sampling time corresponding to the rising edge.

[0111] For example, N=16, such as Figure 9 As shown, the working clock cycle of each waveform generation module is divided into 16 equal parts, resulting in 16 phase decision thresholds.

[0112] S320: Acquire the phase information of the first trigger signal edge and obtain the trigger signal edge phase value according to the phase decision threshold. A phase detection module is used to detect the trigger signal edge phase information. A high-precision phase detection module is preferred, with a detection accuracy of 10 ps. Determining the trigger signal edge phase value according to the phase decision threshold means determining which of the N phase decision thresholds the trigger signal edge falls on. Since the phase decision thresholds are divided according to the operating clock of the digital-to-analog converter, when the phase decision threshold of the trigger signal edge is determined, the sampling time of the digital-to-analog converter at which the trigger signal edge is located can be known, thus further refining the determination of the trigger signal edge phase value. This process is called hard decision.

[0113] S330 uses the edge phase value of the obtained trigger signal as the trigger phase value for waveform generation to control the waveform output. After obtaining the sampling time of the digital-to-analog converter corresponding to the edge of the trigger signal, the digital-to-analog converter signal output can be triggered accordingly.

[0114] For the asynchronous trigger mode (ASYNC), a higher-precision phase decision threshold is obtained by dividing the operating clock period of the waveform generation module into multiple phase decision thresholds according to the sampling clock period of the digital-to-analog converter. Simultaneously, combined with a high-precision phase detection module, the decision accuracy of the trigger signal edge phase is effectively improved, resulting in a signal output as follows: Figure 10 As shown. Figure 10 The horizontal axis represents time in microseconds (μs), and the vertical axis represents amplitude in millivolts (mV). This includes two waveforms, ⑤ and ⑥. Waveform ⑥ is the input trigger signal, and waveform ⑤ is the trigger output signal. As can be seen from the figure, the asynchronous trigger mode (ASYNC) of this application effectively reduces the jitter of the signal trigger output, with jitter as low as 400 ps.

[0115] Figure 8b and Figure 10 The horizontal axis in the image is displayed in microseconds, while the time variation of the waveform is on the order of picoseconds. The display range is much larger than the time variation of the waveform, so the time variation of the waveform is not shown, and its horizontal axis value is the same.

[0116] The workflow of a signal triggering method according to an embodiment of this application is as follows: Figure 11 As shown:

[0117] After activating the trigger function, first configure the trigger signal comparison circuit, configure the high-precision delay adjustment module, and configure the high-precision phase detection module. Then determine whether the trigger mode is synchronous or asynchronous.

[0118] In asynchronous trigger mode, the phase decision threshold is calculated based on the sampling rate during digital-to-analog conversion. Next, it is determined whether the edge phase information of the trigger signal has been acquired. If the edge phase information is not acquired, it is acquired again. If it is acquired, a hard decision is made on the edge phase information of the trigger signal to obtain the trigger phase value, which is then sent to the waveform generation module to control the waveform output; this process continues to continuously control the waveform output.

[0119] If it is in synchronous trigger mode, the phase value of the current first trigger signal is acquired and statistically analyzed. It is then determined whether the phase value of the current first trigger signal is stable. If unstable, the instrument is adjusted, and the acquisition, statistical analysis, and determination are repeated. If stable, further determination is made to choose between adjusting the phase delay (delay adjustment mode) or adjusting the phase decision threshold.

[0120] If the phase decision threshold is adjusted, the real-time phase value of the first trigger signal is acquired, and then it is determined whether it falls within the phase decision threshold range. If so, the real-time phase value of the first trigger signal is sent as the trigger phase value to the waveform generation module to control the waveform output. The real-time phase value of the first trigger signal and subsequent judgment steps are continuously acquired to continuously control the waveform output. If not, it indicates that the first trigger signal has changed, such as when the user replaces the cable, and the stability of the phase value of the first trigger signal needs to be re-determined, and subsequent steps need to be followed.

[0121] If phase delay adjustment (delay adjustment mode) is selected, the delay adjustment level is calculated, and a high-precision delay adjustment circuit is configured to adjust the edge phase of the first trigger signal to obtain the second trigger signal. Then, it is determined whether the edge phase of the second trigger signal is within the fixed phase decision threshold. If yes, the real-time phase value of the first trigger signal and subsequent steps are obtained. If no, it indicates that the edge phase of the second trigger signal exceeds the high and low phase thresholds. In this case, the delay adjustment level is recalculated, and the high-precision delay adjustment circuit is configured to readjust the edge phase of the first trigger signal. Thus, by constantly monitoring whether the phase of the trigger signal exceeds the high and low phase thresholds, if it falls outside the thresholds, the level of the high-precision delay module should be adjusted again to bring the trigger signal edge back within the high and low threshold range.

[0122] Another embodiment of this application provides a signal-triggered output device, see [link to relevant documentation] Figure 12 It includes: a waveform generator, a phase detection module, a phase decision module, and an adaptive calculation module.

[0123] A waveform generator is used to control waveform generation based on the operating clock and the phase value of the trigger signal edge. Optionally, the waveform generator is implemented using a field-programmable gate array (FPGA). The operating clock of the waveform generator is the same as the operating clock of the FPGA.

[0124] The phase detection module acquires the current edge phase information of the first trigger signal and the operating clock of the waveform generator, and detects the edge phase value of the first trigger signal relative to the operating clock of the waveform generator. This phase value is then output to the adaptive calculation module and the phase decision module. The phase detection module employs a high-precision phase detection module with a detection accuracy of up to 10 ps.

[0125] An adaptive calculation module is used to determine whether the current edge phase value of the first trigger signal is stable; and based on the stable edge phase value of the first trigger signal, to calculate the dynamic phase decision threshold that makes the edge phase value of the stable first trigger signal fall between the phase decision thresholds.

[0126] The phase decision module is used to acquire the real-time edge phase value and dynamic phase decision threshold of the first trigger signal, and determine whether the real-time edge phase value is within the dynamic phase decision threshold. If the real-time edge phase value is within the phase decision threshold, it is sent to the generator to control the generation of a predetermined waveform. The module continuously acquires the real-time edge phase value and dynamic phase decision threshold of the first trigger signal, determines whether the real-time edge phase value is within the dynamic phase decision threshold, and if so, sends it to the waveform generator to continuously control waveform generation.

[0127] Another embodiment of this application provides a signal-triggered output device, see [link to relevant documentation] Figure 13 It includes: a waveform generator, a phase detection module, a phase decision module, a time delay adjustment circuit, and an adaptive calculation module.

[0128] A waveform generator is used to control waveform generation based on the operating clock and the phase value of the trigger signal edge. Optionally, the waveform generator is implemented using a field-programmable gate array (FPGA). The operating clock of the waveform generator is the same as the operating clock of the FPGA.

[0129] The phase detection module is used to acquire the current edge phase value of the first trigger signal. This phase value is then output to the adaptive calculation module and the phase decision module. A high-precision phase detection module with a detection accuracy of up to 10 ps is preferred.

[0130] The adaptive calculation module is used to determine whether the current edge phase value of the first trigger signal is stable; and to calculate the delay adjustment level that makes the edge phase value of the stable first trigger signal fall within the fixed phase decision threshold according to the fixed phase decision threshold.

[0131] The delay adjustment circuit is used to adjust the first trigger signal according to the delay adjustment level to obtain the second trigger signal. Preferably, the delay adjustment circuit is a high-precision delay adjustment circuit with a delay adjustment accuracy of 3 ps.

[0132] The phase decision module is used to acquire the real-time edge phase value of the second trigger signal and determine whether the real-time edge phase value is within a fixed phase decision threshold. If the real-time edge phase value is within the fixed phase decision threshold, it is used as the trigger phase value for waveform generation to control the generation of a predetermined waveform. The module continuously acquires the real-time edge phase value of the second trigger signal and determines whether it is within a fixed phase decision threshold. If the real-time edge phase value is within a dynamic phase decision threshold, it sends the real-time edge phase value to the waveform generator to continuously control waveform generation.

[0133] Optional, see Figures 13-14 The aforementioned device further includes a trigger signal comparison circuit, used to receive the input initial trigger signal, adjust the high and low levels of the initial trigger signal according to a preset trigger level, and output the adjusted first trigger signal. The trigger level can be preset according to actual needs or set by the user. The trigger level includes a high level and a low level, used to determine the high and low level range in the trigger signal. The portion of the initial trigger signal with a high level greater than or equal to the trigger level is set to high, and the portion with a low level less than or equal to the trigger level is set to low. After this adjustment, the first trigger signal is obtained. The first trigger signal is then output.

[0134] For example, during analog-to-digital conversion, it is necessary to determine the voltage levels represented by digital signals "0" and "1". Assuming the initial trigger signal has a maximum amplitude of +10V and a minimum amplitude of -10V, and the user-set trigger level is ±5V, then the portion of the initial trigger signal with an amplitude greater than or equal to +5V is set to a high level, representing the digital signal "1", while the portion with an amplitude less than or equal to -5V is set to a low level, thus obtaining the first trigger signal.

[0135] Since the trigger signal comparison circuit only performs level conversion on the initial trigger signal, the edge phase of the first trigger signal is the same as the phase of the initial trigger signal. Adjusting the edge phase of the first trigger signal is equivalent to adjusting the edge phase of the initial trigger signal.

[0136] Optional, see Figures 14-15 The aforementioned device also includes a multiplexer (MUX) for selecting the trigger mode.

[0137] Specific limitations regarding the signal-triggered output device can be found in the limitations of the signal-triggered output method described above, and will not be repeated here. Each module in the aforementioned signal-triggered output device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independently of the processor in the computer device, or stored in software in the memory of the computer device, so that the processor can call and execute the operations corresponding to each module.

[0138] In one embodiment, a computer device is provided, which may be a server. The computer device includes a processor, memory, and a network interface connected via a system bus. The processor of the computer device provides computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. When the computer program is executed by the processor, it implements the aforementioned signal-triggered output method.

[0139] In one embodiment, a computer device is provided, which may be a terminal. The computer device includes a processor, memory, a communication interface, a display screen, and an input device connected via a system bus. The processor of the computer device provides computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The communication interface of the computer device is used for wired or wireless communication with an external terminal; wireless communication can be achieved through Wi-Fi, carrier networks, NFC (Near Field Communication), or other technologies. When the computer program is executed by the processor, it implements the signal-triggered output method of any of the above embodiments. The display screen of the computer device may be a liquid crystal display screen or an e-ink display screen. The input device of the computer device may be a touch layer covering the display screen, or buttons, a trackball, or a touchpad provided on the casing of the computer device, or an external keyboard, touchpad, or mouse, etc.

[0140] This application also provides an electronic device. Figure 16 The diagram shown is a schematic representation of an electronic device according to an embodiment of this application. The electronic device 600 includes: one or more processors 601 and a memory 602; the memory 602 stores computer-executable instructions; the processor 601 is used to execute the computer-executable instructions to implement the steps in the signal-triggered output method as described in any of the above embodiments.

[0141] The processor 601 may be a central processing unit (CPU) or other form of processing unit with data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device to perform desired functions.

[0142] The memory 602 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 601 may execute the program instructions to implement the steps in the signal-triggered output method of any of the above embodiments and / or other desired functions.

[0143] In one example, the electronic device 600 may also include input devices and output devices, which are interconnected via a bus system and / or other forms of connection mechanism (not shown).

[0144] In addition, input devices may include, for example, a keyboard, a mouse, a microphone, etc. Output devices can output various information to the outside, and may include, for example, a monitor, speakers, a printer, and communication networks and their connected remote output devices, etc.

[0145] Of course, for the sake of simplicity, Figure 15 Only a portion of the components of the electronic device 600 relevant to this application are shown in this illustration, omitting components such as buses, input devices / output interfaces, etc. In addition, the electronic device 600 may include any other suitable components depending on the specific application. In one embodiment, a computer-readable storage medium is provided storing a computer program that, when executed by a processor, implements the steps of the signal-triggered output method of any of the above embodiments.

[0146] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical storage, etc. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc.

[0147] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0148] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A signal triggered output method, characterized by, The method comprises the following steps: obtaining an edge phase value of a first trigger signal relative to a working clock of a waveform generator; determining whether the edge phase value of the first trigger signal is stable; if the determination result is stable, determining a phase variation amount, and determining a dynamic phase determination threshold for making the edge phase value of the first trigger signal between phase determination thresholds according to the phase variation amount and the edge phase value of the first trigger signal; obtaining a real-time edge phase value of the first trigger signal, and determining whether the real-time edge phase value is within the dynamic phase determination threshold range; if the real-time edge phase value is within the dynamic phase determination threshold range, determining the real-time edge phase value as a trigger phase value for waveform generation; controlling a predetermined signal waveform output according to the trigger phase value.

2. The signal trigger output method of claim 1, wherein, The dynamic phase determination threshold comprises a high dynamic phase determination threshold and a low dynamic phase determination threshold; wherein the high dynamic phase determination threshold is equal to the edge phase value plus the phase variation amount, and the low dynamic phase determination threshold is equal to the edge phase value minus the phase variation amount.

3. The signal triggered output method according to any one of claims 1-2, characterized in that, Before the step of obtaining the edge phase value of the first trigger signal relative to the working clock of the waveform generator, the method further comprises the following steps: obtaining a trigger mode of the trigger signal; if the trigger mode is an asynchronous trigger mode, the following steps are performed: calculating a phase determination threshold according to a sampling rate during digital-to-analog conversion; obtaining the edge phase value of the first trigger signal according to the phase determination threshold; determining the edge phase value as a trigger phase value for waveform generation; controlling a predetermined signal waveform output according to the trigger phase value.

4. The signal trigger output method of claim 3, wherein, The step of calculating the phase determination threshold according to the sampling rate during digital-to-analog conversion comprises: dividing a working clock period used for waveform generation into N segments according to a working clock period used for digital-to-analog conversion, to obtain N phase determination thresholds, wherein N is a positive integer.

5. The signal triggered output method according to any one of claims 1-2, wherein, After the step of controlling the predetermined signal waveform output according to the trigger phase value, the method further comprises: repeating the steps of obtaining a real-time edge phase value of the first trigger signal, determining whether the real-time edge phase value is within the dynamic phase determination threshold range, and determining the real-time edge phase value as a trigger phase value for waveform generation if the real-time edge phase value is within the dynamic phase determination threshold range; continuously controlling the predetermined signal waveform output according to the trigger phase value.

6. A signal-triggered output method, characterized by, The method comprises the following steps: obtaining an edge phase value of a first trigger signal relative to a working clock of a waveform generator; determining whether the edge phase value of the first trigger signal is stable; if the determination result is stable, determining a phase variation amount according to a fixed phase determination threshold, and determining a time delay adjustment gear for making the edge phase value of the first trigger signal within a fixed phase determination threshold range according to the phase variation amount; adjusting the edge phase of the first trigger signal according to the time delay adjustment gear to obtain a second trigger signal; obtaining a real-time edge phase value of the second trigger signal, and determining whether the real-time edge phase value is within the fixed phase determination threshold range. if the real-time edge phase value is within the fixed phase decision threshold range, the real-time edge phase value is determined as a trigger phase value of waveform generation; a predetermined signal waveform is output according to the trigger phase value.

7. The signal triggered output method according to claim 6, wherein The method further comprises the following steps before the step of obtaining the edge phase value of the first trigger signal relative to the working clock of the waveform generation: calculating a phase decision threshold according to a sampling rate during digital-to-analog conversion; obtaining edge phase information of the first trigger signal, and obtaining the edge phase value of the first trigger signal according to the phase decision threshold; determining the edge phase value as a trigger phase value of waveform generation; outputting a predetermined signal waveform according to the trigger phase value.

8. The signal triggered output method according to any of claims 6-7, characterized by, The step of calculating the phase decision threshold according to the sampling rate during digital-to-analog conversion comprises the following steps: dividing a working clock cycle used for waveform generation into N segments according to a working clock cycle used for digital-to-analog conversion, to obtain N phase decision thresholds, wherein N is a positive integer. The method further comprises the following steps after the step of outputting the predetermined signal waveform according to the trigger phase value: repeating the steps of obtaining the real-time edge phase value of the second trigger signal, judging whether the real-time edge phase value is within the fixed phase decision threshold range, and determining the real-time edge phase value as a trigger phase value of waveform generation if the real-time edge phase value is within the fixed phase decision threshold range; continuously outputting a predetermined signal waveform according to the trigger phase value.

9. The signal triggered output method according to claim 8, wherein, A device for performing the signal trigger output method of any one of claims 1 to 10.

10. The signal triggered output method according to any one of claims 6-7, characterized by, A device for performing the signal trigger output method of any one of claims 1 to 10. ​ ​ 11. A signal triggered output device, characterized by ​

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