Semiconductor memory device and method

Abstract

Embodiments provide a semiconductor memory device and method capable of reducing the amount of data that needs to be held in advance in a memory controller as much as possible without compromising data reliability. The circuit of the semiconductor memory device of the embodiments sets the threshold voltages of a plurality of memory cells in a manner that two first distributions are formed in a first interval on the lowest voltage side among two intervals. N After that, the circuit sets the threshold voltages of the plurality of memory cells in a manner that two second distributions are formed separately in units of two. (1+M) After that, the circuit sets two third distributions in the two intervals. N N ​​

Description

[0001] Reference to relevant applications

[0002] This application claims priority to Japanese Patent Application No. 2022-019173 (filed on February 10, 2022). This application incorporates the entire contents of the said basic application by reference. Technical Field

[0003] Generally speaking, this embodiment relates to a semiconductor memory device and method. Background Technology

[0004] As a semiconductor memory device, a type of NAND (Notand) flash memory is known, where each memory cell can store a large number of bits of data. In this type of NAND flash memory, there are cases where programming operations for a single memory cell are performed in multiple stages. This series of multi-stage programming operations is called multi-stage programming.

[0005] As an example of multi-stage programming, there is the fuzzy fine programming process. According to the fuzzy fine programming process, all bits of data are coarsely programmed into the first memory cell, then coarsely programmed into the second memory cell adjacent to the first memory cell, and finally finely reprogrammed back into the first memory cell. In other words, the fuzzy fine programming process performs a first-stage programming action of coarsely programming all bits of data into each memory cell, followed by a second-stage programming action of finely reprogramming all bits of data. According to the fuzzy fine programming process, in the second-stage programming action, the shift in the threshold voltage of each memory cell can be reduced, thereby suppressing the decrease in data reliability caused by inter-cell interference.

[0006] However, according to the fuzzy-fine programming approach, from the completion of the first stage programming operation for the first memory cell until the execution of the second stage programming operation for the first memory cell, all the data programmed into the first memory cell needs to be stored in the memory controller. Therefore, a large-capacity buffer memory is required for the memory controller, which is disadvantageous in terms of cost. Summary of the Invention

[0007] The problem to be solved by the present invention is to provide a semiconductor storage device and method that can reduce the amount of data that needs to be pre-stored in the storage controller without compromising data reliability.

[0008] According to this embodiment, the semiconductor memory device includes multiple memory cell groups, multiple first word lines, and circuitry. Each memory cell is configured to store 2... and a set threshold voltage. NN bits of data corresponding to each interval. The plurality of first word lines are respectively connected to any one of the plurality of memory cell groups. The circuit performs a first operation on the plurality of memory cell groups. The first operation includes: for each memory cell, receiving 1 bit of first data from an external source; to... N In the first interval of the lowest voltage side of the interval, two separate first distributions corresponding to the first data are formed, and the threshold voltage of multiple memory cells is set. After the first action for the multiple memory cell groups, the circuit performs a second action for the memory cell group connected to each of the two adjacent second word lines in the multiple first word lines. The second action includes: based on the two first distributions, from the memory cell group connected to the first word line (i.e., the fourth word line) that is more than 3 bits away from one of the two second word lines (i.e., the third word line) in the multiple first word lines, for each memory cell, reading 1 bit of second data; for each memory cell, receiving M bits of third data (where 1+M<N) from the outside; and for each memory cell, to transfer 2 bits of fourth data corresponding to (1+M) bits of the second and third data. (1+M) The second distribution is formed in pairs, and a threshold voltage is set for the multiple memory cells included in the memory cell group connected to the third word line. After the second operation for the memory cell group connected to each of the two second word lines, the circuit performs a third operation for the memory cell group connected to one of the two second word lines, namely the fifth word line. The third operation includes: based on the two first distributions, reading 1 bit of the fifth data from each memory cell from the sixth word line, which is more than 3 words away from the fifth word line among the multiple first word lines; based on the two... (1+M) In the second distribution, for each storage cell, M bits of the sixth data are read from the fifth word line; for each storage cell, (NM-1) bits of the seventh data are received from the outside; and for each storage cell, 2 bits of the eighth data corresponding to the N bits containing the fifth, sixth, and seventh data are distributed. N The third distribution is set in the 2 N A range. Attached Figure Description

[0009] Figure 1 This is a schematic diagram illustrating an example configuration of a semiconductor memory device according to an embodiment.

[0010] Figure 2 This is a diagram illustrating an example of the circuit configuration of block BLK in an implementation method.

[0011] Figure 3 This is a diagram illustrating a more detailed circuit configuration of a first memory group MG used to explain the implementation method.

[0012] Figure 4 This diagram shows an example of the planar layout of the memory cell array in an embodiment, focusing on the selection of gate lines SGDa0~a2 and SGDb0~b2.

[0013] Figure 5 This is a diagram showing an example of the planar layout of a memory cell array in an implementation method, focusing on word lines WLa and WLb.

[0014] Figure 6 It is along Figure 5 A cross-sectional view of a storage cell array according to an implementation of the VI-VI line.

[0015] Figure 7 This is a diagram showing the voltage applied to multiple word lines WL connected to a first memory group MG during the read operation of an embodiment.

[0016] Figure 8 This is a diagram illustrating an example of multiple distributions of threshold voltages formed during programming operations in a semiconductor memory device according to a QLC (Quad-Level Cell) configuration.

[0017] Figure 9 This is a schematic diagram illustrating the change in the threshold voltage distribution of the multi-stage programming action that constitutes the implementation method.

[0018] Figure 10 It means that it is able to perform Figure 9 The diagram shows an example of the coding of an implementation of a multi-stage programming action.

[0019] Figure 11 This is a diagram illustrating an example of the execution sequence of the programming operations in the first stage of an embodiment of a semiconductor memory device.

[0020] Figure 12 This is a flowchart illustrating an example of a series of processes performed by a semiconductor memory device in an embodiment, involving SLC (Single Level Cell) programming operations for a second memory group.

[0021] Figure 13 This is a diagram illustrating an example of the execution sequence of the programming operations in the second stage of an embodiment of a semiconductor memory device.

[0022] Figure 14 This is a diagram illustrating an example of the execution sequence of the programming operations in the second stage of an embodiment of a semiconductor memory device.

[0023] Figure 15This is a diagram illustrating an example of the execution sequence of the second and third stages of programming operations in a semiconductor memory device according to an embodiment.

[0024] Figure 16 This is a diagram illustrating an example of the execution sequence of the second and third stages of programming operations in a semiconductor memory device according to an embodiment.

[0025] Figure 17 This is a flowchart illustrating an example of a series of processes performed by a semiconductor memory device in an embodiment to program a TLC (Trinary Level Cell) for a second memory group.

[0026] Figure 18 This is a flowchart illustrating an example of a series of processes performed by a semiconductor memory device in an embodiment for QLC programming operations on a second memory group.

[0027] Figure 19 This diagram illustrates an example of encoding multi-stage programming actions for implementing a method when using a PLC (Programmable Logic Controller). Detailed Implementation

[0028] Hereinafter, with reference to the accompanying drawings, a semiconductor memory device and method according to embodiments will be described in detail. However, the present invention is not limited to the embodiments described herein.

[0029] (Implementation Method)

[0030] As another example of multi-stage programming, a multi-stage programming operation is described in comparison with the implementation method. This multi-stage programming operation is referred to as a comparative example. In the comparative example, the storage unit functions as a buffer memory.

[0031] Specifically, according to the comparative example, in the first stage of programming, a portion of the data from the multi-bit data ultimately stored in the storage unit is programmed. Furthermore, in the second stage of programming following the first stage, the programmed portion of data is read from the storage unit, and all bits of the read portion of data are programmed together with the remaining data received from the storage controller.

[0032] Furthermore, in the comparative example, the storage unit that is the object of the programming action in each stage is selected, for example, in the same way as the fuzzy-fine programming action. That is, the programming action of the first stage is performed on the first storage unit and the second storage unit adjacent to the first storage unit, and then the programming action of the second stage is performed on the first storage unit.

[0033] According to the comparative example, the memory controller stores the remaining bits of data, excluding the portion of data completed in the first stage of programming, in a buffer memory until the first stage of programming ends. Therefore, compared to the fuzzy-fine programming operation, the capacity of the memory controller's buffer memory can be reduced.

[0034] However, in the comparative example, the second-stage programming operation aims to read the data stored in the memory cells from the first-stage programming operation without errors. Generally, the memory controller has the function of correcting errors contained in the read data, because errors cannot be corrected within the semiconductor memory device. Therefore, according to the comparative example, unlike the fuzzy-fine programming operation, it is impossible to increase the number of bits of data stored in the first-stage programming operation. According to the comparative example, since it is impossible to increase the number of bits of data programmed into each memory cell in the first-stage programming operation, when the number of bits of data ultimately stored in each memory cell is large, it is necessary to increase the shift of the threshold voltage of each memory cell in the second-stage programming operation. Therefore, there is greater inter-cell interference in the second-stage programming operation, which compromises data reliability.

[0035] In this embodiment, a semiconductor memory device and method are described that can reduce the capacity of the buffer memory of the memory controller without sacrificing data reliability.

[0036] Figure 1 This is a schematic diagram illustrating an example configuration of the semiconductor memory device 1 according to an embodiment. The semiconductor memory device 1 is a NAND flash memory chip capable of non-volatile data storage. The semiconductor memory device 1 can be controlled by an external memory controller 2. The memory controller 2 includes a buffer memory 3, which can pre-store the data required by the buffer memory 3.

[0037] like Figure 1 As shown, the semiconductor memory device 1 includes, for example, a memory cell array 10, a command register 11, an address register 12, a sequence generator 13, a driver module 14, a line decoder module 15, and a sense amplifier module 16. The sequence generator 13, driver module 14, line decoder module 15, and sense amplifier module 16 are examples of the circuitry in the embodiment.

[0038] The memory cell array 10 comprises multiple blocks BLK0 to BLKn (n is an integer greater than or equal to 1). A block BLK is a collection of multiple memory cells that can non-volatilely store data, for example, used as a data erasure unit. Furthermore, the memory cell array 10 includes multiple bit lines and multiple word lines. Each memory cell is associated with, for example, one bit line and one word line. The detailed configuration of the memory cell array 10 is described below.

[0039] Command register 11 stores commands (CMDs) received by semiconductor memory device 1 from memory controller 2. Commands (CMDs) may include, for example, commands that cause sequence generator 13 to perform read operations, program operations, erase operations, etc.

[0040] Address register 12 stores address information ADD received by semiconductor memory device 1 from memory controller 2. Address information ADD includes, for example, block address BAD, page address PAd, and column address CAd. For example, block address BAD, page address PAd, and column address CAd are used to select block BLK, word line, and bit line, respectively.

[0041] The sequence generator 13 controls the overall operation of the semiconductor memory device 1. For example, the sequence generator 13 controls the driver module 14, the line decoder module 15, and the sense amplifier module 16 based on the command CMD stored in the command register 11, thereby performing read operations, programming operations, and erase operations.

[0042] The driver module 14 generates voltages for read operations, programming operations, and erase operations. Furthermore, the driver module 14 applies the generated voltages to the signal lines corresponding to the selected word lines, for example, based on the page address PAd stored in the address register 12.

[0043] The line decoder module 15 selects one block BLK within the memory cell array 10 based on the block address BAd stored in the address register 12. Furthermore, the line decoder module 15, for example, transmits the voltage applied to the signal line corresponding to the selected word line to the selected word line within the selected block BLK.

[0044] During programming, the sensing amplifier module 16 applies a desired voltage to each bit line based on the write data DAT received from the memory controller 2. Furthermore, during reading, the sensing amplifier module 16 determines the data stored in the memory cell based on the voltage of the bit lines and transmits the determination result as read data DAT to the memory controller 2.

[0045] Furthermore, the sensing amplifier module 16 includes a data register 17. The data register 17 stores write data DAT received from the memory controller 2 until the storage of the memory cell array 10 is complete, or stores read data DAT read from the memory cell array 10 until the output to the memory controller 2 is complete. Additionally, during the multi-stage programming operation of the embodiment, the data register 17 temporarily stores a portion of the data read from the memory cell array 10. Details regarding the multi-stage programming operation of the embodiment are described in detail below.

[0046] The semiconductor memory device 1 and memory controller 2 described above can also be combined to form a semiconductor device. Examples of such semiconductor devices include, for instance, an SD card.TM Memory cards like memory cards, and SSDs (solid state drives), etc.

[0047] Figure 2 This diagram illustrates an example of the circuit configuration of a block BLK in an implementation method. The block BLK contains multiple string units SU( Figure 2 In the example, there are 16 string units SU0 to SU15. Furthermore, Figure 2 A simplified circuit configuration of a portion of two string units SU0 and SU1 contained in block BLK is shown. Each pair of string units SU(2p) and string unit SU(2p+1) contained in block BLK has the same configuration as a pair of string units SU0 and SU1. Figure 2 In the example shown, p is an integer from 0 to 7.

[0048] Each pair of word string units SU(2p) and word string units SU(2p+1) contains multiple first memory groups MG. A word line BL is associated with each of the multiple first memory groups MG. Figure 2 In the example, a pair of string units SU0 and SU1 contain L first memory groups MG (where L is an integer greater than or equal to 1). Each of the L first memory groups MG is associated with one of the bit lines BL0 to BL(L-1).

[0049] Each pair of string units SU(2p) and string unit SU(2p+1) contains L first memory groups MG. Each of the L first memory groups MG contained in each pair is associated with one of the bit lines BL0 to BL(L-1).

[0050] In other words, in a block BLK, each bit line BL is associated with a memory group MG contained in each pair of string units SU(2p) and string unit SU(2p+1).

[0051] In each pair of string units SU(2p) and string unit SU(2p+1), the L NAND strings NSa in the L first memory groups MG constitute the string unit SU(2p). The L NAND strings NSb in the L first memory groups MG constitute the string unit SU(2p+1).

[0052] Figure 3 This describes a more detailed circuit configuration of a memory group MG used to illustrate the implementation method. The first memory group MG included in block BLK has a common configuration. Figure 3 Taking the first memory group MG contained in block BLK as an example, the circuit configuration of the first memory group MG associated with bit line BL0 is shown in a pair of word string units SU0 and word string unit SU1. The following refers to... Figure 2 and Figure 3 Continuing the explanation. Furthermore, from now on, the memory cell transistor MC will be referred to as the memory cell MC.

[0053] The NAND string NSa contains transistors TTa0 to TTa2, transistors TSa0 to TSa2, memory cells MCa0 to MCa63, select transistors STa1 and STa2. Furthermore, the number of TTa transistors in the NAND string NSa is not limited to three. The number of TSa transistors in the NAND string NSa is not limited to three. The number of MCa memory cells in the NAND string NSa is not limited to 64.

[0054] The NAND string NSb contains transistors TDb0 to TDb2, TSb0 to TSb2, memory cells MCb0 to MCb63, select transistors STb1 and STb2. Furthermore, the number of transistors TD in the NAND string NSb is not limited to three. The number of transistors TS in the NAND string NSb is not limited to three. The number of memory cells MCb in the NAND string NSb is not limited to 64.

[0055] String unit SU0 is selected by selection transistors STa1 and STa2 contained in each of the L NAND strings NSb constituting string unit SU0. String unit SU1 is selected by selection transistors STb1 and STb2 contained in each of the L NAND strings NSb constituting string unit SU1.

[0056] The memory cells MCa and MCb each contain a control gate and a charge accumulation layer, and retain data non-volatilely.

[0057] In the NAND string NSa, transistors TSa0-TSa2, memory cells MCa0-MCa63, and transistors TDa0-TDa2 are connected in series. The source of the select transistor STa1 is connected to one end of the series-connected transistors TSa0-TSa2, MCa0-MCa63, and TDa0-TDa2. The other end of the series-connected transistors TSa0-TSa2, MCa0-MCa63, and TDa0-TDa2 is connected to the drain of the select transistor STa2.

[0058] In the NAND string NSb, transistors TSb0-TSb2, memory cells MCb0-MCb63, and transistors TDb0-TSb2 are connected in series. The source of the select transistor STb1 is connected to one end of the series-connected transistors TSb0-TSb2, memory cells MCb0-MCb63, and transistors TDb0-TSb2. The other end of the series-connected transistors TSa0-TSSa2, memory cells MCa0-MCA63, and transistors TDa0-TDu2 is connected to the drain of the select transistor STa2.

[0059] The drains of transistors STa1 and STb1 are connected to the bit line BL, which is associated with the first memory group MG. The sources of transistors STa2 and STb2 are connected to the source line SL.

[0060] Regarding each word string unit SU(2p), the gates of the multiple selection transistors STa1 contained in the same BLK are connected to a common selection gate line SGDa within the word string unit SU(2p). For example, all selection transistors STa1 contained in word string unit SU0 are connected to a common selection gate line SGDa0.

[0061] The select transistors STa2 of each word string unit SU(2p) contained in a block BLK are all connected to the select gate line SGSa.

[0062] Regarding each word string unit SU(2p+1), the gates of the multiple selection transistors STb1 contained in a block BLK are each connected within the word string unit SU(2p+1) to a common selection gate line SGDb. For example, all selection transistors STb1 contained in word string unit SU0 are commonly connected to the selection gate line SGDb0.

[0063] The select transistor STb2 of each word string unit SU(2p+1) contained in a block BLK is connected to the select gate line SGSb.

[0064] The control gates of the memory cells MCa0 to MCa63 contained in a block BLK are all connected to word lines WLa0 to WLa63. The control gates of the memory cells MCb0 to MCb63 contained in a block BLK are all connected to word lines WLb0 to WLb63.

[0065] The control gates of transistors TTa0 to TTa2 in a block BLK are all connected to word lines WLDDa0 to WLDDa2. The control gates of transistors TDb0 to TDb2 in a block BLK are all connected to word lines WLDDb0 to WLDDb2.

[0066] The control gates of transistors TSa0 to TSa2 in a block BLK are all connected to word lines WLDSa0 to WLDSa2. The control gates of transistors TSb0 to TSb2 in a block BLK are all connected to word lines WLDSb0 to WLDSb2.

[0067] Bit lines BL are shared, for example, by memory group MG (a pair of NAND word strings NSa and NSb) that are assigned the same column address. Source lines SL are shared, for example, among multiple blocks BLK. Select gate line SGSa is set for each block BLK. Word lines WLa and WLb, select gate lines SGDa and SGDb, and select gate lines SGSa and SGGSb can each be controlled independently.

[0068] Next, an example of the structure of the memory cell array 10 included in the semiconductor memory device 1 of the embodiment will be described. In the following figures, the X direction corresponds to the extension direction of the word line WL, the Y direction corresponds to the extension direction of the bit line BL, and the Z direction corresponds to the direction perpendicular to the surface of the semiconductor substrate 30 used to form the semiconductor memory device 1. Shading lines have been appropriately added to the top view for easier viewing. The shading lines added to the top view are not necessarily related to the material or characteristics of the constituent elements to which the shading lines are added. Furthermore, in the following figures, to avoid making the figures cumbersome, [the following text is incomplete and requires further context]. Figure 2 and Figure 3 Compared to the example shown, the number of each transistor TD, TS and the number of memory cells MCa, MCb are depicted less.

[0069] Figure 4 This is a diagram showing an example of the planar layout of the memory cell array 10 in this embodiment, with regard to the selection of gate lines SGDa0~a2 and SGDb0~b2. Figure 4 In this process, the regions corresponding to the six sequentially arranged string units SU0 to SU5 are extracted. For example... Figure 4 As shown, the memory cell array 10 includes cell regions CA and replacement regions RA1 and RA2. Furthermore, the memory cell array 10 includes multiple memory trenches MT, multiple memory pillars MP, and multiple replacement vias STH.

[0070] Cell region CA and replacement regions RA1 and RA2 extend in the Y direction. Cell region CA is sandwiched between replacement regions RA1 and RA2 in the X direction. Select gate lines SGDa and SGDb each have a portion extending in the X direction, traversing cell region CA and replacement regions RA1 and RA2. Select gate lines SGDa and SGDb are alternately arranged in the Y direction.

[0071] Each memory trench MT is configured between adjacent select gate lines SGDa and SGDb. The memory trench MT has a portion extending along the X direction, separating adjacent wiring layers in the Y direction. An insulator is embedded, for example, in the memory trench MT.

[0072] Each memory column (MP) functions as the first memory group (MG), overlapping with one memory trench (MT) within the cell region (CA). Furthermore, each memory column (MP) breaks the overlapping memory trench (MT) and contacts each of the adjacent select gate lines (SGDa and SGDb) of the broken memory trench (MT). The portion of the memory column (MP) opposite to the select gate line (SGDa) functions as a select transistor (STa1). The portion of the memory column (MP) opposite to the select gate line (SGDb) functions as a select transistor (STb1).

[0073] In each memory column MP, at least one bit line BL is overlapped and electrically connected. In the region corresponding to each BLK, multiple memory columns MP are arranged in four columns, for example, in an alternating pattern. Furthermore, every two word string units SU, a memory trench MT that does not overlap with the memory column MP is configured. In other words, the memory cell array 10 is divided by memory trenches MT that do not overlap with the memory column MP, thereby separating the even-numbered word string units SU from each other or the odd-numbered word string units from each other.

[0074] Each substitution via STH is used during the formation of multilayer wiring. For example, a plurality of substitution via STHs include: a substitution via STH overlapping the even-numbered memory trench MT in substitution region RA1; and a substitution via STH overlapping the odd-numbered memory trench MT in substitution region RA2. Each substitution via STH breaks the overlapping memory trench MT and contacts each of the select gate lines SGDa and SGDb adjacent to the broken memory trench MT. An insulator is embedded, for example, in the substitution via STH.

[0075] Figure 5 This is a diagram showing an example of the planar layout of the memory cell array 10 in an embodiment, focusing on word lines WLa and WLb. Figure 5 The area of ​​the memory trench MT and the replacement via STH, including the boundary portions of string units SU0 / 1 and SU2 / 3, is shown. Figure 5 As shown, the memory column MP includes a core component 20, a semiconductor layer 21, a tunnel insulating film 22, an insulating film 23, and a barrier insulating film 24.

[0076] Word lines WLa and WLb each have a portion extending along the X direction, traversing cell region CA and substitution regions RA1 and RA2. Word lines WLa and WLb are alternately arranged in the Y direction, and a memory trench MT is disposed between word lines WLa and WLb. That is, word lines WLa and WLb each have a portion that contacts each of the memory cylinder MP and the substitution hole STH. The portions of word lines WLa and WLb that contact each of the memory cylinder MP and the substitution hole STH function as pseudo-cells.

[0077] In addition, the ends of multiple word lines WLa are electrically connected to each block BL. The ends of multiple word lines WLb are electrically connected to each block BLK.

[0078] A core component 20 is disposed in the center of the memory cylinder MP. A semiconductor layer 21 surrounds the core component 20. A tunnel insulating film 22 surrounds the semiconductor layer 21. An insulating film 23 surrounds the tunnel insulating film 22. A barrier insulating film 24 surrounds the insulating film 23. Furthermore, the barrier insulating film 24 contacts each of the adjacent word lines WLa and WLb, and the memory trench MT between the adjacent word lines WLa and WLb.

[0079] The portion of the memory cylinder MP opposite to the word line WLa functions as a memory cell MCa. The portion of the memory cylinder MP opposite to the word line WLb functions as a memory cell MCb. For example, the core component 20 includes an insulator such as silicon oxide (SiO2). The semiconductor layer 21 includes silicon (Si). The tunnel insulating film 22 and the barrier insulating film 24 each include silicon oxide (SiO2). The insulating film 23 includes silicon nitride (SiN).

[0080] Figure 6 It is along Figure 5 A cross-sectional view of the storage cell array 10 according to the implementation of the VI-VI line. Figure 6 This represents an example of the cross-sectional structure of a memory cylinder (MP). For example... Figure 6 As shown, the memory cell array 10 includes, for example, conductive layers 31, 32a, 32b, 34a, 34b, 35a, 35b and 36, insulating layers 40, 43, 44 and 45, and contact CV. The detailed cross-sectional structure of the memory cell array 10 will be described below, starting from the bottom layer.

[0081] A conductive layer 31 is disposed on a dielectric insulating layer 40 on a semiconductor substrate 30. Although not shown in the figure, circuitry such as a sense amplifier module 16 is disposed inside the dielectric insulating layer 40. The conductive layer 31 is formed, for example, in a plate shape extending along the XY plane and is used as a source line SL. The conductive layer 31 contains, for example, phosphorus (P)-doped silicon (Si). The conductive layer 31 may contain various semiconductor layers or metal layers.

[0082] On the conductive layer 31, a dielectric insulating layer 41 is provided with a conductive layer 32. The conductive layer 32 is formed, for example, in a plate shape extending along the XY plane, and is used as a select gate line (SGS). The conductive layer 32 contains, for example, tungsten (W).

[0083] An insulating layer 43 and a conductive layer 34 are alternately stacked on the conductive layer 32. The conductive layer 34 is formed, for example, in a plate shape extending along the XY plane. The stacked conductive layers 34 are used sequentially as word lines WLDS, WL0 to WL6, and WLDD, respectively, starting from the semiconductor substrate 30 side. The conductive layer 34 contains, for example, tungsten (W).

[0084] On the uppermost conductive layer 34, a dielectric insulating layer 44 provides a conductive layer 35. The conductive layer 35 is formed, for example, in a plate shape extending along the XY plane and is used as a select gate line (SGD). The conductive layer 35 contains, for example, tungsten (W).

[0085] On the conductive layer 35, a dielectric insulating layer 45 is provided with a conductive layer 36. The conductive layer 36 is formed, for example, as a line extending along the Y direction and is used as a bit line BL. That is, in the region not shown, a plurality of conductive layers 36 are arranged along the X direction. The conductive layer 36 contains, for example, copper (Cu).

[0086] The memory pillar MP extends along the Z-direction, penetrating the conductive layers 32, 34, and 35, and the insulating layers 41, 43, and 44. A core component 20 within the memory pillar MP extends along the Z-direction. The upper end of the core component 20 is contained within a layer above the conductive layer 35. The lower end of the core component 20 is contained within the layer forming the conductive layer 31. A semiconductor layer 21 covers the area surrounding the core component 20. A tunnel insulating film 22 covers the sides and bottom of the semiconductor layer 21. An insulating film 23 covers the sides and bottom of the tunnel insulating film 22. A barrier insulating film 24 covers the sides and bottom of the insulating film 23. The conductive layer 31 contacts the semiconductor layer 21 via the sides of the memory pillar MP.

[0087] A columnar contact CV is provided on the semiconductor layer 21 within the memory column MP. A conductive layer 36 (bit line BL) contacts the contact CV. Similarly, the memory column MP corresponding to the first memory group MG associated with the column address is connected to the common conductive layer 36 via the contact CV.

[0088] Conductor layer 32 is separated into conductor layers 32a and 32b corresponding to the select gate lines SGSa and SGSb, respectively. Conductor layer 34 is separated into conductor layers 34a and 34b corresponding to word lines WLDSa and WLDSb, respectively; conductor layers 34a and 34b corresponding to word lines WLa and WLb, respectively; or conductor layers 34a and 34b corresponding to word lines WLDDa and WLDDb, respectively. Conductor layer 35 is separated into conductor layers 35a and 35b corresponding to the select gate lines SGDa and SGDb, respectively.

[0089] In the semiconductor memory device 1 of the embodiments described above, the insulating film 23 is used as a charge accumulation layer for memory cells MCa and MCb. Transistors TTa and TDb, memory cells MCa and MCb, transistors TSa and TSb, and selection transistors STa1, STb1, STa2, and STb2 share a common channel (semiconductor layer 21). The groups of selection transistors STa1 and STa2, transistors TTa and TSa, and memory cells MCa0 to MCa6 arranged in the Z-direction correspond to the NAND string NSa. The groups of selection transistors STb1 and STb2, transistors TDb and TSb, and memory cells MCb0 to MCb6 arranged in the Z-direction correspond to the NAND string NSb.

[0090] Furthermore, in a direction parallel to the surface of the semiconductor substrate 30 (e.g., the Y direction), memory cells MCa0 to MCa6, transistors TDa and TSa, and selection transistors STDa1 and STDa2 are respectively opposite to memory cells MCb0 to MCb7, transistors TDb and TSb, and selection transistors STb1 and STb2.

[0091] In the semiconductor memory device 1 of the embodiment, the threshold voltage of the memory cell MC in which charge is accumulated in the charge accumulation layer (i.e., the insulating film 23) is higher than the threshold voltage of the memory cell MC in which no charge is accumulated in the charge accumulation layer. Utilizing this phenomenon, data can be stored in any memory cell MC by injecting charge into the charge accumulation layer. The action of storing data in the memory cell MC by injecting charge into the memory cell MC is called a programming action.

[0092] Based on the threshold voltage of the data, the data stored in the storage unit MC is determined. The action of determining the data stored in the storage unit MC is called a read action.

[0093] The data stored in the memory cell MC is erased by removing the charge accumulated in the charge accumulation layer. The action of erasing the data stored in the memory cell MC is called an erase action.

[0094] Erasing operations are performed on a block-by-block (BLK) basis. Programming and reading operations can be performed on multiple (...) bytes belonging to a single string unit (SU) within a memory cell (MC) connected to a single word line (WL). Figure 2 In the example, a group of L memory cells MCs is executed together. The group containing multiple memory cells MCs that can perform the programming and reading operations is called the second memory group.

[0095] use Figure 7 The operation method of the first memory group MG in the reading operation of the embodiment will be described. Figure 7 This is a diagram showing the voltage applied to multiple word lines WL connected to a first memory group MG during the read operation of an embodiment.

[0096] in addition, Figure 7 In this example, let's take memory cell MCa4 as the read target. There are cases where the read target memory cell MC, i.e., memory cell MCa4, is designated as the selection cell MCa4. There are cases where other memory cells MCa belonging to the NAND string NSa, which are the same as the selection cell MCa4, are designated as non-selection cells. There are cases where, among the memory cells MC of the NAND string NSb that share a channel (semiconductor layer 21) with both the selection cell MCa4 and the non-selection cells, the memory cell MCb4 opposite to the selection cell MCa4 is designated as the target cell MCb4. There are cases where other memory cells MCb belonging to the NAND string NSb that share a channel (semiconductor layer 21) with both the selection cell MCa4 and the non-selection cells are designated as slanted cells.

[0097] During a read operation, the line decoder module 15 applies a read voltage Vread generated by the driver module 14 to the word line WL of the non-selected cell. The read voltage Vread is such that, regardless of whether charge has accumulated in the charge accumulation layer, the portion of the channel opposite to the charge accumulation layer is in a conducting state. Therefore, the non-selected cell is in a conducting state regardless of the programmed data.

[0098] The line decoder module 15 applies a back voltage VBB generated by the driver module 14 to the word line WLb4 of the opposing unit MCb4. The back voltage VBB is a voltage such that, regardless of whether charge has accumulated on the charge accumulation film, the portion of the channel opposite to the charge accumulation layer is in a non-conductive state and is lower than the read voltage Vread, for example, ground voltage, i.e., 0V. Therefore, regardless of whether data is programmed and what the programmed data is, the opposing unit MCb4 remains in a non-conductive state.

[0099] The line decoder module 15 applies a read voltage Vread to the word line WL of the slant position cells. As a result, these slant position cells become conductive regardless of whether charge has accumulated on the charge accumulation film.

[0100] The line decoder module 15 applies the turn-on voltage Vcc generated by the driver module 14 to the word lines SGDa0, SGDb0, SGSa, SGGSb, WLDDa, WLDDb, WLDSa, and WLDSB of the selection transistors STa1, STb1, STb1, STb2, TSa, TDb, TSa, and TSb. This turns on the selection transistors STa1, STb1, STa2, and STb2, as well as the transistors TDa, TDb, TSa, and TSb.

[0101] Furthermore, a bit line voltage Vbl is applied to the bit line BL. As a result, depending on the on state of the selection unit MCa4, current flows from the bit line BL through the channel to the source line SL. This current is denoted as the on-state current Icell. The magnitude of the on-state current Icell depends on the threshold voltage of the selection unit MCa4.

[0102] In this state, the line decoder module 15 applies a detection voltage Vsense generated by the driver module 14 to the word line LLa4 of the selection unit MCa4. The driver module 14 sequentially boosts the detection voltage Vsense, for example, from near the ground voltage to near the read voltage. That is, VBB < Vsense < Vread. Furthermore, the sense amplifier module 16 determines the threshold voltage of the selection unit MC4a by measuring the change in the on-state current Icell, thereby reading the data programmed into the selection unit MCa.

[0103] During the programming process, the threshold voltage of the memory cell MC is set within the range corresponding to the data.

[0104] More specifically, the threshold voltage range of the memory cell MC is divided into N distinct data bits (where N is an integer greater than or equal to 1) to establish corresponding 2... N There are several intervals. Furthermore, during the programming process, by injecting charge into the charge accumulation layer of the memory cell MC, the threshold voltage of the memory cell MC is set at 2. N Within a given interval, the interval corresponding to the data is defined. During the read operation, at least one voltage corresponding to the boundary of an adjacent interval is sequentially applied as a detection voltage Vsense to identify the interval containing the threshold voltage of the memory cell MC. Furthermore, the data corresponding to the identified interval is acquired and stored in the memory cell MC.

[0105] A storage cell (MC) can store more than one bit of data. Storing one bit of data in the MC is called SLC (Single Level Cell). Storing two or more bits of data in the MC is called MLC (Multi Level Cell). Storing three bits of data in the MC is called TLC (Triple Level Cell). Storing four bits of data in the MC is called QLC (Quad-Level Cell). Storing five or more bits of data in the MC is called PLC (Penta-Level Cell).

[0106] When programming the second memory group, the threshold voltages of the memory cells MC constituting the second memory group form multiple distributions. As an example, the multiple distributions of the threshold voltages of the multiple memory cells MC that store data in QLC mode will be explained. Figure 8 This is a diagram illustrating an example of multiple distributions of threshold voltages formed during programming operations via QLC in a semiconductor memory device 1 according to an embodiment. Figure 8 In the diagram, the horizontal axis represents voltage, and the vertical axis represents the number of memory cells (MCs).

[0107] In the case of QLC, 16 intervals R0 to R15 are set for different 4-bit data. For example, on the lowest voltage side, the interval R0 is set up up to voltage Vc1. On the side with a higher voltage than the interval R0, the following intervals are set: R1 from voltage Vc1 to voltage Vc2, R2 from voltage Vc2 to voltage Vc3, R3 from voltage Vc3 to voltage Vc4, R4 from voltage Vc4 to voltage Vc5, R5 from voltage Vc5 to voltage Vc6, R6 from voltage Vc6 to voltage Vc7, R7 from voltage Vc7 to voltage Vc8, R8 from voltage Vc8 to voltage Vc9, R9 from voltage Vc9 to voltage Vc10, R10 from voltage Vc10 to voltage Vc11, R11 from voltage Vc11 to voltage Vc12, R12 from voltage Vc12 to voltage Vc13, R13 from voltage Vc13 to voltage Vc14, R14 from voltage Vc14 to voltage Vc15, and R15 on the side with a higher voltage than voltage Vc15.

[0108] Furthermore, the lower limit of the lowest voltage side interval R, i.e., interval R0, is at least greater than the back voltage VBB. When the target cell sharing the channel with the first memory cell MC, i.e., the second memory cell MC, is the read target, the back voltage VBB is applied to the control gate of the first memory cell MC. By setting the lower limit of interval R0 to be greater than the back voltage VBB, the first memory cell MC is ensured to be in a non-conducting state when the back voltage VBB is applied to the control gate of the first memory cell MC.

[0109] Furthermore, the upper limit of the highest voltage range R, i.e., range R15, does not reach the read voltage Vread. Therefore, regardless of the data stored in each memory cell MC, it can become conductive when the read voltage Vread is applied.

[0110] During the programming process, the threshold voltage of each memory cell (MC) is set within the interval corresponding to the data. As a result, the threshold voltages of multiple memory cell MCs form a lobe-like distribution according to each interval. The state of the threshold voltage set with the interval RX as the target is denoted as state SX. The distribution of the threshold voltage set with the interval RX as the target is denoted as distribution SX. X in Figure 8 The example shown uses integers from 0 to 15.

[0111] Furthermore, during the erase operation, the threshold voltage of the storage cell MC is set to be lower than voltage Vc1. That is, state S0 can be considered as a state where data has been erased. Therefore, state S0 can also be denoted as state Er. Additionally, distribution S0 can also be denoted as distribution Er.

[0112] During the read operation, the threshold voltage of the memory cell MC is determined to be contained within a specific interval R by setting the voltage corresponding to the boundary of the adjacent interval R as the detection voltage Vsense. For example, voltages Vc1, Vc2, Vc3, Vc4, Vc5, Vc6, Vc7, Vc8, Vc9, Vc10, Vc11, Vc12, Vc13, Vc14, and Vc15 can each be used as the detection voltage Vsense.

[0113] The threshold voltage of a memory cell MC can vary due to various reasons including interference between cells. Therefore, the narrower the interval R, the more difficult it is to set or maintain the distribution of the threshold voltage within said interval R. As a result, there are cases where a portion of the high-voltage side or a portion of the low-voltage side of the lobe-like distribution formed in each interval R extends into adjacent intervals R. According to... Figure 8 In the example shown, at the boundary of adjacent intervals R, because parts of the lobe-shaped distributions extend beyond each other, parts of the distributions in adjacent intervals R overlap.

[0114] If a portion of the lobe-shaped distribution S formed in the target interval R extends into an adjacent interval R, during a read operation, erroneous data will be read from the memory cell MC, whose threshold voltage is contained within the extended portion. The erroneous data is sent to the memory controller 2, where it is corrected using an error correction function.

[0115] Hereinafter, as an example, in the semiconductor memory device 1 of the embodiment, each memory cell MC is configured to ultimately store data in a QLC manner through a programming operation.

[0116] As described above, programming actions can be performed simultaneously on multiple memory cells (MCs) constituting the second memory group. Furthermore, according to the QLC method, 4-bit data is stored in each memory cell (MC). The data with the least significant bit among the 4-bit data representing the amount in the second memory group is called the lower page. The data with the second least significant bit among the 4-bit data representing the amount in the second memory group is called the middle page. The data with the third least significant bit among the 4-bit data representing the amount in the second memory group is called the upper page. The data with the most significant bit among the 4-bit data representing the amount in the second memory group is called the top page.

[0117] In this implementation, multi-stage programming actions are performed. Figure 9 This is a schematic diagram illustrating the change in the threshold voltage distribution of the multi-stage programming action that constitutes the implementation method. Figure 9 Four graphs are shown to illustrate the changes in the threshold voltage of the memory cell MC group that constitutes a second memory group at various stages. In each graph, the horizontal axis represents voltage, and the vertical axis represents the number of memory cells MC.

[0118] In the block BLK after the erase operation, all memory cells (MC) become state Er. This is especially true if no programming has started after the erase operation, such as... Figure 9 As shown in the topmost diagram, the threshold voltage of the memory cell MC forms a large lobe shape distribution in the range below voltage Vc1. Furthermore, this distribution extends beyond voltage VBB to the low-voltage side.

[0119] For the second memory group after the erase operation, one bit of data is stored in each memory cell MC through the programming operation of the first stage (also referred to as ST1). That is, one page of data is stored in the second memory group.

[0120] Based on the programming actions in Phase 1, such as from Figure 9As shown in the second layer of the diagram above, distributions EP1 and EP2 are formed in the interval R0. Distributions EP1 and EP2 correspond to 1 distinct data point. Distributions EP1 and EP2 exist separately from each other across a specific voltage Va. Distribution EP1 on the lower voltage side of both distributions EP1 and EP2 does not exceed voltage Va to reach the higher voltage side, and distribution EP2 on the higher voltage side of both distributions EP1 and EP2 does not exceed voltage Va to reach the lower voltage side.

[0121] Therefore, if the semiconductor memory device 1 performs a read operation on the memory cell MC that has completed the programming operation in the first stage, using the voltage Va as the detection voltage Vsense, then it can obtain 1 bit of data without errors from the memory cell MC.

[0122] In this specification, the programming action in the first stage is based on the meaning of storing 1 bit of data in each memory cell transistor, and is also referred to as the SLC programming action.

[0123] Next, through the second stage (also referred to as ST2) programming action, 2 more bits of data are added to each memory cell MC. That is, through the second stage programming action, 2 pages of data are added to the second memory group, and the second memory group becomes a state that stores a total of 3 pages of data.

[0124] Based on the programming actions in Phase 2, such as from Figure 9 As shown in the third layer of the diagram above, in the range from voltage VBB to voltage Vb1, distributions ER (also denoted as distribution S0') and S2' are formed from the low voltage side. In the range from voltage VB1 to voltage VB2, distributions S4' and S6' are formed from the low voltage side. In the range from voltage VB2 to voltage VB3, distributions S8' and S10' are formed from the low voltage side. In the range from voltage VB3 to the high voltage side, distributions S12' and S14' are formed from the low voltage side.

[0125] Distributions S0' and S2' may overlap. Distributions S4' and S6' may also overlap. Distributions S8' and S10' may also overlap. Distributions S12' and S14' may also overlap.

[0126] However, distributions S0' and S2' did not exceed voltage Vb1 to reach the high-voltage side. Distributions S4' and S6' did not exceed voltage Vb1 to reach the low-voltage side. Distributions S4' and S6' did not exceed voltage Vb2 to reach the high-voltage side. Distributions S8' and S10' did not exceed voltage Vb2 to reach the low-voltage side. Distributions S8' and S10' did not exceed voltage Vb3 to reach the high-voltage side. Distributions S12' and S14' did not exceed voltage Vb3 to reach the low-voltage side. In other words, according to the programming operation of the second stage, the threshold voltage groups of the multiple memory cells MC constituting the second memory group are set to form 8 distributions separated in units of 2.

[0127] Therefore, if the semiconductor memory device 1 performs a read operation on the memory cell MC after the programming operation in the second stage, using voltages Vb1, Vb2, and Vb2 as the detection voltage Vsense, then it can obtain two bits of data without errors from the memory cell MC.

[0128] Furthermore, the overlapping distributions S0' and S2' can be separately encoded using 1-bit data pre-stored via SLC programming operations. The overlapping distributions S4' and S6' can also be separately encoded using 1-bit data pre-stored via SLC programming operations. The overlapping distributions S8' and S10' can also be separately encoded using 1-bit data pre-stored via SLC programming operations. The data encoding will be described below.

[0129] In this specification, the second stage of programming refers to storing 3 bits of data in each memory cell transistor, also known as TLC programming.

[0130] Next, through the third stage (also referred to as ST3) programming action, one bit of data is added to each memory cell MC. That is, through the third stage programming action, one page of data is added to the second memory group, and the second memory group becomes a state that stores a total of 4 pages of data.

[0131] In the third stage of programming, by maintaining or slightly increasing the threshold voltage of the memory cells MC contained in distribution S0', distribution S0' is divided into distribution S0 and distribution S1. By slightly increasing the threshold voltage of the memory cells MC contained in distribution S2', distribution S2' is divided into distribution S2 and distribution S3. By slightly increasing the threshold voltage of the memory cells MC contained in distribution S4', distribution S4' is divided into distribution S4 and distribution S5. By slightly increasing the threshold voltage of the memory cells MC contained in distribution S6', distribution S6' is divided into distribution S6 and distribution S7. By slightly increasing the threshold voltage of the memory cells MC contained in distribution S8', distribution S8' is divided into distribution S8 and distribution S9. By slightly increasing the threshold voltage of the memory cells MC contained in distribution S10', distribution S10' is divided into distribution S10 and distribution S11. By slightly increasing the threshold voltage of the memory cells MC contained in distribution S12', distribution S12' is divided into distribution S12 and distribution S13. By slightly increasing the threshold voltage of the memory cell MC contained in distribution S14', distribution S14' is divided into distribution S14 and distribution S15.

[0132] Thus, in the multi-stage programming operation of the implementation method, three stages of programming operations are performed.

[0133] Before the programming actions in stages 2 and 3, one bit of data stored in each memory cell MC through the programming action in stage 1 is read and used in the programming actions in stages 2 and 3. In addition, before the programming action in stage 3, two bits of data appended to each memory cell MC through the programming action in stage 2 are read and used in the programming action in stage 3.

[0134] In other words, according to the implementation method, it is possible to read 1 bit of data stored in the storage unit MC through the first stage programming operation and 2 bits of data stored in the storage unit MC through the second stage programming operation. Therefore, the storage controller 2 does not need to pre-store the 1 bit of data stored in the storage unit MC through the first stage programming operation and the 2 bits of data stored in the storage unit MC through the second stage programming operation in the buffer memory 3 until all bits of data storage is completed. That is, compared to a configuration that performs fuzzy-fine programming operations, the amount of data that should be pre-stored in the buffer memory 3 of the storage controller 2 can be significantly reduced.

[0135] Furthermore, according to the implementation method, since the programming action from the last stage to the previous stage, that is, the second stage programming action, stores as many bits of data as possible ( Figure 9(In the example shown, the data is 3 bits). Therefore, through the second stage of programming, the threshold voltage of each memory cell MC can be set near the target range R. As a result, in the final stage of programming, that is, the shift of the threshold voltage, the data reliability reduction caused by the mutual interference between cells can be suppressed.

[0136] In other words, according to the implementation method, the amount of data that needs to be pre-stored in the storage controller 2 can be reduced without compromising the reliability of the data.

[0137] Figure 10 It means that it can be performed. Figure 9 The diagram shows an example of the coding of an implementation of a multi-stage programming action. According to the coding example shown in this diagram, the data "1111" corresponds to state S0, the data "1110" corresponds to state S1, the data "1100" corresponds to state S2, the data "1101" corresponds to state S3, the data "0101" corresponds to state S4, the data "0100" corresponds to state S5, the data "0110" corresponds to state S6, the data "0111" corresponds to state S7, the data "0011" corresponds to state S8, the data "0010" corresponds to state S9, the data "0000" corresponds to state S10, the data "0001" corresponds to state S11, the data "1001" corresponds to state S12, the data "1000" corresponds to state S13, the data "1010" corresponds to state S14, and the data "1011" corresponds to state S15. In the case of data "abcd", "a" represents the position belonging to the lower page, "b" represents the position belonging to the middle page, "c" represents the position belonging to the upper page, and "d" represents the position belonging to the top page.

[0138] according to Figure 10 The code shown in the diagram stores data for the top page in the first stage of programming. In the second stage, it adds data for the bottom and middle pages. Furthermore, in the third stage, it adds data for the top page.

[0139] According to the encoding, by storing the bits of the upper page in the first stage of programming actions, the distributions S0' (i.e., the distributions before being divided into distributions S0 and S1) and S2' (i.e., the distributions before being divided into distributions S2 and S3), which are allowed to overlap, formed by storing the lower and middle pages in the second stage of programming actions, can be separated. Furthermore, the distributions S4' (i.e., the distributions before being divided into distributions S4 and S5) and S6' (i.e., the distributions before being divided into distributions S6 and S7) can be separated. The distributions S8' (i.e., the distributions before being divided into distributions S8 and S9) and S10' (i.e., the distributions before being divided into distributions S10 and S11) can be separated. The distributions S12' (i.e., the distributions before being divided into distributions S12 and S13) and S14' (i.e., the distributions before being divided into distributions S14 and S15) can be separated.

[0140] Thus, the encoding is defined as follows: by storing bits in the first stage of programming, two distributions that are allowed to overlap and are formed by the second programming action can be separated. Furthermore, as long as the two distributions that are allowed to overlap and are formed by the second programming action can be separated by storing bits in the first stage of programming, the encoding can be defined arbitrarily.

[0141] Next, refer to Figures 11-15 This section describes an example of the details of the multi-stage programming operations performed in the semiconductor memory device 1 according to the embodiment. Hereinafter, the operation of storing data in a single block BLK will be described.

[0142] Figure 11 This is a diagram illustrating an example of the execution sequence of the programming operations in the first stage of the semiconductor memory device 1 in an embodiment. Figure 11 The arrows shown indicate the programming actions in stage 1, which is the sequence of SLC programming actions. Additionally, Figure 11 The content shown is in accordance with Figure 2 Examples of its composition.

[0143] Semiconductor memory device 1 performs an SLC programming operation to store the data of the upper pages in all the second memory groups of the block BLK after the erase operation. For example, as Figure 11 As shown, word lines WL connected to the second memory group are selected from the source line SL side in word line number order. Furthermore, for each word string unit SU connected to the selected word line WL in the second memory group, SLC programming operations are performed in word string unit SU number order. Additionally, word line WLa is used in the SLC programming operation for word string unit SU(2p), and word line WLb is used in the SLC programming operation for word string unit SU(2p+1).

[0144] After all word lines WL are selected, three word lines WLDD are selected sequentially. During the selection of each word line WLDD, SLC programming actions are performed on each group of pseudo-units of each word string unit SU connected to the selected word line WL.

[0145] Like the memory unit (MC), the pseudo-cell is configured to be programmable via SLC, such as from... Figure 9 The threshold voltage is set as shown in the second layer of the diagram starting from the top.

[0146] A semiconductor memory device stores data of the upper page of one word line (WL) for each pseudo-cell group of at least three word lines (WLDD).

[0147] Figure 12 This is a flowchart illustrating an example of a series of processes performed by the semiconductor memory device 1 in an embodiment, involving SLC programming operations for a second memory group. Figure 12 The series of processes shown is also performed on the pseudo-unit group. Figure 12 The series of processes shown is an example of the first action. Figure 12 The series of processes shown is executed through the cooperation of the circuitry of the embodiment, namely the sequence generator 13, the driver module 14, the line decoder module 15, and the sense amplifier module 16.

[0148] First, the semiconductor memory device 1 receives data from the upper page from the memory controller 2 (step 101). Then, the semiconductor memory device 1 stores the received upper page data into the memory connected to the memory controller 2 via an SLC programming operation. Figure 11 The word lines WL selected in the order shown belong to the order of selection. Figure 11 The second memory group of the sequentially selected string unit SU is shown (step 102). Next, a series of processes for SLC programming operations on one of the second memory groups concludes.

[0149] Furthermore, in the SLC programming operation, the final storage terminal is the upper part of the second memory group connected to word line WLi and belonging to word string unit SUj. During the first stage of the programming operation, this data is stored in the second memory group connected to word line WL(i+3) and belonging to word string unit SUj. Additionally, Figure 12 In the example shown, i is an integer from 0 to 63, and j is an integer from 0 to 15.

[0150] Thus, the reason why the upper data is stored in word line WL, which is 3 word lines away from the final storage end on the bit line BL side, is that due to the inter-cell interference when performing the second-stage programming operation and the third-stage programming operation on each of the second memory groups connected to word line WLi, it is impossible to read the data stored in the upper pages of word line WL(i+1) and word line WL(i+2) without error.

[0151] Furthermore, the upper-level data of the second memory group connected to word line WL61 and belonging to word string unit SUj, which is the final storage end, is stored, for example, in the pseudo-cell group connected to word line WLDD2 and belonging to word string unit SUj during the programming operation of the first stage. Additionally, the upper-level data of the second memory group connected to word line WL62 and belonging to word string unit SUj, which is the final storage end, is stored, for example, in the pseudo-cell group connected to word line WLDD1 and belonging to word string unit SUj. Furthermore, the upper-level data of the second memory group connected to word line WL63 and belonging to word string unit SUj is stored, for example, in the pseudo-cell group connected to word line WLDD0 and belonging to word string unit SUj.

[0152] Furthermore, for each of the second memory groups connected to each of the word lines WL0 to WL2, one page of arbitrary data can be stored during the programming operation in the first stage.

[0153] The word line WL at the final storage end of the upper data and the word line WL at the storage end of the upper data described in the first stage of programming are not limited to three word lines WL. The word line WL at the final storage end of the upper data and the word line WL at the storage end of the upper data described in the first stage of programming can also be four or more word lines WL. When the word line WL at the final storage end of the upper data and the word line WL at the storage end of the upper data described in the first stage of programming are four or more word lines WLDD to WLDS, each BLK has four or more word lines WLDD to WLDS connecting the pseudo-unit groups of each string unit SU, and the first stage of programming is performed on each pseudo-unit group connected to the four or more word lines WLDD to WLDS.

[0154] Figure 13 , Figure 14 , Figure 15 and Figure 16 This is a diagram illustrating an example of the execution sequence of the second and third stages of programming operations in the semiconductor memory device 1 according to an embodiment. Figure 13 , Figure 14 , Figure 15 and Figure 16 The arrows indicate the sequence of the programming actions in Stage 2 (TLC programming) and Stage 3 (QLC programming). Furthermore, the content shown in these diagrams follows a specific order. Figure 2 Examples of its composition.

[0155] For the block BLK that completes the programming actions in the first stage, firstly as follows: Figure 13 As shown, TLC programming operations are performed on all second memory groups connected to word line WL0 in the order of word string cell numbering.

[0156] Because the threshold voltage shift of the TLC programming operation is larger than that of the SLC or QLC programming operations, data stored via the SLC programming operation cannot be read accurately from the second memory group in adjacent word lines (WL). Therefore, for example... Figure 13 As shown, if a TLC programming operation is performed on the five second memory groups connected to word line WL0 and belonging to word string units SU0 to SU4, then the data stored by the SLC programming operation cannot be read without error from the five second memory groups connected to word line WL1 and belonging to word string units SU0 to SU4.

[0157] After the TLC programming operations for all second memory groups connected to word line WL0 are completed, as follows Figure 14 As shown, TLC programming operations are performed on all second memory groups connected to word line WL1 in the order of word string cell numbering.

[0158] After performing TLC programming operations on all second memory groups connected to word line WL1, for the reasons stated above, it is not possible to read the data stored by the SLC programming operations without error on all second memory groups connected to word line WL1.

[0159] Next, as Figure 15 As shown, QLC programming actions are performed on all second memory groups connected to word line WL0 in the order of word string cell numbering.

[0160] The following, such as Figure 16 As shown, the process is repeated: for all second memory groups connected to word line WL(i+1), TLC programming operations are performed in word string cell numbering order; subsequently, for all second memory groups connected to word line WLi, QLC programming operations are performed in word string cell numbering order. Thus, for each unit cell connected to each word line WL, data storage of 4 pages is completed.

[0161] Thus, the execution order of the second-stage programming operation and the third-stage programming operation is determined by performing the second-stage programming operation on all second memory groups connected to two adjacent word lines WL, and then performing the third-stage programming operation on all second memory groups connected to one of the two word lines WL.

[0162] Figure 17 This is a flowchart illustrating an example of a series of processes performed by the semiconductor memory device 1 according to an embodiment for TLC programming operations on a second memory group. The flowchart shows the sequence of TLC programming operations performed on the second memory group connected to the word line WLi. Figure 17 The series of processes shown is an example of the second action. Figure 17 The series of processes shown is executed through the cooperation of the circuitry of the embodiment, namely the sequence generator 13, the driver module 14, the line decoder module 15, and the sense amplifier module 16.

[0163] Semiconductor memory device 1 transfers data from the upper page of the second memory group, which is pre-stored on word line WL(i+3), to data register 17 (step 201). Semiconductor memory device 1 receives data from the lower page and the middle page from memory controller 2 (step 202). Subsequently, semiconductor memory device 1 stores three pages of data—including the lower page data and the middle page data received in step 201, and the upper page data obtained from data register 17 in step 201—into the second memory group connected to word line WLi through a TLC programming operation (step 203). Then, the series of processes for the TLC programming operation of one second memory group ends.

[0164] in addition, Figure 17 In the series of processes shown, the execution order of steps 201 and 202 is not limited to the order described above. Step 202 may also be executed before step 201.

[0165] Figure 18 This is a flowchart illustrating an example of a series of processes performed by the semiconductor memory device 1 of the embodiment for QLC programming operations on a second memory group. In this figure, a series of processes are shown where the QLC programming operations are performed on the second memory group connected to the word line WLi. Figure 18 The series of processes shown is executed through the cooperation of the circuitry of the embodiment, namely the sequence generator 13, the driver module 14, the line decoder module 15, and the sense amplifier module 16.

[0166] Semiconductor memory device 1 transfers data pre-stored in the upper pages of the second memory group connected to word line WL(i+3) from the second memory group to data register 17 (step 301). Semiconductor memory device 1 further transfers data from the data storage terminals of the QLC programming operation, namely the data pre-stored in the lower and middle pages of the second memory group connected to word line WLi, from the second memory group to data register 17 (step 302). In addition, semiconductor memory device 1 receives data from the top page from memory controller 2 (step 303).

[0167] Subsequently, the semiconductor memory device 1 stores four pages of data—including the data from the lower and middle pages obtained from the data register 17 in step 302, the data from the upper page obtained from the data register 17 in step 301, and the data from the top page received in step 303—in the second memory group connected to the word line WLi via a QLC programming operation (step 304). Then, the series of QLC programming operations for one of the second memory groups concludes.

[0168] in addition, Figure 18 In the series of processes shown, the execution order of steps 301 to 303 is not limited to the order described above. The execution order of steps 301 to 303 can be arbitrarily changed.

[0169] The above explanation focuses on an example of storing data in a storage unit (MC) using a QLC (Quick Data Library) approach. However, storing data in the MC is not limited to QLC. For example, a PLC approach can be used to store 5 bits of data in the MC, or a method can be used to store 6 or more bits of data in the MC.

[0170] Figure 19This diagram illustrates an example of encoding multi-stage programming actions for implementation methods when using a PLC. According to the encoding example shown in this diagram, the data "11111" corresponds to state S0, "11110" corresponds to state S1, "11100" corresponds to state S2, "11101" corresponds to state S3, "11001" corresponds to state S4, "11011" corresponds to state S5, "11010" corresponds to state S6, and "11000" corresponds to state S7. Establish correspondences: data "01000" corresponds to state S8; data "01001" corresponds to state S9; data "01011" corresponds to state S10; data "01010" corresponds to state S11; data "01110" corresponds to state S12; data "01100" corresponds to state S13; data "01101" corresponds to state S14; and data "01111" corresponds to state S15. Accordingly, data "00111" corresponds to state S16, data "00110" corresponds to state S17, data "00100" corresponds to state S18, data "00101" corresponds to state S19, data "00001" corresponds to state S20, data "00011" corresponds to state S21, data "00010" corresponds to state S22, and data "00000" corresponds to state S23. The data "10000" corresponds to state S24, "10001" corresponds to state S25, "10011" corresponds to state S26, "10010" corresponds to state S27, "10110" corresponds to state S28, "10100" corresponds to state S29, "10101" corresponds to state S30, and "10111" corresponds to state S31. When the data is denoted as "abcde", "a" indicates a position belonging to the basic page, "b" indicates a position belonging to the lower page, "c" indicates a position belonging to the middle page, "d" indicates a position belonging to the upper page, and "e" indicates a position belonging to the top page.

[0171] according to Figure 19 The coding shown in the diagram involves storing data for the middle page in the first stage of programming. In the second stage, data for the base page and the lower page is additionally stored. Furthermore, in the third stage, data for the upper page and the top page is further additionally stored.

[0172] Furthermore, in the example described above, during the second stage of programming, two pages of data are appended to each memory unit MC. The number of bits in the data stored during the second stage of programming only needs to be 2 or more. That is, if we set the number of bits of the final data stored in the memory unit MC to N, and the number of bits of the data appended to the memory unit MC during the second stage of programming to M, then if N is an integer greater than 4, M is an integer greater than 2, and 1 + M < N, then N and M can be arbitrarily set.

[0173] As described above, the circuitry of the embodiment, namely the sequence generator 13, driver module 14, line decoder module 15, and sense amplifier module 16, performs the first operation on the multiple memory cell groups (i.e., the multiple second memory groups) (e.g., refer to...). Figure 11 The first action includes: receiving 1 bit of the first data from the outside for each memory cell (e.g., reference...). Figure 12 Step 101); to be in 2 N Within the first interval on the lowest voltage side of each interval, two separate first distributions corresponding to the first data are formed (e.g., referencing from...). Figure 9 The threshold voltage of multiple memory cells is set in the way of the second layer of the diagram from the top (e.g., reference). Figure 12 Step 102). After the first operation for a plurality of memory cell groups, the circuit performs a second operation for each of two adjacent second word lines connected in the plurality of first word lines (e.g., refer to...). Figure 13 , Figure 14 The second action includes: from a group of memory cells connected to one of the two second word lines (i.e., the third word line) that is more than three word lines away from the first word line (i.e., the fourth word line), based on the two first distributions, reading one bit of second data from each group of memory cells (e.g., referencing...). Figure 17 Step 201); Receive M bits of the third data from the outside for each memory cell (e.g., reference...) Figure 17 Step 202); and for each storage cell, to assign the 2 bits corresponding to the (1+M) bits of the fourth data containing the second and third data to the storage cell. (1 +M) The second distribution (e.g., reference from) Figure 9 The third layer of the diagram (from the topmost layer) is arranged in units of two, setting the threshold voltage (e.g., reference) for multiple memory cells within the memory cell group connected to the third word line. Figure 17 Step 203). Furthermore, after the second operation for the memory cell group connected to each of the two second word lines, the circuit performs a third operation for the memory cell group connected to one of the two second word lines, namely the fifth word line (see, for example, reference...). Figure 15 , Figure 16The third action includes: from the first word line that is more than three word lines away from the fifth word line (i.e., the sixth word line), based on two first word distributions, reading one bit of the fifth data for each memory cell (e.g., refer to...). Figure 18 Step 301); Based on 2 (1+M) The second distribution reads M bits of the sixth data from each memory cell of the fifth word line (e.g., reference). Figure 18 Step 302); Receive (NM-1) bits of the 7th data (e.g., reference) from the outside for each memory cell. Figure 18 Step 303); and for each storage cell, the 2 bits corresponding to the N bits of the 8th data containing the 5th data, 6th data, and 7th data are... N The third distribution is set at 2 N A range (e.g., reference) Figure 18 Step 304).

[0174] The storage controller 2 does not need to store the 1 bit of data stored in the storage unit MC through the first stage programming action and the M bits of data stored in the storage unit MC through the second stage programming action in the buffer memory 3 until all bits of data have been stored. Therefore, compared with the configuration that performs fuzzy-fine programming actions, the amount of data that should be pre-stored in the buffer memory 3 of the storage controller 2 can be significantly reduced.

[0175] Furthermore, since as many bits of data as possible are stored in the programming operation from the last stage to the previous stage, that is, the second stage programming operation, the threshold voltage of each memory cell MC can be set near the target range R through the second stage programming operation. As a result, in the last stage programming operation, that is, the shift of the threshold voltage is suppressed, so the decrease in data reliability caused by mutual interference between cells can be suppressed.

[0176] In other words, according to the implementation method, the amount of data that needs to be pre-stored in the storage controller 2 can be reduced without compromising the reliability of the data.

[0177] Furthermore, according to the implementation, the block BLK includes at least three pseudo 7th word lines (e.g., word line WLDD) and a plurality of pseudo memory cell groups (i.e., pseudo cell groups) connected to each of the at least three pseudo 7th word lines. The circuit performs the first operation (e.g., referring to...) on each of the plurality of pseudo memory cell groups connected to each of the at least three pseudo 7th word lines. Figure 11 ).

[0178] As described above, the circuit stores data through the first-stage programming operation at a position more than three word lines (WL) away from the word lines of the second memory group connected to the final storage terminal. Therefore, for a single block BLK, storing the amount of data for all the second memory groups it contains through the first-stage programming operation requires a lengthy storage area of ​​more than three word lines (WL). In this embodiment, the block BLK has more than three lengthy word lines (WLDD) and pseudo-cell groups connected to the word lines (WLDD). Thus, the block BLK can store the data for all the second memory groups stored through the first-stage programming operation within the block BLK.

[0179] Furthermore, according to the implementation method, the circuit is, for example, as follows Figure 11 As shown, after performing the first action on all second memory groups and all pseudo memory groups connected to the word line WLDD, the second action begins.

[0180] Furthermore, if the circuit performs the first operation on a second memory group connected to each of at least four word lines WL arranged in a continuous sequence, then the first operation can be performed on a second memory group connected to one of the four word lines WL.

[0181] Furthermore, according to the embodiment, a plurality of second memory groups include: a memory cell MC (denoted as a first memory cell MC); and a second memory cell MC, belonging to a different second memory group than the first memory cell MC, and sharing a channel with the first memory cell MC. The first memory cell MC and the second memory cell MC belong to the same first memory group MG and are opposite to each other. When reading from the first memory cell MC, the circuit applies a voltage VBB to the word line WL connected to the second memory cell MC. N The lower limit of the interval R0 on the lowest voltage side of the interval is less than the voltage VBB.

[0182] During a read operation of the first memory cell MC, a voltage VBB is applied to the gate electrode of the second memory cell MC, causing the second memory cell MC to become non-conductive. Therefore, the cell current Icell, corresponding to the threshold voltage of the first memory cell MC, flows from the bit line BL to the source line SL. Thus, the data stored in the first memory cell MC can be read appropriately.

[0183] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included within the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

[0184] [Symbol Explanation]

[0185] 1: Semiconductor memory devices

[0186] 2: Storage Controller

[0187] 3: Buffer memory

[0188] 10: Memory cell array

[0189] 11: Command Register

[0190] 12: Address Register

[0191] 13: Sequence Generator

[0192] 14: Driver Module

[0193] 15: Line decoder module

[0194] 16: Sensing Amplifier Module

[0195] 17: Data Register

[0196] 20: Core Components

[0197] 21: Semiconductor layer

[0198] 22: Tunnel insulation film

[0199] 23: Insulating film

[0200] 24: Barrier insulating film

[0201] 30: Semiconductor substrate.

Claims

1. A semiconductor memory device comprising: Multiple groups of storage cells; each storage cell is configured to store 2 and a set threshold voltage. N N bits of data corresponding to each interval; Multiple first word lines are respectively connected to any one of the multiple memory cell groups; and Circuit; and Perform the first action on the plurality of memory cell groups; The first action includes: receiving 1 bit of first data from an external source for each storage cell; and in the second... N Within the first interval on the lowest voltage side of the interval, two separate first distributions corresponding to the first data are formed, and threshold voltages for multiple storage cells are set. After the first action for the plurality of memory cell groups, the second action is performed on the memory cell group connected to each of the two adjacent second word lines in the plurality of first word lines. The second action includes: based on the two first distributions, reading 1 bit of second data from each of the group of storage cells connected to the plurality of first word lines that are more than 3 word lines away from one of the two second word lines (i.e., the third word line); and receiving M (wherein, The third data (1+M<N) bits; and for each storage cell, to assign 2 bits corresponding to the fourth data (1+M) bits containing the second and third data. (1+M) The second distribution is formed in such a way that each pair of units is separated, and the threshold voltage of the multiple memory units contained in the memory unit group connected to the third word line is set. After the second action is performed on the group of memory cells connected to each of the two second word lines, the third action is performed on the group of memory cells connected to one of the two groups of second word lines, namely the fifth word line. The third action includes: based on the two first distributions, reading one bit of the fifth data from each storage unit from the sixth word line (a first word line that is more than three positions away from the fifth word line) among the plurality of first word lines; based on the two... (1+M) The second distribution reads M bits of the 6th data from the 5th word line for each storage cell; for each storage cell, receives (NM-1) bits of the 7th data from the outside; and for each storage cell, assigns 2 bits of the 8th data corresponding to the N bits containing the 5th data, the 6th data, and the 7th data. N The third distribution is set in the 2 N A range.

2. The semiconductor memory device according to claim 1, comprising: The block comprises: the plurality of memory cell groups and the plurality of first word lines; at least three pseudo seventh word lines; and a plurality of pseudo memory cell groups connected to each of the at least three pseudo seventh word lines; The circuit performs the first action for each of the plurality of pseudo memory cell groups connected to each of the at least three pseudo seventh word lines.

3. The semiconductor memory device according to claim 1, wherein... After the first operation is completed for all of the plurality of memory cell groups connected to the plurality of first word lines, the circuit begins the second operation for each of the memory cell groups connected to the two second word lines.

4. The semiconductor memory device according to claim 2, wherein After the circuit completes the first operation for each of the plurality of memory cell groups connected to the plurality of first word lines and for each of the plurality of pseudo memory groups connected to each of the at least three pseudo seventh word lines, it begins the second operation for the memory cell groups connected to each of the two second word lines.

5. The semiconductor memory device according to claim 1, wherein... The plurality of storage cell groups include: a first storage cell; and a second storage cell, which belongs to a different storage cell group than the first storage cell and shares a channel with the first storage cell; When the circuit reads from the first memory cell, it applies a voltage of a first value to the word line among the plurality of first word lines that is connected to the second memory cell. The first value is less than the lower limit of the first interval.

6. The semiconductor memory device according to claim 2, wherein The plurality of storage cell groups include: a first storage cell; and a second storage cell, which belongs to a different storage cell group than the first storage cell and shares a channel with the first storage cell; When the circuit reads from the first memory cell, it applies a voltage of a first value to the word line among the plurality of first word lines that is connected to the second memory cell. The first value is less than the lower limit of the first interval.

7. The semiconductor memory device according to claim 3, wherein The plurality of storage cell groups include: a first storage cell; and a second storage cell, which belongs to a different storage cell group than the first storage cell and shares a channel with the first storage cell; When the circuit reads from the first memory cell, it applies a voltage of a first value to the word line among the plurality of first word lines that is connected to the second memory cell. The first value is less than the lower limit of the first interval.

8. The semiconductor memory device according to claim 4, wherein The plurality of storage cell groups include: a first storage cell; and a second storage cell, which belongs to a different storage cell group than the first storage cell and shares a tunnel with the first storage cell; When the circuit reads from the first memory cell, it applies a voltage of a first value to the word line among the plurality of first word lines that is connected to the second memory cell. The first value is less than the lower limit of the first interval.

9. A method for controlling a memory cell array, the memory cell array comprising: a plurality of memory cell groups, each memory cell configured to store 2 with a set threshold voltage. N The method comprises: N bits of data corresponding to each interval; and multiple first word lines, each connected to any one of the multiple memory cell groups; the method includes: Perform the first action on the plurality of memory cell groups; The first action includes: receiving 1 bit of first data from an external source for each storage unit; and in the second... N The first interval on the lowest voltage side of the interval is formed into two separate first distributions corresponding to the first data, and the threshold voltage of multiple storage cells is set. After the first action for the plurality of memory cell groups, the second action is performed on the memory cell group connected to each of the two adjacent second word lines in the plurality of first word lines. The second action includes: based on the two first distributions, reading 1 bit of second data from each of the group of storage cells connected to the plurality of first word lines that are more than 3 bits away from one of the two second word lines (i.e., the third word line); and for each storage cell, receiving M (where M is the number of bits of data that is the first word line) from the outside. The third data (1+M<N) bits; and for each storage cell, to assign 2 bits corresponding to the fourth data (1+M) bits containing the second and third data. (1+M) The second distribution is formed in units of two, and the threshold voltage of the multiple memory cells included in the memory cell group connected to the third word line is set. After the second action is performed on the group of memory cells connected to each of the two second word lines, the third action is performed on the group of memory cells connected to one of the two groups of second word lines, namely the fifth word line. The third action includes: based on the two first distributions, reading one bit of the fifth data from each storage unit from the sixth word line (a first word line that is more than three positions away from the fifth word line) among the plurality of first word lines; based on the two... (1+M) In the second distribution, for each storage cell, M bits of the sixth data are read from the fifth word line; for each storage cell, (NM-1) bits of the seventh data are received from the outside; and for each storage cell, 2 bits of the eighth data corresponding to the N bits containing the fifth, sixth, and seventh data are distributed. N The third distribution is set in the 2 N A range.

10. The method of claim 9, wherein The storage cell array includes a block comprising: the plurality of storage cell groups and the plurality of first word lines; at least three pseudo seventh word lines; and a plurality of pseudo storage cell groups connected to each of the at least three pseudo seventh word lines; The method further includes performing the first action for each of the plurality of pseudo memory cell groups connected to each of the at least three pseudo seventh word lines.

11. The method of claim 9, further comprising: After the first action is completed for all of the plurality of memory cell groups connected to the plurality of first word lines, the second action begins for each of the memory cell groups connected to the two second word lines.

12. The method of claim 10, further comprising: After the first action is completed for each of the plurality of memory cell groups connected to the plurality of first word lines and for each of the plurality of pseudo-cell groups connected to each of the at least three pseudo-seventh word lines, the second action is started for the memory cell groups connected to each of the two second word lines.

13. The method of claim 9, wherein The plurality of storage cell groups include: a first storage cell; and a second storage cell, which belongs to a different storage cell group than the first storage cell and shares a channel with the first storage cell; The method includes: during a read operation of the first group of memory cells, applying a voltage of a first value to the word lines of the plurality of first word lines connected to the second memory cell. The first value is less than the lower limit of the first interval.

14. The method of claim 10, wherein The plurality of storage cell groups include: a first storage cell; and a second storage cell, which belongs to a different storage cell group than the first storage cell and shares a channel with the first storage cell; The method includes: during a read operation of the first group of memory cells, applying a voltage of a first value to the word lines of the plurality of first word lines connected to the second memory cell. The first value is less than the lower limit of the first interval.

15. The method of claim 11, wherein The plurality of storage cell groups include: a first storage cell; and a second storage cell, which belongs to a different storage cell group than the first storage cell and shares a channel with the first storage cell; The method includes: during a read operation of the first group of memory cells, applying a voltage of a first value to the word lines of the plurality of first word lines connected to the second memory cell. The first value is less than the lower limit of the first interval.

16. The method of claim 12, wherein The plurality of storage unit groups include: a first storage unit; and a second storage unit, which is a different storage unit from the first storage unit and shares a channel with the first storage unit; The method includes: during a read operation of the first group of memory cells, applying a voltage of a first value to the word lines of the plurality of first word lines connected to the second memory cell. The first value is less than the lower limit of the first interval.

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