A method for implementing a pulse interference detection and elimination circuit

Abstract

The purpose of this invention is to provide a method for implementing pulse interference detection and elimination circuitry, comprising the following steps: S1: Data from the analog-to-digital converter is input to a data buffer circuit; S2: The data from the analog-to-digital converter is simultaneously input to a numerical judgment and statistics circuit; S3: The numerical judgment and statistics circuit detects and statistically analyzes the interference in the data from the analog-to-digital converter; S4: The data buffer circuit outputs delayed data to a data clearing selection circuit; S5: The data clearing selection circuit outputs the data. This invention can achieve pulse interference detection and elimination. Pulse interference typically exhibits a much higher concentration in the time domain than background noise, and the amplitude of sample data affected by pulse interference is significantly higher than at other locations. This method can be implemented without delay and only triggers processing when interference is present.

Description

Technical Field

[0001] This invention relates to the field of navigation receiver technology, and in particular to a method for implementing a pulse interference detection and cancellation circuit. Background Technology

[0002] In satellite navigation systems, if the pulse signal and the navigation signal are in the same frequency band, it will affect the performance of the navigation system and may even cause the receiver to malfunction. The magnitude of this impact depends on the strength, duty cycle, and period of the pulse signal. Satellite navigation receivers are typical direct-sequence spread-spectrum receivers, and one of their main characteristics is weak received signals, making them susceptible to pulse interference. Therefore, a special circuit needs to be designed to detect and eliminate pulse interference. Summary of the Invention

[0003] To address the problem of pulse interference affecting satellites, this invention provides a method for implementing pulse interference detection and elimination circuitry.

[0004] A method for implementing a pulse interference detection and cancellation circuit includes the following steps:

[0005] S1: Data input to the data buffer circuit of the analog-to-digital converter;

[0006] S2: The data from the analog-to-digital converter is simultaneously input to the numerical judgment and statistical circuit;

[0007] S3: The numerical judgment and statistical circuit detects and statistically analyzes interference in the data of the analog-to-digital converter;

[0008] S4: The data buffer circuit outputs delayed data to the data clearing selection circuit;

[0009] S5: The data clearing selection circuit outputs the data.

[0010] Furthermore, in a method for implementing pulse interference detection and elimination circuit, step S1 further includes a shift register in the data storage circuit for buffering data at a depth that is affected by the application scenario.

[0011] Furthermore, in a method for implementing a pulse interference detection and cancellation circuit, step S2 further includes the following sub-steps:

[0012] S21: Average the energy of the length of the data from the analog-to-digital converter;

[0013] S22: Calculate the interference threshold;

[0014] S23: Threshold equals average energy plus 6 dB;

[0015] S24: Interference Detection

[0016] If the energy of two points in the statistical length is greater than the threshold, it is naturally determined that there is pulse interference in that time period.

[0017] If the energy of no more than two points in the statistical length is greater than the threshold, it is naturally determined that there is no pulse interference in that time period.

[0018] S25: The data buffer circuit generates a data clear flag and a data selection flag;

[0019] S26:

[0020] The generated data clearing flag is output to the data buffer circuit;

[0021] The generated data selection flag is output to the data selection clearing circuit.

[0022] Furthermore, in a method for implementing pulse interference detection and elimination circuit, step S26 further includes clearing all data and subsequent data in the shift register using a data clearing flag.

[0023] Furthermore, a method for implementing a pulse interference detection and elimination circuit is provided, wherein the circuit of the method includes a data buffer circuit, a numerical judgment and statistics circuit, and a data clearing selection circuit.

[0024] Furthermore, a method for implementing a pulse interference detection and cancellation circuit is provided, wherein the data buffer circuit functions to store data from the analog-to-digital converter, which is achieved through a shift register.

[0025] Furthermore, a method for implementing a pulse interference detection and elimination circuit is provided, wherein the function of the numerical judgment and statistics circuit is to set the interference threshold, and to output the statistics of interference points and the zeroing flag within a certain time period.

[0026] Furthermore, a method for implementing a pulse interference detection and elimination circuit is provided, wherein the data clearing selection circuit function includes outputting delayed data or setting the delayed data to zero.

[0027] The beneficial effects of the present invention are as follows: By implementing a pulse interference detection and elimination circuit method, pulse interference can be detected and eliminated. The clustering of pulse interference in the time domain is usually much higher than that of background noise, and the amplitude of sample data affected by pulse interference is significantly higher than that of other locations. This method can be implemented without delay and is only triggered for processing when interference exists. Attached Figure Description

[0028] Figure 1 This is a schematic diagram illustrating the implementation of pulse interference detection and cancellation.

[0029] Figure 2 This is a flowchart of the present invention. Implementation

[0030] To provide a clearer understanding of the technical features, objectives, and effects of the present invention, specific embodiments of the present invention will now be described with reference to the accompanying drawings.

[0031] As attached Figure 1 As shown, a method for implementing a pulse interference detection and cancellation circuit includes the following steps:

[0032] S1: Data input to the data buffer circuit of the analog-to-digital converter;

[0033] S2: The data from the analog-to-digital converter is simultaneously input to the numerical judgment and statistical circuit;

[0034] S3: The numerical judgment and statistical circuit detects and statistically analyzes interference in the data of the analog-to-digital converter;

[0035] S4: The data buffer circuit outputs delayed data to the data clearing selection circuit;

[0036] S5: The data clearing selection circuit outputs the data.

[0037] Furthermore, in a method for implementing pulse interference detection and elimination circuit, step S1 further includes a shift register in the data storage circuit for buffering data at a depth that is affected by the application scenario.

[0038] Furthermore, in a method for implementing a pulse interference detection and cancellation circuit, step S2 further includes the following sub-steps:

[0039] S21: Average the energy of the length of the data from the analog-to-digital converter;

[0040] S22: Calculate the interference threshold;

[0041] S23: Threshold equals average energy plus 6 dB;

[0042] S24: Interference Detection

[0043] If the energy of two points in the statistical length is greater than the threshold, it is naturally determined that there is pulse interference in that time period.

[0044] If the energy of no more than two points in the statistical length is greater than the threshold, it is naturally determined that there is no pulse interference in that time period.

[0045] S25: The data buffer circuit generates a data clear flag and a data selection flag;

[0046] S26:

[0047] The generated data clearing flag is output to the data buffer circuit;

[0048] The generated data selection flag is output to the data selection clearing circuit.

[0049] Furthermore, in a method for implementing pulse interference detection and elimination circuit, step S26 further includes clearing all data and subsequent data in the shift register using a data clearing flag.

[0050] Furthermore, a method for implementing a pulse interference detection and elimination circuit is provided, wherein the circuit of the method includes a data buffer circuit, a numerical judgment and statistics circuit, and a data clearing selection circuit.

[0051] Furthermore, a method for implementing a pulse interference detection and cancellation circuit is provided, wherein the data buffer circuit functions to store data from the analog-to-digital converter, which is achieved through a shift register.

[0052] Furthermore, a method for implementing a pulse interference detection and elimination circuit is provided, wherein the numerical judgment and statistics circuit functions to set an interference threshold, count interference points within a certain time period, and output a zeroing flag.

[0053] Furthermore, a method for implementing a pulse interference detection and elimination circuit is provided, wherein the data clearing selection circuit function includes outputting delayed data or setting the delayed data to zero.

[0054] As attached Figure 2 As shown, the specific operation process of Example 1 is as follows:

[0055] (a) Input 16-bit wide ADC data into the data buffer circuit. The data enters a shift register with a depth of 256 for buffering. The buffer depth can be changed according to different application scenarios.

[0056] (b) The ADC data is simultaneously fed into the numerical judgment and statistical circuit for interference detection and statistics;

[0057] Furthermore, step (b) includes the following steps:

[0058] (b1) Perform average energy statistics on ADC data with a length of 256 points. The length can be set differently according to different application scenarios.

[0059] (b2) Calculation of interference threshold: add 6dB to the average energy as the threshold. For example, if the average energy is 2500, then the threshold is 4125.

[0060] (b3) Interference determination: If there are 2 or more points with energy greater than the threshold 4125 among the 256 points counted, then it is considered that there is pulse interference in that time period.

[0061] (b4) After detecting interference, a clear flag and a data selection flag are generated. Due to the trailing phenomenon of pulse interference, the flag is generated to clear all data in the shift register and the subsequent 256 data points.

[0062] (c) Data clearing selection circuit, receive data selection flag, select whether to output buffered data or cleared data.

[0063] After repeating steps (a), (b), and (c) above, impulse interference detection and elimination can be achieved. The clustering of impulse interference in the time domain is usually much higher than that of background noise, and the amplitude of sample data affected by impulse interference is significantly higher than that of other locations. This method can be implemented without delay and is only triggered for processing when interference exists.

[0064] This solution implements a pulse interference detection and elimination circuit method, which can realize pulse interference detection and elimination. The clustering of pulse interference in the time domain is usually much higher than that of background noise, and the amplitude of sample data affected by pulse interference is significantly higher than that of other locations. This method can be implemented without delay and is only triggered for processing when interference exists.

[0065] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of this invention is defined by the appended claims and their equivalents.

Claims

1. A method for implementing a pulse interference detection and cancellation circuit, characterized in that, Includes the following steps: S1: Data input to the data buffer circuit of the analog-to-digital converter; S2: The data from the analog-to-digital converter is simultaneously input to the numerical judgment and statistical circuit, including the following sub-steps: S21: Average the energy of the length of the data from the analog-to-digital converter; S22: Calculate the interference threshold; S23: Threshold equals average energy plus 6 dB; S24: Interference Detection If the energy of two points in the statistical length is greater than the threshold, it is determined that there is pulse interference in that time period. If the energy of no more than two points in the statistical length is greater than the threshold, it is determined that there is no pulse interference in that time period. S25: The numerical judgment and statistical circuit generates a data clearing flag and a data selection flag; S26: The generated data clearing flag is output to the data buffer circuit; The generated data selection flag is output to the data selection clearing circuit; S3: The numerical judgment and statistical circuit detects and statistically analyzes interference in the data of the analog-to-digital converter; S4: The data buffer circuit outputs delayed data to the data clearing selection circuit; S5: The data clearing selection circuit outputs the data.

2. The method for implementing a pulse interference detection and cancellation circuit according to claim 1, characterized in that, The S1 also includes a shift register in the data storage circuit for caching the data entry depth, which is affected by the application scenario.

3. The method for implementing a pulse interference detection and cancellation circuit according to claim 1, characterized in that, S26 further includes clearing the data zeroing flag to clear all data and subsequent data in the shift register.

4. The method for implementing a pulse interference detection and cancellation circuit according to claim 1, characterized in that, The circuit of the pulse interference detection and elimination circuit implementation method includes a data buffer circuit, a numerical judgment and statistics circuit, and a data clearing selection circuit.

5. The method for implementing a pulse interference detection and cancellation circuit according to claim 4, characterized in that, The data buffer circuit is used to store data from the analog-to-digital converter, which is achieved through a shift register.

6. The method for implementing a pulse interference detection and cancellation circuit according to claim 4, characterized in that, The numerical judgment and statistics circuit functions to set the interference threshold, count the interference points within a preset time, and output the zeroing flag.

7. The method for implementing a pulse interference detection and cancellation circuit according to claim 4, characterized in that, The data clearing selection circuit function includes outputting delayed data or setting delayed data to zero.

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