Constant power control circuit and electronic device

Abstract

The application provides a constant power control circuit, comprising a PWM unit, an output dynamic adjustable duty ratio PWM signal; a load branch, comprising a load resistor, outputting constant power according to the dynamic adjustable duty ratio PWM signal; a load mirror branch, comprising a mirror load resistor, a first current flowing through the load resistor and a second current flowing through the mirror load resistor being in a first preset proportion; a conversion circuit converting a voltage of the load resistor into a third current and converting a voltage of the mirror load resistor into a fourth current; an energy storage unit charging by using the third current and the fourth current respectively; a counting unit converting a charging time of the energy storage unit into a digital parameter; a logic control unit calculating real-time power of the load according to the digital parameter, and dynamically adjusting a duty ratio of the PWM signal output by the PWM unit according to the real-time power, so as to realize constant output of the load power.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to a constant power control circuit and electronic device. Background Technology

[0002] In consumer power products, lithium batteries are increasingly used in various applications. Typically, the output voltage of a lithium battery gradually decreases as the battery charge diminishes. To maximize battery life per charge, electronic devices fully utilize the battery's output voltage range. For example, given that lithium batteries have an output voltage range of 4.2V to 3V, conventional electronic devices are designed to operate normally within this voltage range.

[0003] However, in some applications, as the battery voltage decreases, the output power of the lithium battery will gradually decrease, making it impossible to guarantee constant power output and affecting the user's experience with electronic products. Summary of the Invention

[0004] The purpose of this invention is to provide a constant power control circuit and electronic device that can solve the above-mentioned problems.

[0005] One aspect of this invention provides a constant power control circuit, including a PWM unit for outputting a dynamically adjustable duty cycle PWM signal; a load branch electrically connected to the PWM unit, the load branch including a load resistor, the load resistor outputting constant power according to the dynamically adjustable duty cycle PWM signal; a load mirror branch electrically connected to the load branch, the load mirror branch including a mirror load resistor, a first current flowing through the load resistor and a second current flowing through the mirror load resistor forming a first preset ratio; a conversion circuit electrically connected to the load branch and the load mirror branch, for converting the voltage of the load resistor into a third current and converting the voltage of the mirror load resistor into a fourth current; and an energy storage unit electrically connected to the load unit. The conversion circuit is used to charge the energy storage unit using the third current and the fourth current, respectively. A counting unit, electrically connected to the energy storage unit, is used to calculate the first time required for the voltage of the energy storage unit to rise to a reference voltage when charged by the third current, and to calculate the second time required for the voltage of the energy storage unit to rise to the reference voltage when charged by the fourth current. It is also used to convert the first time and the second time into a first digital parameter and a second digital parameter, respectively. A logic control unit, electrically connected to the counting unit and the PWM unit, is used to calculate the real-time power of the load resistor based on the first digital parameter and the second digital parameter, and to adjust the duty cycle of the PWM signal output by the PWM unit based on the real-time power.

[0006] Preferably, the load branch includes: a first MOSFET, the gate of which is electrically connected to the PWM unit, and the drain of which is electrically connected to the power supply; a load resistor, one end of which is electrically connected to the source of the first MOSFET, and the other end of which is grounded; the load mirror branch includes: a second MOSFET, the gate of which is electrically connected to the PWM unit, and the drain of which is electrically connected to the power supply; a third MOSFET, the source of which is electrically connected to the source of the second MOSFET; a first operational amplifier, the non-inverting input of which is electrically connected to the common terminal of the first MOSFET and the load resistor, the inverting input of which is electrically connected to the common terminal of the second MOSFET and the third MOSFET, and the output of which is electrically connected to the gate of the third MOSFET; and a mirror load resistor, one end of which is electrically connected to the drain of the third MOSFET, and the other end of which is grounded.

[0007] Preferably, the voltage across the mirrored load resistor is: V2=R2 I² = R² I1 / n; Wherein, V2 is the voltage value of the mirror load resistor, R2 is the resistance value of the mirror load resistor, I2 is the current value of the second current, I1 is the current value of the first current, and n is the first preset ratio.

[0008] Preferably, the conversion circuit includes: a switching circuit, including a first switch and a second switch, wherein a first terminal of the first switch is electrically connected to the common terminal of the load resistor and the first MOSFET, and a control terminal of the first switch is electrically connected to the logic control unit; a first terminal of the second switch is electrically connected to the common terminal of the mirrored load resistor and the third MOSFET, and a control terminal of the second switch is electrically connected to the logic control unit; a current conversion circuit, including a second operational amplifier, a fourth MOSFET, and a first resistor, wherein the non-inverting input terminal of the second operational amplifier is electrically connected to the second terminal of the first switch and the second terminal of the second switch; the gate of the fourth MOSFET is electrically connected to the output terminal of the second operational amplifier, and the drain of the fourth MOSFET is electrically connected to the power supply; one end of the first resistor is electrically connected to the first... The second operational amplifier has its inverting input terminal and the source terminal of the fourth MOS transistor connected to ground at the other end. The voltage at the non-inverting input terminal of the second operational amplifier is equal to the voltage at its inverting input terminal. When the logic control unit controls the first switch to be on and the second switch to be off, the voltage of the load resistor is input to the non-inverting input terminal of the second operational amplifier through the first switch, and the current conversion circuit converts the voltage of the load resistor into the third current flowing through the first resistor. When the logic control unit controls the first switch to be off and the second switch to be on, the voltage of the mirrored load resistor is input to the non-inverting input terminal of the second operational amplifier through the second switch, and the current conversion circuit converts the voltage of the mirrored load resistor into the fourth current flowing through the first resistor.

[0009] Preferably, the conversion circuit further includes a current mirror, the current mirror comprising: a fifth MOSFET, the drain of the fifth MOSFET being electrically connected to the drain of the fourth MOSFET and the gate of the fifth MOSFET; a sixth MOSFET, the drain of the sixth MOSFET being electrically connected to the source of the fifth MOSFET and the gate of the sixth MOSFET, the source of the sixth MOSFET being electrically connected to the power supply; a seventh MOSFET, the drain of the seventh MOSFET being electrically connected to the energy storage unit, the gate of the seventh MOSFET being electrically connected to the gate of the fifth MOSFET; and an eighth MOSFET, the drain of the eighth MOSFET being electrically connected to the source of the seventh MOSFET. The gate of the eighth MOS transistor is electrically connected to the gate of the sixth MOS transistor, and the source of the eighth MOS transistor is electrically connected to the power supply. The fifth MOS transistor and the sixth MOS transistor form a first branch. When the first switch is on and the second switch is off, the current flowing through the first branch is the third current. When the first switch is off and the second switch is on, the current flowing through the first branch is the fourth current. The seventh MOS transistor and the eighth MOS transistor form a mirror branch. The current of the first branch is mirrored to the mirror branch. The mirror current of the mirror branch is proportional to the current of the first branch in a second preset ratio.

[0010] Preferably, the energy storage unit includes: a first capacitor, one end of which is electrically connected to the drain of the seventh MOS transistor, and the other end grounded; a third switch, the first end of which is electrically connected to one end of the first capacitor, the second end of which is grounded, and the control terminal of which is electrically connected to the logic control unit; and a comparator, the non-inverting input of which is connected to the reference voltage, the inverting input of which is electrically connected to the first end of the third switch, and the output of which is electrically connected to the counting unit.

[0011] Preferably, the logic control unit is further configured to control the on / off state of the third switch to clear the charge of the first capacitor; the logic control unit is further configured to control the first switch to close, the second switch to open, and the third current of the first branch to be mirrored to the mirror branch so that the first mirror current charges the first capacitor, and the first capacitor enters a first time period of charging, wherein the third current is: I3a = V3 / R3 = V1 / R3; The first mirror current is: I4a=m I3a; among which, I4a is the first mirror current within the first time period, I3a is the current value of the third current, m is the second preset ratio, V3 is the voltage of the first resistor, R3 is the resistance value of the first resistor, and V1 is the voltage of the load resistor; when the first capacitor enters the charging phase of the first time period, the counting unit starts counting; until the voltage at the inverting input terminal of the comparator is greater than the reference voltage, and the output voltage at the output terminal of the comparator flips, the counting unit stops counting and converts the first time required for the voltage of the first capacitor to rise to the reference voltage into the first digital parameter: Data1=VR C1 / I4a= VR C1 Given R3 / V1 / m, the voltage across the load resistor is: V1 = VR C1 R3 / Data1 / m; Wherein, Data1 is the first digital parameter corresponding to the first time, VR is the reference voltage, and C1 is the capacitance value of the first capacitor.

[0012] Preferably, the counting unit is further configured to automatically reset the count after the first time period ends; the logic control unit is further configured to control the opening and closing of the third switch to reset the charge of the first capacitor after the first time period ends; the logic control unit is further configured to control the first switch to open and the second switch to open after the first capacitor is reset, so that the fourth current of the first branch is mirrored to the mirror branch, causing the second mirror current to charge the first capacitor, and the first capacitor enters the charging phase of the second time period, wherein the fourth current is: I3b=V2 / R3=R2 I1 / n / R3; The second mirror current is: I4b=m I3b= m R2 I1 / n / R3; Wherein, I3b is the current value of the fourth current; I4b is the second mirror current within the second time period; the counting unit is also used to start counting when the first capacitor enters the charging phase of the second time period, until the voltage at the inverting input of the comparator is greater than the reference voltage, and the output voltage at the output of the comparator flips, at which point counting stops, and the second time required for the voltage of the first capacitor to rise to the reference voltage is converted into a second digital parameter: Data2=VR C1 / I4b= VR C1 R3 n / (m R2 I1), then, the first current is: I1= VR C1 R3 n / (m R2 Data2) Wherein, Data2 is the second digital parameter corresponding to the second time, and R3 is the resistance value of the first resistor.

[0013] Preferably, the logic control unit calculates the real-time power of the load resistor based on the first voltage value and the first current value of the load resistor, and dynamically adjusts the duty cycle of the PWM signal based on the real-time power.

[0014] Another aspect of the present invention provides an electronic device including the constant power control circuit described in any of the preceding claims.

[0015] Compared to existing technologies, the constant power control circuit and electronic device proposed in this invention include a load branch and a mirror load branch. The voltage of the load resistor in the load branch and the mirror load resistor in the mirror load branch are converted into current at different time periods through a conversion circuit. By charging the energy storage unit with current, the voltage signal is converted into the length of the charging time. Then, the voltage signal is converted into a digital signal using a counting unit. The real-time power of the load resistor is obtained based on the converted digital signal, thereby adjusting the duty cycle of the PWM signal to achieve constant power output of the load resistor. The use of mixed digital and analog signals avoids the unavoidable nonlinear errors introduced by analog devices.

[0016] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 A schematic diagram of a constant power control circuit according to Embodiment 1 of the present invention is shown.

[0019] Figure 2 The schematic diagram illustrates a constant power control circuit according to Embodiment 1 of the present invention.

[0020] Figure 3 The diagram illustrates the charging waveform and counting unit waveform of the constant power control circuit according to Embodiment 2 of the present invention.

[0021] Figure 4 The schematic diagram illustrates the switching timing of a constant power control circuit according to Embodiment 2 of the present invention.

[0022] Explanation of key component symbols: Constant power control circuit 1 PWM Unit 10 Load branch 20 Mirrored load branch 30 Conversion circuit 40 Switching circuit 400 Current conversion circuit 401 Current mirror 402 Energy storage unit 50 Counting unit 60 Logic control unit 70 Load resistor R1 Mirror load resistor R2 First resistor R3 First switch SW1 Second switch SW2 Third switch SW3 Third current I3a Fourth current I3b Load voltage V1 Mirror load voltage V2 First resistor voltage V3 First capacitor voltage V4 Output voltage V5 First mirror current I4a Second mirror current I4b First Time T1 Second time T2 power supply VDD First MOSFET - Eighth MOSFET M1-M8 First operational amplifier A1 Second operational amplifier A2 Comparator A3 Detailed Implementation The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can be arranged and designed in various different configurations. The present invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present invention more thorough and complete. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0023] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0024] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set up," "connected," and "electrically connected" should be interpreted broadly. For example, they can refer to a direct connection or an indirect connection through an intermediate medium, or they can refer to the internal connection of two elements. It should be noted that when one element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intervening element present.

[0025] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0026] The terminology involved in this invention is explained as follows: Constant power: The output power of the circuit load is constant.

[0027] PWM: Pulse Width Modulation, a pulse signal with a fixed frequency and adjustable duty cycle.

[0028] The inventors have discovered that lithium batteries are increasingly used in consumer power products, and their output voltage typically decreases as the battery charge diminishes. To maximize battery life, electronic devices utilize the battery's output voltage range; for example, given the lithium battery's output voltage range of 4.2V to 3V, conventional electronic devices are designed to operate normally within this range. However, in certain applications, as the battery voltage decreases, the lithium battery's output power also gradually decreases, making it impossible to guarantee a constant power output.

[0029] The inventors discovered that the duty cycle of the PWM control signal can be adjusted based on the measured real-time power of the load to achieve constant output power. However, most power supply products currently use purely analog circuits for constant power output, and purely analog circuits have relatively large power control errors. Therefore, accurately controlling the output power is key to maintaining constant power output.

[0030] In view of this, embodiments of the present invention provide a constant power control circuit and an electronic device, thereby solving the problem that the electronic device cannot maintain a constant power output.

[0031] Specifically: A new constant power control circuit is provided. This new constant power control circuit includes a load branch and a mirror load branch. A conversion circuit converts the voltage of the load resistor in the load branch and the mirror load resistor in the mirror load branch into current at different time periods. By charging the energy storage unit with current, the voltage signal is converted into the length of the charging time. Then, a counting unit finally converts the voltage signal into a digital signal. The real-time power of the load resistor is obtained based on the converted digital signal, thereby adjusting the duty cycle of the PWM signal. A combination of analog and digital circuits is used to control the constant power output of the load resistor.

[0032] Example 1 Figure 1 A schematic diagram of a constant power control circuit 1 according to Embodiment 1 of the present invention is shown. The constant power control circuit 10 is mainly used in electronic devices containing batteries, such as mobile phones and tablets. Figure 1As shown, the constant power control circuit 1 includes a PWM unit 10, a load branch 20, a mirror load branch 30, a conversion circuit 40, an energy storage unit 50, a counting unit 60, and a logic control unit 70. The PWM unit 10 outputs a dynamically adjustable duty cycle PWM signal. The load branch 20 is electrically connected to the PWM unit 10 and includes a load resistor R1. According to the dynamically adjustable duty cycle PWM signal, the load resistor R1 outputs constant power. The load mirror branch 30 is electrically connected to the load branch 20 and includes a mirror load resistor R2. The first current I1 flowing through the load resistor R1 and the second current I2 flowing through the mirror load resistor R2 are in a first preset ratio. The conversion circuit 40 is electrically connected to the load branch 20 and the load mirror branch 30, and is used to convert the voltage of the load resistor R1 into a third current I3a and the voltage of the mirror load resistor R2 into a fourth current I3b. Energy storage unit 50, electrically connected to conversion circuit 40, is charged using the third current I3a and the fourth current I3b, respectively. Counter unit 60, electrically connected to energy storage unit 50, is used to calculate the first time T1 required for the voltage of energy storage unit 50 to rise to a reference voltage when charged using the third current I3a, and to calculate the second time T2 required for the voltage of energy storage unit 50 to rise to the reference voltage when charged using the fourth current I3b. It is also used to convert the first time T1 and the second time T2 into first digital parameters and second digital parameters, respectively. Logic control unit 70, electrically connected to conversion circuit 40, energy storage unit 50, counter unit 60, and PWM unit 10, is used to calculate the real-time power of load resistor R1 based on the first and second digital parameters, and to adjust the duty cycle of the PWM signal output by PWM unit 10 according to the real-time power, thereby controlling the load resistor R1 to output a constant power.

[0033] Example 2 Figure 2 A schematic diagram of the circuit structure of a constant power control circuit 1 according to Embodiment 2 of the present invention is shown. Figure 2 As shown, in this embodiment, the load branch 20 includes a first MOSFET M1 and a load circuit R1. The gate of the first MOSFET M1 is electrically connected to the PWM unit 10 and is controlled by the PWM unit 10. The drain of the first MOSFET M1 is electrically connected to the power supply VDD. The load resistor R1 has one end electrically connected to the source of the first MOSFET M1 and the other end grounded. In a specific embodiment of the present invention, the first MOSFET M1 is a power output NMOS transistor. In other embodiments, it can be adjusted to other types of MOSFETs according to the actual circuit, and is not limited here.

[0034] The load mirror branch 30 includes a second MOSFET M2, a third MOSFET M3, a first operational amplifier A1, and a mirror load resistor R2. The gate of the second MOSFET M1 is electrically connected to the PWM unit 10 and is controlled by the PWM unit 10; the drain of the second MOSFET M2 is electrically connected to the power supply VDD. The source of the third MOSFET M3 is electrically connected to the source of the second MOSFET M2. The non-inverting input of the first operational amplifier A1 is electrically connected to the common terminal of the first MOSFET M1 and the load resistor R1; the inverting input of the first operational amplifier A1 is electrically connected to the common terminal of the second MOSFET M2 and the third MOSFET M3; and the output of the first operational amplifier A1 is electrically connected to the gate of the third MOSFET M3. One end of the mirror load resistor R2 is electrically connected to the drain of the third MOSFET M3, and the other end is grounded.

[0035] In this embodiment, the second MOSFET M2 is preferably an NMOS transistor, and the third MOSFET M3 is preferably a PMOS transistor. A second current I2, precisely proportional to the first current I1, is generated through a load mirror branch consisting of the second NMOS transistor M2, the first operational amplifier A1, the third MOSFET M3, and the mirrored load resistor R2. The sources of the second NMOS transistor M2 and the third MOSFET M3 are connected and connected to the inverting input of the first operational amplifier A1, denoted as VA. The non-inverting input of the first operational amplifier A1 is connected to the voltage across the load resistor R1, denoted as V1. The output of the first operational amplifier A1 is electrically connected to the gate of the third MOSFET M3. Under the negative feedback, the load mirror branch 30 makes VA = V1. Therefore, the second current I2 flowing through the second NMOS transistor M2 is a precise mirror of the first current I1 flowing through the first NMOS transistor M1, and the proportional relationship between the second current I2 and the first current I1 is determined by the size relationship between M2 and M1. For example, if the size ratio of M1 and M2 is set to n:1, then the ratio of I1 and I2 is also I1:I2 = n:1. Therefore, the voltage V2 across the mirrored load resistor R2 is: V2=R2 I² = R² I1 / n (1) Where V2 is the voltage value of the mirror load resistor R2, R2 is the resistance value of the mirror load resistor, I2 is the current value of the second current, I1 is the current value of the first current, and n is the first preset ratio.

[0036] In this embodiment, taking n set to 1000 as an example, the first current I1 is usually quite large. If the ratio is set too low, the mirrored second current I2 will also be very large, resulting in unnecessary power consumption. Therefore, the voltage V2 across resistor R2 is: V2=R2 I² = R² I1 / 1000 (2) In this embodiment, the conversion circuit 40 includes a switching circuit 400, a current conversion circuit 401, and a current mirror 402. The switching circuit 400 includes a first switch SW1 and a second switch SW2. The first terminal of the first switch SW1 is electrically connected to the common terminal of the load resistor R1 and the first MOSFET M1, and the control terminal of the first switch SW1 is electrically connected to the logic control unit 70. The first terminal of the second switch SW2 is electrically connected to the common terminal of the mirrored load resistor R2 and the third MOSFET M3, and the control terminal of the second switch SW2 is electrically connected to the logic control unit 70.

[0037] The current conversion circuit 401 includes a second operational amplifier A2, a fourth MOSFET M4, and a first resistor R3. The non-inverting input of the second operational amplifier A2 is electrically connected to the second terminal of the first switch SW1 and the second terminal of the second switch SW2. The gate of the fourth MOSFET M4 is electrically connected to the output of the second operational amplifier A2, and the drain of the fourth MOSFET M4 is electrically connected to the power supply VDD. One end of the first resistor R3 is electrically connected to the inverting input of the second operational amplifier A2 and the source of the fourth MOSFET M4, and the other end is grounded. The fourth MOSFET M4 is preferably an NMOS transistor.

[0038] According to the principle of negative feedback, the voltage at the non-inverting input terminal of the second operational amplifier A2 is equal to the voltage at the inverting input terminal of the second operational amplifier A2. When the logic control unit 70 controls the first switch SW1 to be turned on and the second switch SW2 to be turned off, the voltage of the load resistor R2 is input to the non-inverting input terminal of the second operational amplifier A2 through the first switch SW1. At this time, V3 = V1, and the current conversion circuit 401 converts the voltage V1 of the load resistor R1 into a third current I3a flowing through the first resistor R3. When the logic control unit 70 controls the first switch SW1 to be turned off and the second switch SW2 to be turned on, the voltage V2 of the mirror load resistor R2 is input to the non-inverting input terminal of the second operational amplifier A2 through the second switch SW2. At this time, V3 = V2, and the current conversion circuit 401 converts the voltage V2 of the mirror load resistor R2 into a fourth current I3b flowing through the first resistor R3.

[0039] The current mirror 402 includes a fifth MOSFET M5, a sixth MOSFET M6, a seventh MOSFET M7, and an eighth MOSFET M8. The drain of the fifth MOSFET M5 is electrically connected to the drain of the fourth MOSFET M4 and the gate of the fifth MOSFET M5. The drain of the sixth MOSFET M6 is electrically connected to the source of the fifth MOSFET M5 and the gate of the sixth MOSFET M6, and the source of the sixth MOSFET M6 is electrically connected to the power supply VDD. The drain of the seventh MOSFET M7 is electrically connected to the energy storage unit 50, and the gate of the seventh MOSFET M7 is electrically connected to the gate of the fifth MOSFET M5. The drain of the eighth MOSFET M8 is electrically connected to the source of the seventh MOSFET M7, the gate of the eighth MOSFET M8 is electrically connected to the gate of the sixth MOSFET M6, and the source of the eighth MOSFET M8 is electrically connected to the power supply VDD. The fifth MOSFET M5 and the sixth MOSFET M6 form a first branch. When the first switch SW1 is turned on and the second switch SW2 is turned off, the current flowing through the first branch is a third current I3a. When the first switch SW1 is open and the second switch SW2 is open, the current flowing through the first branch is the fourth current I3b. The seventh MOSFET M7 and the eighth MOSFET M8 form a mirror branch, and the current of the first branch is mirrored into the mirror branch; that is, the mirrored current of the mirror branch and the current of the first branch are in a second preset ratio. In this embodiment, the fifth MOSFET M5, the sixth MOSFET M6, the seventh MOSFET M7, and the eighth MOSFET M8 are preferably PMOS transistors.

[0040] In this embodiment, the energy storage unit 50 includes a first capacitor C1, a third switch SW3, and a comparator A3. One end of the first capacitor C1 is electrically connected to the drain of the seventh MOSFET M7, and the other end is grounded. The first end of the third switch SW3 is electrically connected to one end of the first capacitor C1, the second end of the third switch SW3 is grounded, and the control terminal of the third switch SW3 is electrically connected to the logic control unit 70. The non-inverting input terminal of the comparator A3 is connected to the reference voltage VR, the inverting input terminal of the comparator A3 is electrically connected to the first terminal of the third switch SW3, and the output terminal of the comparator A3 is electrically connected to the counting unit 60.

[0041] Combined with appendix Figure 3 and appendix Figure 4 , attached Figure 3 The attached diagram shows the charging waveform and counting unit waveform of the constant power control circuit according to Embodiment 2 of the present invention. Figure 4This is a schematic diagram of the switching timing of the constant power control circuit according to Embodiment 2 of the present invention. Before charging the first capacitor C1, its charge must be cleared to ensure that the charging starting point of the first capacitor C1 is 0. The logic control unit 70 is also used to control the opening and closing of the third switch SW3 to clear the charge of the first capacitor C1. Specifically, the logic control unit 70 outputs a high-level signal to control the third switch SW3 to be turned on, and the first capacitor C1 is shorted to ground. When the charge of the first capacitor C1 is cleared, the logic control unit 70 outputs a low-level signal to control the third switch SW3 to be turned off. The logic control unit 70 then outputs a high-level signal to control the first switch SW1 to be closed, and outputs a low-level signal to control the second switch SW2 to be turned off. The third current I3a of the first branch is mirrored to the mirror branch, so that the first mirror current I4a of the mirror branch charges the first capacitor C1, and the first capacitor C1 enters the charging of the first time period T10. The third current I3a is: I3a=V3 / R3=V1 / R3 (3) I4a=m I3a(4); where, I4a is the first mirror current within the first time period, I3a is the current value of the third current, m is the second preset ratio, V3 is the voltage of the first resistor, R3 is the resistance value of the first resistor, and V1 is the voltage of the load resistor.

[0042] In this embodiment, m is preferably 1, then I4a=I3a=V3 / R3=V1 / R3 (5) When the first capacitor C1 enters the first charging time period, the counting unit 60 starts counting. Until the voltage at the inverting input of comparator A3, i.e., the voltage V4 of the first capacitor C1, rises to the reference voltage VR, slightly exceeding the reference voltage VR, the output voltage V5 of comparator A3 flips, i.e., the output voltage V5 of comparator A3 changes from high to low. The counting unit 60 stops counting and converts the first time T1 required for the voltage V4 of the first capacitor C1 to rise to the reference voltage VR into the first digital parameter: Data1=VR C1 / I4a=VR C1 R3 / V1 (6), then the voltage across the load resistor R1 is: V1=VR C1 R3 / Data1 (7) Wherein, Data1 is the first digital parameter corresponding to the first time T1, VR is the reference voltage, and C1 is the capacitance value of the first capacitor.

[0043] After the first time period ends, the counting unit 60 automatically resets to zero; the logic control unit 70 controls the third switch SW3 to open and close, clearing the charge of the first capacitor C1. When the first capacitor C1 is cleared, the logic control unit 70 controls the first switch SW1 to open and the second switch SW2 to open. The fourth current I3b of the first branch is mirrored to the mirrored branch, causing the mirrored current to charge the first capacitor C1. The first capacitor C1 then enters the second time period of charging. The fourth current I3b is: I3b=V2 / R3=R2 I1 / 1000 / R3 (8); When the first capacitor C1 enters the second time period of charging, the counting unit 60 restarts counting. When the voltage at the inverting input terminal of comparator A3, i.e., the voltage V4 of the first capacitor C1, rises to the reference voltage VR, slightly greater than the reference voltage VR, and the output voltage V5 at the output terminal of comparator A3 flips, the counting unit 60 stops counting and converts the second time T2 required for the voltage V4 of the first capacitor C1 to rise to the reference voltage VR into the second digital parameter: Data2=VR C1 / I4b=VR C1 R3 n / (R2 I1) (9), then, the first current is: I1=VR C1 R3 n / (R2 Data2)(10) Wherein, Data2 is the second digital parameter corresponding to the second time T2, VR is the reference voltage, C1 is the capacitance value of the first capacitor, and I4b is the second mirror current during the second time period.

[0044] In practical applications, the reference voltage VR, the first capacitor C1, the mirror load resistor R2, and the first resistor R3 are all known fixed values. Therefore, the logic control unit can calculate the current actual power of the load resistor R1 according to formulas (7) and (10). That is, the logic control unit 70 calculates the real-time power of the load resistor R1 based on the first voltage and the first current of the load resistor R1, and adjusts the duty cycle of the PWM signal according to the real-time power. For example, when the calculated actual power is 10W and the target power is 5W, the logic control unit 70 controls the duty cycle of the PWM signal output by the PWM unit 10 to be adjusted to 50%.

[0045] In this embodiment, the charging time can be adjusted by changing the values ​​of the first resistor R3 and the first capacitor C1, or by adjusting the mirror ratio of the current mirror 402. When the charging conversion speed becomes fast enough, multiple power calculations can be performed within each PWM switching cycle, thereby achieving higher precision real-time power control.

[0046] Compared to existing technologies, the constant power control circuit and electronic device proposed in this invention include a load branch and a mirror load branch. The voltage of the load resistor in the load branch and the mirror load resistor in the mirror load branch are converted into current at different time periods through a conversion circuit. By charging the energy storage unit with current, the voltage signal is converted into the length of the charging time. Then, the voltage signal is converted into a digital signal using a counting unit. The real-time power of the load resistor is obtained based on the converted digital signal, thereby adjusting the duty cycle of the PWM signal to achieve constant power output of the load resistor. The use of mixed digital and analog signals avoids the unavoidable nonlinear errors introduced by analog devices.

[0047] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A constant power control circuit, characterized in that, include: The PWM unit is used to output a PWM signal with a dynamically adjustable duty cycle. The load branch is electrically connected to the PWM unit. The load branch includes a load resistor. According to the dynamically adjustable duty cycle PWM signal, the load resistor outputs constant power. A load mirror branch is electrically connected to the load branch. The load mirror branch includes a mirror load resistor. The first current flowing through the load resistor and the second current flowing through the mirror load resistor are in a first preset ratio. A conversion circuit, electrically connected to the load branch and the load mirror branch, is used to convert the voltage of the load resistor into a third current and the voltage of the mirror load resistor into a fourth current. The energy storage unit is electrically connected to the conversion circuit and is charged using the third current and the fourth current, respectively. A counting unit, electrically connected to the energy storage unit, is used to calculate the first time required for the voltage of the energy storage unit to rise to a reference voltage when the energy storage unit is charged with the third current and to calculate the second time required for the voltage of the energy storage unit to rise to the reference voltage when the energy storage unit is charged with the fourth current. It is also used to convert the first time and the second time into a first digital parameter and a second digital parameter, respectively. A logic control unit, electrically connected to the counting unit and the PWM unit, is used to calculate the real-time power of the load resistor based on the first digital parameter and the second digital parameter, and to adjust the duty cycle of the PWM signal output by the PWM unit based on the real-time power. The load branch includes: The first MOSFET has its gate electrically connected to the PWM unit and its drain electrically connected to the power supply. The load resistor has one end electrically connected to the source of the first MOS transistor and the other end grounded. The load mirroring branch includes: The second MOSFET has its gate electrically connected to the PWM unit and its drain electrically connected to the power supply. The third MOS transistor, the source of which is electrically connected to the source of the second MOS transistor; A first operational amplifier, wherein the non-inverting input terminal of the first operational amplifier is electrically connected to the common terminal of the first MOS transistor and the load resistor, the inverting input terminal of the first operational amplifier is electrically connected to the common terminal of the second MOS transistor and the third MOS transistor, and the output terminal of the first operational amplifier is electrically connected to the gate of the third MOS transistor. The mirror load resistor has one end electrically connected to the drain of the third MOS transistor and the other end grounded.

2. The constant power control circuit according to claim 1, characterized in that, The voltage across the mirrored load resistor is: V2=R2 I2=R2 I1 / n; Wherein, V2 is the voltage value of the mirror load resistor, R2 is the resistance value of the mirror load resistor, I2 is the current value of the second current, I1 is the current value of the first current, and n is the first preset ratio.

3. The constant power control circuit according to claim 2, characterized in that, The conversion circuit includes: A switching circuit includes a first switch and a second switch. The first terminal of the first switch is electrically connected to the common terminal of the load resistor and the first MOSFET, and the control terminal of the first switch is electrically connected to the logic control unit. The first terminal of the second switch is electrically connected to the common terminal of the mirrored load resistor and the third MOSFET, and the control terminal of the second switch is electrically connected to the logic control unit. A current conversion circuit includes a second operational amplifier, a fourth MOSFET, and a first resistor. The non-inverting input of the second operational amplifier is electrically connected to the second terminal of the first switch and the second terminal of the second switch. The gate of the fourth MOSFET is electrically connected to the output of the second operational amplifier, and the drain of the fourth MOSFET is electrically connected to the power supply. One end of the first resistor is electrically connected to the inverting input of the second operational amplifier and the source of the fourth MOSFET, and the other end is grounded. The voltage at the non-inverting input terminal of the second operational amplifier is equal to the voltage at the inverting input terminal of the second operational amplifier; When the logic control unit controls the first switch to be turned on and the second switch to be turned off, the voltage of the load resistor is input to the non-inverting input terminal of the second operational amplifier through the first switch, and the current conversion circuit converts the voltage of the load resistor into the third current flowing through the first resistor; when the logic control unit controls the first switch to be turned off and the second switch to be turned on, the voltage of the mirror load resistor is input to the non-inverting input terminal of the second operational amplifier through the second switch, and the current conversion circuit converts the voltage of the mirror load resistor into the fourth current flowing through the first resistor.

4. The constant power control circuit according to claim 3, characterized in that, The conversion circuit further includes a current mirror, the current mirror comprising: The fifth MOS transistor, the drain of which is electrically connected to the drain of the fourth MOS transistor and the gate of the fifth MOS transistor; The sixth MOS transistor has its drain electrically connected to the source of the fifth MOS transistor and the gate of the sixth MOS transistor, and its source electrically connected to the power supply. The seventh MOS transistor has its drain electrically connected to the energy storage unit and its gate electrically connected to the gate of the fifth MOS transistor. The eighth MOS transistor has its drain electrically connected to the source of the seventh MOS transistor, its gate electrically connected to the gate of the sixth MOS transistor, and its source electrically connected to the power supply. The fifth MOSFET and the sixth MOSFET form a first branch. When the first switch is on and the second switch is off, the current flowing through the first branch is the third current. When the first switch is off and the second switch is on, the current flowing through the first branch is the fourth current. The seventh MOSFET and the eighth MOSFET form a mirror branch. The current of the first branch is mirrored to the mirror branch. The mirror current of the mirror branch is proportional to the current of the first branch in a second preset ratio.

5. The constant power control circuit according to claim 4, characterized in that, The energy storage unit includes: The first capacitor has one end electrically connected to the drain of the seventh MOS transistor, and the other end grounded. The third switch has its first terminal electrically connected to one end of the first capacitor, its second terminal grounded, and its control terminal electrically connected to the logic control unit. The comparator has its non-inverting input connected to the reference voltage, its inverting input electrically connected to the first terminal of the third switch, and its output electrically connected to the counting unit.

6. The constant power control circuit according to claim 5, characterized in that: The logic control unit is also used to control the on / off state of the third switch to clear the charge of the first capacitor; The logic control unit is also used to control the first switch to close, the second switch to open, and the third current of the first branch to be mirrored to the mirror branch, so that the first mirror current charges the first capacitor, and the first capacitor enters a first time period of charging, wherein the third current is: I3a = V3 / R3 = V1 / R3; The first mirror current is: I4a=m I3a; among which, I4a is the first mirror current within the first time period, I3a is the current value of the third current, m is the second preset ratio, V3 is the voltage of the first resistor, R3 is the resistance value of the first resistor, and V1 is the voltage of the load resistor. When the first capacitor enters the first charging period, the counting unit starts counting; until the voltage at the inverting input of the comparator is greater than the reference voltage, and the output voltage at the output of the comparator flips, the counting unit stops counting and converts the first time required for the voltage of the first capacitor to rise to the reference voltage into the first digital parameter: Data1=VR C1 / I4a= VR C1 Given R3 / V1 / m, the voltage across the load resistor is: V1= VR C1 R3 / Data1 / m; Wherein, Data1 is the first digital parameter corresponding to the first time, VR is the reference voltage, and C1 is the capacitance value of the first capacitor.

7. The constant power control circuit according to claim 6, characterized in that: The counting unit is also used to automatically reset the count to zero after the first time period ends; The logic control unit is also used to control the opening and closing of the third switch and clear the charge of the first capacitor when the first time period ends. The logic control unit is further configured to, when the first capacitor is cleared to zero, control the first switch to open and the second switch to open, so that the fourth current of the first branch is mirrored to the mirror branch, causing the second mirror current to charge the first capacitor, and the first capacitor enters a second charging time period, wherein the fourth current is: I3b=V2 / R3=R2 I1 / n / R3; The second mirror current is: I4b=m I3b= m R2 I1 / n / R3; where I3b is the current value of the fourth current; I4b is the second mirror current during the second time period; The counting unit is further configured to start counting when the first capacitor enters the second charging time period, and stop counting when the voltage at the inverting input of the comparator is greater than the reference voltage and the output voltage at the output of the comparator flips, and convert the second time required for the voltage of the first capacitor to rise to the reference voltage into a second digital parameter: Data2=VR C1 / I4b= VR C1 R3 n / (m R2 I1), then, the first current is: I1=VR C1 R3 n / (m R2 Data2) Wherein, Data2 is the second digital parameter corresponding to the second time, and R3 is the resistance value of the first resistor.

8. The constant power control circuit according to claim 2, characterized in that, The logic control unit calculates the real-time power of the load resistor based on the first voltage value and the first current value of the load resistor, and dynamically adjusts the duty cycle of the PWM signal based on the real-time power.

9. An electronic device, characterized in that, Includes the constant power control circuit as described in any one of claims 1 to 8.

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