Ferroelectric random access memory and electronic devices
By connecting multiple capacitors in parallel within the memory cell and linking them to transistors, and combining word line and bit line designs, the problems of low storage density and insufficient capacity of existing ferroelectric random access memories are solved, achieving higher storage density and capacity.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HUAWEI TECH CO LTD
- Filing Date
- 2022-07-28
- Publication Date
- 2026-06-12
Smart Images
Figure CN117524274B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technology, and more specifically, to a ferroelectric random access memory and electronic device. Background Technology
[0002] With the rapid development of technologies such as cloud computing, artificial intelligence, and the Internet of Things, memory has been widely used. Memory generally includes read-only memory (ROM) and random access memory (RAM). Ferroelectric random access memory (FeRAM), as a type of random access memory, has the advantage of low latency. However, although the ferroelectric random access memory provided by related technologies stores data through transistors and capacitors, the transistors are integrated in an array planar manner, and the transistors and capacitors each occupy the integrated area of the ferroelectric random access memory, resulting in low storage density and limited capacity.
[0003] Therefore, there is an urgent need for a ferroelectric random access memory with high storage density and large capacity. Summary of the Invention
[0004] This application provides a ferroelectric random access memory and an electronic device, which realizes data storage through transistors and multiple capacitors, thereby increasing the capacity of the ferroelectric random access memory and improving its storage density.
[0005] In a first aspect, this application provides a ferroelectric random access memory, which may include one or more memory cells.
[0006] The memory cell may include transistors and multiple capacitors. These capacitors may correspond one-to-one with multiple capacitor lines.
[0007] Furthermore, the first terminal of each capacitor can be connected to a corresponding capacitor line, and the second terminal of each capacitor can be connected to the first terminal of the transistor; that is, multiple capacitors can be connected in parallel. The control terminal of the transistor can be connected to the word line, and the second terminal of the transistor can be connected to the bit line.
[0008] Alternatively, the transistor can be used to select any one of a plurality of capacitors based on the voltages of the capacitor line, word line, and bit line.
[0009] Each capacitor can be used to store data (such as binary data).
[0010] The ferroelectric random access memory provided in this application stores data using a transistor and multiple capacitors, which not only increases the capacity of the ferroelectric random access memory, but also improves the integration of the ferroelectric random access memory (i.e., improves the area utilization of the ferroelectric random access memory), thereby increasing the storage density of the ferroelectric random access memory.
[0011] In one possible implementation, multiple capacitors in the memory cell can be stacked, realizing the stacking of the ferroelectric random access memory in three dimensions and improving the integration density of the ferroelectric random access memory. Of course, multiple capacitors can also be arranged in other ways, which are not limited in this application.
[0012] Furthermore, the ferroelectric random access memory provided in this application may include at least two memory cells, which may be arranged along a first direction or a second direction. That is, at least two memory cells may be arranged along the first direction to form a row of memory cells. At least two memory cells may also be arranged along the second direction, which may also form a row of memory cells.
[0013] In one example, the first direction and the second direction can be different. Understandably, the first direction and the second direction are not parallel; there can be an angle between them. The angle can be 90 degrees, meaning the first direction is perpendicular to the second direction. The angle can also be 60 degrees, etc., and this application does not limit this.
[0014] In another example, the first direction can be perpendicular to the stacking direction of the multiple capacitors, and the second direction can also be perpendicular to the stacking direction. That is, the first direction and the second direction are respectively perpendicular to the stacking direction of the multiple capacitors.
[0015] For example, the first direction can be the Y direction, the second direction can be the X direction, and the stacking direction of multiple capacitors can be the Z direction, thus realizing the three-dimensional arrangement of the ferroelectric random access memory.
[0016] In some embodiments, along the first direction, capacitors in the same layer of at least two memory cells can be connected to different capacitor lines, the control electrode of the transistor in each of the at least two memory cells can be connected to different word lines, and the second electrode of the transistor in each memory cell is connected to the same bit line.
[0017] In other embodiments, along the second direction, capacitors in the same layer of at least two memory cells can be connected to the same capacitor line, the control electrode of the transistor in each of the at least two memory cells can be connected to the same word line, and the second electrode of the transistor in each memory cell can be connected to different bit lines.
[0018] It can be seen that, in the first or second direction, the ferroelectric random access memory can be set in the capacitor stacking direction by connecting capacitors to capacitor lines and transistors to word lines and bit lines, which is beneficial to improving the integration density of ferroelectric random access memory.
[0019] In one possible implementation, the ferroelectric random access memory (FRAM) provided in this application includes at least four memory cells. These four memory cells can be arranged in a matrix along a first direction and a second direction. That is, along the first and second directions, the at least four memory cells can be arranged three-dimensionally, which not only improves the area utilization of the FRAM but also increases its capacity.
[0020] In one embodiment, along the first direction, capacitors located in the same layer and in the same column of at least four memory cells can be connected to the same capacitor line, the control electrode of transistors located in the same column of at least four memory cells can be connected to the same word line, and the second electrode of transistors located in the same column of at least four memory cells can be connected to different bit lines.
[0021] In another embodiment, along the second direction, capacitors in the same layer and in the same row of at least four memory cells can be connected to different capacitor lines, control electrodes of transistors in the same row of at least four memory cells can be connected to different word lines, and second electrodes of transistors in the same row of at least four memory cells can be connected to the same bit line.
[0022] It can be seen that, in the first and second directions, the ferroelectric random access memory can be set in the capacitor stacking direction by connecting capacitors to capacitor lines and transistors to word lines and bit lines, which is beneficial to improving the integration density of ferroelectric random access memory.
[0023] In one possible implementation, the second terminal of each capacitor can be used to connect to the first terminal of the transistor via a floating source terminal. It can be seen that a floating source terminal can achieve the connection between the capacitor and the transistor.
[0024] Furthermore, the floating source end can be a columnar structure, and each capacitor can be arranged on the floating source end along its extension direction. It can be seen that the floating source end can support and fix multiple capacitors.
[0025] In one example, each capacitor can be a ferroelectric capacitor. Of course, capacitors can also be of other types, which are not limited in this application.
[0026] In another example, the transistor can be a field-effect transistor. Of course, transistors can take other types, which are not limited in this application.
[0027] Among them, field-effect transistors can be metal-oxide-semiconductor field-effect transistors (MOSFETs), etc.
[0028] Furthermore, the first electrode of a transistor can be the source, and the second electrode can be the drain.
[0029] In yet another example, the first terminal of each capacitor can be the negative terminal, and the second terminal of each capacitor can be the positive terminal.
[0030] Secondly, this application provides an electronic device that may include the ferroelectric random access memory provided in the first aspect and its possible implementations.
[0031] It should be understood that the second aspect of this application is consistent with the technical solution of the first aspect of this application, and the beneficial effects achieved by each aspect and the corresponding feasible implementation are similar, so they will not be repeated here. Attached Figure Description
[0032] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0033] Figure 1 This is a schematic structural diagram of a ferroelectric random access memory in an embodiment of this application;
[0034] Figure 2 This is another schematic structural diagram of the ferroelectric random access memory in the embodiments of this application;
[0035] Figure 3 This is another schematic structural diagram of a ferroelectric random access memory in the embodiments of this application;
[0036] Figure 4 This is another schematic structural diagram of a ferroelectric random access memory in the embodiments of this application;
[0037] Figure 5 This is a schematic diagram illustrating the working process of the ferroelectric random access memory in the embodiments of this application. Detailed Implementation
[0038] The technical solutions in this application will now be described with reference to the accompanying drawings.
[0039] The terms "first," "second," etc., used in the specification, embodiments, claims, and drawings of this application are for distinguishing purposes only and should not be construed as indicating or implying relative importance or order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, such as including a series of steps or units. A method, system, product, or apparatus is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses.
[0040] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.
[0041] "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or multiple items. For example, at least one of a, b, or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.
[0042] With the rapid development of technologies such as cloud computing, artificial intelligence, and the Internet of Things, memory has been widely used. Memory generally includes read-only memory (ROM) and random access memory (RAM). Ferroelectric random access memory (FeRAM), as a type of random access memory, has the advantage of low latency. However, although the ferroelectric random access memory provided by related technologies stores data through transistors and capacitors, the transistors are integrated in an array planar manner, and the transistors and capacitors each occupy the integrated area of the ferroelectric random access memory, resulting in low storage density and limited capacity.
[0043] To overcome the above shortcomings, this application provides a ferroelectric random access memory (FRAM). The FRAM 100 may include a storage unit 10, such as... Figure 1 As shown.
[0044] Optionally, the memory cell 10 may include a transistor T00 and eight capacitors. The eight capacitors may correspond one-to-one with eight capacitor lines (CLs).
[0045] The eight capacitors may include capacitors C001, C002, C003, C004, C005, C006, C007, and C008. The eight capacitor lines may include capacitor lines CL001, CL002, CL003, CL004, CL005, CL006, CL007, and CL008.
[0046] Furthermore, the first terminal (e.g., the negative terminal) of each of the eight capacitors can be connected to a corresponding capacitor line via a floating source (FS), and the second terminal (e.g., the positive terminal) of each capacitor can be connected to the first terminal (e.g., the source terminal) of transistor T00. In other words, the eight capacitors can be connected in parallel. The control terminal of transistor T00 can be connected to the word line (WL), and the second terminal of the transistor (which can be the drain terminal) can be connected to the bit line (BL).
[0047] For example, the negative terminal of capacitor C001 can be connected to the corresponding capacitor line CL001, and the positive terminal of capacitor C001 can be connected to the source of transistor T00 through the floating source terminal FS00.
[0048] For example, the negative terminal of capacitor C002 can be connected to the corresponding capacitor line CL002, and the positive terminal of capacitor C002 can be connected to the source of transistor T00 through the floating source terminal FS00.
[0049] It can be seen that the parallel connection of 8 capacitors can be achieved through the floating source terminal FS00, and the connection of 8 capacitors to transistor T00 can also be achieved.
[0050] Furthermore, the control electrode of transistor T00 can be connected to word line WL0, and the drain of transistor T00 can be connected to bit line BL0.
[0051] Optionally, transistor T00 can be used to select any one of eight capacitors based on the voltage of each of the capacitor lines (including capacitor lines CL001 to CL008), word line WL0, and bit line BL0.
[0052] Each capacitor (e.g., capacitor C001) can be used to store data (e.g., binary data).
[0053] The ferroelectric random access memory 100 provided in this application embodiment can store data through transistor T00 and 8 capacitors, which not only increases the capacity of the ferroelectric random access memory 100, but also improves the integration of the ferroelectric random access memory 100 (that is, improves the area utilization of the ferroelectric random access memory 100), thereby improving the storage density of the ferroelectric random access memory 100.
[0054] It should be noted that this application Figure 1 The following description uses a storage unit 10 with eight capacitors as an example. Of course, the storage unit 10 can also include nine, ten, or more capacitors to further increase the capacity of the ferroelectric random access memory 100, which will not be described in detail in this embodiment.
[0055] like Figure 1 As shown, the eight capacitors can be stacked, realizing the three-dimensional stacking of the ferroelectric random access memory 100 and improving the integration density of the ferroelectric random access memory 100. Of course, the eight capacitors can also be arranged in other ways, and this embodiment does not limit the specific arrangements.
[0056] In one example, the floating source terminal FS00 can be a columnar structure, and eight capacitors can be arranged on the floating source terminal FS00 along its extension direction. It can be seen that the floating source terminal FS00 can support and fix the eight capacitors.
[0057] In another example, the eight capacitors can all be ferroelectric capacitors. Of course, the eight capacitors can also be of other types, and this application does not limit them.
[0058] In another example, transistor T00 can be a field-effect transistor (such as a metal-oxide-semiconductor field-effect transistor (MOSFET)). Of course, transistor T00 can also take other types, which are not limited in the embodiments of this application.
[0059] This application also provides another ferroelectric random access memory, such as... Figure 2 As shown. The ferroelectric random access memory 100 may include two memory cells. The two memory cells may include memory cell 10 (as described above) and memory cell 20. Memory cell 10 and memory cell 20 may be along a second direction (i.e. Figure 2 Arranged in the X direction.
[0060] Optionally, the memory cell 20 may include a transistor T01 and eight capacitors. The eight capacitors may correspond one-to-one with eight capacitor lines.
[0061] The eight capacitors in the storage unit 20 may include capacitors C011, C012, C013, C014, C015, C016, C017, and C018. The eight capacitor lines corresponding to these eight capacitors may include capacitor lines CL011, CL012, CL013, CL014, CL015, CL016, CL017, and CL018.
[0062] Similar to memory cell 10, in memory cell 20, the first terminal (e.g., the negative terminal) of each of the eight capacitors can be connected to a corresponding capacitor line via the floating source terminal FS01, and the second terminal (e.g., the positive terminal) of each capacitor can be connected to the first terminal (e.g., the source terminal) of transistor T01. In other words, the eight capacitors in memory cell 20 can be connected in parallel. The control terminal of transistor T01 can be connected to word line WL1, and the second terminal (which can be the drain terminal) of transistor T01 can be connected to bit line BL0.
[0063] For example, the negative terminal of capacitor C011 can be connected to the corresponding capacitor line CL011, and the positive terminal of capacitor C011 can be connected to the source of transistor T01 through the floating source terminal FS01.
[0064] For example, the negative terminal of capacitor C012 can be connected to the corresponding capacitor line CL012, and the positive terminal of capacitor C012 can be connected to the source of transistor T01 through the floating source terminal FS01.
[0065] It can be seen that the eight capacitors in the memory cell 20 can be connected in parallel through the floating source terminal FS01, and the connection between the eight capacitors in the memory cell 20 and the transistor T01 can also be realized.
[0066] Furthermore, the control electrode of transistor T01 can be connected to word line WL1, and the drain of transistor T01 can be connected to bit line BL0.
[0067] Optionally, transistor T02 can be used to select any one of eight capacitors based on the voltage of each of the capacitor lines (including capacitor lines CL011 to CL018), word line WL1, and bit line BL0.
[0068] Each capacitor in storage cell 20 (e.g., capacitor C011) can be used to store data (e.g., binary data).
[0069] It should be noted that this application Figure 2The following description uses storage unit 20, which includes eight capacitors, as an example. Of course, similar to storage unit 10, storage unit 20 can also include nine, ten, or more capacitors to further increase the capacity of the ferroelectric random access memory 100. This embodiment will not be described in detail here.
[0070] like Figure 2 As shown, the eight capacitors in storage cell 20 can be stacked, realizing the three-dimensional stacking of the ferroelectric random access memory 100 and improving the integration density of the ferroelectric random access memory 100. Of course, the eight capacitors in storage cell 20 can also be arranged in other ways, and this embodiment does not limit the specific arrangements.
[0071] In one example, the floating source terminal FS01 can be a columnar structure, and the eight capacitors in the storage cell 20 can be arranged on the floating source terminal FS01 along its extension direction. It can be seen that the floating source terminal FS01 can support and fix the eight capacitors in the storage cell 20.
[0072] In another example, similar to storage cell 10, the eight capacitors in storage cell 20 can also be ferroelectric capacitors. Of course, the eight capacitors in storage cell 20 can also be of other types, and this application embodiment does not limit them.
[0073] In yet another example, similar to transistor T00, transistor T01 can be a field-effect transistor. Of course, transistor T01 can also take other types, which are not limited in the embodiments of this application.
[0074] In some embodiments of this application, reference is made to Figure 2 Along the second direction, the capacitors in the same layer of memory cell 10 and memory cell 20 can be connected to different capacitor lines, the control electrode of the transistor of each memory cell in memory cell 10 and memory cell 20 can be connected to different word lines, and the second electrode of the transistor of memory cell 10 and the second electrode (such as the drain) of the transistor of memory cell 20 are connected to the same bit line.
[0075] For example, capacitors C001 and C011 are located on the same layer. Capacitor C001 can be connected to capacitor line CL001, and capacitor C011 can be connected to capacitor line CL011. In other words, capacitors C001 and C011, which are located on the same layer, can be connected to different capacitor lines.
[0076] For example, capacitors C002 and C012 are located on the same layer. Capacitor C002 can be connected to capacitor line CL002, and capacitor C012 can be connected to capacitor line CL012. In other words, capacitors C002 and C012, which are located on the same layer, can be connected to different capacitor lines.
[0077] For example, the control electrode of transistor T00 can be connected to word line WL0, and the drain of transistor T00 can be connected to bit line BL0. The control electrode of transistor T01 can be connected to word line WL1, and the drain of transistor T01 can be connected to bit line BL0. That is, the control electrodes of transistor T00 and transistor T01 can be connected to different word lines, and the drains of transistor T00 and transistor T01 can be connected to the same bit line.
[0078] Optionally, the second direction can be perpendicular to the stacking direction (which can be the Z direction) of the capacitors in the storage cell 10 and storage cell 20, which can realize the three-dimensional arrangement of the ferroelectric random access memory 100.
[0079] from Figure 2 As can be seen, in the second direction, the ferroelectric random access memory 100 can be configured in the capacitor stacking direction by connecting the eight capacitors in storage cell 10 to their corresponding capacitor lines, connecting the eight capacitors in storage cell 20 to their corresponding capacitor lines, connecting the transistor T00 to the word line WL0 and the bit line BL0, and connecting the transistor T01 to the word line WL1 and the bit line BL0. This is beneficial to improving the integration of the ferroelectric random access memory 100 and thus improving the storage density of the ferroelectric random access memory 100.
[0080] It should be noted that, Figure 2 Only one schematic diagram of a ferroelectric random access memory 100 with two storage cells arranged along the second direction is shown. Of course, the ferroelectric random access memory 100 may also include three, four, or more storage cells, and the multiple storage cells may also be arranged along the second direction. This embodiment will not be described in detail here.
[0081] This application also provides another ferroelectric random access memory, such as... Figure 3 As shown. With Figure 2 Similarly, the ferroelectric random access memory 100 may include two memory cells. These two memory cells may include memory cell 10 (see above description) and memory cell 30. Figure 2 The difference is, Figure 3 The storage cells 10 and 30 can be along the first direction (i.e. Figure 3 Arranged in the Y direction.
[0082] Optionally, the memory cell 30 may include a transistor T10 and eight capacitors. The eight capacitors may correspond one-to-one with eight capacitor lines.
[0083] The eight capacitors in storage cell 30 may include capacitors C101, C102, C103, C104, C105, C106, C107, and C108. Since capacitors located on the same layer along the first direction can be connected to the same capacitor line, the eight capacitor lines corresponding to the eight capacitors in storage cell 30 are the same as the eight capacitor lines corresponding to the eight capacitors in storage cell 10 (including capacitor lines CL001, CL002, CL003, CL004, CL005, CL006, CL007, and CL008).
[0084] Similar to memory cells 10 and 20, in memory cell 30, the first terminal (e.g., the negative terminal) of each of the eight capacitors can be connected to a corresponding capacitor line via the floating source terminal FS10, and the second terminal (e.g., the positive terminal) of each capacitor can be connected to the first terminal (e.g., the source terminal) of transistor T10. In other words, the eight capacitors in memory cell 30 can be connected in parallel. The control terminal of transistor T10 can be connected to the word line WL0, and the second terminal (which can be the drain terminal) of transistor T10 can be connected to the bit line BL1.
[0085] For example, the negative terminal of capacitor C101 can be connected to the corresponding capacitor line CL001, and the positive terminal of capacitor C101 can be connected to the source of transistor T10 through the floating source terminal FS10.
[0086] For example, the negative terminal of capacitor C102 can be connected to the corresponding capacitor line CL002, and the positive terminal of capacitor C102 can be connected to the source of transistor T10 through the floating source terminal FS10.
[0087] It can be seen that the eight capacitors in the memory cell 30 can be connected in parallel through the floating source terminal FS10, and the connection between the eight capacitors in the memory cell 30 and the transistor T10 can also be realized.
[0088] Furthermore, the control electrode of transistor T10 can be connected to word line WL0, and the drain of transistor T10 can be connected to bit line BL1.
[0089] Optionally, transistor T10 can be used to select any one of the eight capacitors in memory cell 30 based on the voltage of each capacitor line (including capacitor lines CL001 to CL008), word line WL0, and bit line BL1.
[0090] Each capacitor in storage cell 30 (such as capacitor C101) can be used to store data (such as binary data).
[0091] It should be noted that this application Figure 3The following description uses storage unit 30, which includes eight capacitors, as an example. Of course, similar to storage units 10 and 20, storage unit 30 can also include nine, ten, or more capacitors to further increase the capacity of the ferroelectric random access memory 100. This embodiment will not be described in detail here.
[0092] like Figure 3 As shown, the eight capacitors in the storage unit 30 can be stacked, realizing the three-dimensional stacking of the ferroelectric random access memory 100 and improving the integration density of the ferroelectric random access memory 100. Of course, the eight capacitors in the storage unit 30 can also be arranged in other ways, and this embodiment does not limit the specific arrangements.
[0093] In one example, the floating source terminal FS10 can be a columnar structure, and the eight capacitors in the memory cell 30 can be arranged on the floating source terminal FS10 along its extension direction. It can be seen that the floating source terminal FS10 can support and fix the eight capacitors in the memory cell 30.
[0094] In another example, similar to storage cell 10, the eight capacitors in storage cell 30 can also be ferroelectric capacitors. Of course, the eight capacitors in storage cell 30 can also be of other types, and this application embodiment does not limit them.
[0095] In yet another example, similar to transistor T00, transistor T10 can be a field-effect transistor. Of course, transistor T10 can also take other types, which are not limited in the embodiments of this application.
[0096] In some embodiments of this application, reference is made to Figure 3 Along the first direction, capacitors in the same layer of memory cell 10 and memory cell 30 can be connected to the same capacitor line, the control electrode of the transistor of each memory cell in memory cell 10 and memory cell 30 can be connected to the same word line, and the second electrode of the transistor of memory cell 10 and the second electrode (such as the drain) of the transistor of memory cell 30 can be connected to different bit lines.
[0097] For example, capacitors C001 and C101 are located on the same layer. Capacitor C001 can be connected to capacitor line CL001, and capacitor C101 can also be connected to capacitor line CL001. In other words, capacitors C001 and C101, which are located on the same layer, can be connected to the same capacitor line (i.e., capacitor line CL001).
[0098] For example, capacitors C002 and C102 are located on the same layer. Capacitor C002 can be connected to capacitor line CL002, and capacitor C102 can also be connected to capacitor line CL002. In other words, capacitors C002 and C102, which are located on the same layer, can be connected to the same capacitor line (i.e., capacitor line CL002).
[0099] For example, the gate electrode of transistor T00 can be connected to word line WL0, and the drain of transistor T00 can be connected to bit line BL0. The gate electrode of transistor T10 can be connected to word line WL0, and the drain of transistor T10 can be connected to bit line BL1. That is, the gate electrodes of transistor T00 and transistor T10 can be connected to the same word line (i.e., word line WL1), while the drains of transistor T00 and transistor T10 can be connected to different bit lines.
[0100] Optionally, the first direction can be perpendicular to the stacking direction (which can be the Z direction) of the capacitors in the storage cell 10 and storage cell 30, which can realize the three-dimensional arrangement of the ferroelectric random access memory 100.
[0101] from Figure 3 As can be seen, in the first direction, the ferroelectric random access memory 100 can be configured in the capacitor stacking direction by connecting the eight capacitors in the storage cell 10 to their corresponding capacitor lines, connecting the eight capacitors in the storage cell 30 to their corresponding capacitor lines, connecting the transistor T00 to the word line WL0 and the bit line BL0, and connecting the transistor T10 to the word line WL0 and the bit line BL1. This is beneficial to improving the integration of the ferroelectric random access memory 100 and thus improving the storage density of the ferroelectric random access memory 100.
[0102] It should be noted that, with Figure 2 similar, Figure 3 Only one schematic diagram of a ferroelectric random access memory 100 with two storage cells arranged along the first direction is shown. Of course, the ferroelectric random access memory 100 may also include three, four, or more storage cells, and the multiple storage cells may also be arranged along the first direction. This embodiment will not be described in detail here.
[0103] This application also provides another ferroelectric random access memory, such as... Figure 4 As shown. The ferroelectric random access memory 100 may include four memory cells. The four memory cells may include memory cell 10 (see above description), memory cell 20 (see above description), memory cell 30 (see above description), and memory cell 40.
[0104] Similar to memory cells 10, 20, and 30, memory cell 40 may include a transistor T11 and eight capacitors. The eight capacitors may correspond one-to-one with eight capacitor lines.
[0105] The eight capacitors in storage cell 40 may include capacitors C111, C112, C113, C114, C115, C116, C117, and C118. Since capacitors located on the same layer along the second direction can be connected to the same capacitor line, the eight capacitor lines corresponding to the eight capacitors in storage cell 40 are the same as the eight capacitor lines corresponding to the eight capacitors in storage cell 20 (including capacitor lines CL011, CL012, CL013, CL014, CL015, CL016, CL017, and CL018).
[0106] Similar to memory cells 10, 20, and 30, in memory cell 40, the first terminal (e.g., the negative terminal) of each of the eight capacitors can be connected to a corresponding capacitor line via the floating source terminal FS11, and the second terminal (e.g., the positive terminal) of each capacitor can be connected to the first terminal (e.g., the source terminal) of transistor T11. In other words, the eight capacitors in memory cell 40 can be connected in parallel. The control terminal of transistor T11 can be connected to word line WL1, and the second terminal (which can be the drain terminal) of transistor T11 can be connected to bit line BL1.
[0107] For example, the negative terminal of capacitor C111 can be connected to the corresponding capacitor line CL011, and the positive terminal of capacitor C111 can be connected to the source of transistor T11 through the floating source terminal FS11.
[0108] For example, the negative terminal of capacitor C112 can be connected to the corresponding capacitor line CL012, and the positive terminal of capacitor C112 can be connected to the source of transistor T11 through the floating source terminal FS11.
[0109] It can be seen that the eight capacitors in the memory cell 40 can be connected in parallel through the floating source terminal FS11, and the connection between the eight capacitors in the memory cell 40 and the transistor T11 can also be realized.
[0110] Furthermore, the control electrode of transistor T11 can be connected to word line WL1, and the drain electrode of transistor T10 can be connected to bit line BL1.
[0111] Optionally, transistor T11 can be used to select any one of the eight capacitors in memory cell 40 based on the voltage of each capacitor line (including capacitor lines CL011 to CL018), word line WL1, and bit line BL1.
[0112] Each capacitor in storage cell 40 (such as capacitor C111) can be used to store data (such as binary data).
[0113] Optionally, the four storage cells can be arranged along the first direction (i.e., Figure 4 The Y direction) and the second direction (i.e. Figure 4 The four memory cells are arranged in a matrix along the X direction. In other words, the four memory cells can be arranged in three dimensions along the first and second directions, which not only improves the area utilization of the ferroelectric random access memory 100, but also increases the capacity of the ferroelectric random access memory 100.
[0114] It should be noted that this application Figure 4 The following description uses storage unit 40, which includes eight capacitors, as an example. Of course, similar to storage units 10, 20, and 30, storage unit 40 can also include nine, ten, or more capacitors to further increase the capacity of the ferroelectric random access memory 100. This embodiment will not be described in detail here.
[0115] like Figure 4 As shown, the eight capacitors in the storage unit 40 can be stacked, realizing the three-dimensional stacking of the ferroelectric random access memory 100 and improving the integration density of the ferroelectric random access memory 100. Of course, the eight capacitors in the storage unit 40 can also be arranged in other ways, and this embodiment does not limit the specific arrangements.
[0116] In one example, the floating source terminal FS11 can be a columnar structure, and the eight capacitors in the memory cell 40 can be arranged on the floating source terminal FS11 along its extension direction. It can be seen that the floating source terminal FS11 can support and fix the eight capacitors in the memory cell 40.
[0117] In another example, similar to storage cells 10, 20, and 30, the eight capacitors in storage cell 40 can also be ferroelectric capacitors. Of course, the eight capacitors in storage cell 40 can also be of other types, and this embodiment does not limit their use.
[0118] In yet another example, similar to transistors T00, T01, and T10, transistor T11 can be a field-effect transistor. Of course, transistor T11 can also be of other types, and this application embodiment does not limit this.
[0119] In some embodiments of this application, reference continues to be made to Figure 4 Along the first direction, capacitors in the same layer and in the same column of memory cells 10, 20, 30 and 40 can be connected to the same capacitor line, the control electrodes of transistors in the same column of memory cells 10, 20, 30 and 40 can be connected to the same word line, and the second electrodes of transistors in the same column of memory cells 10, 20, 30 and 40 can be connected to different bit lines.
[0120] For example, capacitor C001 and capacitor C101 are located on the same layer and in the same column. Capacitor C001 can be connected to capacitor line CL001, and capacitor C101 can also be connected to capacitor line CL001. That is to say, capacitor C001 and capacitor C101, which are located on the same layer and in the same column, can be connected to the same capacitor line (i.e., capacitor line CL001).
[0121] Similarly, capacitors C011 and C111 are located on the same layer and in the same column. Capacitor C011 can be connected to capacitor line CL011, and capacitor C111 can also be connected to capacitor line CL011. That is to say, capacitors C011 and C111, which are located on the same layer and in the same column, can be connected to the same capacitor line (i.e., capacitor line CL011).
[0122] For example, capacitors C002 and C102 are located on the same layer and in the same column. Capacitor C002 can be connected to capacitor line CL002, and capacitor C102 can also be connected to capacitor line CL002. That is, capacitors C002 and C102, which are located on the same layer and in the same column, can be connected to the same capacitor line (i.e., capacitor line CL002).
[0123] Similarly, capacitors C012 and C112 are located on the same layer and in the same column. Capacitor C012 can be connected to capacitor line CL012, and capacitor C112 can also be connected to capacitor line CL012. That is to say, capacitors C012 and C112, which are located on the same layer and in the same column, can be connected to the same capacitor line (i.e., capacitor line CL012).
[0124] For example, transistors T00 and T10 are located in the same column. The control electrode of transistor T00 can be connected to word line WL0, and the control electrode of transistor T10 can also be connected to word line WL0. That is, the control electrodes of transistors T00 and T10, which are located in the same column, can be connected to the same word line (i.e., word line WL0). The drain of transistor T00 can be connected to bit line BL0, and the drain of transistor T10 can be connected to bit line BL1. That is, the drains of transistors T00 and T10, which are located in the same column, can be connected to different bit lines.
[0125] Similarly, transistors T01 and T11 are located in the same column. The gate electrode of transistor T01 can be connected to word line WL1, and the gate electrode of transistor T11 can also be connected to word line WL1. That is, the gate electrodes of transistors T01 and T11, located in the same column, can be connected to the same word line (i.e., word line WL1). The drain of transistor T01 can be connected to bit line BL0, and the drain of transistor T11 can be connected to bit line BL1. That is, the drains of transistors T01 and T11, located in the same column, can be connected to different bit lines.
[0126] Optionally, the first direction can be perpendicular to the stacking direction (which can be the Z direction) of the capacitors in the storage cells 10 to 40, which can realize the three-dimensional arrangement of the ferroelectric random access memory 100.
[0127] In other embodiments of this application, reference is made to Figure 4 Along the second direction, capacitors located in the same layer and in the same row in memory cells 10, 20, 30 and 40 can be connected to different capacitor lines, the control electrodes of transistors located in the same row in memory cells 10, 20, 30 and 40 can be connected to different word lines, and the second electrodes of transistors located in the same row in memory cells 10, 20, 30 and 40 can be connected to the same bit line.
[0128] For example, capacitors C001 and C011 are located on the same layer and in the same row. Capacitor C001 can be connected to capacitor line CL001, and capacitor C011 can be connected to capacitor line CL011. That is, capacitors C001 and C011, which are located on the same layer and in the same row, can be connected to different capacitor lines.
[0129] Similarly, capacitors C101 and C111 are located on the same layer and in the same row. Capacitor C101 can be connected to capacitor line CL001, and capacitor C111 can also be connected to capacitor line CL011. That is to say, capacitors C101 and C111, which are located on the same layer and in the same row, can be connected to different capacitor lines.
[0130] For example, capacitors C002 and C012 are located on the same layer and in the same row. Capacitor C002 can be connected to capacitor line CL002, and capacitor C012 can be connected to capacitor line CL012. That is, capacitors C002 and C012, which are located on the same layer and in the same row, can be connected to different capacitor lines.
[0131] Similarly, capacitors C102 and C112 are located on the same layer and in the same row. Capacitor C102 can be connected to capacitor line CL002, and capacitor C112 can also be connected to capacitor line CL012. That is to say, capacitors C102 and C112, which are located on the same layer and in the same row, can be connected to different capacitor lines.
[0132] For example, transistors T00 and T01 are located in the same row. The control electrode of transistor T00 can be connected to word line WL0, and the control electrode of transistor T01 can be connected to word line WL1. That is, the control electrodes of transistors T00 and T01, which are located in the same row, can be connected to different word lines. The drain of transistor T00 can be connected to bit line BL0, and the drain of transistor T01 can be connected to bit line BL0. That is, the drains of transistors T00 and T01, which are located in the same row, can be connected to the same bit line.
[0133] Similarly, transistors T10 and T11 are located in the same row. The control electrode of transistor T10 can be connected to word line WL0, and the control electrode of transistor T11 can be connected to word line WL1. That is, the control electrodes of transistors T10 and T11, located in the same row, can be connected to different word lines. The drain of transistor T10 can be connected to bit line BL1, and the drain of transistor T11 can be connected to bit line BL1. That is, the drains of transistors T10 and T11, located in the same row, can be connected to the same bit line.
[0134] Optionally, the second direction can be perpendicular to the stacking direction (which can be the Z direction) of the capacitors in the storage cells 10 to 40, which can realize the three-dimensional arrangement of the ferroelectric random access memory 100.
[0135] from Figure 4 It can be seen that, in the first and second directions, the ferroelectric random access memory 100 can be configured in the capacitor stacking direction by connecting the eight capacitors in storage cell 10 to their corresponding capacitor lines, the eight capacitors in storage cell 30 to their corresponding capacitor lines, the eight capacitors in storage cell 20 to their corresponding capacitor lines, the eight capacitors in storage cell 40 to their corresponding capacitor lines, the transistor T00 to its word line WL0 and bit line BL0, the transistor T10 to its word line WL0 and bit line BL1, the transistor T01 to its word line WL1 and bit line BL0, and the transistor T11 to its word line WL1 and bit line BL1. This is beneficial for improving the integration of the ferroelectric random access memory 100 and thus increasing its storage density.
[0136] It should be noted that, Figure 4 Only one schematic diagram of a ferroelectric random access memory 100 with four storage cells arranged in a square matrix along the first and second directions is shown. Of course, the ferroelectric random access memory 100 may also include five, six, or more storage cells, and the multiple storage cells may also be arranged in a rectangular matrix along the first and second directions. This embodiment will not be described in detail here.
[0137] In some embodiments of this application, Figures 1 to 4The operating phases of the provided ferroelectric random access memory 100 may include a standby phase S1, an act phase S2, a read phase S3, and a pre-charge phase S4, such as... Figure 5 As shown.
[0138] The activation phase S2 may include a read pre-charge phase S21, a fecapswitching phase S22, a charge sharing phase S23, and an amplification (SA sensing) phase S24.
[0139] The pre-charge phase S4 may include the write-back phase S41 and the standby pre-charge phase S42.
[0140] The following is for reference. Figure 5 The voltage (can be expressed in V) of the word lines (which can be any of the word lines mentioned above, such as word line WL0, etc.) in the above stages. WL The voltage (in V) of the capacitor line (which can be any of the above-mentioned capacitor lines, such as capacitor line CL001, etc.) is expressed as follows: CL The voltage (which can be represented by V) of the bit line (which can be any of the bit lines mentioned above, such as bit line BL0, etc.) and the bit line (which can be represented by V) BL (This is an explanation of the meaning of the text.)
[0141] (1) During the standby phase S1, the voltage V of the word line WL It can be the common ground voltage (can be V) ss This indicates that 0V can be used. The voltage V across the capacitor line. CL and the voltage V of the bit line BL The protection voltage of the capacitor can be set separately (using V). prot This means that 1V can be taken.
[0142] Additionally, during the standby phase S1, the voltage (which can be any of the aforementioned floating source terminals, such as floating source terminal FS00, etc.) of the floating source terminal (can be expressed as V) FS (This can be represented as) the protection voltage V of the capacitor. prot .
[0143] (2) During the read precharge phase S21, the voltage V of the word line is... WL It can be determined by the common ground voltage V ss Increase the on-state voltage of the transistor (such as transistor T00, etc.) (which can be expressed in V). dd This indicates that 2.9V can be taken and maintained at the transistor's on-state voltage V. dd The voltage V on the capacitor line CLIt can continue to be maintained at the capacitor's protection voltage V prot Voltage V of the bit line BL The protection voltage V of the capacitor can be used. prot Reduce to common ground voltage V ss And maintain the voltage V at the common ground terminal. ss .
[0144] Additionally, during the read precharge phase S21, the voltage V of the bit line... BL Similarly, the voltage V at the floating source terminal FS It can also be determined by the capacitor's protection voltage V. prot Reduce to common ground voltage V ss And maintain the voltage V at the common ground terminal. ss .
[0145] (3) During the destruction phase S22, the voltage V of the word line WL It can be determined by the transistor's on-state voltage V dd Reduce to common ground voltage V ss And maintain the voltage V at the common ground terminal. ss The voltage V on the capacitor line CL The protection voltage V of the capacitor can be used to determine this. prot Increase to the write voltage of the capacitor (can be expressed in V). w This indicates that 2V can be taken and maintained at the capacitor's write voltage V. w Voltage V of the bit line BL It can be determined by the common ground voltage V ss Increase to the reference voltage of the bit line (can be V) ref This indicates that a reference voltage V (0.5V) can be taken and maintained on the bit line. ref .
[0146] Additionally, during the destruction phase S22, the voltage V at the floating source terminal... FS There are two possible scenarios:
[0147] Scenario 1: If the binary data stored in the capacitor is 1, then the capacitor's polarity is reversed, and the capacitor can release its charge. The voltage V at the floating source terminal connected to the capacitor... FS Increase. When the binary data stored in the capacitor is 1, the voltage at the floating source terminal can be expressed as V. FS-r1 This indicates that you can refer to it. Figure 5 .
[0148] It should be noted that when the binary data stored in the capacitor is 1, the voltage V at the floating source terminal is... FS-r1 During the failure phase S22, the voltage will not increase to the capacitor's protection voltage V. prot In other words, the voltage V at the floating source terminal is 1 when the binary data stored in the capacitor is 1. FS-r1During the failure phase S22, the voltage can be less than the capacitor's protection voltage V. prot .
[0149] Scenario 2: If the binary data stored in the capacitor is 0, the polarity of the capacitor remains unchanged, the capacitor will not release charge, and the voltage V at the floating source terminal connected to the capacitor will remain constant. FS Continue to maintain the voltage V at the common ground terminal. ss When the binary data stored in the capacitor is 0, the voltage at the floating source terminal can be expressed as V. FS-r0 This indicates that you can refer to it. Figure 5 .
[0150] It should be noted that when the binary data stored in the capacitor is 0, the voltage V at the floating source terminal is... FS-r0 With common ground voltage V ss They may not be strictly equal in a mathematical sense. That is, when the binary data stored in the capacitor is 0, the voltage V at the floating source terminal... FS-r0 With common ground voltage V ss There can be discrepancies. For example, the voltage V at the floating source terminal when the binary data stored in the capacitor is 0. FS-r0 It can be greater than the common ground voltage V ss .
[0151] (4) During the charge sharing phase S23, the voltage V of the word line WL It can be determined by the common ground voltage V ss Increase to the transistor's on-state voltage V dd And maintain the transistor's on-state voltage V dd The voltage V on the capacitor line CL The write voltage V of the capacitor can be used to determine the capacitance. w Reduce to the capacitor's protection voltage V prot And maintain the capacitor's protection voltage V prot .
[0152] During the charge sharing phase S23, the voltage V of the bit line BL It can be based on the voltage V at the floating source terminal. FS With the reference voltage V of the bit line ref The size relationship is determined, and can be divided into the following two cases:
[0153] Case 1: If the voltage V at the floating source terminal FS The reference voltage V of the bit line is greater than ref Voltage V of the bit line BL From the reference voltage V of the bit line ref Increase. When the binary data stored in the capacitor is 1, the voltage on the bit line can be expressed in V. BL-r1 This indicates that you can refer to it. Figure 5 .
[0154] It should be noted that when the binary data stored in the capacitor is 1, the voltage V of the bit line is... BL-r1 During the charge sharing phase S23, the voltage will not increase to the capacitor's protection voltage V. prot In other words, during the charge sharing phase S23, when the binary data stored in the capacitor is 1, the voltage V of the bit line is... BL-r1 It can be less than the capacitor's protection voltage V prot .
[0155] Scenario 2: If the voltage V at the floating source terminal FS Less than the reference voltage V of the bit line ref Voltage V of the bit line BL From the reference voltage V of the bit line ref Decrease. When the binary data stored in the capacitor is 0, the voltage on the bit line can be expressed in V. BL-r0 This indicates that you can refer to it. Figure 5 .
[0156] Additionally, during the charge sharing phase S23, when the binary data stored in the capacitor is 1, the voltage V at the floating source terminal is... FS-r1 The voltage V at the floating source terminal can remain at 1 when the binary data stored in the capacitor during the destruction phase S22 is 1. FS-r1 The increased voltage. The voltage V at the floating source when the binary data stored in the capacitor is 0. FS-r0 The voltage V at the floating source terminal can remain at 0 when the binary data stored in the capacitor during the destruction phase S22 is 0. FS-r0 It can continue to maintain the voltage V at the common ground terminal. ss .
[0157] (5) During the amplification stage S24, the voltage V of the word line WL It can continue to maintain the transistor's on-state voltage V dd The voltage V on the capacitor line CL It can continue to be maintained at the capacitor's protection voltage V prot .
[0158] The voltage V of the bit line when the binary data stored in the capacitor is 1 BL-r1 The voltage increased during the charge-sharing phase S23 can be increased to the capacitor's protection voltage V. prot And maintain the capacitor's protection voltage V prot The voltage V on the bit line when the binary data stored in the capacitor is 0. BL-r0 The voltage can be reduced from the reduced voltage in charge-sharing stage S23 to the common ground voltage V. ss And maintain the voltage V at the common ground terminal. ss .
[0159] Additionally, during the amplification stage S24, the voltage V at the floating source terminal is 1 when the binary data stored in the capacitor is 1. FS-r1 The voltage can be increased to the capacitor's protection voltage V based on the charge sharing stage S23. prot And maintain the capacitor's protection voltage V prot The voltage V at the floating source terminal when the binary data stored in the capacitor is 0. FS-r0 It can continue to maintain the voltage V at the common ground terminal. ss .
[0160] (6) During the read phase S3, the voltage V of the word line WL It can continue to maintain the transistor's on-state voltage V dd The voltage V on the capacitor line CL It can continue to be maintained at the capacitor's protection voltage V prot Voltage V of the bit line BL (This could be the voltage V of the bit line when the binary data stored in the capacitor is 1) BL-r1 Or the voltage V of the bit line when the binary data stored in the capacitor is 0. BL-r0 It can continue to maintain the capacitor's protection voltage V. prot .
[0161] Additionally, during the read phase S3, the voltage V at the floating source terminal... FS (This can be expressed as V when the binary data stored in the capacitor is 1.) FS-r1 The voltage at the floating source terminal can be expressed as V when the binary data stored in the capacitor is 0. FS-r0 ) can be the protection voltage V of the capacitor prot .
[0162] (7) During the write-back phase S41, the voltage V of the word line WL It can be determined by the transistor's on-state voltage V dd Reduce to common ground voltage V ss And maintain the voltage V at the common ground terminal. ss The voltage V on the capacitor line CL The protection voltage V of the capacitor can be used. prot Reduce to common ground voltage V ss And maintain the voltage V at the common ground terminal. ss Voltage V of the bit line BL It can continue to be maintained at the capacitor's protection voltage V prot .
[0163] Additionally, during the write-back phase S41, the voltage at the floating source terminal when the binary data stored in the capacitor is 1 can be represented by V. FS-r1 The protection voltage V of the capacitor can be used. prot Increase to the minimum write voltage of the capacitor (which can be expressed in V). WMINThis indicates that 1.8V can be taken and maintained at the minimum write voltage V of the capacitor. WMIN The voltage V at the floating source terminal when the binary data stored in the capacitor is 0. FS-r0 The protection voltage V of the capacitor can be used. prot Decrease.
[0164] It should be noted that when the binary data stored in the capacitor is 0, the voltage V at the floating source terminal is... FS-r0 It will not decrease to the common ground voltage V ss In other words, during the write-back phase S41, when the binary data stored in the capacitor is 0, the voltage V at the floating source terminal is... FS-r0 It can be greater than the common ground voltage V ss .
[0165] (8) During the standby pre-charge phase S42, the voltage V of the word line is... WL It can be determined by the common ground voltage V ss Increase to the transistor's on-state voltage V dd And maintain the transistor's on-state voltage V dd After that, the voltage V of the word line... WL It can be determined by the transistor's on-state voltage V dd Reduce to common ground voltage V ss Therefore, the ferroelectric random access memory 100 returns to the standby stage S1. The voltage V on the capacitor line... CL It can be determined by the common ground voltage V ss Increase to the capacitor's protection voltage V prot And maintain the capacitor's protection voltage V prot Voltage V of the bit line BL It can continue to be maintained at the capacitor's protection voltage V prot .
[0166] Additionally, during the standby pre-charge phase S42, the voltage V at the floating source terminal... FS The protection voltage V of the capacitor can be used. prot .
[0167] In some embodiments of this application, it can be based on Figure 5 The voltage V of the word line shown WL Voltage V of the capacitor line CL and the voltage V of the bit line BL accomplish Figures 1 to 4 Selection of capacitors.
[0168] For example, targeting Figure 1 The voltage of word line WL0, capacitor line CL001, and bit line BL0 can be set as follows: Figure 5 The change process is shown. Therefore, the selection of capacitor C001 can be achieved.
[0169] For example, targeting Figure 2 The voltage of word line WL1, capacitor line CL018, and bit line BL0 can be set as follows: Figure 5 The change process is shown. Therefore, the selection of capacitor C018 can be achieved.
[0170] For example, targeting Figure 3 The voltages of word line WL0, capacitor line CL001, bit line BL0, and bit line BL1 can be set as follows: Figure 5 The change process is shown. Therefore, the selection of capacitors C001 and C101 can be achieved.
[0171] For example, targeting Figure 4 The voltages of word line WL0, capacitor line CL008, bit line BL0, and bit line BL1 can be set as follows: Figure 5 The change process is shown. Therefore, the selection of capacitors C008 and C108 can be achieved.
[0172] Therefore, the capacitors in storage cell 10 other than capacitor C008 (such as capacitor C007, etc.) and the capacitors in storage cell 20 other than capacitor C108 (such as capacitor C107, etc.) can be considered unselected capacitors. The voltage (which can be expressed in V) of the capacitor line corresponding to the unselected capacitor (such as capacitor line CL007, etc.) unselCL (This is a reference) Figure 5 .
[0173] like Figure 5 As shown, in the standby phase S1, read precharge phase S21, destruction phase S22, charge sharing phase S23, amplification phase S24, and read phase S3, the voltage V corresponding to the unselected capacitor line is... unselCL The protection voltage V of the capacitor can be used. prot In the write-back phase S41, the voltage V corresponding to the unselected capacitor line... unselCL The protection voltage V of the capacitor can be used. prot Increase to the write voltage V of the capacitor W During the standby pre-charge phase S42, the voltage V corresponding to the unselected capacitor line... unselCL The write voltage V of the capacitor can be used to determine the capacitance. W Reduce to the capacitor's protection voltage V prot And maintain the capacitor's protection voltage V prot .
[0174] Understandably, during the write-back phase S41, the voltage V corresponding to the unselected capacitor line... unselCL The write voltage V of the capacitor WThis causes the unselected capacitor lines to form a charge pump, thereby causing the voltage V at the source to float. FS It can be based on the voltage V corresponding to the unselected capacitor line. unselCL And increase to the minimum write voltage V of the capacitor WMIN Therefore, the voltage difference across the capacitor causes the ferroelectric polarity of the capacitor to be in the other direction, thus enabling the storage of binary data 1.
[0175] This application also provides an electronic device that may include the aforementioned ferroelectric random access memory 100. Of course, the electronic device may also include other components, and this application does not limit the scope of the invention.
[0176] Optionally, the electronic device can be a mobile phone, laptop computer, etc. Of course, the electronic device can also be other devices, and this application embodiment does not limit the scope.
[0177] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A ferroelectric random access memory, characterized in that, Includes storage units; The storage unit includes transistors and multiple capacitors; The first terminal of each of the plurality of capacitors is used to connect to a corresponding capacitor line, the second terminal of each of the capacitors is used to connect to the first electrode of the transistor, the control electrode of the transistor is used to connect to the word line, the second electrode of the transistor is used to connect to the bit line, and the polarity of the second terminal of each capacitor is the same. The transistor is used to select any one of the plurality of capacitors based on the voltage of each of the capacitor line, the word line, and the bit line. Each capacitor is used to store data.
2. The ferroelectric random access memory according to claim 1, characterized in that, The multiple capacitors are stacked.
3. The ferroelectric random access memory according to claim 2, characterized in that, The ferroelectric random access memory includes at least two storage cells, which are arranged along a first direction or a second direction. The first direction is different from the second direction.
4. The ferroelectric random access memory according to claim 3, characterized in that, Along the first direction, the capacitors located on the same layer in the at least two memory cells are connected to different capacitor lines, the control electrode of the transistor in each of the at least two memory cells is connected to different word lines, and the second electrode of the transistor in each memory cell is connected to the same bit line.
5. The ferroelectric random access memory according to claim 3 or 4, characterized in that, Along the second direction, the capacitors in the same layer of the at least two memory cells are connected to the same capacitor line, the control electrode of the transistor in each of the at least two memory cells is connected to the same word line, and the second electrode of the transistor in each memory cell is connected to different bit lines.
6. The ferroelectric random access memory according to claim 2, characterized in that, The ferroelectric random access memory includes at least four storage cells, which are arranged in a matrix along a first direction and a second direction.
7. The ferroelectric random access memory according to claim 6, characterized in that, Along the first direction, the capacitors in the same layer and in the same column of the at least four memory cells are connected to the same capacitor line, the control electrodes of the transistors in the same column of the at least four memory cells are connected to the same word line, and the second electrodes of the transistors in the same column of the at least four memory cells are connected to different bit lines.
8. The ferroelectric random access memory according to claim 6 or 7, characterized in that, Along the second direction, the capacitors in the same layer and in the same row of the at least four memory cells are connected to different capacitor lines, the control electrodes of the transistors in the same row of the at least four memory cells are connected to different word lines, and the second electrodes of the transistors in the same row of the at least four memory cells are connected to the same bit line.
9. The ferroelectric random access memory according to any one of claims 3 to 8, characterized in that, The first direction is perpendicular to the second direction.
10. The ferroelectric random access memory according to any one of claims 3 to 9, characterized in that, The first direction is perpendicular to the stacking direction of the plurality of capacitors; The second direction is perpendicular to the stacking direction.
11. The ferroelectric random access memory according to any one of claims 2 to 10, characterized in that, The second terminal of each capacitor is used to connect to the first terminal of the transistor via a floating source terminal.
12. The ferroelectric random access memory according to claim 11, characterized in that, The floating source terminal has a columnar structure, and each capacitor is arranged on the floating source terminal along the extension direction of the floating source terminal.
13. The ferroelectric random access memory according to any one of claims 1 to 12, characterized in that, Each of the capacitors is a ferroelectric capacitor.
14. The ferroelectric random access memory according to any one of claims 1 to 13, characterized in that, The transistor is a field-effect transistor.
15. The ferroelectric random access memory according to any one of claims 1 to 14, characterized in that, The first electrode of the transistor is the source, and the second electrode of the transistor is the drain.
16. The ferroelectric random access memory according to any one of claims 1 to 15, characterized in that, The first terminal of each capacitor is the negative terminal, and the second terminal of each capacitor is the positive terminal.
17. An electronic device, characterized in that, The electronic device includes a ferroelectric random access memory as claimed in any one of claims 1 to 16.
Citation Information
Patent Citations
Memory cell arrangement and method thereof
CN114446345A