Detection drive circuit and system

Abstract

The application discloses a detection driving circuit and system, wherein the detection driving circuit is connected with a power device and a sampling module, the sampling module is connected with the power device to sample current on the power device and generate a sampling signal, and the detection driving circuit comprises a control module, a driving unit, a signal detection module and a signal processing module. The detection driving circuit and system of the application sample current on the power device through the sampling module, detect whether a chip pin is accidentally suspended through an open circuit signal generation module, process signals generated by the sampling module and the open circuit signal generation module through the signal detection module and the signal processing module, and then determine whether to forcibly close the power device through the control module to ensure safety of the device and the system. The control module can automatically restart and recover to normal after a certain time without an additional external reset signal, which is simpler in application and is beneficial to reducing system cost.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a detection drive circuit and system. Background Art

[0002] The voltage and current of a circuit directly determine the power. To ensure safe and reliable use over a long period of time, each electronic device has a maximum power limit, which is usually achieved through overcurrent protection (OCP).

[0003] The detection and drive circuitry of a driver chip typically consists of an overcurrent detection section and an overcurrent processing section. Overcurrent detection can be achieved by directly sensing the current in the channel or indirectly by detecting the voltage across a sampling resistor through which the current flows. The sampling resistor is typically located externally and connected to the on-chip circuitry via a sampling pin. After detecting an overcurrent in the channel, the overcurrent processing section is triggered to respond. This response typically begins by shutting down the corresponding circuit through a soft turn-off. This then requires waiting for an external reset signal (reset). After a certain period of soft turn-off, the circuit automatically restarts based on the external reset signal and returns to normal operation.

[0004] Existing driver chips lack the ability to detect when the sampling pin is left floating. Consequently, the overcurrent protection function fails to operate properly when the sampling pin is accidentally left floating. Furthermore, since an external reset signal is required to restart the circuit, the driver chip must report the overcurrent triggering signal to an external controller after detecting an overcurrent in the external power device. The external controller then generates a reset signal to reset the driver unit circuit before the external power device can be restarted. This results in a complex and costly system.

[0005] The information disclosed in this background technology section is only intended to enhance understanding of the overall background of the invention and should not be regarded as an admission or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the Invention

[0006] The object of the present invention is to provide a detection drive circuit and system, which can automatically detect overcurrent and pin hanging of power devices and trigger overcurrent protection when these problems occur.

[0007] To achieve the above-mentioned object, a specific embodiment of the present invention provides a detection drive circuit connected to a power device and a sampling module. The sampling module is connected to the power device to sample the current on the power device and generate a sampling signal. The detection drive circuit includes: a control module, a drive unit, a signal detection module, and a signal processing module;

[0008] The control module is used to control the driving unit to generate a driving signal based on the input signal to drive the power device; the signal detection module is connected to the sampling module and forms a first node and a second node to receive the sampling signal and generate a detection signal based on the sampling signal and the reference signal;

[0009] The signal processing module is connected to the signal detection module, and the signal processing module is used to generate a first control signal based on the input signal and the drive signal, and to generate a second control signal based on the first control signal and the detection signal; the control module is connected to the signal processing module, and the control module controls the drive unit to adjust the drive signal based on the second control signal.

[0010] In one or more embodiments of the present invention, the detection drive circuit further includes an open circuit signal generating module;

[0011] The open circuit signal generating module is connected to the first node, and the open circuit signal generating module is used to generate a first characterization signal indicating whether an open circuit occurs between the sampling module and the first node; the signal detection module is used to generate a detection signal based on the first characterization signal and the reference signal or the sampling signal and the reference signal; or

[0012] The open circuit signal generating module is connected to the first node and the second node, and is used to generate a first characterization signal indicating whether an open circuit occurs between the sampling module and the first node and / or generate a second characterization signal indicating whether an open circuit occurs between the sampling module and the second node; the signal detection module is used to generate a detection signal based on the sampling signal and the reference signal, or the first characterization signal and / or the second characterization signal.

[0013] In one or more embodiments of the present invention, the signal processing module is configured to generate a first control signal when the input signal is at a valid level and the driving signal is greater than a threshold voltage of the power device.

[0014] In one or more embodiments of the present invention, the sampling module includes a sampling resistor, a first end of the sampling resistor is connected to the power device and the signal detection module to form a first node, and a second end of the sampling resistor is connected to the second voltage and the signal detection module to form a second node; or

[0015] The sampling module includes a sampling resistor, a first resistor, a second resistor, and a capacitor. The first end of the first resistor and the first end of the sampling resistor are connected to the power device, the second end of the first resistor and the first end of the capacitor are connected to the signal detection module and form a first node, the second end of the capacitor and the first end of the second resistor are connected to the signal detection module and form a second node, and the second end of the second resistor and the second end of the sampling resistor are connected to the second voltage.

[0016] In one or more embodiments of the present invention, the open circuit signal generating module includes a first resistor unit, a first end of the first resistor unit is connected to a first voltage, and a second end of the first resistor unit is connected to a first node to generate a first characterization signal indicating whether an open circuit occurs between the sampling module and the first node; or

[0017] The open circuit signal generating module includes a first resistance unit and a second resistance unit, wherein the first end of the first resistance unit and the first end of the second resistance unit are connected to a first voltage, the second end of the first resistance unit is connected to a first node to generate a first characterization signal indicating whether an open circuit occurs between the sampling module and the first node, and the second end of the second resistance unit is connected to a second node to generate a second characterization signal indicating whether an open circuit occurs between the sampling module and the second node.

[0018] In one or more embodiments of the present invention, the signal detection module includes a comparison module, a first input end of the comparison module is used to receive a sampling signal, a second input end of the comparison module is used to receive a reference signal, and the comparison module is used to compare the sampling signal with the reference signal to generate a detection signal.

[0019] In one or more embodiments of the present invention, the signal detection module includes a comparison module, a first input terminal of the comparison module is connected to the first node to receive the sampling signal or the first characterization signal, a second input terminal of the comparison module is used to receive the reference signal, and the comparison module is used to compare the sampling signal with the reference signal or compare the first characterization signal with the reference signal to generate a detection signal, or

[0020] The signal detection module includes a comparison module, a detection module and a first logic circuit. The first input end of the comparison module is connected to the first node, the second input end of the comparison module is used to receive a reference signal, the comparison module is used to compare the sampling signal with the reference signal to generate a third characterization signal, the detection module is connected to the first node and the second node, the detection module is used to generate a first open-circuit characterization signal based on the first characterization signal and a second open-circuit characterization signal based on the second characterization signal, the first logic circuit is connected to the comparison module and the detection module, and the first logic circuit is used to perform logical operations on the third characterization signal, the first open-circuit characterization signal and the second open-circuit characterization signal to generate a detection signal.

[0021] In one or more embodiments of the present invention, the detection module includes a first detection circuit and a second detection circuit, the input end of the first detection circuit is connected to the first node, the output end of the first detection circuit is connected to the first logic circuit, the first detection circuit is used to generate a first open-circuit characterization signal based on the first characterization signal, the input end of the second detection circuit is connected to the second node, the output end of the second detection circuit is connected to the first logic circuit, and the second detection circuit is used to generate a second open-circuit characterization signal based on the second characterization signal.

[0022] In one or more embodiments of the present invention, the first detection circuit includes a first switching tube, a second switching tube, a first current source, a second current source, and a trigger, wherein the control end of the first switching tube is used to form an input end of the first detection circuit, the first end of the first switching tube and the first end of the second current source are connected to a first voltage, the second end of the first switching tube and the first end of the first current source are connected to the control end of the second switching tube, the second end of the first current source and the first end of the second switching tube are connected to a second voltage, the second end of the second current source and the second end of the second switching tube are connected to the input end of the trigger, and the output end of the trigger is used to output a first open circuit characterization signal; or

[0023] The first detection circuit includes a first switching tube, a second switching tube, a first current source, a second current source, a trigger and a delay circuit, wherein the control end of the first switching tube is used to form the input end of the first detection circuit, the first end of the first switching tube and the first end of the second current source are connected to a first voltage, the second end of the first switching tube and the first end of the first current source are connected to the control end of the second switching tube, the second end of the first current source and the first end of the second switching tube are connected to a second voltage, the second end of the second current source and the second end of the second switching tube are connected to the input end of the trigger, and the delay circuit is connected to the output end of the trigger to delay the signal output by the trigger to generate a first open circuit characterization signal; and / or

[0024] The structure of the second detection circuit is the same as that of the first detection circuit.

[0025] In one or more embodiments of the present invention, the signal processing module includes a first processing unit and a second processing unit, the first processing unit is used to generate a first control signal based on the input signal and the drive signal, the second processing unit is connected to the control signal generating unit, the signal detection module and the control module, and the second processing unit is used to generate a second control signal based on the first control signal and the detection signal.

[0026] In one or more embodiments of the present invention, the first processing unit includes a judgment unit and a first delay unit, the judgment unit is used to judge the driving signal and the input signal and generate a judgment signal, and the first delay unit is used to delay the judgment signal and generate a first control signal.

[0027] In one or more embodiments of the present invention, the second processing unit includes a second logic circuit and a second delay unit, the second logic circuit is connected to the first processing unit, the signal detection module and the second delay unit, the second logic circuit is used to perform logical operations on the detection signal and the first control signal, and the second delay unit is used to delay the operation result of the second logic circuit and generate a second control signal.

[0028] In one or more embodiments of the present invention, the control module is configured to control the driving unit to adjust the driving signal under the control of the second control signal and then control the driving unit to generate the driving signal based on the input signal.

[0029] The present invention also discloses a detection drive system, comprising a drive chip, a power device and a sampling module, wherein the control module, the drive unit, the signal detection module and the signal processing module are arranged in the drive chip;

[0030] The control module, the driving unit and the power device are connected in sequence, the control module is used to control the driving unit to generate a driving signal based on an input signal to drive the power device, and the power device generates a current based on the driving signal;

[0031] The driver chip is provided with a first pin and a second pin, the sampling module is connected to the power device, the first pin and the second pin, and the sampling module is used to collect the current on the power device to obtain a sampling signal and transmit the sampling signal to the first pin and the second pin;

[0032] The signal detection module is connected to the first pin and the second pin, and the signal detection module is used to generate a detection signal based on the sampling signal and the reference signal;

[0033] The signal processing module is connected to the signal detection module, and the signal processing module is used to generate a first control signal based on the input signal and the drive signal, and generate a second control signal based on the first control signal and the detection signal;

[0034] The control module is connected to the signal processing module, and the control module controls the driving unit to adjust the driving signal based on the second control signal.

[0035] In one or more embodiments of the present invention, the driver chip is further provided with an open circuit signal generating module;

[0036] The open circuit signal generating module is connected to the first pin, and the open circuit signal generating module is used to generate a first characterization signal indicating whether an open circuit occurs between the first pin and the sampling module; the signal detection module is used to generate a detection signal based on the first characterization signal and the reference signal or the sampling signal and the reference signal; or

[0037] The open circuit signal generating module is connected to the first pin and the second pin, and is used to generate a first characterization signal indicating whether an open circuit occurs between the first pin and the sampling module and / or generate a second characterization signal indicating whether an open circuit occurs between the second pin and the sampling module; the signal detection module is used to generate a detection signal based on the sampling signal and the reference signal, or the first characterization signal and / or the second characterization signal.

[0038] Compared with the existing technology, the detection drive circuit and system of the present invention samples the current on the power device through the sampling module to effectively detect whether the current of the power device exceeds the safe operating current. The open-circuit signal generation module detects whether each node or chip pin is accidentally left floating. The signal detection module and the signal processing module process the signals generated by the sampling module and the open-circuit signal generation module, and then decide through the control module whether to forcibly shut down the power device to ensure the safety of the device and the system.

[0039] The open-circuit signal generation module ensures that power devices remain off even if nodes or chip pins are accidentally left floating, preventing uncontrolled current flow in the power devices and improving system safety. The control module automatically restarts and returns to normal operation after a certain period without requiring an external reset signal, simplifying application and reducing system costs. By activating the driver unit based on the edge of the input signal, the driver chip restart process is safer. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments described in the present invention. Those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0041] Figure 1 4 is a circuit schematic diagram of the detection drive circuit in embodiment 1 of the present invention.

[0042] Figure 2 4 is a circuit schematic diagram of the detection circuit in Example 1 of the present invention.

[0043] Figure 3 2 is a signal waveform diagram of the detection driving circuit in the first embodiment of the present invention.

[0044] Figure 4 2 is a circuit schematic diagram of the detection drive circuit in the second embodiment of the present invention. DETAILED DESCRIPTION

[0045] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0046] The terms "coupled," "connected," or "connected" as used in this specification encompass both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrically conductive medium, which may have parasitic inductance or capacitance. An indirect connection may also include a connection through other active or passive devices, such as switches, follower circuits, or other circuits or components, to achieve the same or similar functional objectives. Furthermore, in the invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another and do not necessarily require or imply a specific relationship, quantity, or order between these technical features.

[0047] Example 1

[0048] like Figure 1 and Figure 3 As shown, the detection drive circuit in one embodiment of the present invention is connected to the power device Mp and the sampling module 30. The sampling module 30 is connected to the power device Mp to sample the current on the power device Mp and generate a sampling signal OCP. The detection drive circuit includes a control module 10, a drive unit 20, an open circuit signal generating module 40, a signal detection module 50 and a signal processing module 60.

[0049] The control module 10 is connected to the drive unit 20, which is connected to the control terminal of the power device Mp. The control module 10 is configured to control the drive unit 20 to generate a drive signal OUT based on an input signal IN to drive the power device Mp. In one embodiment, the power device Mp is an N-channel MOS transistor, the control terminal of the power device Mp is the gate, and the sampling terminal of the power device Mp is connected to the source of the power device Mp. The sampling terminal of the power device Mp outputs a sampling current Isense proportional to the current flowing through the power device Mp. In other embodiments, the power device Mp may be a P-channel MOS transistor.

[0050] The signal detection module 50 is connected to the sampling module 30 and forms a first node OCPP and a second node OCPN to receive the sampling signal OCP.

[0051] The open circuit signal generating module 40 is connected to the first node OCPP and the second node OCPN. The open circuit signal generating module 40 is used to generate a first characterization signal indicating whether an open circuit occurs between the sampling module 30 and the first node OCPP, and to generate a second characterization signal indicating whether an open circuit occurs between the sampling module 30 and the second node OCPN.

[0052] The signal detection module 50 is configured to generate a detection signal based on the sampling signal OCP and the reference signal VREF, or the first characterization signal and / or the second characterization signal.

[0053] The signal processing module 60 is connected to the signal detection module 50, and the signal processing module 60 is used to generate a first control signal OCPBT based on the input signal IN and the drive signal OUT, and to generate a second control signal OCP based on the first control signal OCPBT and the detection signal trigger In one embodiment, the signal processing module 60 is used to: TH In one embodiment, the high level is the effective level of the input signal IN.

[0054] The control module 10 is connected to the signal processing module 60. The control module 10 is based on the second control signal OCP. trigger The driving unit 20 is controlled to adjust the driving signal OUT.

[0055] In one embodiment, if Figure 1 and Figure 3 As shown, the drive unit 20 includes a main drive circuit and a soft-off drive circuit. The input signal IN is a digital signal with two states: high and low. When the input signal IN is high, the control module 10 controls the main drive circuit in the drive unit 20, which has strong current driving capability, to generate a higher voltage drive signal OUT, enabling the power device Mp to be quickly turned on and generate current.

[0056] like Figure 1As shown, the sampling module 30 includes a sampling resistor Rsense, a first resistor R1, a second resistor R2, and a capacitor C1. The first end of the first resistor R1 and the first end of the sampling resistor Rsense are connected to the sampling terminal of the power device Mp. The second end of the first resistor R1 and the first end of the capacitor C1 are connected to the signal detection module 50 to form a first node OCPP. The second end of the capacitor C1 and the first end of the second resistor R2 are connected to the signal detection module 50 to form a second node OCPN. The second end of the second resistor R2 and the second end of the sampling resistor Rsense are connected to the second voltage.

[0057] like Figure 1 and Figure 3 As shown, the first end of sampling resistor Rsense is connected to the sampling terminal of power device Mp, converting the sampled current Isense into a sampling signal OCP. First resistor R1, second resistor R2, and capacitor C1 form a common-mode filter, enhancing the sampling signal OCP's anti-interference capability. The sampling signal OCP is differentially input to first node OCPP and second node OCPN. When the current flowing through power device Mp is stable, the voltage at first node OCPP equals the sampling signal OCP, and the voltage at second node OCPN equals the second voltage.

[0058] The open circuit signal generating module 40 includes a first resistor unit and a second resistor unit. The first end of the first resistor unit and the first end of the second resistor unit are connected to a first voltage. The second end of the first resistor unit is connected to a first node OCPP to generate a first signal indicating whether an open circuit has occurred between the sampling module 30 and the first node OCPP. The second end of the second resistor unit is connected to a second node OCPN to generate a second signal indicating whether an open circuit has occurred between the sampling module 30 and the second node OCPN. In one embodiment, the first voltage is the power supply voltage VDD, and the second voltage is the ground voltage GND.

[0059] In one embodiment, the first resistor unit includes a third resistor R3, and the second resistor unit includes a fourth resistor R4. A first end of the third resistor R3 and a first end of the fourth resistor R4 are connected to a first voltage, a second end of the third resistor R3 is connected to a first node OCPP, and a second end of the fourth resistor R4 is connected to a second node OCPN.

[0060] When the circuit between the sampling module 30 and the first node OCPP is open, the third resistor R3 pulls up the voltage at the first node OCPP to the first voltage, generating a first indicative signal of a high level (VDD). When the circuit between the sampling module 30 and the second node OCPN is open, the fourth resistor R4 pulls up the voltage at the second node OCPN to the first voltage, generating a second indicative signal of a high level (VDD).

[0061] like Figure 1As shown, the signal detection module 50 comprises a comparison module CMP, a detection module and a first logic circuit OR.

[0062] A first input terminal of the comparison module CMP is connected with the first node OCPP, and a second input terminal of the comparison module CMP is configured to receive a reference signal VREF. In an embodiment, the reference signal VREF is generated by a voltage generating circuit connected with the second node OCPN, i.e. the reference signal VREF is generated relative to a ground voltage GND. The comparison module CMP is configured to compare the sampling signal OCP with the reference signal VREF to generate a third characteristic signal representing whether the power device Mp is overcurrent. In an embodiment, the comparison module CMP is a comparator, the first input terminal of the comparison module CMP is a positive input terminal, and the second input terminal of the comparison module CMP is a negative input terminal.

[0063] When the sampling signal OCP is less than the reference signal VREF, the third characteristic signal output by the comparison module CMP is low, indicating that the power device Mp is not overcurrent. When the sampling signal OCP is greater than or equal to the reference signal VREF, the third characteristic signal output by the comparison module CMP is high, indicating that the current on the power device Mp is too large.

[0064] As shown in Figure 1 The detection module is connected with the first node OCPP and the second node OCPN, and is configured to generate a first open-circuit characteristic signal based on the first characteristic signal and a second open-circuit characteristic signal based on the second characteristic signal.

[0065] Specifically, the detection module comprises a first detection circuit 51 and a second detection circuit 52. An input terminal of the first detection circuit 51 is connected with the first node OCPP, and an output terminal of the first detection circuit 51 is configured to generate the first open-circuit characteristic signal. An input terminal of the second detection circuit 52 is connected with the second node OCPN, and an output terminal of the second detection circuit 52 is configured to generate the second open-circuit characteristic signal.

[0066] As shown in Figure 2As shown, the first detection circuit 51 comprises a first switch tube M1, a second switch tube M2, a first current source I1, a second current source I2, a flip-flop SMT and a delay circuit Delay. The control end of the first switch tube M1 is used to form an input end of the first detection circuit 51, the first end of the first switch tube M1 and the first end of the second current source I2 are connected to the first voltage, the second end of the first switch tube M1 and the first end of the first current source I1 are connected to the control end of the second switch tube M2, the second end of the first current source I1 and the first end of the second switch tube M2 are connected to the second voltage, the second end of the second current source I2 and the second end of the second switch tube M2 are connected to the input end of the flip-flop SMT, the input end of the delay circuit Delay is connected to the output end of the flip-flop SMT, and the output end of the delay circuit Delay forms an output end of the first detection circuit 51 to output a first open circuit characteristic signal after delay. The interference signal in the circuit is filtered out through the delay circuit Delay to output the first open circuit characteristic signal. In other embodiments, the delay circuit Delay can not be provided.

[0067] In an embodiment, the first switch tube M1 is a P-channel MOS tube, the second switch tube M2 is an N-channel MOS tube, the first end of the first switch tube M1 and the first end of the second switch tube M2 are source electrodes, the second end of the first switch tube M1 and the second end of the second switch tube M2 are drain electrodes, and the control end of the first switch tube M1 and the control end of the second switch tube M2 are gate electrodes. The flip-flop SMT is a Schmitt trigger. In other embodiments, the first switch tube M1 can be an N-channel MOS tube, and the second switch tube M2 can be a P-channel MOS tube, and their connection modes are adaptively adjusted.

[0068] The current value of the first current source I1 is I1, and the current value of the second current source I2 is I2. When the voltage of the first node OCPP is greater than VDD-|Vgs1| (where Vgs1 is the gate-source voltage when the saturation current of the first switch tube M1 is equal to I1), the first switch tube M1 is disconnected, the first current source I1 pulls down the gate voltage of the second switch tube M2, the second switch tube M2 is disconnected, the second current source I2 pulls up the input end voltage of the flip-flop SMT, the flip-flop SMT generates a high-level signal, and after the delay of the delay circuit Delay, a high-level signal is output. Conversely, when the voltage of the first node OCPP is less than VDD-|Vgs1|, the first switch tube M1 is turned on, the gate of the second switch tube M2 is pulled up, the second switch tube M2 is turned on and the input end voltage of the flip-flop SMT is pulled down, the flip-flop SMT outputs a low-level signal, and after the delay of the delay circuit Delay, a low-level signal is output.

[0069] As can be seen from the foregoing, when the circuit between the sampling module 30 and the first node OCPP is open, the third resistor R3 pulls the voltage at the first node OCPP up to the first voltage, causing the first detection circuit 51 to output a high-level first open-circuit indication signal. When the sampling module 30 is properly connected to the first node OCPP, the voltage at the first node OCPP will not turn off the first switch M1, as the reference signal VREF for determining whether the power device Mp has an overcurrent is significantly lower than VDD-|Vgs1|. Consequently, the first open-circuit indication signal output by the first detection circuit 51 will be low.

[0070] The structure, connection relationship, and signal generation method of the second detection circuit 52 are the same as those of the first detection circuit 51. When the circuit between the sampling module 30 and the second node OCPN is open, the second detection circuit 52 outputs a second open circuit indication signal of a high level. When the sampling module 30 and the second node OCPN are properly connected, the second detection circuit 52 outputs a second open circuit indication signal of a low level.

[0071] In other embodiments, the first voltage may also be other voltage sources, as long as its voltage value is greater than VDD-|Vgs1|.

[0072] like Figure 1 As shown, the three input terminals of the first logic circuit OR are connected to the output terminal of the comparison module CMP, the output terminal of the first detection circuit 51, and the output terminal of the second detection circuit 52, and the output terminal of the first logic circuit OR is connected to the signal processing module 60. The first logic circuit OR is used to perform an OR logic operation on the third indication signal, the first open circuit indication signal, and the second open circuit indication signal to generate a detection signal.

[0073] When the power device Mp is overcurrent, or the circuit between the sampling module 30 and the first node OCPP is open, or the circuit between the sampling module 30 and the second node OCPN is open, or both the circuits between the sampling module 30 and the first node OCPP and the second node OCPN are open, the detection signal will flip to a high level, thereby triggering protection. Only when the sampling module 30 is properly connected to the first node OCPP and the second node OCPN, and the power device Mp is not overcurrent, will the detection signal be a low level.

[0074] like Figure 1 As shown, the signal processing module 60 includes a first processing unit and a second processing unit. The first processing unit is used to generate a first control signal OCPBT based on the input signal IN and the drive signal OUT. In one embodiment, the signal processing module 60 is used to generate a first control signal OCPBT when the input signal IN is at a valid level and the drive signal OUT is greater than the threshold voltage V THThe second processing unit is connected to the first processing unit, the signal detection module 50 and the control module 10, and is used to generate a second control signal OCP based on the first control signal OCPBT and the detection signal trigger .

[0075] The first processing unit includes a judgment unit 61 and a first delay unit 62. The judgment unit 61 is used to perform a logical judgment on the drive signal OUT and the input signal IN and generate a judgment signal. In one embodiment, the judgment unit 61 generates a judgment signal when the input signal IN is at a valid level and the drive signal OUT is greater than the threshold voltage V TH The first delay unit 62 is used to delay the judgment signal and generate a first control signal OCPBT.

[0076] Specifically, when the driving signal OUT is greater than the threshold voltage V TH , and when the input signal IN is high, the judgment unit 61 generates a judgment signal of high level, otherwise the judgment signal is low level. The first delay unit 62 delays the rising edge of the judgment signal by a first time t OCPBT Then the first control signal OCPBT is generated.

[0077] The second processing unit includes a second logic circuit AND and a second delay unit 63. Input terminals of the second logic circuit AND are connected to the first processing unit, the signal detection module 50 and the second delay unit 63. The second logic circuit AND is configured to perform an AND logic operation on the detection signal and the first control signal OCPBT.

[0078] The second delay unit 63 is used to delay the result of the AND logic operation and generate a second control signal OCP trigger .

[0079] Specifically, the second delay unit 63 delays the rising edge of the AND logic operation result by a second time t deglitch Then generate the second control signal OCP trigger .

[0080] like Figure 3 As shown, during the power-up process, the input signal IN transitions from low to high. The control module 10 controls the main drive circuit to generate a high-level drive signal OUT to drive the power device Mp. The sampling signal OCP increases synchronously with the sampling current Isense in the power device Mp. When the power device Mp has an overcurrent, or when there is an open circuit between the sampling module 30 and the first node OCPP, or between the sampling module 30 and the second node OCPN, or when there are open circuits between the sampling module 30 and the first node OCPP and between the sampling module 30 and the second node OCPN, the signal detection module 50 will generate a high-level detection signal.

[0081] When the voltage value of the driving signal OUT is detected to exceed the threshold voltage V TH of the power device Mp, and the input signal IN is also at a high level, the judgment signal generated by the judgment unit 61 rises to a high level, and the rising edge of the judgment signal indicates that the circuit enters the power-on stage. Then the first delay unit 62 delays the judgment signal by a first time t OCPBT and then generates the first control signal OCPBT. Because of the sudden increase in current caused by the sudden opening of the power device Mp, the sampling signal OCP has a large ring (oscillation and distortion) due to the parasitic inductance of the wire, and it takes a period of time to stabilize, which can make the detection signal rise and trigger the overcurrent protection. The first control signal OCPBT has a low level during the power-on process, and the "and" logic of the second logic circuit AND shields the detection signal, so that only when the first control signal OCPBT rises, the high level of the detection signal can be transmitted to the output of the second logic circuit AND, thereby preventing the circuit protection from being triggered by mistake.

[0082] Because the first delay unit 62 only delays the rising edge and does not delay the falling edge, when the input signal IN is at a low level, the first control signal OCPBT is synchronized to be at a low level, that is, when the power device Mp is not driven, even if the first node OCPP and / or the second node OCPN is open-circuited or other abnormal overcurrent phenomenon occurs, the circuit protection will not be triggered.

[0083] The second delay unit 63 delays the logic operation result signal of the second logic circuit AND to delay the arrival of the rising edge of the logic operation result signal of the second logic circuit AND, thereby filtering the spike pulse and further enhancing the anti-interference ability.

[0084] In addition, the control module 10 controls the soft turn-off driving circuit in the driving unit to adjust the driving signal OUT under the control of the second control signal OCP trigger , and then controls the main driving circuit of the driving unit to generate the driving signal OUT based on the input signal IN after the hiccup time t HICCUP .

[0085] Specifically, the high level of the second control signal OCPtrigger is effective, and after the control module 10 receives the high level of the second control signal OCPtrigger, the soft turn-off driving circuit generates a gradually decreasing driving signal OUT, thereby performing soft turn-off on the power device Mp. After the control module 10 receives the high level of the second control signal OCP trigger , the soft turn-off driving circuit performs soft turn-off on the power device Mp, and the driving signal OUT is forced to remain at a low level for a period of time, i.e. the hiccup time t HICCUPDuring the hiccup time, whether the input signal IN is high or not, the drive signal OUT remains low. HICCUP After the hiccup time t, the drive signal OUT turns high again and turns on the power device Mp when the input signal IN has a rising edge. That is, the restart of the power device Mp is synchronized with the rising edge of the input signal IN. HICCUP After the drive signal OUT is directly turned high, it may happen that the input signal IN changes from high to low. In this case, the drive signal OUT will send a narrow pulse that may cause the power device Mp to turn on abnormally. By synchronizing the rising edge of the drive signal OUT with the input signal IN, such a narrow pulse can be avoided, thereby ensuring the normal operation of the power device Mp.

[0086] In other embodiments, the second control signal OCPtrigger may also be valid at a low level, in which case the control module 10 adopts the opposite control logic, and the signal detection module 50 and the signal processing module 60 may generate the second control signal OCPtrigger having the opposite characterization meaning by adding an inverter or adjusting the circuit structure.

[0087] The shutdown mode is not limited to the common soft shutdown mode of directly pulling down the driving signal OUT, but may also be other shutdown modes such as two-stage shutdown mode.

[0088] In other embodiments, the sampling module 30 can be replaced with a current sampling circuit, and the comparator can be replaced with a current comparator. The current sampling circuit obtains a current proportional to the external device, and the current comparator is used internally to determine overcurrent and generate a third characterization signal. Alternatively, the voltage across the power device can be directly detected to generate a sampling signal reflecting the current magnitude.

[0089] like Figure 1 As shown, one embodiment of the present invention further discloses a detection and driving system, including a driver chip, a power device Mp, and a sampling module 30. The driver chip is provided with the aforementioned control module 10, drive unit 20, open-circuit signal generating module 40, signal detection module 50, and signal processing module 60. In other embodiments, the sampling module 30 and the power device Mp may be replaced by other external circuits.

[0090] The driver chip is provided with a first pin, a second pin, an input pin and an output pin.

[0091] The control module 10 and the judgment unit 61 are connected to the input pin to receive the input signal IN, and the driving module 20 is connected to the control terminal of the power device Mp through the output pin to transmit the driving signal OUT to the power device Mp.

[0092] The first pin and the second pin correspond to the first node OCPP and the second node OCPN. The second end of the third resistor R3, the first input end of the comparison module CMP, and the input end of the first detection circuit 51 are connected to the first pin. The first pin is also connected to the second end of the first resistor R1 and the first end of the capacitor C1 in the sampling module 30.

[0093] The second end of the fourth resistor R4, the second end of the voltage source, and the input end of the second detection circuit 52 are connected to the second pin, which is also connected to the first end of the second resistor R2 and the second end of the capacitor C1 in the sampling module 30.

[0094] When the sampling module 30 is properly connected to the first and second pins, the on-chip circuitry performs its overcurrent protection function normally. When the first and / or second pins are left floating, the corresponding first detection circuit 51 or second detection circuit 52 generates a high-level signal, causing the second control signal OCPtrigger to go high, triggering circuit protection. The detailed circuit principles can be found in the description of the detection and drive circuit and are not detailed here.

[0095] Example 2

[0096] like Figure 4 As shown, the difference between this embodiment and the first embodiment lies in the circuit structures of the sampling module 30 , the open-circuit signal generating module 40 and the signal detecting module 50 .

[0097] Specifically, the sampling module 30 includes a sampling resistor Rsense. A first end of the sampling resistor Rsense is connected to the sampling terminal of the power device Mp and the signal detection module 50 to form a first node OCPP. A second end of the sampling resistor Rsense is connected to the second voltage and signal detection module 50 to form a second node OCPN. The sampling resistor Rsense converts the sampled current Isense in the power device Mp into a sampled signal. When the current in the power device Mp is stable, the voltage at the first node OCPP equals the sampled signal, and the voltage at the second node OCPP equals a second voltage. In one embodiment, the second voltage is the ground voltage GND.

[0098] The open circuit signal generating module 40 includes a first resistor unit. In one embodiment, the first resistor unit includes a third resistor R3. A first end of the third resistor R3 is connected to the first voltage, and a second end of the third resistor R3 is connected to the first node OCPP to generate a first indication signal indicating whether an open circuit exists between the sampling module 30 and the first node OCPP.

[0099] When the circuit between the sampling module 30 and the first node OCPP is open, the third resistor R3 pulls up the voltage of the first node OCPP to the first voltage, and the generated first characteristic signal is a high level (VDD).

[0100] The signal detection module 50 includes a comparison module CMP. A first input terminal of the comparison module CMP is connected to the first node OCPP. A second input terminal of the comparison module CMP is used to receive a reference signal VREF. The comparison module CMP is used to compare the sampling signal OCP with the reference signal VREF or compare the first characterization signal with the reference signal VREF to generate a detection signal.

[0101] In one embodiment, the comparison module CMP is a comparator, wherein the first input terminal of the comparison module CMP is a positive input terminal, and the second input terminal of the comparator is a negative input terminal. The reference signal VREF is generated by a voltage generating circuit connected to the second voltage, and the reference signal VREF is much smaller than the first voltage.

[0102] When the sampling signal is less than the reference signal VREF, the comparison module CMP outputs a detection signal of a low level. When the sampling signal OCP is greater than or equal to the reference signal VREF, the comparison module CMP outputs a detection signal of a high level.

[0103] When the circuit between the sampling module 30 and the first node OCPP is open and the first characterization signal is at a high level (VDD), the detection signal output by the comparison module CMP is also at a high level.

[0104] Because the sampling signal OCP uses a single-ended input, only the voltage at the first node OCPP needs to be detected. A single comparison module can simultaneously detect both overcurrent and open-circuit anomalies. No additional detection circuit is required to detect whether the voltage at the first node OCPP is pulled up by the third resistor R3, simplifying the circuit. In other embodiments, the open-circuit signal generating module 40 may be omitted, and only overcurrent anomalies may be detected by the signal detection module 50.

[0105] In this embodiment, the structures and functions of the control module 10 , the driving unit 20 , the power device Mp and the signal processing module 60 are the same as those in the first embodiment, and are not described again here.

[0106] like Figure 4 As shown, this embodiment also discloses a detection and driving system, including a driver chip, a power device Mp, and a sampling module 30. The driver chip is provided with the aforementioned control module 10, drive unit 20, open-circuit signal generating module 40, signal detection module 50, and signal processing module 60. In other embodiments, the sampling module 30 and the power device Mp may be replaced by other external circuits.

[0107] The driver chip further includes a first pin, a second pin, an input pin and an output pin.

[0108] The control module 10 and the judgment unit 61 are connected to the input pin to receive the input signal IN, and the driving module 20 is connected to the control terminal of the power device Mp through the output pin to transmit the driving signal OUT to the power device Mp.

[0109] The first and second pins correspond to the first and second nodes OCPP and OCPN. The second end of the third resistor R3 and the first input of the comparison module CMP are connected to the first pin, which is also connected to the first end of the sampling resistor Rsense. A voltage generation circuit is connected to the second pin to generate a reference signal VREF. The second pin OCPN is also connected to the second end of the sampling resistor Rsense.

[0110] When the first end of the sampling resistor Rsense is normally connected to the first pin, the circuit in the driver chip performs overcurrent detection. When an overcurrent phenomenon occurs in the power device Mp, causing the voltage on the first pin to be too high and greater than the reference signal VREF, the second control signal OCPtrigger turns high, and the circuit in the driver chip normally performs the overcurrent protection function. When the first pin is left floating, the voltage on the first input terminal of the comparison module CMP is pulled up by the third resistor R3, the second control signal OCPtrigger turns high, and the circuit protection is triggered.

[0111] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

[0112] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A detection drive circuit connected to a power device and a sampling module, wherein the sampling module is connected to the power device to sample the current on the power device and generate a sampling signal, characterized in that: The detection drive circuit includes: a control module, a drive unit, a signal detection module and a signal processing module; The control module is used to control the driving unit to generate a driving signal based on the input signal to drive the power device; the signal detection module is connected to the sampling module and forms a first node and a second node to receive the sampling signal and generate a detection signal based on the sampling signal and the reference signal; The signal processing module is connected to the signal detection module, and the signal processing module is used to generate a first control signal based on the input signal and the driving signal, and generate a second control signal based on the first control signal and the detection signal; the control module is connected to the signal processing module, and the control module controls the driving unit to adjust the driving signal based on the second control signal; The detection drive circuit also includes an open circuit signal generating module; The open circuit signal generating module is connected to the first node, and the open circuit signal generating module is used to generate a first characterization signal indicating whether an open circuit occurs between the sampling module and the first node; the signal detection module is used to generate a detection signal based on the first characterization signal and the reference signal or the sampling signal and the reference signal; or The open circuit signal generating module is connected to the first node and the second node, and is used to generate a first characterization signal indicating whether an open circuit occurs between the sampling module and the first node and / or generate a second characterization signal indicating whether an open circuit occurs between the sampling module and the second node; the signal detection module is used to generate a detection signal based on the sampling signal and the reference signal, or the first characterization signal and / or the second characterization signal.

2. The detection drive circuit according to claim 1, characterized in that: The signal processing module is used to generate a first control signal when the input signal is at a valid level and the driving signal is greater than a threshold voltage of the power device.

3. The detection drive circuit according to claim 1, wherein: The sampling module includes a sampling resistor, a first end of the sampling resistor is connected to the power device and the signal detection module to form a first node, and a second end of the sampling resistor is connected to the second voltage and signal detection module to form a second node; or The sampling module includes a sampling resistor, a first resistor, a second resistor, and a capacitor. The first end of the first resistor and the first end of the sampling resistor are connected to the power device, the second end of the first resistor and the first end of the capacitor are connected to the signal detection module and form a first node, the second end of the capacitor and the first end of the second resistor are connected to the signal detection module and form a second node, and the second end of the second resistor and the second end of the sampling resistor are connected to the second voltage.

4. The detection drive circuit according to claim 1, wherein: The open circuit signal generating module includes a first resistor unit, a first end of the first resistor unit is connected to a first voltage, and a second end of the first resistor unit is connected to a first node to generate a first characterization signal indicating whether an open circuit occurs between the sampling module and the first node; or The open circuit signal generating module includes a first resistance unit and a second resistance unit, wherein the first end of the first resistance unit and the first end of the second resistance unit are connected to a first voltage, the second end of the first resistance unit is connected to a first node to generate a first characterization signal indicating whether an open circuit occurs between the sampling module and the first node, and the second end of the second resistance unit is connected to a second node to generate a second characterization signal indicating whether an open circuit occurs between the sampling module and the second node.

5. The detection drive circuit according to claim 1, wherein: The signal detection module includes a comparison module, a first input terminal of the comparison module is used to receive a sampling signal, a second input terminal of the comparison module is used to receive a reference signal, and the comparison module is used to compare the sampling signal with the reference signal to generate a detection signal.

6. The detection drive circuit according to claim 1, characterized in that: The signal detection module includes a comparison module, a first input terminal of the comparison module is connected to the first node to receive the sampling signal or the first characterization signal, a second input terminal of the comparison module is used to receive the reference signal, and the comparison module is used to compare the sampling signal with the reference signal or compare the first characterization signal with the reference signal to generate a detection signal, or The signal detection module includes a comparison module, a detection module and a first logic circuit. The first input end of the comparison module is connected to the first node, the second input end of the comparison module is used to receive a reference signal, the comparison module is used to compare the sampling signal with the reference signal to generate a third characterization signal, the detection module is connected to the first node and the second node, the detection module is used to generate a first open-circuit characterization signal based on the first characterization signal and a second open-circuit characterization signal based on the second characterization signal, the first logic circuit is connected to the comparison module and the detection module, and the first logic circuit is used to perform logical operations on the third characterization signal, the first open-circuit characterization signal and the second open-circuit characterization signal to generate a detection signal.

7. The detection drive circuit according to claim 6, characterized in that: The detection module includes a first detection circuit and a second detection circuit, the input end of the first detection circuit is connected to the first node, the output end of the first detection circuit is connected to the first logic circuit, the first detection circuit is used to generate a first open-circuit characterization signal based on the first characterization signal, the input end of the second detection circuit is connected to the second node, the output end of the second detection circuit is connected to the first logic circuit, and the second detection circuit is used to generate a second open-circuit characterization signal based on the second characterization signal.

8. The detection drive circuit according to claim 7, characterized in that: The first detection circuit includes a first switching tube, a second switching tube, a first current source, a second current source and a trigger, wherein the control end of the first switching tube is used to form an input end of the first detection circuit, the first end of the first switching tube and the first end of the second current source are connected to a first voltage, the second end of the first switching tube and the first end of the first current source are connected to the control end of the second switching tube, the second end of the first current source and the first end of the second switching tube are connected to a second voltage, the second end of the second current source and the second end of the second switching tube are connected to the input end of the trigger, and the output end of the trigger is used to output a first open circuit characterization signal; or The first detection circuit includes a first switching tube, a second switching tube, a first current source, a second current source, a trigger and a delay circuit, wherein the control end of the first switching tube is used to form the input end of the first detection circuit, the first end of the first switching tube and the first end of the second current source are connected to a first voltage, the second end of the first switching tube and the first end of the first current source are connected to the control end of the second switching tube, the second end of the first current source and the first end of the second switching tube are connected to a second voltage, the second end of the second current source and the second end of the second switching tube are connected to the input end of the trigger, and the delay circuit is connected to the output end of the trigger to delay the signal output by the trigger to generate a first open circuit characterization signal; and / or The structure of the second detection circuit is the same as that of the first detection circuit.

9. The detection drive circuit according to claim 1, characterized in that: The signal processing module includes a first processing unit and a second processing unit, the first processing unit is used to generate a first control signal based on the input signal and the drive signal, the second processing unit is connected to the control signal generating unit, the signal detection module and the control module, and the second processing unit is used to generate a second control signal based on the first control signal and the detection signal.

10. The detection drive circuit according to claim 9, characterized in that: The first processing unit includes a judgment unit and a first delay unit. The judgment unit is used to judge the driving signal and the input signal and generate a judgment signal. The first delay unit is used to delay the judgment signal and generate a first control signal.

11. The detection drive circuit according to claim 9, characterized in that: The second processing unit includes a second logic circuit and a second delay unit. The second logic circuit is connected to the first processing unit, the signal detection module and the second delay unit. The second logic circuit is used to perform logical operations on the detection signal and the first control signal. The second delay unit is used to delay the operation result of the second logic circuit and generate a second control signal.

12. The detection drive circuit according to claim 1, wherein: The control module is configured to control the driving unit to adjust the driving signal under the control of the second control signal and then control the driving unit to generate the driving signal based on the input signal.

13. A detection drive system, characterized in that: It comprises a driver chip, a power device and a sampling module, wherein the driver chip is provided with a control module, a driving unit, a signal detection module and a signal processing module as claimed in any one of claims 1 to 12; The control module, the driving unit and the power device are connected in sequence, the control module is used to control the driving unit to generate a driving signal based on an input signal to drive the power device, and the power device generates a current based on the driving signal; The driver chip is provided with a first pin and a second pin, the sampling module is connected to the power device, the first pin and the second pin, and the sampling module is used to collect the current on the power device to obtain a sampling signal and transmit the sampling signal to the first pin and the second pin; The signal detection module is connected to the first pin and the second pin, and the signal detection module is used to generate a detection signal based on the sampling signal and the reference signal; The signal processing module is connected to the signal detection module, and the signal processing module is used to generate a first control signal based on the input signal and the drive signal, and generate a second control signal based on the first control signal and the detection signal; The control module is connected to the signal processing module, and the control module controls the driving unit to adjust the driving signal based on the second control signal.

14. The detection drive system according to claim 13, characterized in that: The driver chip is also provided with an open circuit signal generating module; The open circuit signal generating module is connected to the first pin, and is used to generate a first characterization signal indicating whether an open circuit occurs between the first pin and the sampling module; the signal detection module is used to generate a detection signal based on the first characterization signal and the reference signal or the sampling signal and the reference signal; or The open circuit signal generating module is connected to the first pin and the second pin, and is used to generate a first characterization signal indicating whether an open circuit occurs between the first pin and the sampling module and / or generate a second characterization signal indicating whether an open circuit occurs between the second pin and the sampling module; the signal detection module is used to generate a detection signal based on the sampling signal and the reference signal, or the first characterization signal and / or the second characterization signal.

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