Reorder buffer verification method and related equipment

Abstract

The embodiment of the present application provides a reorder buffer verification method and related equipment, including: obtaining instruction information of a test instruction for verifying the reorder buffer and processing information when the reorder buffer processes the test instruction, wherein the processing information when the reorder buffer processes the test instruction is obtained in real time; based on the instruction information and processing information, predicting the processing result of the reorder buffer on the test instruction, and taking the predicted processing result as the predicted result; when the obtained processing information includes the actual processing result of the test instruction in the reorder buffer, determining the verification result of the reorder buffer based on the actual processing result and the predicted result, wherein, when the verification result is that the test instruction is wrong, extracting the processing information of the test instruction. The reorder buffer verification scheme realizes the fine verification of the reorder buffer and reduces the error probability of the reorder buffer.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of integrated circuit design and manufacturing, and specifically to a reordering buffer verification method and related equipment. Background Art

[0002] The reorder buffer (ROB) is a component within the CPU (central processing unit) that stores and manages instruction execution results. It is used to submit instruction processing results back to the original instruction order in an out-of-order execution environment. With the development of technologies such as multi-issue and renaming, the complexity within high-performance processors has increased exponentially, and the dependencies and interactions between instructions have become more complex. Consequently, the ROB requires a more complex structure to handle the task of sorting instructions executed out-of-order.

[0003] However, the more complex the reorder buffer structure is, the higher the error probability it faces. Therefore, it is necessary to perform detailed verification of the reorder buffer during the chip design phase to reduce the error probability of the reorder buffer. Summary of the Invention

[0004] In view of this, an embodiment of the present application provides a reorder buffer verification method and related devices, which implements fine verification of the reorder buffer and reduces the error probability of the reorder buffer.

[0005] An embodiment of the present application provides a reorder buffer verification method, comprising:

[0006] Acquire instruction information for verifying the instruction to be tested in the reorder buffer and processing information when the reorder buffer processes the instruction to be tested, wherein the processing information when the reorder buffer processes the instruction to be tested is acquired in real time;

[0007] Predicting a processing result of the reorder buffer on the instruction to be tested based on the instruction information and the processing information, and using the predicted processing result as a prediction result;

[0008] When the acquired processing information includes the actual processing result of the instruction to be tested in the reorder buffer, the verification result of the reorder buffer is determined based on the actual processing result and the prediction result, wherein when the verification result is that the instruction to be tested is wrong, the processing information of the instruction to be tested is extracted.

[0009] Preferably, there are multiple instructions to be tested, and the multiple instructions to be tested constitute an instruction group to be tested. The instructions to be tested in the instruction group to be tested are used for parallel and out-of-order execution. The obtaining of instruction information for verifying the instruction to be tested in the reorder buffer and processing information when the reorder buffer processes the instruction to be tested includes:

[0010] Batch obtain instruction information of each instruction to be tested in the instruction group to be tested;

[0011] The processing information of each instruction to be tested in the instruction group to be tested in the reordering buffer is obtained in real time.

[0012] Preferably, the processing information includes a plurality of different information types, and different information types are correspondingly configured with different information queues; and the real-time acquisition of the processing information of each instruction to be tested in the instruction group to be tested in the reordering buffer includes:

[0013] Collect and send information of different types based on different information queues;

[0014] In the information sending phase of the information queue, each information queue transmits the information of the corresponding instruction to be tested from the corresponding interface based on the instruction identifier of the instruction to be tested.

[0015] Preferably, the instruction information includes an instruction identifier of the instruction to be tested, the instruction identifier being used to indicate the order of the instruction to be tested in the instruction group to be tested, and the predicting, based on the instruction information and the processing information, of the processing result of the instruction to be tested by the reorder buffer, and using the predicted processing result as the prediction result, includes:

[0016] Based on the order of the instructions to be tested in the instruction group to be tested, establishing an instruction item corresponding to each instruction to be tested in the instruction group to be tested;

[0017] Based on the processing information, updating the instruction completion progress of the instruction to be tested in the instruction item corresponding to the instruction to be tested;

[0018] Based on the order of the instruction items corresponding to the instructions to be tested, the processing results of the instructions to be tested whose instruction completion progress indications have been completed are submitted in sequence, and the submitted processing results of the instructions to be tested are used as the prediction results.

[0019] Preferably, the instruction to be tested includes an operation task of at least one operation type among a plurality of operation types, and the instruction item includes a progress indicator corresponding to each operation type;

[0020] The method of establishing a one-to-one correspondence between each instruction to be tested and each instruction to be tested in the instruction group to be tested includes: determining an operation task of the instruction to be tested; using the operation type corresponding to the operation task of the instruction to be tested as the target operation type, marking the progress identifier corresponding to the target operation type in the instruction item as unfinished, and marking other progress identifiers as completed;

[0021] The processing information includes task completion information, and the task completion information is used to indicate the completed operation task in the instruction to be tested. The updating of the instruction completion progress of the instruction to be tested in the instruction item corresponding to the instruction to be tested includes: based on the operation task indicated by the task completion information, marking the progress identifier of the operation type corresponding to the operation task in the instruction item as completed.

[0022] Preferably, based on the order of the instruction items corresponding to the instruction to be tested, the processing results of the instruction to be tested whose instruction completion progress indication has been completed are submitted in sequence, and the submitted processing results of the instruction to be tested are used as the prediction result, specifically:

[0023] When the instruction completion progress of the instruction to be tested at the head position indicates that the instruction to be tested has been processed, the processing result of the instruction to be tested at the head position is submitted as the prediction result, wherein the instruction to be tested at the head position is the instruction to be tested at the front end of the sequence among the instructions to be tested that have not yet been submitted and are sorted based on the order of instruction items in the instruction group to be tested.

[0024] Preferably, the predicting, based on the instruction information and the processing information, the processing result of the reorder buffer on the instruction to be tested, and using the predicted processing result as the prediction result, further includes:

[0025] When the instruction refresh information is received, the instruction to be tested corresponding to the instruction refresh information is invalidated.

[0026] Preferably, determining the verification result of the reorder buffer based on the actual processing result and the prediction result includes:

[0027] Comparing the actual processing result with the result information of the instruction to be tested in the predicted result to see whether they match;

[0028] If not, the verification result is that the instruction to be tested is wrong;

[0029] The result information of the instruction to be tested includes at least one of the following information:

[0030] The submission status of the instruction to be tested;

[0031] The number of instructions to be tested submitted in parallel within the clock cycle in which the instruction to be tested is located;

[0032] Instruction identifiers of the instructions to be tested submitted in parallel within the clock cycle in which the instruction to be tested is located;

[0033] Content information of the processing result of the instruction to be tested;

[0034] The functional module required to send the submission status of the instruction to be tested.

[0035] Preferably, after the step of obtaining instruction information for verifying the instruction to be tested in the reorder buffer and processing information when the reorder buffer processes the instruction to be tested, and before the step of predicting the processing result of the reorder buffer on the instruction to be tested based on the instruction information and processing information, the method further includes:

[0036] Based on the transmission information and instruction submission information in the processing information, it is determined whether the transmitted instruction to be tested has timed out; if so, the instruction to be tested is faulty.

[0037] Preferably, in the prediction result or the actual processing result, if the submission status of the instruction to be tested is abnormal, the processing information of the instruction to be tested with the abnormal submission status is also extracted while extracting the processing information of the instruction to be tested.

[0038] The embodiment of the present application further provides a reorder buffer verification platform, including:

[0039] A monitor, configured to obtain instruction information for verifying the instruction to be tested in the reorder buffer and processing information when the reorder buffer processes the instruction to be tested, wherein the processing information when the reorder buffer processes the instruction to be tested is obtained in real time;

[0040] a predictor, configured to predict a processing result of the reorder buffer on the instruction to be tested based on the instruction information and the processing information, and use the predicted processing result as a prediction result;

[0041] A scoreboard is used to determine a verification result of the reorder buffer based on the actual processing result and the prediction result when the acquired processing information includes the actual processing result of the instruction to be tested in the reorder buffer, wherein when the verification result is that the instruction to be tested is an error, the processing information of the instruction to be tested is extracted.

[0042] Preferably, the instruction information includes an instruction identifier of the instruction to be tested, and the instruction identifier is used to indicate the order of the instruction to be tested in the instruction group to be tested. The predictor is configured with a reorder buffer model; the reorder buffer model is used to:

[0043] Based on the order of the instructions to be tested in the instruction group to be tested, establishing an instruction item corresponding to each instruction to be tested in the instruction group to be tested;

[0044] Based on the processing information, updating the instruction completion progress of the instruction to be tested in the instruction item corresponding to the instruction to be tested;

[0045] Based on the order of the instruction items corresponding to the instructions to be tested, the processing results of the instructions to be tested whose instruction completion progress indications have been completed are submitted in sequence, and the submitted processing results of the instructions to be tested are used as the prediction results.

[0046] Preferably, there are multiple instructions to be tested, and the multiple instructions to be tested constitute an instruction group to be tested. The instructions to be tested in the instruction group to be tested are used for parallel and out-of-order execution. The monitor obtains instruction information for verifying the instruction to be tested in the reorder buffer and processing information when the reorder buffer processes the instruction to be tested, including:

[0047] Batch obtain instruction information of each instruction to be tested in the instruction group to be tested;

[0048] The processing information of each instruction to be tested in the instruction group to be tested in the reordering buffer is obtained in real time.

[0049] Preferably, it also includes an instruction generation and decoding module, a scheduler, an integer module, a memory access module and a floating point module; wherein,

[0050] The instruction generation and decoding module is used to generate the instruction to be tested;

[0051] The scheduler is used to transmit the instruction to be tested to the corresponding module based on the operation type of the operation task in the instruction to be tested, and send the corresponding instruction transmission information to the monitor;

[0052] The hourly module is used to execute the instruction to be tested sent by the scheduler, and when the operation task of the instruction to be tested is completed, it feeds back the hourly instruction completion information and hourly operation results to the monitor and reorder buffer;

[0053] The floating-point module is used to execute the instruction to be tested sent by the scheduler, and when the operation task of the instruction to be tested is completed, it feeds back the floating-point instruction completion information and floating-point operation results to the monitor and reorder buffer;

[0054] The memory access module is used to execute the instruction to be tested sent by the scheduler, and when the operation task of the instruction to be tested is completed, it feeds back the memory access instruction completion information to the monitor and the reorder buffer.

[0055] Preferably, the monitor is configured with a plurality of different information queues, and the different information queues are used to collect and send different types of processing information;

[0056] Among them, the multiple different information queues include a read instruction completion queue, a write instruction completion queue, a floating-point instruction completion queue, an hourly instruction completion queue and a jump instruction completion queue. In the read instruction completion queue, the write instruction completion queue, the floating-point instruction completion queue, the hourly instruction completion queue and the jump instruction completion queue, information collection is performed asynchronously.

[0057] Preferably, a queue to be submitted is configured in the predictor, and a launch pointer and a commit pointer are configured in the queue to be submitted. The launch pointer is used to point to the location where the next instruction to be tested stored in the queue to be submitted is stored, and the commit pointer is used to point to the location where the next instruction to be tested to be read in the queue to be submitted is stored; wherein, the launch pointer is updated based on the instruction launch information of the instruction to be tested, and the commit pointer is updated based on the commit operation of the instruction to be tested. If the instruction to be tested pointed to by the commit pointer has been processed, the instruction to be tested is submitted.

[0058] An embodiment of the present application further provides an electronic device, which is used to configure the reorder buffer verification platform provided in the embodiment of the present application.

[0059] An embodiment of the present application further provides a storage medium, which stores one or more computer-executable instructions. When the one or more computer-executable instructions are executed, the reorder buffer verification method provided in the embodiment of the present application is implemented.

[0060] To achieve the above objectives, the present invention provides the following technical solutions:

[0061] An embodiment of the present application provides a reorder buffer verification method and related equipment, wherein the method includes: obtaining instruction information of a test instruction for verifying the reorder buffer and processing information when the reorder buffer processes the test instruction, wherein the processing information when the reorder buffer processes the test instruction is obtained in real time; based on the instruction information and the processing information, predicting the processing result of the reorder buffer on the test instruction, and taking the predicted processing result as the prediction result; when the acquired processing information includes the actual processing result of the test instruction in the reorder buffer, determining the verification result of the reorder buffer based on the actual processing result and the prediction result, wherein when the verification result is that the test instruction is wrong, extracting the processing information of the test instruction.

[0062] It can be seen that the reorder buffer verification method described in the embodiment of the present application predicts the processing result of the reorder buffer on the instruction to be tested based on the instruction information of the instruction to be tested and the processing information obtained in real time when the reorder buffer processes the instruction to be tested, takes the predicted processing result as the prediction result, and determines the verification result of the reorder buffer based on the actual processing result of the instruction in the processing information obtained in real time and the predicted result, thereby realizing fine verification of the reorder buffer based on the real-time processing information of the reorder buffer, so that when the verification result is that the instruction to be tested is wrong, the processing information of the instruction to be tested can be extracted, the cause of the error can be accurately analyzed, the error factors can be eliminated, and the error probability of the reorder buffer can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0064] Figure 1 A schematic diagram of an optional structure of a reorder buffer verification platform provided in an embodiment of the present application;

[0065] Figure 2 A schematic diagram of an optional flow chart of a reorder buffer verification method provided in an embodiment of the present application;

[0066] Figure 3 Schematic diagram of an optional process of step S100 provided in an embodiment of the present application;

[0067] Figure 4 Schematic diagram of an optional process of step S110 provided in an embodiment of the present application;

[0068] Figure 5 This is an optional example diagram of a reorder buffer verification method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0069] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0070] As described in the background technology, with the development of technologies such as multi-issue and renaming, the internal complexity of high-performance processors has increased exponentially, and the dependencies and interactions between instructions have become more complicated. Accordingly, the reorder buffer in the out-of-order execution environment requires a more complex structure to undertake the task of sorting instructions executed out-of-order.

[0071] As the structure of the reorder buffer becomes increasingly complex, how to provide a reorder buffer verification solution to achieve precise verification of the reorder buffer and reduce the error probability of the reorder buffer has become an urgent problem to be solved in this field.

[0072] In view of this, an embodiment of the present application provides a reordering buffer verification method and related equipment, wherein the method includes: obtaining instruction information of the instruction to be tested used to verify the reordering buffer and processing information when the reordering buffer processes the instruction to be tested, wherein the processing information when the reordering buffer processes the instruction to be tested is obtained in real time; based on the instruction information and processing information, predicting the processing result of the reordering buffer on the instruction to be tested, and taking the predicted processing result as the predicted result; when the acquired processing information includes the actual processing result of the instruction to be tested in the reordering buffer, determining the verification result of the reordering buffer based on the actual processing result and the predicted result, wherein when the verification result is that the instruction to be tested is wrong, extracting the processing information of the instruction to be tested.

[0073] It can be seen that the reorder buffer verification method described in the embodiment of the present application predicts the processing result of the reorder buffer on the instruction to be tested based on the instruction information of the instruction to be tested and the processing information obtained in real time when the reorder buffer processes the instruction to be tested, takes the predicted processing result as the prediction result, and determines the verification result of the reorder buffer based on the actual processing result of the instruction in the processing information obtained in real time and the predicted result, thereby realizing fine verification of the reorder buffer based on the real-time processing information of the reorder buffer, so that when the verification result is that the instruction to be tested is wrong, the processing information of the instruction to be tested can be extracted, the cause of the error can be accurately analyzed, the error factors can be eliminated, and the error probability of the reorder buffer can be reduced.

[0074] To better understand the solution provided in the embodiment of the present application, the specific content of the reordering buffer verification solution is further explained below.

[0075] In the embodiment of the present application, a reordering buffer verification platform is provided, referring to Figure 1 1 shows an optional structural diagram of a reorder buffer verification platform, which includes: a monitor 110 , a predictor 120 and a scoreboard 130 .

[0076] Among them, the monitor 110 is connected to the reorder buffer 200 to be verified (which can also be understood as the design to be verified, hereinafter referred to as the reorder buffer), and is used to obtain the input information and output information of the reorder buffer 200, and based on the interface between components, transmit the obtained information to the predictor 120, and the predictor 120 simulates the action of the reorder buffer 200 and predicts the processing result of the reorder buffer 200, wherein the predicted processing result is the prediction result.

[0077] The output information of the reorder buffer 200 obtained by the monitor 110 includes the actual processing result of the reorder buffer 200. The actual processing result can be transmitted to the scoreboard 130 via the transmission line between the monitor 110 and the scoreboard 130. At the same time, the prediction result of the predictor 120 can be sent to the scoreboard 130 connected thereto. The scoreboard 130, having obtained the actual processing result and the prediction result, can determine the verification result of the reorder buffer based on the actual processing result and the prediction result. If the verification result indicates that the instruction under test has an error, the scoreboard 130 can extract the processing information of the instruction under test.

[0078] In a further example, the reorder buffer verification platform may also include an instruction generation and decoding module 140, a scheduler 150, an hourly module 160, a memory access module 170 and a floating-point module 180, wherein each module is connected to the monitor 110 to transmit the instruction information and processing information generated by each module to the monitor 110.

[0079] The instruction generation and decoding module 140 is used to generate an instruction to be tested. The instruction to be tested may be a microinstruction, which may be decoded from a complex instruction. Accordingly, the instruction generation and decoding module may generate a complex instruction and convert it into a microinstruction according to decoding rules, with the microinstruction serving as the instruction to be tested. The complex instruction may be, for example, an x86 instruction, which may be randomly generated by the instruction generation and decoding module.

[0080] After the instruction generation and decoding module 140 generates the instruction to be tested, the corresponding instruction information may be transmitted to the monitor 110 and the scheduler 150 , wherein the monitor 110 is used to transmit the corresponding instruction information to the predictor 120 .

[0081] The scheduler 150 is used to transmit the instruction under test based on the instruction content of the instruction under test (i.e., microinstruction). The instruction content includes the operation task contained in the instruction under test. The scheduler 150 transmits the instruction under test to the corresponding module based on the operation type of the operation task. For example, the instruction under test requiring hourly calculation is transmitted to the hourly calculation module 160, the instruction under test requiring floating-point calculation is transmitted to the floating-point module 180, and the instruction under test requiring memory access is transmitted to the memory access module 170. It should be noted that a single instruction under test can include multiple operation tasks. For example, to read data from register X, add 1 to the data, and then write it to register X, the instruction under test includes three operation tasks: a read task, a calculation task, and a write task. Because a single instruction under test can include multiple operation tasks, the scheduler needs to transmit the instruction under test to different modules respectively. When the scheduler 150 transmits the instruction under test, it also sends the corresponding instruction transmission information to the monitor 110.

[0082] The hourly module 160 is used to execute the instruction to be tested sent by the scheduler 150 , and when completing the operation task of the instruction to be tested, feed back hourly instruction completion information and hourly operation results to the monitor 110 and the reorder buffer 200 .

[0083] The floating point module 180 is used to execute the instruction to be tested sent by the scheduler 150 , and when completing the operation task of the instruction to be tested, feed back floating point instruction completion information and floating point operation results to the monitor 110 and the reorder buffer 200 .

[0084] The memory access module 170 is used to execute the instruction to be tested sent by the scheduler 150, and when the operation task of the instruction to be tested is completed, it feeds back memory access instruction completion information (which may include read instruction completion information and write instruction completion information) to the monitor 110 and the reorder buffer 200.

[0085] The reorder buffer 200 to be verified is used to output the actual processing result of the instruction to be tested based on the input instruction information and processing information. It should be noted that in the actual processing result, the submission status of the instruction to be tested can be submitted (retire) or exception. Among them, the submission status of the instruction to be tested indicates that the instruction to be tested is submitted to the subsequent process, and the submission status of the instruction to be tested is exception. It indicates that the instruction to be tested is processed abnormally and the corresponding exception process is executed. The exception process can be, for example, executing the refresh process of the instruction to be tested and re-issuing it for execution after the refresh.

[0086] In an optional example, the scheduler 150, the timing module 160, the reorder buffer 200, the memory access module 170, and the floating-point module 180 can all be RTL (resistance transistor logic), thereby processing instructions based on the specific chip design. The scheduler 150, the timing module 160, the reorder buffer 200, the memory access module 170, and the floating-point module 180 can all be understood as the RTL side, while the monitor, predictor, and scoreboard used to provide a verification environment can be understood as the verification side.

[0087] It should be noted that the predictor can be adaptively configured based on the specific design of the reorder buffer, so as to accurately predict the result that the reorder buffer should obtain.

[0088] Based on the above reorder buffer verification platform, in an embodiment of the present application, a reorder buffer verification method is further provided. The method can be executed based on the above reorder buffer verification platform or based on other verification platforms with equivalent processes. Figure 2 FIG. 4 is a schematic diagram of an optional flow chart of a reorder buffer verification method, wherein the method comprises:

[0089] Step S100: obtaining instruction information of the instruction to be tested used for verifying the reorder buffer and processing information when the reorder buffer processes the instruction to be tested;

[0090] The reorder buffer is an object to be verified. During the chip design phase, the reorder buffer can be a design to be verified. Accordingly, the embodiments of the present application are verification schemes for the corresponding reorder buffer designs. The reorder buffer can be understood as a software design, a hardware design, or a combination of software and hardware. In a specific example, the reorder buffer can be resistor transistor logic (RTL).

[0091] The instruction to be tested is an instruction provided by the reorder buffer for verifying the reorder buffer, wherein, in the scenario for verifying the reorder buffer, there are multiple instructions to be tested, and at least some of the multiple instructions to be tested are executed in parallel and out of order, thereby verifying the instruction sorting function of the reorder buffer. Based on the microinstruction as the unit of processing in the CPU, the instruction to be tested in this example can be a microinstruction. Specifically, the instruction to be tested can be a microinstruction generated by a complex instruction (such as an x86 instruction) according to a decoding rule.

[0092] The instruction to be tested may be obtained based on a specific verification instance, or may be randomly generated. In a specific example, the instruction to be tested may be a microinstruction obtained by decoding a randomly generated complex instruction.

[0093] The instruction information may include attribute information and / or identification information indicating the instruction to be tested, thereby providing a basis for subsequent instruction processing procedures. In an optional example, the instruction information may include an instruction identification of the instruction to be tested, wherein the instruction identification is used to indicate sequence information of the instruction to be tested, so that the subsequent submission process can be executed based on the sequence information.

[0094] Furthermore, the instruction information may also include operational information of the instruction to be tested, such as the types of each operational task performed by the instruction to be tested. It should be noted that the instruction to be tested may include multiple operational tasks. For example, to read data from register X, increment the data by 1, and then write it back to register X, the instruction to be tested would accordingly include three operational tasks: a read task, a calculation task, and a write task. Accordingly, the operational information in the instruction information is used to identify the type of each operational task.

[0095] In an optional example, the instruction information may also be specific instruction content, so that corresponding attribute information, identification information, operation information, etc. can be extracted based on the instruction content.

[0096] The processing information of the reorder buffer when processing the instruction to be tested is used to indicate the information input to the reorder buffer during the processing flow of the instruction to be tested, as well as the information output from the reorder buffer. The information input to the reorder buffer may include, for example, task completion information of each task of the instruction to be tested, and the information output from the reorder buffer may include, for example, the instruction to be tested processed by the reorder buffer (including submitted and abnormal instructions to be tested), as well as result information corresponding to the instruction to be tested, etc.

[0097] In an embodiment of the present application, the processing information of the reorder buffer when processing the instruction to be tested is obtained in real time, so that based on the real-time input information of the reorder buffer, the processing result that the reorder buffer should give is simulated and predicted, and based on the real-time output information of the reorder buffer, the verification result is determined.

[0098] In some examples, instruction information and processing information corresponding to the instruction to be tested can be obtained based on the monitor and transmitted by the monitor to the predictor, which then predicts the processing result of the instruction to be tested by the reorder buffer based on the instruction information and processing information.

[0099] In a specific example, there are multiple instructions to be tested, and the multiple instructions to be tested constitute an instruction group to be tested. The instructions to be tested in the instruction group to be tested are used for parallel and disorderly execution. Figure 3 The optional flow diagram of step S100 is shown, and this step may specifically include:

[0100] Step S101: batch acquiring instruction information of each instruction to be tested in the instruction group to be tested;

[0101] The instruction group to be tested can be understood as a combination of multiple instructions to be tested that are executed in parallel. In the instruction group to be tested, the number of instructions to be tested can be less than or equal to a first preset value, which is the maximum number of instructions that can be processed by the processor corresponding to the reorder buffer to be verified in the parallel processing instruction mechanism. In a preferred example, in order to ensure sufficient verification of the reorder buffer, the number of instructions to be tested in the instruction group to be tested is equal to the first preset value. In a specific example, the first preset value can be, for example, 128, 256, or 512.

[0102] The instruction group to be tested can be understood as an instance provided for verifying the reorder buffer, and based on the parallel and out-of-order execution strategy of the instruction group to be tested, a verification environment is provided for the reorder buffer.

[0103] In the instruction group to be tested, the instructions to be tested have a preset order, which can be reflected based on the instruction identifier in the instruction information; in an optional example, the preset order can be the arrangement order of the preset instructions in the instruction group to be tested, and the corresponding instruction identifier can be determined based on the instruction arrangement order.

[0104] The instruction identifier of the instruction to be tested can indicate the order information of the instruction to be tested in the instruction group to be tested (such as the order value of the instruction to be tested in the instruction group to be tested), so that the subsequent submission process can be executed based on the order information. Accordingly, the instruction identifier can be obtained at the same time as the instruction information of the instruction to be tested is obtained.

[0105] When batch acquiring instruction information for each instruction to be tested in the instruction group to be tested, the instruction information for each instruction to be tested in the instruction group to be tested can be acquired in batches based on a parallel interface, thereby establishing a corresponding instruction item for each instruction to be tested in the instruction group to be tested during the initial stage of a subsequent prediction process. In a specific example, if the instruction to be tested is a microinstruction, the acquired instruction information is the microinstruction information corresponding to the microinstruction.

[0106] In a specific example, the instruction information of the instruction group to be tested can be transmitted based on the monitor. When the monitor obtains the corresponding instruction information, the monitor sends the instruction information to the predictor based on the interface between the components (i.e., the interface between the monitor and the predictor). There can be multiple interfaces between the components, and they correspond to the preset order of the instructions to be tested in the instruction group to be tested. Accordingly, the instruction identifier of the instruction to be tested can also be the interface number between the components.

[0107] Step S102: acquiring in real time the processing information of each instruction to be tested in the instruction group to be tested in the reordering buffer;

[0108] Because the instructions to be tested in the instruction group to be tested are executed in parallel and out of order, the corresponding processing information is also out of order. Therefore, the reorder buffer needs to sort based on the processing information to determine the processing progress (i.e., the degree of completion) of the instructions. Accordingly, the processing information input to the reorder buffer at different time sequences is used to indicate the basic information of the instructions processed by the reorder buffer, and the processing information output from the reorder buffer at different time sequences is used to indicate the result information of the instructions processed by the reorder buffer.

[0109] Therefore, by obtaining the processing information of each instruction to be tested in the reordering buffer in real time in the instruction group to be tested, the basic information of the reordering buffer processing instructions is determined, and the result prediction is performed based on the basic information, and the prediction result is verified based on the result information of the reordering buffer processing instructions, and then the corresponding verification result is determined.

[0110] In a specific example, the processing information includes multiple different information types, and different information types are correspondingly configured with different information queues. Among them, the processing information input to the reorder buffer may include, for example, instruction issuance information, read instruction completion information, write instruction completion information, operation instruction completion information (for example, it may include floating-point instruction completion information and hourly instruction completion information), operation result information, jump instruction completion information, instruction refresh (flush) information, etc.; among them, read instruction completion information, write instruction completion information, operation instruction completion information (for example, it may include floating-point instruction completion information and hourly instruction completion information), operation result information, jump instruction completion information can be understood as task completion information; the processing information output from the reorder buffer may include, for example, instruction submission information, etc.

[0111] In a specific example, processing information of the instruction to be tested in the reorder buffer can be transmitted based on the monitor. The monitor can be configured with multiple different information queues, each used to collect and send different types of processing information. The multiple different information queues can include, for example, an instruction issue queue, a read instruction completion queue, a write instruction completion queue, an arithmetic instruction completion queue (e.g., a floating-point instruction completion queue and an hourly instruction completion queue), a jump instruction completion queue, an instruction submission information queue, etc., thereby enabling the collection and transmission of different types of information based on different information queues.

[0112] Specifically, the instruction issuance queue can be used to collect the instruction issuance information issued by the scheduler, and send the instruction issuance information to the predictor in sequence based on the pointer pointing in the queue; the read instruction completion queue can be used to collect the read instruction completion information returned by the memory access unit, and send the read instruction completion information to the predictor in sequence based on the pointer pointing in the queue; the write instruction completion queue can be used to collect the write instruction completion information returned by the memory access unit, and send the write instruction completion information to the predictor in sequence based on the pointer pointing in the queue; the floating-point instruction completion queue can be used to collect the floating-point instruction completion information returned by the floating-point unit, and send the floating-point instruction completion information to the predictor in sequence based on the pointer pointing in the queue; the hourly instruction completion queue can be used to collect the hourly instruction completion information returned by the hourly unit, and send the hourly instruction completion information to the predictor in sequence based on the pointer pointing in the queue; the jump instruction completion queue can be used to collect the jump instruction completion information, and send the hourly instruction completion information to the predictor in sequence based on the pointer pointing in the queue.

[0113] When the interface between the monitor and the predictor corresponds to the preset order of the instructions to be tested in the instruction group to be tested, the information queues can transmit information of the corresponding instructions to be tested from the corresponding interface based on the instruction identifiers of the instructions to be tested.

[0114] It should be noted that the collection of information in the read instruction completion queue, write instruction completion queue, floating-point instruction completion queue, hourly instruction completion queue, and jump instruction completion queue can all be performed by asynchronous sampling, thereby performing the collection and sending of corresponding information based on the real-time processing progress of the instruction to be tested.

[0115] The instruction issue queue can execute the collection and transmission of corresponding information based on the timing of instruction issuance.

[0116] The instruction submission information queue can be used to collect the result information of the reorder buffer, and send the result information to the scoreboard in sequence based on the pointer in the queue; wherein, the instruction submission information queue can trigger the instruction submission information queue to execute information collection based on the result information sent by the reorder buffer, that is, each time the reorder buffer submits an instruction to be tested, it triggers the instruction submission information queue to execute information collection once.

[0117] The instruction refresh information can be collected by configuring refresh entries in the monitor, and the information of the corresponding instruction to be tested can be transmitted based on the corresponding interface.

[0118] In a further optional example, after step S100, the existing information may be further analyzed and determined to determine whether an error exists. Specifically, after step S100, step S200 is further included: based on the transmission information and instruction submission information in the processing information, determining whether the transmitted instruction to be tested has timed out; if so, the instruction to be tested has an error. In a specific example, the instruction to be tested corresponding to the transmission information may be used as the current instruction to be tested, and clock cycles may be calculated based on a counter. If the instruction submission information for the current instruction to be tested has not been received when the counter reaches a threshold, the current instruction to be tested has an error.

[0119] It is understandable that the timeout mechanism based on the instruction to be tested can locate the specific instruction to be tested more quickly during verification and report the timeout error earlier, greatly shortening the time for test case errors and reducing the time required to reproduce a large number of problems.

[0120] Continue to refer Figure 2 , executing step S110: predicting a processing result of the reorder buffer on the instruction to be tested based on the instruction information and the processing information, and using the predicted processing result as a prediction result;

[0121] After obtaining the corresponding instruction information and processing information, the corresponding processing result can be predicted, and then the specific verification result can be determined based on the prediction result.

[0122] The processing result of the instruction to be tested may include information corresponding to a single instruction to be tested, and may further include the timing relationship between multiple instructions to be tested, etc. In a specific example, the result information may include the submission status of the instruction to be tested, the number of instructions to be tested submitted in parallel within the clock cycle where the instruction to be tested is located; the instruction identifiers of the instructions to be tested submitted in parallel within the clock cycle where the instruction to be tested is located; the content information of the processing result of the instruction to be tested; the functional module required to send the submission status of the instruction to be tested, etc. Among them, the number of instructions to be tested submitted in parallel within the clock cycle where the instruction to be tested is located; the instruction identifiers of the instructions to be tested submitted in parallel within the clock cycle where the instruction to be tested is located are used to confirm the timing relationship between multiple instructions to be tested.

[0123] It should be noted that in the embodiment of the present application, the predicted result information is the predicted result, and the processing result obtained in the reordering buffer is the actual processing result. Therefore, in subsequent steps, the verification result can be determined based on the comparison between the predicted result and the actual processing result.

[0124] In some examples, the prediction of the result of the reorder buffer processing the instruction to be tested can be implemented based on a predictor.

[0125] In a specific example, the predictor may be configured with an instruction information receiving queue and a processing information receiving queue. After obtaining instruction information of the instruction group to be tested, the predictor may receive the instruction information based on the instruction information receiving queue of the predictor. After obtaining processing information of the instruction to be tested, the predictor may receive processing information based on the processing information receiving queue of the predictor.

[0126] The processing information includes multiple different information types, and different receiving queues are configured for information of different information types. Corresponding to the configuration of the instruction emission queue, read instruction completion queue, write instruction completion queue, operation instruction completion queue (for example, it may include a floating-point instruction completion queue and an hourly instruction completion queue), jump instruction completion queue, etc. in the aforementioned monitor, the predictor may be configured with an instruction emission reception queue, a read instruction completion reception queue, a write instruction completion reception queue, operation instruction completion reception queue (for example, it may include a floating-point instruction completion reception queue and an hourly instruction completion reception queue), jump instruction completion reception queue, etc., to receive the read instruction completion information, write instruction completion information, operation instruction completion information (for example, it may include a floating-point instruction completion information and an hourly instruction completion information), jump instruction completion information, etc. issued by the monitor.

[0127] The above prediction step can predict the result based on the instruction group to be tested. In a specific example, there are multiple instructions to be tested, and the multiple instructions to be tested constitute the instruction group to be tested. The instructions to be tested in the instruction group to be tested are used for parallel and out-of-order execution. The instruction information of the instruction to be tested includes the instruction identifier of the instruction to be tested, and the instruction identifier is used to indicate the order of the instruction to be tested in the instruction group to be tested. Figure 4 The optional flow diagram of step S110 is shown, and this step may specifically include:

[0128] Step S111: creating an instruction item corresponding to each instruction to be tested in the instruction group to be tested based on the order of the instructions to be tested in the instruction group to be tested;

[0129] The instruction items corresponding to the test instructions are used to record the processing progress of the test instructions to determine whether the test instructions are completed. Accordingly, by establishing one-to-one corresponding instruction items for the test instructions, the processing progress of the test instructions is recorded in the instruction items.

[0130] Wherein, when the instruction information in the instruction group to be tested is acquired in batches, step S111 can also perform batch processing. Accordingly, step S111 can batch establish instruction items that correspond one-to-one to the instructions to be tested.

[0131] The instruction item may include an instruction identifier (e.g., an interface code) and a progress identifier corresponding to the instruction to be tested, wherein there may be multiple progress identifiers. Specifically, the instruction to be tested may include an operation task of at least one operation type among multiple operation types, and the instruction item may include a progress identifier corresponding to each operation type.

[0132] For example, the progress indicator may include one or more of a read instruction indicator for indicating whether a read instruction is completed, a write instruction indicator for indicating whether a write instruction is completed, a floating-point instruction indicator for indicating whether a floating-point instruction is completed, an hourly instruction indicator for indicating whether an hourly instruction is completed, and a jump instruction indicator for indicating whether a jump instruction is completed. Different progress indicators may be indicated based on a single bit of data at a specific location, for example, using data "0" at that location as a marker indicating that the instruction to be tested is incomplete, and using data "1" at that location as a marker indicating that the instruction to be tested is completed.

[0133] Specifically, this step may further include the following process: determining the operation task of the instruction to be tested; taking the operation type corresponding to the operation task of the instruction to be tested as the target operation type, marking the progress identifier corresponding to the target operation type in the instruction item as incomplete, and marking other progress identifiers as completed.

[0134] It is understandable that when a corresponding operation task exists, it is necessary to determine whether the corresponding operation task is completed based on real-time processing information. For an operation task that does not exist, it is defaulted to a completed state to avoid affecting the instruction completion progress of the instruction to be tested.

[0135] Step S112: Based on the processing information, updating the instruction completion progress of the instruction to be tested in the instruction item corresponding to the instruction to be tested;

[0136] The processing information includes task completion information, which indicates completed operation tasks in the instruction to be tested. The task completion information may include, for example, read instruction completion information, write instruction completion information, arithmetic instruction completion information (for example, floating-point instruction completion information and integer instruction completion information), jump instruction completion information, etc. Based on the task completion information, the instruction completion progress in the instruction item may be updated.

[0137] Specifically, the updating step in step S112 may include marking the progress indicator of the operation type corresponding to the operation task in the instruction item as completed based on the operation task indicated by the task completion information. For example, when the read operation task is completed, the read instruction indicator at the preset position corresponding to the read operation task is updated to completed based on the read instruction completion information. In an example where data "0" is used as a marker indicating that the instruction to be tested is incomplete and data "1" is used as a marker indicating that the instruction to be tested is completed, the progress indicator of the completed operation task is updated to "1."

[0138] It should be noted that the processing information is acquired in real time, and the corresponding process of updating the instruction completion progress of the instruction to be tested is also in real time, thereby ensuring the accuracy of the prediction result in terms of timing.

[0139] This is because, given that the instructions under test are in a parallel and out-of-order execution environment, the corresponding instruction processing progress also changes in real time, and the real-time processing information reflects the corresponding instruction processing progress. In the embodiments of the present application, the instruction completion progress of the instructions under test is updated based on the real-time processing information obtained, which can ensure the timing matching of the prediction environment and the processing environment of the reorder buffer, thereby more accurately simulating the processing progress of the reorder buffer and predicting the processing results that the reorder buffer should provide.

[0140] Step S113: Based on the order of the instruction items corresponding to the instruction to be tested, the processing results of the instruction to be tested whose instruction completion progress indications have been completed are submitted in sequence, and the submitted processing results of the instruction to be tested are used as the prediction results.

[0141] Based on the order of the instruction items corresponding to the instructions to be tested, the processing results of the instructions to be tested can be submitted sequentially when the instruction completion progress of the instructions to be tested indicates that the instructions to be tested have been processed. As previously mentioned, the order of the instruction items is the order of the instructions to be tested indicated by the instruction identifiers within the instruction group to be tested. In hardware, this order is based on the order of the interface numbers. Submitting the processing results of the instructions to be tested based on the order of the instructions ensures that the order in which the instructions to be tested are submitted is a preset order.

[0142] It is understood that the instruction completion progress indicates that the instruction to be tested has been processed, which means that all operation tasks in the instruction to be tested have been completed. Accordingly, in the corresponding instruction item, all progress indicators in the instruction item are marked as completed.

[0143] During the instruction submission process, instructions must be submitted sequentially based on the order of the instruction items corresponding to the instructions to be tested. Because the instructions to be tested are executed in parallel and out of order, the corresponding instruction processing progress changes in real time, and it is unclear when the instruction to be tested will be completed. Therefore, it is necessary to confirm whether the instruction completion progress in the instruction item corresponding to the instruction to be tested indicates that the instruction to be tested has been processed. Furthermore, during the sequential submission of the instructions to be tested, if the instructions to be tested that are to be submitted in order have been processed, then the instruction to be tested is submitted.

[0144] In an optional example, the number of instructions submitted simultaneously may be one or more. Specifically, among the unsubmitted instructions to be tested in the instruction group to be tested, which are sorted based on the order of the instruction items, the instruction to be tested at the front of the sequence is the instruction to be tested at the head position. Accordingly, when the instruction completion progress of the instruction to be tested at the head position indicates that the instruction to be tested has been processed, the processing result of the instruction to be tested at the head position is submitted as the predicted result.

[0145] The number of instructions to be tested at the header position may be one or more. In a specific example, the number of instructions to be tested at the header position may be configured as a preset threshold, for example, 8. This preset threshold is used to limit the maximum number of instructions to be tested that can be submitted simultaneously within a clock cycle. This preset threshold only limits the number of instructions submitted within a clock cycle and does not affect the specific submission order and content of the instructions.

[0146] For example, when the preset threshold is 8, if all 8 instructions to be tested have been processed, the processing results of the 8 instructions to be tested will be submitted at the same time. If only 6 of the 8 instructions to be tested have been processed, and only 4 of the 6 instructions to be tested are instructions to be submitted under the sequential submission mechanism, only these 4 will be submitted, and all 6 will not be submitted at the same time.

[0147] In a specific example, a pending submission queue can be configured to store information about pending test instructions. The pending submission queue can also be configured with an issue pointer and a commit pointer. The issue pointer is used to point to the location where the next pending test instruction stored in the pending submission queue is stored, and the commit pointer is used to point to the location where the next pending test instruction to be read in the pending submission queue is stored. The issue pointer is updated based on the instruction issue information of the pending test instruction, and the commit pointer is updated based on the commit operation of the pending test instruction. If the pending test instruction pointed to by the commit pointer has been processed, the pending test instruction is committed.

[0148] In a further example, for instruction flush information, step S110 may further include:

[0149] Step S114: when the instruction refresh information is received, the instruction to be tested corresponding to the instruction refresh information is invalidated.

[0150] By invalidating the instruction to be tested corresponding to the instruction refresh information, consistency with the reorder buffer (i.e., the RTL side) is maintained. In a specific example, the invalidation of the instruction to be tested can be implemented based on the pending submission queue. Specifically, the instruction to be tested corresponding to the instruction refresh information in the pending submission queue can be invalidated. At the same time, the update of the issue pointer and the commit pointer is maintained, and the valid instruction to be tested is retained to prepare for the input of subsequent instructions.

[0151] In a specific example, a reorder buffer model (also called a ROB model, ROB stands for reorder buffer) can be configured in the predictor to execute the above steps S111, S112 and S113, thereby realizing the prediction of the processing result of the reorder buffer based on the reorder buffer model. The reorder buffer model can be judged by independent design documents and specifications, so that the behavior of the RTL in each clock cycle can be predicted based on the reorder buffer model and design requirements without being affected by the RTL signal in the actual design, that is, the behavior of the reorder buffer model is completely independent of the RTL side (that is, the reorder buffer side), avoiding the interference caused by the signal problem of the RTL itself.

[0152] Continue to refer Figure 2 , executing step S120: when the acquired processing information includes an actual processing result of the instruction to be tested in the reorder buffer, determining a verification result of the reorder buffer based on the actual processing result and the prediction result, wherein when the verification result is that the instruction to be tested is an error, extracting the processing information of the instruction to be tested;

[0153] It is understandable that, in the processing information obtained in real time, if the actual processing result of the instruction to be tested in the reorder buffer is obtained, the result of the reorder buffer can be determined based on the actual processing result.

[0154] The verification result may also be determined in real time during the verification process, that is, within a certain clock cycle, when both the actual processing result and the prediction result have been obtained, the verification result is determined.

[0155] In a specific example, the verification result can be determined based on a comparison method. Specifically, the actual processing result is compared with the result information of the instruction to be tested in the predicted result to see if they match; if so, the verification result is passed; if not, the verification result is that the instruction to be tested has an error.

[0156] In a specific example, the result information of the instruction to be tested includes at least one item of the following information: the submission status of the instruction to be tested; the number of instructions to be tested submitted in parallel within the clock cycle where the instruction to be tested is located; the instruction identifier of the instructions to be tested submitted in parallel within the clock cycle where the instruction to be tested is located; the content information of the processing result of the instruction to be tested; and the functional module required to send the submission status of the instruction to be tested.

[0157] The submission status of the instruction to be tested may be, for example, submission or exception; the number of instructions to be tested submitted in parallel within the clock cycle in which the instruction to be tested is located, which is used to determine the number of instructions to be tested submitted in parallel within a certain clock cycle; the instruction identifiers of the instructions to be tested submitted in parallel within the clock cycle in which the instruction to be tested is located, which is used to determine the instruction identifiers of the instructions to be tested submitted in parallel within a certain clock cycle; the content information of the processing result of the instruction to be tested may, for example, include integer operation results and floating-point operation results, which are used to compare possible operation results of the instruction to be tested; the functional module to which the submission status of the instruction to be tested is sent is used to ensure the subsequent process of the instruction to be tested, for example, sending the submission status to the instruction fetch module of the front-end scheduler so that the instruction fetch module updates the corresponding program pointer to execute the instruction fetch of the next program, or sending the submission status to the floating-point module so that the floating-point module releases its own physical registers and buffers based on the information, or sending the submission information to the memory access module so that the memory access module releases the submitted memory access instructions based on the information, freeing up the entrances and exits for subsequent memory access instructions to enter.

[0158] Where the result information includes multiple pieces of information, if any of the information does not match, the verification result is considered to be an error in the instruction under test. Accordingly, if an error occurs in the instruction under test, processing information for the instruction under test is extracted. In a specific example, after extracting the processing information for the instruction under test, the processing information for the instruction under test is printed to a log, so that the cause of the error can be analyzed based on the log records.

[0159] In a further example, for an instruction under test with an abnormal submission status, processing information of the instruction under test can be simultaneously extracted to determine the error location in the processing flow of the instruction under test. It is understood that for the abnormal instruction under test, the RTL side will refresh and re-issue the instruction under test after the refresh. Accordingly, the predictor can stop the issuance process of the abnormal instruction under test and send the instruction information of the abnormal instruction under test to the instruction generation and decoding module, triggering the instruction generation and decoding module to execute the instruction under test again.

[0160] In a specific example, step S120 may be performed by a scoreboard, thereby confirming the verification result.

[0161] It should be noted that, based on the embodiment of the present application, the entire process of the instruction to be tested from the branch stage to the submission stage is tracked, so that the processing information of the extracted instruction to be tested can more comprehensively describe the processing process of the instruction to be tested, so that the cause of the error can be quickly and accurately located after the error is discovered, without the need for waveform tracking like some existing technologies, thereby improving verification efficiency.

[0162] refer to Figure 5An optional example diagram of a reorder buffer verification method is shown, and the reorder buffer verification method may specifically include: step S20, the instruction generation and decoding module sends microinstructions (i.e., the instruction to be tested) to the monitor and scheduler, step S21, the monitor samples the instruction information of the microinstructions and sends it to the predictor, and then executes step S22, the scheduler sends the corresponding operation task to the memory access module, the integer module and the floating-point module, and after the operation task is completed, executes step S23, and returns the corresponding completion information (including integer completion information, floating-point completion information, memory access completion information, etc.) to the monitor, and the monitor samples and sends it to the predictor. The predictor generates refresh information sampled based on the Flush event, executes step S24, determines whether the instruction to be tested has a Flush (i.e., there is refresh information), if so, executes step S25, processes the Flush refresh information, flushes out invalid instructions, and maintains pointers (including the launch pointer and commit pointer in the queue to be submitted), if not, executes step S26, collects the microinstruction of the current commit pointer (such as the instruction identifier, etc.), wherein the microinstruction is used as the instruction waiting to retire (i.e., the instruction to be submitted), and further executes step S27, confirms whether the microinstruction currently waiting to retire has an exception to be processed (i.e., whether the microinstruction has exception information), if so, executes step S28, processes the exception, stops retire, and waits for subsequent launch instructions (i.e., subsequently re-launches the microinstruction), if not, executes step S29, predicts retire (i.e., predicts that the microinstruction is in the commit state), updates the pointers (including the launch pointer and commit pointer in the queue to be submitted), and generates retire information that needs to be given to other modules. After that, after the scoreboard occurs a retire on the RTL side and outputs a retire-related signal, it obtains the actual processing result sampled by the monitor, and executes step S30 to compare whether the predicted result matches the actual processing result. If so, the result is sent to the instruction generation and decoding module, and the instruction generation and decoding module determines whether to continue verification based on the specific verification plan. If not, step S31 is executed, the scoreboard reports an error and records the error information to the log.

[0163] Below, a comprehensive introduction is given to the reorder buffer verification platform provided in the embodiment of the present application. The reorder buffer verification platform described below can be considered as the software functional module or hardware functional module required to implement the reorder buffer verification platform method provided in the embodiment of the present application; the content of the reorder buffer verification platform described below can be referenced in correspondence with the method content and hardware module content described above.

[0164] In an optional implementation, the reorder buffer verification platform may include:

[0165] A monitor, configured to obtain instruction information for verifying the instruction to be tested in the reorder buffer and processing information when the reorder buffer processes the instruction to be tested, wherein the processing information when the reorder buffer processes the instruction to be tested is obtained in real time;

[0166] a predictor, configured to predict a processing result of the reorder buffer on the instruction to be tested based on the instruction information and the processing information, and use the predicted processing result as a prediction result;

[0167] A scoreboard is used to determine a verification result of the reorder buffer based on the actual processing result and the prediction result when the acquired processing information includes the actual processing result of the instruction to be tested in the reorder buffer, wherein when the verification result is that the instruction to be tested is an error, the processing information of the instruction to be tested is extracted.

[0168] Optionally, there are multiple instructions to be tested, and the multiple instructions to be tested constitute an instruction group to be tested, and the instructions to be tested in the instruction group to be tested are used for parallel and out-of-order execution. The monitor is used to obtain instruction information of the instruction to be tested for verifying the reorder buffer and processing information when the reorder buffer processes the instruction to be tested, including:

[0169] Batch obtain instruction information of each instruction to be tested in the instruction group to be tested;

[0170] The processing information of each instruction to be tested in the instruction group to be tested in the reordering buffer is obtained in real time.

[0171] Optionally, the processing information includes a plurality of different information types, and different information types are configured with corresponding information queues; the monitor is used to obtain processing information of each instruction to be tested in the instruction group to be tested in the reorder buffer, including:

[0172] Collect and send information of different types based on different information queues;

[0173] In the information sending phase of the information queue, each information queue transmits the information of the corresponding instruction to be tested from the corresponding interface based on the instruction identifier of the instruction to be tested.

[0174] Optionally, the instruction information includes an instruction identifier of the instruction to be tested, where the instruction identifier is used to indicate the order of the instruction to be tested in the instruction group to be tested. The predictor is used to predict a processing result of the reorder buffer on the instruction to be tested based on the instruction information and processing information, and use the predicted processing result as the prediction result, including:

[0175] Based on the order of the instructions to be tested in the instruction group to be tested, establishing an instruction item corresponding to each instruction to be tested in the instruction group to be tested;

[0176] Based on the processing information, updating the instruction completion progress of the instruction to be tested in the instruction item corresponding to the instruction to be tested;

[0177] Based on the order of the instruction items corresponding to the instructions to be tested, the processing results of the instructions to be tested whose instruction completion progress indications have been completed are submitted in sequence, and the submitted processing results of the instructions to be tested are used as the prediction results.

[0178] Optionally, the instruction to be tested includes an operation task of at least one operation type among multiple operation types, and the instruction item includes a progress indicator corresponding to each operation type;

[0179] The predictor is configured to establish an instruction item corresponding to each instruction to be tested in the instruction group to be tested, including: determining an operation task of the instruction to be tested; using the operation type corresponding to the operation task existing in the instruction to be tested as the target operation type, marking the progress indicator corresponding to the target operation type in the instruction item as incomplete, and marking other progress indicators as completed;

[0180] The processing information includes task completion information, and the task completion information is used to indicate the completed operation task in the instruction to be tested. The predictor is used to update the instruction completion progress of the instruction to be tested in the instruction item corresponding to the instruction to be tested, including: based on the operation task indicated by the task completion information, marking the progress identifier of the operation type corresponding to the operation task in the instruction item as completed.

[0181] Optionally, the predictor is configured to sequentially submit processing results of the instructions to be tested whose instruction completion progress indications have been completed based on the order of the instruction items corresponding to the instructions to be tested, and use the submitted processing results of the instructions to be tested as the prediction results, specifically:

[0182] When the instruction completion progress of the instruction to be tested at the head position indicates that the instruction to be tested has been processed, the processing result of the instruction to be tested at the head position is submitted as the prediction result, wherein the instruction to be tested at the head position is the instruction to be tested at the front end of the sequence among the instructions to be tested that have not yet been submitted and are sorted based on the order of instruction items in the instruction group to be tested.

[0183] Optionally, the predictor is further configured to:

[0184] When the instruction refresh information is received, the instruction to be tested corresponding to the instruction refresh information is invalidated.

[0185] Optionally, the scoreboard is used to determine the verification result of the reorder buffer based on the actual processing result and the prediction result, including:

[0186] Comparing the actual processing result with the result information of the instruction to be tested in the predicted result to see whether they match;

[0187] If not, the verification result is that the instruction to be tested is wrong;

[0188] The result information of the instruction to be tested includes at least one of the following information:

[0189] The submission status of the instruction to be tested;

[0190] The number of instructions to be tested submitted in parallel within the clock cycle in which the instruction to be tested is located;

[0191] Instruction identifiers of the instructions to be tested submitted in parallel within the clock cycle in which the instruction to be tested is located;

[0192] Content information of the processing result of the instruction to be tested;

[0193] The functional module required to send the submission status of the instruction to be tested.

[0194] Optionally, the monitor is further configured to:

[0195] Based on the transmission information and instruction submission information in the processing information, it is determined whether the transmitted instruction to be tested has timed out; if so, the instruction to be tested is faulty.

[0196] Optionally, the scoreboard is used to extract processing information of the instruction to be tested with an abnormal submission status if the submission status of the instruction to be tested is abnormal in the prediction result or the actual processing result.

[0197] Optionally, the reorder buffer verification platform further includes an instruction generation and decoding module, a scheduler, an integer module, a memory access module and a floating point module; wherein,

[0198] The instruction generation and decoding module is used to generate the instruction to be tested;

[0199] The scheduler is used to transmit the instruction to be tested to the corresponding module based on the operation type of the operation task in the instruction to be tested, and send the corresponding instruction transmission information to the monitor;

[0200] The hourly module is used to execute the instruction to be tested sent by the scheduler, and when the operation task of the instruction to be tested is completed, it feeds back the hourly instruction completion information and hourly operation results to the monitor and reorder buffer;

[0201] The floating-point module is used to execute the instruction to be tested sent by the scheduler, and when the operation task of the instruction to be tested is completed, it feeds back the floating-point instruction completion information and floating-point operation results to the monitor and reorder buffer;

[0202] The memory access module is used to execute the instruction to be tested sent by the scheduler, and when the operation task of the instruction to be tested is completed, it feeds back the memory access instruction completion information to the monitor and the reorder buffer.

[0203] Optionally, the monitor is configured with a plurality of different information queues, and the different information queues are used to collect and send different types of processing information;

[0204] Among them, the multiple different information queues include a read instruction completion queue, a write instruction completion queue, a floating-point instruction completion queue, an hourly instruction completion queue and a jump instruction completion queue. In the read instruction completion queue, the write instruction completion queue, the floating-point instruction completion queue, the hourly instruction completion queue and the jump instruction completion queue, information collection is performed asynchronously.

[0205] Optionally, a to-be-submitted queue is configured in the predictor, and an issue pointer and a commit pointer are configured in the to-be-submitted queue, the issue pointer is used to point to a location where the next to-be-tested instruction stored in the to-be-submitted queue is stored, and the commit pointer is used to point to a location where the next to-be-tested instruction to be read in the to-be-submitted queue is stored;

[0206] HGTD2023090014CN1.HG-PA230112-CN, in which the emission pointer is updated based on the instruction emission information of the instruction to be tested, and the submission pointer is updated based on the submission operation of the instruction to be tested. If the instruction to be tested pointed to by the submission pointer has been processed, the instruction to be tested is submitted.

[0207] An embodiment of the present application further provides an electronic device, which is configured as a reorder buffer verification platform as provided in the above embodiment.

[0208] An embodiment of the present application further provides a storage medium, which stores one or more computer-executable instructions. When the one or more computer-executable instructions are executed, the reorder buffer verification method in the embodiment of the present application is implemented.

[0209] The above describes multiple embodiment schemes provided by the embodiments of the present application. The various optional methods introduced in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible embodiment schemes, which can all be considered as embodiment schemes disclosed and open in the embodiments of the present application.

[0210] Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined by the claims.

Claims

1. A reorder buffer verification method, characterized in that: include: Acquire instruction information for verifying the instruction to be tested in the reorder buffer and processing information when the reorder buffer processes the instruction to be tested, wherein the processing information when the reorder buffer processes the instruction to be tested is acquired in real time; Predicting, by a reorder buffer model configured in the predictor, based on the instruction information and the processing information, a processing result of the reorder buffer on the instruction to be tested, and using the predicted processing result as a prediction result; When the acquired processing information includes the actual processing result of the instruction to be tested in the reorder buffer, the verification result of the reorder buffer is determined based on the actual processing result and the prediction result, wherein when the verification result is that the instruction to be tested is wrong, the processing information of the instruction to be tested is extracted.

2. The method according to claim 1, characterized in that There are multiple instructions to be tested, and the multiple instructions to be tested constitute an instruction group to be tested. The instructions to be tested in the instruction group to be tested are used for parallel and out-of-order execution. The obtaining of instruction information for verifying the instruction to be tested in the reorder buffer and processing information when the reorder buffer processes the instruction to be tested includes: Batch obtain instruction information of each instruction to be tested in the instruction group to be tested; The processing information of each instruction to be tested in the instruction group to be tested in the reordering buffer is obtained in real time.

3. The method according to claim 2, characterized in that The processing information includes a plurality of different information types, and different information types are correspondingly configured with different information queues; the real-time acquisition of the processing information of each instruction to be tested in the instruction group to be tested in the reorder buffer includes: Collect and send information of different types based on different information queues; In the information sending phase of the information queue, each information queue transmits the information of the corresponding instruction to be tested from the corresponding interface based on the instruction identifier of the instruction to be tested.

4. The method according to claim 1, wherein The instruction information includes an instruction identifier of the instruction to be tested, the instruction identifier being used to indicate the order of the instruction to be tested in the instruction group to be tested, and predicting a processing result of the instruction to be tested by the reorder buffer based on the instruction information and the processing information, and using the predicted processing result as the prediction result, including: Based on the order of the instructions to be tested in the instruction group to be tested, establishing an instruction item corresponding to each instruction to be tested in the instruction group to be tested; Based on the processing information, updating the instruction completion progress of the instruction to be tested in the instruction item corresponding to the instruction to be tested; Based on the order of the instruction items corresponding to the instructions to be tested, the processing results of the instructions to be tested whose instruction completion progress indications have been completed are submitted in sequence, and the submitted processing results of the instructions to be tested are used as the prediction results.

5. The method according to claim 4, characterized in that The instruction to be tested includes an operation task of at least one operation type among a plurality of operation types, and the instruction item includes a progress indicator corresponding to each operation type; The method of establishing a one-to-one correspondence between each instruction to be tested and each instruction to be tested in the instruction group to be tested includes: determining an operation task of the instruction to be tested; using the operation type corresponding to the operation task of the instruction to be tested as the target operation type, marking the progress identifier corresponding to the target operation type in the instruction item as unfinished, and marking other progress identifiers as completed; The processing information includes task completion information, and the task completion information is used to indicate the completed operation task in the instruction to be tested. The updating of the instruction completion progress of the instruction to be tested in the instruction item corresponding to the instruction to be tested includes: based on the operation task indicated by the task completion information, marking the progress identifier of the operation type corresponding to the operation task in the instruction item as completed.

6. The method according to claim 4, characterized in that The processing results of the instructions to be tested whose instruction completion progress indications have been completed are submitted in sequence based on the order of the instruction items corresponding to the instructions to be tested, and the submitted processing results of the instructions to be tested are used as the prediction results, specifically: When the instruction completion progress of the instruction to be tested at the head position indicates that the instruction to be tested has been processed, the processing result of the instruction to be tested at the head position is submitted as the prediction result, wherein the instruction to be tested at the head position is the instruction to be tested at the front end of the sequence among the instructions to be tested that have not yet been submitted and are sorted based on the order of instruction items in the instruction group to be tested.

7. The method according to claim 4, characterized in that The method further includes predicting a processing result of the reorder buffer on the instruction to be tested based on the instruction information and the processing information, and using the predicted processing result as the prediction result: When the instruction refresh information is received, the instruction to be tested corresponding to the instruction refresh information is invalidated.

8. The method according to claim 1, characterized in that The determining, based on the actual processing result and the prediction result, a verification result of the reorder buffer, includes: Comparing the actual processing result with the result information of the instruction to be tested in the predicted result to see whether they match; If not, the verification result is that the instruction to be tested is wrong; The result information of the instruction to be tested includes at least one of the following information: The submission status of the instruction to be tested; The number of instructions to be tested submitted in parallel within the clock cycle in which the instruction to be tested is located; Instruction identifiers of the instructions to be tested submitted in parallel within the clock cycle in which the instruction to be tested is located; Content information of the processing result of the instruction to be tested; The functional module required to send the submission status of the instruction to be tested.

9. The method according to claim 1, characterized in that After the step of obtaining instruction information for verifying the instruction to be tested in the reorder buffer and processing information when the reorder buffer processes the instruction to be tested, and before the step of predicting a processing result of the reorder buffer on the instruction to be tested based on the instruction information and processing information, the method further includes: Based on the transmission information and instruction submission information in the processing information, it is determined whether the transmitted instruction to be tested has timed out; if so, the instruction to be tested is faulty.

10. The method according to claim 1, characterized in that In the prediction result or the actual processing result, if the submission status of the instruction to be tested is abnormal, the processing information of the instruction to be tested whose submission status is abnormal is also extracted while extracting the processing information of the instruction to be tested.

11. A reorder buffer verification platform, characterized in that: include: A monitor, configured to obtain instruction information for verifying the instruction to be tested in the reorder buffer and processing information when the reorder buffer processes the instruction to be tested, wherein the processing information when the reorder buffer processes the instruction to be tested is obtained in real time; a predictor configured to predict a processing result of the reorder buffer on the instruction to be tested based on the instruction information and the processing information, and to use the predicted processing result as a prediction result; the predictor being configured with a reorder buffer model to implement prediction of the processing result of the reorder buffer based on the reorder buffer model; A scoreboard is used to determine a verification result of the reorder buffer based on the actual processing result and the prediction result when the acquired processing information includes the actual processing result of the instruction to be tested in the reorder buffer, wherein when the verification result is that the instruction to be tested is an error, the processing information of the instruction to be tested is extracted.

12. The reorder buffer verification platform according to claim 11, characterized in that: The instruction information includes an instruction identifier of the instruction to be tested, and the instruction identifier is used to indicate the order of the instruction to be tested in the instruction group to be tested. The predictor is configured with a reorder buffer model; the reorder buffer model is used to: Based on the order of the instructions to be tested in the instruction group to be tested, establishing an instruction item corresponding to each instruction to be tested in the instruction group to be tested; Based on the processing information, updating the instruction completion progress of the instruction to be tested in the instruction item corresponding to the instruction to be tested; Based on the order of the instruction items corresponding to the instructions to be tested, the processing results of the instructions to be tested whose instruction completion progress indications have been completed are submitted in sequence, and the submitted processing results of the instructions to be tested are used as the prediction results.

13. The reorder buffer verification platform according to claim 11, characterized in that: There are multiple instructions to be tested, and the multiple instructions to be tested constitute an instruction group to be tested. The instructions to be tested in the instruction group to be tested are used for parallel and out-of-order execution. The monitor obtains instruction information for verifying the instructions to be tested in the reorder buffer and processing information when the reorder buffer processes the instructions to be tested, including: Batch obtain instruction information of each instruction to be tested in the instruction group to be tested; The processing information of each instruction to be tested in the instruction group to be tested in the reordering buffer is obtained in real time.

14. The reorder buffer verification platform according to claim 11, characterized in that: It also includes an instruction generation and decoding module, a scheduler, an integer module, a memory access module and a floating point module; wherein, The instruction generation and decoding module is used to generate the instruction to be tested; The scheduler is used to transmit the instruction to be tested to the corresponding module based on the operation type of the operation task in the instruction to be tested, and send the corresponding instruction transmission information to the monitor; The hourly module is used to execute the instruction to be tested sent by the scheduler, and when the operation task of the instruction to be tested is completed, it feeds back the hourly instruction completion information and hourly operation results to the monitor and reorder buffer; The floating-point module is used to execute the instruction to be tested sent by the scheduler, and when the operation task of the instruction to be tested is completed, it feeds back the floating-point instruction completion information and floating-point operation results to the monitor and reorder buffer; The memory access module is used to execute the instruction to be tested sent by the scheduler, and when the operation task of the instruction to be tested is completed, it feeds back the memory access instruction completion information to the monitor and the reorder buffer.

15. The reorder buffer verification platform according to claim 11, characterized in that: The monitor is configured with a plurality of different information queues, and the different information queues are used to collect and send different types of processing information; Among them, the multiple different information queues include a read instruction completion queue, a write instruction completion queue, a floating-point instruction completion queue, an hourly instruction completion queue and a jump instruction completion queue. In the read instruction completion queue, the write instruction completion queue, the floating-point instruction completion queue, the hourly instruction completion queue and the jump instruction completion queue, information collection is performed asynchronously.

16. The reorder buffer verification platform according to claim 11, characterized in that: A queue to be submitted is configured in the predictor, and an emission pointer and a submission pointer are configured in the queue to be submitted. The emission pointer is used to point to the location where the next instruction to be tested stored in the queue to be submitted is stored, and the submission pointer is used to point to the location where the next instruction to be tested to be read in the queue to be submitted is stored; wherein, the emission pointer is updated based on the instruction emission information of the instruction to be tested, and the submission pointer is updated based on the submission operation of the instruction to be tested. If the instruction to be tested pointed to by the submission pointer has been processed, the instruction to be tested is submitted.

17. An electronic device, characterized in that: The electronic device is configured as a reorder buffer verification platform as claimed in any one of claims 11 to 16.

18. A storage medium, characterized in that The storage medium stores one or more computer-executable instructions, and when the one or more computer-executable instructions are executed, the reorder buffer verification method according to any one of claims 1 to 10 is implemented.

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