Chip defect detection method, device and terminal equipment

Abstract

The application discloses a kind of chip defect detection method, device and terminal equipment, comprising: based on the state distribution information of chip acquisition chip based on the running data of chip, and based on the state distribution information obtains the abnormal running state of chip, abnormal running program and associated abnormal structure;Based on the three-dimensional temperature distribution map of chip is constructed based on the temperature data of chip, determines temperature abnormal structure based on the three-dimensional temperature distribution map;Based on the associated abnormal structure and temperature abnormal structure predict the target abnormal structure of chip and abnormal information, generate defect detection result.Through running information, temperature data and so on multiple angle analysis each chip target abnormal structure, and the abnormal information of target abnormal structure, the comprehensiveness of each abnormal structure of chip is identified to improve the abnormal information of each abnormal structure, to comprehensively improve the efficiency of chip defect detection.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of Internet of Things chip, and particularly to a chip defect detection method, device and terminal equipment. BACKGROUND

[0002] At present, during the running of integrated circuit chips, the internal structure of the chip may gradually age and be damaged due to long running time, excessively high running temperature, abnormal program running and the like. In addition to the integrated circuit chips applied in large equipment which are regularly manually detected and replaced, the integrated circuit chips in general small and medium-sized equipment are usually detected for error, failure and damage of the chip only when the chip reports an error, fails or is damaged. Therefore, how to estimate potential problems of the chip in advance through chip regular detection to improve the service life of the chip is the current research focus.

[0003] The existing chip detection method detects the chip through manual program detection and then detects the chip through a chip detection device. The detection is time-consuming, consumes a large amount of human resources and has high cost of the chip detection device, thereby resulting in high cost of chip detection and low efficiency of chip defect detection. SUMMARY

[0004] The present application provides a chip defect detection method, device and terminal equipment to reduce the cost of chip detection and improve the efficiency of chip detection.

[0005] To solve the above technical problems, the present application provides a chip defect detection method, comprising:

[0006] obtaining state distribution information of the chip based on running data of the chip, and obtaining abnormal running state, abnormal running program and associated abnormal structure of the chip based on the state distribution information;

[0007] constructing a three-dimensional temperature distribution map of the chip based on temperature data of the chip, and determining a temperature abnormal structure based on the three-dimensional temperature distribution map;

[0008] predicting target abnormal structure and abnormal information of the chip based on the associated abnormal structure and the temperature abnormal structure, and generating a defect detection result.

[0009] Further, the state distribution information of the chip is obtained based on running data of the chip, comprising:

[0010] obtaining running information of the chip within a preset time period at regular intervals, and splitting the running information based on running types to obtain sub-running information of each running type;

[0011] The sub-operation information of each operation type is arranged according to time sequence, and sub-operation distribution information of each operation type is obtained;

[0012] Chip state information corresponding to each operation type is collected, and chip state data of each operation type is obtained according to the chip state information and the sub-operation information;

[0013] The chip state data is arranged and processed based on the distribution, and sub-state distribution information corresponding to each operation type is obtained, and the state distribution information of the chip is generated based on the sub-state distribution information.

[0014] Further, the state distribution information is used to obtain the abnormal operation state, the abnormal operation program and the associated abnormal structure of the chip, including:

[0015] The abnormal operation state of the chip is obtained based on the preset standard operation range and the state distribution information;

[0016] The abnormal operation program is determined based on the abnormal operation state, and the associated abnormal structure is obtained based on the abnormal operation program.

[0017] Further, the abnormal operation state of the chip is obtained based on the preset standard operation range and the state distribution information, including:

[0018] The state trend information of each operation type is obtained based on the sub-state distribution information of each type;

[0019] The first abnormal operation state is obtained based on the sub-state distribution information and the standard operation range;

[0020] The second abnormal operation state is obtained based on the state trend information and the standard operation range;

[0021] The abnormal operation state of the chip is generated based on the first abnormal operation state and the second abnormal operation state.

[0022] Further, the abnormal operation program is determined based on the abnormal operation state, and the associated abnormal structure is obtained based on the abnormal operation program, including:

[0023] The operation type corresponding to the abnormal operation state is obtained, and the abnormal operation program is determined according to the operation type;

[0024] The first abnormal structure participating in the running of the abnormal operation program in the chip is obtained, and the participation degree of the first abnormal structure is obtained, and the second abnormal structure is obtained according to the participation degree; The participation degree represents the participation degree of the first abnormal structure in the running of the abnormal operation program.

[0025] Furthermore, the construction of a three-dimensional temperature distribution map of the chip based on the chip's temperature data, and the determination of temperature anomaly structures based on the three-dimensional temperature distribution map, includes:

[0026] Obtain the structural and thermal information of the chip; the structural information includes the material information, thermal information, shape information, and spatial connection information of each structure; the thermal information includes the thermal conductivity and specific heat capacity coefficient of each component.

[0027] A three-dimensional structural model of the chip is constructed based on the structural information, and a heat conduction model of the chip is constructed based on the thermal information and the three-dimensional structural model.

[0028] Temperature distribution information for each measurement point is generated based on preset measurement points, temperature data, and heat conduction models.

[0029] Based on the temperature distribution information and the three-dimensional structural model, a three-dimensional temperature distribution map of the chip is generated, and the temperature anomaly structure is determined based on the three-dimensional temperature distribution map.

[0030] Furthermore, determining the temperature anomaly structure based on the three-dimensional temperature distribution map includes:

[0031] The temperature thresholds of each structure are obtained, and the sub-temperature distribution maps of each structure are determined based on the three-dimensional temperature distribution map;

[0032] The temperature anomaly structure is determined based on the sub-temperature distribution map and the temperature threshold.

[0033] Furthermore, the step of predicting the target abnormal structure and abnormal information of the chip based on the associated abnormal structure and temperature abnormal structure, and generating defect detection results, includes:

[0034] Based on the aforementioned associated abnormal structure and temperature abnormal structure, the first abnormal structure and its corresponding abnormal information are filtered.

[0035] Based on the aforementioned associated anomaly structure, filter the second anomaly structure and its corresponding anomaly information;

[0036] Based on the aforementioned temperature anomaly structure, a third anomaly structure and its corresponding anomaly information are selected.

[0037] Integrate the first abnormal structure, the second abnormal structure, and the third abnormal structure to generate the target abnormal structure and its corresponding abnormal information, and generate the defect detection result; the abnormal information includes the cause of the abnormality, the target time period, the location point of the abnormal structure, and the target abnormal state.

[0038] In a second aspect, the present invention provides a chip defect detection device, comprising: a state anomaly monitoring module, a temperature anomaly monitoring module, and a prediction module;

[0039] The state anomaly monitoring module is used to obtain the state distribution information of the chip based on the chip's operating data, and to obtain the abnormal operating state, abnormal operating program and associated abnormal structure of the chip based on the state distribution information.

[0040] The temperature anomaly monitoring module is used to construct a three-dimensional temperature distribution map of the chip based on the chip's temperature data, and to determine the temperature anomaly structure based on the three-dimensional temperature distribution map.

[0041] The prediction module is used to predict the target abnormal structure and abnormal information of the chip based on the associated abnormal structure and temperature abnormal structure, and generate defect detection results.

[0042] Thirdly, the present invention provides a terminal device, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein the processor executes the computer program to implement the chip defect detection method described above. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of a chip defect detection method provided in an embodiment of the present invention;

[0044] Figure 2 This is a schematic diagram of a chip defect detection device provided in an embodiment of the present invention;

[0045] Figure 3 This is another schematic flowchart of a chip defect detection method provided in an embodiment of the present invention. Detailed Implementation

[0046] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. The following examples are for illustrative purposes only and are not intended to limit the scope of the invention.

[0047] The terms "first" and "second," etc., in the specification, claims, and drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such processes, methods, products, or apparatus.

[0048] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0049] Example 1

[0050] See Figure 1 , Figure 1 This is a schematic diagram of a chip defect detection method provided in an embodiment of the present invention. The embodiment of the present invention provides a chip defect detection method, including steps 101 to 103, as detailed below:

[0051] Step 101: Obtain the chip's state distribution information based on the chip's operating data, and obtain the chip's abnormal operating state, abnormal operating program, and associated abnormal structure based on the state distribution information;

[0052] In this embodiment, obtaining the chip's state distribution information based on the chip's operational data includes:

[0053] The chip's operating information is acquired periodically within a preset time period, and the operating information is split based on the operating type to obtain sub-operating information for each operating type;

[0054] Arrange the sub-run information of each run type according to the time sequence to obtain the sub-run distribution information of each run type;

[0055] Collect chip status information corresponding to each operating type, and obtain chip status data for each operating type based on the chip status information and sub-operation distribution information;

[0056] Based on the chip state data, the distribution and arrangement processing is performed to obtain the sub-state distribution information corresponding to each operating type, and the chip state distribution information is generated based on the sub-state distribution information.

[0057] In this embodiment, a preset sampling period is set, and the terminal periodically obtains the chip's operating information according to the sampling period. The operating information includes the operating speed and the processing log information of each running program of the chip.

[0058] In this embodiment, the state distribution information of the chip is identified based on the operation information, wherein the state distribution information includes sub-state information corresponding to the operation information of different operation types.

[0059] In this embodiment, after obtaining the sub-run information for each run type, the sub-run information for each run type is arranged according to time order to obtain the initial sub-run distribution information for each run type. Then, the initial sub-run distribution information is fitted using a fitting algorithm to obtain the sub-run distribution information for each run type. The fitting algorithm is a curve fitting algorithm based on the least squares method.

[0060] In this embodiment, a fitting algorithm is used to fit the distribution information of each sub-run, avoiding the interference of discrete data with the data analysis process and improving the accuracy of the obtained sub-state distribution information.

[0061] In this embodiment, each operation type corresponds to a running program and a chip structure. The operation type is used to represent the functional information corresponding to the chip type. The operation types include structure control type, data processing type, data transmission type, data receiving type, and data sending type. The structure control type corresponds to the chip's controller, the data processing type corresponds to the chip's processing structure, the data transmission type corresponds to the chip's transmission structure, the data receiving type corresponds to the chip's receiving port, and the data sending type corresponds to the chip's data sending port, etc.

[0062] In this embodiment, chip status information corresponding to each operating type is obtained. Based on the chip status information corresponding to each operating type and the sub-operation distribution information of each operating type, the chip status data corresponding to each operating data in the sub-operation distribution information of each operating type is identified through the status database. The chip status data is then distributed and arranged according to the distribution method between the operating data corresponding to each chip status data to obtain the sub-state distribution information corresponding to each operating type.

[0063] In this embodiment, a state database is pre-constructed, which includes chip state information corresponding to each operating type, as well as the correlation between data changes for each operating type and data changes in the chip state information. By querying the state database, the chip state information corresponding to each operating type, and the chip state data corresponding to each operating data, can be obtained.

[0064] In this embodiment, obtaining the abnormal operating state, abnormal operating program, and associated abnormal structure of the chip based on the state distribution information includes:

[0065] The abnormal operating state of the chip is obtained based on the preset standard operating range and the state distribution information;

[0066] The abnormal running program is determined based on the abnormal running state, and the associated abnormal structure is obtained based on the abnormal running program.

[0067] In this embodiment, based on the sub-state distribution information corresponding to each operating type, the state trend information corresponding to each operating type is identified, and the standard operating range of each chip's operating state is obtained. The abnormal operating state of the chip is obtained based on the abnormal state determination rules, the preset standard operating range, and the state distribution information.

[0068] In this embodiment, obtaining the abnormal operating state of the chip based on the preset standard operating range and the state distribution information includes:

[0069] Obtain state trend information for each running type based on the sub-state distribution information of each type;

[0070] The first abnormal operating state is obtained based on the sub-state distribution information and the standard operating range;

[0071] The second abnormal operating state is obtained based on the state trend information and the standard operating range;

[0072] The abnormal operating state of the chip is generated based on the first abnormal operating state and the second abnormal operating state.

[0073] In this embodiment, the abnormal state determination rule stipulates that: for each operating type, the state distribution information in the sub-state distribution information of the operating type that is greater than the standard operating range is selected as the first abnormal operating state; the segment of the sub-state trend information of the operating type that is greater than the normal operating range is selected as the second abnormal operating state; the first abnormal operating state and the second abnormal operating state are used as the abnormal operating states of the chip.

[0074] In this embodiment, the running program corresponding to the running type is identified based on the abnormal running state; the running program corresponding to the running type with an abnormal running state is regarded as the abnormal running program corresponding to the abnormal running state.

[0075] In this embodiment, based on the sub-state distribution information corresponding to each operating type, the state trend information corresponding to each operating type is identified, and the standard operating range of each chip's operating state is obtained. The state trend information is used to characterize the predicted state distribution information of each operating type over a fixed future period. The identification process of this state trend information involves analyzing the predicted state distribution information of the sub-state distribution information using a trend line analysis strategy, based on the slope and distribution range of the curve corresponding to each operating type. This trend line analysis strategy corresponds to the trend line analysis program in MATLAB.

[0076] In this embodiment, the step of determining the abnormal running program based on the abnormal running state and obtaining the associated abnormal structure based on the abnormal running program includes:

[0077] Obtain the running type corresponding to the abnormal running state, and determine the abnormal running program based on the running type;

[0078] Obtain a first abnormal structure in the chip that participates in the execution of the abnormal program, and obtain the participation degree of the first abnormal structure. Obtain a second abnormal structure based on the participation degree. The second abnormal structure is an associated abnormal structure. The participation degree represents the degree to which the abnormal structure participates in the execution of the abnormal program.

[0079] In this embodiment, state distribution information exceeding the standard operating range in the sub-state distribution information of the operating type is filtered according to the abnormal state determination rules and designated as the first abnormal operating state; state trend information corresponding to the operating type is identified, and sub-state trend information segments exceeding the standard operating state are filtered and designated as the second abnormal operating state. Then, the terminal uses the first and second abnormal operating states as the abnormal operating states of the chip and identifies the running program corresponding to the operating type. Finally, the terminal designates the running program corresponding to the operating type with abnormal operating states as the abnormal running program corresponding to the abnormal operating states.

[0080] In this embodiment, by analyzing the current abnormal state and predicted abnormal state of the curve, which are the running programs corresponding to each running type, the accuracy, comprehensiveness, and potential of the identified running programs are improved.

[0081] In this embodiment, in a preset chip database, the structure participating in each abnormal running program in each structure of the chip is queried as the first abnormal structure of each abnormal running program; for each abnormal running program, the degree of participation of the first abnormal structure in the abnormal running program is identified, and the first abnormal structures are sorted in descending order of participation degree, and the abnormal structures with a higher degree of participation are selected as the second abnormal structure according to a preset number, and the second abnormal structure is the associated abnormal structure of the abnormal running program.

[0082] In this embodiment, for each abnormally running program, the degree of participation of each initial associated abnormal structure (first abnormal structure) in the abnormally running program is identified. Specifically, the database stores the associated structures corresponding to each running program and the running content of the running program corresponding to each associated structure. The terminal determines the degree of participation of each initial associated abnormal structure in the abnormally running program according to the proportion of the running content of the running program corresponding to each associated structure to the total running content of that running program. A preset number of initial associated abnormal structures are then selected as associated abnormal structures for the abnormally running program based on the order of participation degree from highest to lowest. This preset number can be set according to the structure ratio or can be adjusted manually.

[0083] In this embodiment, by selecting abnormal structures with a high degree of correlation as associated abnormal structures, the accuracy of identifying associated abnormal structures is improved.

[0084] Step 102: Construct a three-dimensional temperature distribution map of the chip based on the chip's temperature data, and determine the temperature anomaly structure based on the three-dimensional temperature distribution map;

[0085] In this embodiment, measurement points are preset in the chip, and temperature sensors are installed at these measurement points. The measurement points include the chip casing, chip connection points, and the chip motherboard.

[0086] In this embodiment, while obtaining the chip's operating information according to the sampling period, the chip's temperature data is also obtained based on a preset temperature sensor.

[0087] In this embodiment, constructing a three-dimensional temperature distribution map of the chip based on its temperature data, and determining the temperature anomaly structure based on the three-dimensional temperature distribution map, includes:

[0088] Obtain the structural and thermal information of the chip; the structural information includes the material information, thermal information, shape information, and spatial connection information of each structure; the thermal information includes the thermal conductivity and specific heat capacity coefficient of each component.

[0089] A three-dimensional structural model of the chip is constructed based on the structural information, and a heat conduction model of the chip is constructed based on the thermal information and the three-dimensional structural model.

[0090] Temperature distribution information for each measurement point is generated based on preset measurement points, temperature data, and heat conduction models.

[0091] Based on the temperature distribution information and the three-dimensional structural model, a three-dimensional temperature distribution map of the chip is generated, and the temperature anomaly structure is determined based on the three-dimensional temperature distribution map.

[0092] In this embodiment, structural material information, structural shape information, and spatial connection information between the various structures of the chip are collected to generate structural information, and thermal information corresponding to the structural material information is obtained. The structural material information refers to the constituent materials of the structure, such as monocrystalline silicon, polyester plastic, or metal. The thermal information includes the thermal conductivity and specific heat capacity of each structural material. This thermal information is used to analyze the temperature data transfer rate and transfer loss rate between each structure, thereby identifying the distribution of temperature data within the chip.

[0093] In this embodiment, a basic chip information database is pre-built based on the chip's structural and thermal information. The chip's structural and thermal information can be quickly obtained by querying this database.

[0094] In this embodiment, a three-dimensional structural model of the chip is constructed based on the structural shape information of each structure and the spatial connection information between the structures. The three-dimensional structural model can be constructed using a finite element simulation model. Based on the thermal information of the structural material information of each structure, the thermal conductivity coefficient and specific heat capacity coefficient of each structure are identified. Based on the thermal conductivity coefficient, specific heat capacity coefficient, and three-dimensional structural model of each structure, a thermal conduction model of the chip is constructed. Based on the thermal conduction model of the chip and the position information of each measurement point, the initial temperature distribution information of the chip corresponding to the current temperature data of each measurement point is generated. The initial temperature distribution information corresponding to each measurement point is then fitted to obtain the current temperature distribution information of the chip.

[0095] In this embodiment, the current temperature distribution information of the chip is obtained by fitting the chip temperature distribution information corresponding to the temperature data of each measurement point, thereby improving the accuracy of the identified chip temperature distribution information.

[0096] In this embodiment, after obtaining the temperature distribution information of the chip, the sub-temperature distribution information of each structure of the chip is identified, and the fitted temperature data of each structure is added to the three-dimensional structural model of the chip to obtain a three-dimensional temperature distribution map of the chip. The temperature data at different locations in this three-dimensional temperature distribution map are distinguished by different colored markers.

[0097] In this embodiment, by visually mapping the fitted temperature distribution information onto a three-dimensional structural model, a three-dimensional temperature distribution map of the chip is obtained, which improves the accuracy of the obtained three-dimensional temperature distribution map.

[0098] In this embodiment, determining the temperature anomaly structure based on the three-dimensional temperature distribution map includes:

[0099] The temperature thresholds of each structure are obtained, and the sub-temperature distribution maps of each structure are determined based on the three-dimensional temperature distribution map;

[0100] The temperature anomaly structure is determined based on the sub-temperature distribution map and the temperature threshold.

[0101] In this embodiment, the temperature threshold of each structure is collected, and a sub-temperature distribution map of each structure is obtained based on the three-dimensional temperature distribution map of the chip. For the sub-temperature distribution map of each structure, the abnormal structure location points corresponding to the temperature data greater than the temperature threshold in each structure are selected, and the structures with abnormal structure location points are regarded as temperature abnormal structures.

[0102] In this embodiment, by identifying the abnormal structural locations of different structures under the structural temperature threshold conditions of the structure, the accuracy and comprehensiveness of identifying temperature-abnormal structures are improved.

[0103] Step 103: Based on the associated abnormal structure and temperature abnormal structure, predict the target abnormal structure and abnormal information of the chip, and generate defect detection results.

[0104] In this embodiment, the step of predicting the target abnormal structure and abnormal information of the chip based on the associated abnormal structure and temperature abnormal structure, and generating defect detection results, includes:

[0105] Based on the aforementioned associated abnormal structure and temperature abnormal structure, the first abnormal structure and its corresponding abnormal information are filtered.

[0106] Based on the aforementioned associated anomaly structure, filter the second anomaly structure and its corresponding anomaly information;

[0107] Based on the aforementioned temperature anomaly structure, a third anomaly structure and its corresponding anomaly information are selected.

[0108] Integrate the first abnormal structure, the second abnormal structure, and the third abnormal structure to generate the target abnormal structure and its corresponding abnormal information, and generate the defect detection result; the abnormal information includes the cause of the abnormality, the target time period, the location point of the abnormal structure, and the target abnormal state.

[0109] In this embodiment, filtering the first abnormal structure and its corresponding abnormal information based on the associated abnormal structure and temperature abnormal structure includes: filtering the first abnormal structure that is both an associated abnormal structure and a temperature abnormal structure among the various structures of the chip; identifying the abnormal cause of each first abnormal structure based on the abnormal temperature data corresponding to the location points of each abnormal structure and the first abnormal operating state of each first abnormal structure; predicting the target abnormal time period and the target abnormal state of each first abnormal structure based on the second abnormal operating state of each first abnormal structure; and using the abnormal cause, the target abnormal time period, and the target abnormal state of each first abnormal structure as the abnormal information of each first abnormal structure.

[0110] In this embodiment, filtering second abnormal structures and their corresponding abnormal information based on the associated abnormal structures includes: filtering second abnormal structures that are only associated abnormal structures among the various structures of the chip; identifying the abnormal probability of each second abnormal structure based on the degree of participation of each second abnormal structure with the abnormal running program; identifying the abnormal cause of each second abnormal structure based on the first abnormal running state of each second abnormal structure; identifying the target abnormal state and the target abnormal time period of each second abnormal structure based on the second abnormal running state of each second abnormal structure; and using the abnormal probability, the abnormal cause, the target abnormal state, and the target abnormal time period of each second abnormal structure as the abnormal information of each second abnormal structure.

[0111] In this embodiment, the screening of a third abnormal structure and its corresponding abnormal information based on the temperature abnormal structure includes: screening a third abnormal structure that is only a temperature abnormal structure among the various structures of the chip, and identifying the temperature change information of each third abnormal structure over a fixed period of time; identifying the temperature trend information of the third abnormal structure based on the temperature change information of each third abnormal structure, and using the temperature abnormality and the temperature trend information as the abnormal information of the third abnormal structure.

[0112] In this embodiment, each first abnormal structure, each second abnormal structure, and each third abnormal structure are regarded as each target abnormal structure of the chip, and the abnormal information of each first abnormal structure, each second abnormal structure, and each third abnormal structure are regarded as the abnormal information of each target abnormal structure of the chip.

[0113] In this embodiment, by decomposing and analyzing the anomalous information of different anomalous field structures, the anomalous information of each anomalous structure is obtained, thereby improving the pertinence and accuracy of identifying anomalous information of anomalous structures.

[0114] In this embodiment, chip defect self-detection is performed by periodically acquiring the chip's current operating information and current temperature data from multiple measurement points over a fixed period of time. This avoids the inefficiency of manual periodic detection and improves the efficiency of chip defect self-detection. Simultaneously, by analyzing the acquired data, associated abnormal structures and temperature abnormal structures of the chip are identified, thereby predicting each target abnormal structure of the chip and its abnormal information. This not only improves the comprehensiveness and accuracy of chip defect self-detection but also enhances the efficiency of generating early warning and handling strategies for chip abnormal structures by predicting potentially abnormal structures using the aforementioned information. Furthermore, by analyzing the target abnormal structures and their abnormal information from multiple perspectives, such as operating information and temperature data, the comprehensiveness of identifying the abnormal information of each abnormal structure of the chip is improved, thus comprehensively enhancing the efficiency of chip defect detection.

[0115] Please refer to Figure 2 , Figure 2 A schematic diagram of a chip defect detection device provided in an embodiment of the present invention includes: a state anomaly monitoring module 201, a temperature anomaly monitoring module 202, and a prediction module 203;

[0116] The state anomaly monitoring module 201 is used to obtain the state distribution information of the chip based on the chip's operating data, and to obtain the abnormal operating state, abnormal operating program and associated abnormal structure of the chip based on the state distribution information.

[0117] The temperature anomaly monitoring module 202 is used to construct a three-dimensional temperature distribution map of the chip based on the chip's temperature data, and to determine the temperature anomaly structure based on the three-dimensional temperature distribution map.

[0118] The prediction module 203 is used to predict the target abnormal structure and abnormal information of the chip based on the associated abnormal structure and temperature abnormal structure, and generate defect detection results.

[0119] In this embodiment, the status anomaly monitoring module 201 is specifically used to: periodically acquire the chip's operating information within a preset time period, and split the operating information based on the operating type to acquire sub-operating information for each operating type;

[0120] Arrange the sub-run information of each run type according to the time sequence to obtain the sub-run distribution information of each run type;

[0121] Collect chip status information corresponding to each operating type, and obtain chip status data for each operating type based on the chip status information and sub-operation distribution information;

[0122] Based on the chip state data, the distribution and arrangement processing is performed to obtain the sub-state distribution information corresponding to each operating type, and the chip state distribution information is generated based on the sub-state distribution information.

[0123] In this embodiment, the status anomaly monitoring module 201 is further configured to:

[0124] The abnormal operating state of the chip is obtained based on the preset abnormal state determination rules, standard operating range, and the state distribution information.

[0125] The abnormal running program is determined based on the abnormal running state, and the associated abnormal structure is obtained based on the abnormal running program.

[0126] In this embodiment, the status anomaly monitoring module 201 is further configured to:

[0127] Obtain state trend information for each running type based on the sub-state distribution information of each type;

[0128] The first abnormal operating state is obtained based on the sub-state distribution information and the standard operating range;

[0129] The second abnormal operating state is obtained based on the state trend information and the standard operating range;

[0130] The abnormal operating state of the chip is generated based on the first abnormal operating state and the second abnormal operating state.

[0131] In this embodiment, the status anomaly monitoring module 201 is further configured to:

[0132] Obtain the running type corresponding to the abnormal running state, and determine the abnormal running program based on the running type;

[0133] Obtain a first abnormal structure in the chip that participates in the execution of the abnormal program, and obtain the participation degree of the first abnormal structure. Obtain a second abnormal structure based on the participation degree. The second abnormal structure is an associated abnormal structure. The participation degree represents the degree to which the abnormal structure participates in the execution of the abnormal program.

[0134] In this embodiment, the temperature anomaly monitoring module 202 is specifically used for:

[0135] Obtain the structural and thermal information of the chip; the structural information includes the material information, thermal information, shape information, and spatial connection information of each structure; the thermal information includes the thermal conductivity and specific heat capacity coefficient of each component.

[0136] A three-dimensional structural model of the chip is constructed based on the structural information, and a heat conduction model of the chip is constructed based on the thermal information and the three-dimensional structural model.

[0137] Temperature distribution information for each measurement point is generated based on preset measurement points, temperature data, and heat conduction models.

[0138] Based on the temperature distribution information and the three-dimensional structural model, a three-dimensional temperature distribution map of the chip is generated, and the temperature anomaly structure is determined based on the three-dimensional temperature distribution map.

[0139] In this embodiment, the temperature anomaly monitoring module 202 is further configured to:

[0140] The temperature thresholds of each structure are obtained, and the sub-temperature distribution maps of each structure are determined based on the three-dimensional temperature distribution map;

[0141] The temperature anomaly structure is determined based on the sub-temperature distribution map and the temperature threshold.

[0142] In this embodiment, the prediction module 203 is specifically used for:

[0143] Based on the aforementioned associated abnormal structure and temperature abnormal structure, the first abnormal structure and its corresponding abnormal information are filtered.

[0144] Based on the aforementioned associated anomaly structure, filter the second anomaly structure and its corresponding anomaly information;

[0145] Based on the aforementioned temperature anomaly structure, a third anomaly structure and its corresponding anomaly information are selected.

[0146] Integrate the first abnormal structure, the second abnormal structure, and the third abnormal structure to generate the target abnormal structure and its corresponding abnormal information, and generate the defect detection result; the abnormal information includes the cause of the abnormality, the target time period, the location point of the abnormal structure, and the target abnormal state.

[0147] In this embodiment, chip defect self-detection is performed by periodically acquiring the chip's current operating information and current temperature data from multiple measurement points over a fixed period of time. This avoids the inefficiency of manual periodic detection and improves the efficiency of chip defect self-detection. Simultaneously, by analyzing the acquired data, associated abnormal structures and temperature abnormal structures of the chip are identified, thereby predicting each target abnormal structure of the chip and its abnormal information. This not only improves the comprehensiveness and accuracy of chip defect self-detection but also enhances the efficiency of generating early warning and handling strategies for chip abnormal structures by predicting potentially abnormal structures using the aforementioned information. Furthermore, by analyzing the target abnormal structures and their abnormal information from multiple perspectives, such as operating information and temperature data, the comprehensiveness of identifying the abnormal information of each abnormal structure of the chip is improved, thus comprehensively enhancing the efficiency of chip defect detection.

[0148] Please refer to Figure 3 , Figure 3 Another schematic flowchart of a chip defect detection method provided in an embodiment of the present invention includes steps 301 to 305, as follows:

[0149] Step 301: Periodically acquire the current operating information of the chip for a fixed period of time, as well as the current temperature data of multiple measurement points of the chip, and identify the state distribution information of the chip based on the current operating information of the chip;

[0150] Step 302: Perform distribution processing on the current temperature data of each measurement point to obtain the current temperature distribution information of the chip, and construct a three-dimensional temperature distribution map of the chip based on the current temperature distribution information of the chip;

[0151] Step 303: Based on the state distribution information of the chip, identify the abnormal operating state of the chip and the abnormal operating program corresponding to the abnormal operating state, and query the associated abnormal structure corresponding to the abnormal operating program;

[0152] Step 304: Based on the three-dimensional temperature distribution map of the chip, filter out temperature abnormal structures in each structure of the chip, and predict each target abnormal structure of the chip and the abnormal information of each target abnormal structure based on each associated abnormal structure and each temperature abnormal structure.

[0153] Step 305: The abnormal structures of each target and the abnormal information of each target abnormal structure are used as the target detection results of the chip.

[0154] This invention also provides a chip defect detection system, including an acquisition module, a construction module, an identification module, a prediction module, and a determination module;

[0155] The acquisition module is used to periodically acquire the current operating information of the chip for a fixed period of time, as well as the current temperature data of multiple measurement points of the chip, and to identify the state distribution information of the chip based on the current operating information of the chip.

[0156] The construction module is used to perform distribution processing on the current temperature data of each measurement point to obtain the current temperature distribution information of the chip, and to construct a three-dimensional temperature distribution map of the chip based on the current temperature distribution information of the chip.

[0157] The identification module is used to identify the abnormal operating state of the chip and the abnormal operating program corresponding to the abnormal operating state based on the state distribution information of the chip, and to query the associated abnormal structure corresponding to the abnormal operating program.

[0158] The prediction module is used to filter out temperature abnormal structures in each structure of the chip based on the three-dimensional temperature distribution map of the chip, and predict each target abnormal structure of the chip and the abnormal information of each target abnormal structure based on each associated abnormal structure and each temperature abnormal structure.

[0159] The determining module is used to take each of the target abnormal structures and the abnormal information of each of the target abnormal structures as the target detection result of the chip.

[0160] In this embodiment, chip defect self-detection is performed by periodically acquiring the chip's current operating information and current temperature data from multiple measurement points over a fixed period of time. This avoids the inefficiency of manual periodic detection and improves the efficiency of chip defect self-detection. Simultaneously, by analyzing the acquired data, associated abnormal structures and temperature abnormal structures of the chip are identified, thereby predicting each target abnormal structure of the chip and its abnormal information. This not only improves the comprehensiveness and accuracy of chip defect self-detection but also enhances the efficiency of generating early warning and handling strategies for chip abnormal structures by predicting potentially abnormal structures using the aforementioned information. Furthermore, by analyzing the target abnormal structures and their abnormal information from multiple perspectives, such as operating information and temperature data, the comprehensiveness of identifying the abnormal information of each abnormal structure of the chip is improved, thus comprehensively enhancing the efficiency of chip defect detection.

[0161] In this embodiment of the invention, a terminal device is also provided, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor. When the processor executes the computer program, it implements the chip defect detection method described above.

[0162] For example, a computer program can be divided into one or more modules, one or more of which are stored in memory and executed by a processor to perform the present invention. The one or more modules can be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of the computer program in a terminal device.

[0163] The terminal device may be a desktop computer, laptop, handheld computer, or cloud server, etc. The terminal device may include, but is not limited to, a processor, memory, and display. Those skilled in the art will understand that the above components are merely examples of terminal devices and do not constitute a limitation on the terminal device. It may include more or fewer components, or combinations of certain components, or different components. For example, the terminal device may also include input / output devices, network access devices, buses, etc.

[0164] The processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor. The processor is the control center of the terminal device, connecting all parts of the terminal device through various interfaces and lines.

[0165] Memory can be used to store computer programs and / or modules. The processor implements various functions of the terminal device by running or executing the computer programs and / or modules stored in the memory, and by accessing data stored in the memory. Memory can mainly include a program storage area and a data storage area. The program storage area can store the operating system, at least one application program required for a function (such as sound playback function, text conversion function, etc.), etc.; the data storage area can store data created based on the use of the mobile phone (such as audio data, text message data, etc.). In addition, memory can include high-speed random access memory, and can also include non-volatile memory, such as hard disk, RAM, plug-in hard disk, Smart Memory Card (SMC), Secure Digital (SD) card, Flash Card, at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0166] Wherein, if the modules of the terminal device are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of the present invention can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. Those skilled in the art can understand and implement this without any inventive effort.

[0167] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. A chip defect detection method, characterized in that, include: The method involves obtaining chip state distribution information based on chip operating data, and then obtaining abnormal operating states, abnormal operating programs, and associated abnormal structures based on the state distribution information. This includes: obtaining abnormal operating states of the chip based on preset abnormal state determination rules, standard operating ranges, and the state distribution information; obtaining the operating type corresponding to the abnormal operating state, and determining the abnormal operating program based on the operating type; obtaining a first abnormal structure in the chip that participates in the operation of the abnormal operating program, and obtaining the participation degree of the first abnormal structure; obtaining a second abnormal structure based on the participation degree, wherein the second abnormal structure is an associated abnormal structure; the participation degree indicates the extent to which the abnormal structure participates in the operation of the abnormal operating program. A three-dimensional temperature distribution map of the chip is constructed based on the chip's temperature data, and the temperature anomaly structure is determined based on the three-dimensional temperature distribution map. Based on the associated abnormal structure and temperature abnormal structure, the target abnormal structure and abnormal information of the chip are predicted, and defect detection results are generated.

2. The chip defect detection method as described in claim 1, characterized in that, The acquisition of chip state distribution information based on chip operating data includes: The chip's operating information is acquired periodically within a preset time period, and the operating information is split based on the operating type to obtain sub-operating information for each operating type; Arrange the sub-run information of each run type according to the time sequence to obtain the sub-run distribution information of each run type; Collect chip status information corresponding to each operating type, and obtain chip status data for each operating type based on the chip status information and sub-operation distribution information; Based on the chip state data, the distribution and arrangement processing is performed to obtain the sub-state distribution information corresponding to each operating type, and the chip state distribution information is generated based on the sub-state distribution information.

3. The chip defect detection method as described in claim 2, characterized in that, The process of obtaining the abnormal operating state of the chip based on preset abnormal state determination rules, standard operating range, and state distribution information includes: Obtain state trend information for each running type based on the sub-state distribution information of each type; The first abnormal operating state is obtained based on the sub-state distribution information and the standard operating range; The second abnormal operating state is obtained based on the state trend information and the standard operating range; The abnormal operating state of the chip is generated based on the first abnormal operating state and the second abnormal operating state.

4. The chip defect detection method as described in claim 1, characterized in that, The process of constructing a three-dimensional temperature distribution map of the chip based on its temperature data, and determining temperature anomaly structures based on the three-dimensional temperature distribution map, includes: Obtain the structural and thermal information of the chip; the structural information includes the material information, thermal information, shape information, and spatial connection information of each structure; the thermal information includes the thermal conductivity and specific heat capacity coefficient of each structure. A three-dimensional structural model of the chip is constructed based on the structural information, and a heat conduction model of the chip is constructed based on the thermal information and the three-dimensional structural model. Temperature distribution information for each measurement point is generated based on preset measurement points, temperature data, and heat conduction models. Based on the temperature distribution information and the three-dimensional structural model, a three-dimensional temperature distribution map of the chip is generated, and the temperature anomaly structure is determined based on the three-dimensional temperature distribution map.

5. The chip defect detection method as described in claim 4, characterized in that, The determination of the temperature anomaly structure based on the three-dimensional temperature distribution map includes: The temperature thresholds of each structure are obtained, and the sub-temperature distribution maps of each structure are determined based on the three-dimensional temperature distribution map; The temperature anomaly structure is determined based on the sub-temperature distribution map and the temperature threshold.

6. A chip defect detection method according to any one of claims 1 to 5, characterized in that, The method of predicting the target abnormal structure and abnormal information of the chip based on the associated abnormal structure and temperature abnormal structure, and generating defect detection results, includes: Based on the aforementioned associated abnormal structure and temperature abnormal structure, the first abnormal structure and its corresponding abnormal information are filtered. Based on the aforementioned associated anomaly structure, filter the second anomaly structure and its corresponding anomaly information; Based on the aforementioned temperature anomaly structure, a third anomaly structure and its corresponding anomaly information are selected. Integrate the first abnormal structure, the second abnormal structure, and the third abnormal structure to generate the target abnormal structure and its corresponding abnormal information, and generate the defect detection result; the abnormal information includes the cause of the abnormality, the target abnormal time period, the location point of the abnormal structure, and the target abnormal state.

7. A chip defect detection device, characterized in that, include: Anomaly monitoring module, temperature anomaly monitoring module, and prediction module; The anomaly monitoring module is used to obtain the chip's state distribution information based on the chip's operating data, and to obtain the chip's abnormal operating state, abnormal operating program, and associated abnormal structure based on the state distribution information; including: obtaining the chip's abnormal operating state based on preset abnormal state determination rules, standard operating range, and the state distribution information; obtaining the operating type corresponding to the abnormal operating state, and determining the abnormal operating program according to the operating type; obtaining a first abnormal structure in the chip that participates in the operation of the abnormal operating program, and obtaining the participation degree of the first abnormal structure, and obtaining a second abnormal structure based on the participation degree, wherein the second abnormal structure is an associated abnormal structure; the participation degree represents the degree of participation of the abnormal structure in the operation of the abnormal operating program; The temperature anomaly monitoring module is used to construct a three-dimensional temperature distribution map of the chip based on the chip's temperature data, and to determine the temperature anomaly structure based on the three-dimensional temperature distribution map. The prediction module is used to predict the target abnormal structure and abnormal information of the chip based on the associated abnormal structure and temperature abnormal structure, and generate defect detection results.

8. A terminal device, characterized in that, It includes a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein the processor executes the computer program to implement a chip defect detection method as described in any one of claims 1 to 6.

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