High-precision successive approximation type ADC test circuit and test method

Abstract

The invention provides a high-precision successive approximation type ADC test circuit and test method, and relates to the field of analog-to-digital converter test. The circuit mainly comprises a control bus end, a control comparison module, an integrator module, a power supply module and an input signal conditioning module. Wherein the control bus end generates an initial digital signal to generate an adjustment control signal according to a key power carry point which is easy to introduce a DNL error, and controls the power supply module to charge and discharge the integrator module. The integrator module is used for integrating the input current and outputting an integral voltage in direct proportion to an integral value to the input signal conditioning module; the input signal conditioning module is used for generating an analog input signal ADIN according to the integral voltage, sending the analog input signal ADIN to the tested ADC for analog-to-digital conversion, outputting a digital code value and generating a target voltage signal. Through the test circuit structure and the test process, the DNL error characteristic of the ADC can be accurately evaluated.

Description

Technical Field

[0001] The present application relates to the field of analog-to-digital converter testing, and in particular to a high-precision successive approximation ADC testing circuit and testing method. Background Art

[0002] Successive approximation analog-to-digital converters (SAR ADCs) are widely used in various electronic devices due to their low power consumption, high speed, and high resolution. With the continuous development of technology, the accuracy requirements for ADCs are getting higher and higher. However, ADCs often have differential nonlinearity (DNL) errors in practical applications, that is, the jump step lengths between adjacent code values ​​are inconsistent, resulting in reduced conversion accuracy.

[0003] At present, the common method for testing ADC differential nonlinearity error is to use a high-precision digital-to-analog converter (DAC) to generate an analog signal corresponding to the ADC input range and measure the output digital code value of the ADC. By comparing the difference between the ideal code value and the actual code value, the DNL error can be calculated. However, this method has certain limitations. First, the cost of high-precision DAC is high, and it is difficult to ensure the linearity and stability of its output signal, which is easy to introduce additional test errors. Secondly, this method needs to traverse the entire input range of the ADC, the test time is long, and the efficiency is low. In addition, since the conversion characteristics of the ADC are different at different code values, it is difficult to accurately capture the DNL error at the key code value by simply scanning the input signal at equal intervals, which affects the reliability of the test results. Summary of the invention

[0004] The present application provides a high-precision successive approximation ADC test circuit and test method, which are used to improve the accuracy of ADC performance evaluation.

[0005] In a first aspect, the present application provides a high-precision successive approximation ADC test circuit, the circuit comprising: a control bus terminal, a control comparison module, an integrator module, a power supply module and an input signal conditioning module; The control comparison module is electrically connected to the ADC under test; the control comparison module is electrically connected to the integrator module; the integrator module is electrically connected to the input signal conditioning module; the input signal conditioning module is electrically connected to the ADC under test; the power supply module is electrically connected to the control comparison module, the integrator module and the input signal conditioning module; the control bus terminal is electrically connected to the control comparison module; The control bus terminal is used to generate an initial digital signal according to a key weight carry point that is easy to introduce a DNL error, and output the initial digital signal to the control comparison module to start the test; The control comparison module is used to generate an initial control signal according to the digital signal; The control comparison module is further used to generate an adjustment control signal according to the data output by the ADC under test; The power supply module is used to charge or discharge the integrator module according to the initial control signal or the adjustment control signal; The integrator module is used to integrate the input current according to the initial control signal or the adjustment control signal output by the control comparison module to obtain an integral value, and output an integral voltage proportional to the integral value to the input signal conditioning module; The input signal conditioning module is used to generate an analog input signal ADIN according to the integrated voltage to perform analog-to-digital conversion on the ADC under test and output a digital code value; The input signal conditioning module is further used to generate a target voltage signal according to the integrated voltage.

[0006] By adopting the above technical scheme, the high-precision successive approximation ADC test circuit provided by the present invention realizes efficient and accurate testing of ADC differential nonlinearity error through a carefully designed hardware structure and test method. The test circuit includes a control bus terminal, a control comparison module, an integrator module, a power supply module and an input signal conditioning module, and each module is connected electrically to form a complete test system. The control bus terminal generates an initial digital signal to generate an initial control signal according to the key weight carry point that is easy to introduce DNL error, and generates an adjustment control signal according to the data output by the ADC under test. The power supply module charges or discharges the integrator module according to the initial control signal or the adjustment control signal to achieve precise control of the test signal. The integrator module integrates the input current according to the initial control signal or the adjustment control signal output by the control comparison module to obtain an integral value, and outputs an integral voltage proportional to the integral value to the input signal conditioning module. The input signal conditioning module generates an analog input signal ADIN according to the integrated voltage to perform analog-to-digital conversion on the ADC under test, outputs a digital code value, and also generates a target voltage signal according to the integrated voltage. Through the coordinated work of the above hardware structure, the test circuit can be a high-precision successive approximation ADC test circuit, so that the voltage value of the operational amplifier output after differential amplification is stabilized at a level corresponding to the preset digital signal. This automatic adjustment mechanism can effectively compensate for environmental interference and device drift during the test process, ensure the accuracy and stability of the test signal, and thus improve the reliability of the test results. Compared with the traditional method of using a high-precision DAC to generate a test signal, the present invention does not require the use of expensive DAC devices, reduces the test cost, and avoids additional errors caused by insufficient linearity and stability of the DAC output signal.

[0007] Optionally, the value of the initial digital signal is related to the reference voltage of the ADC under test, the supply voltage of the DAC, and the input voltage range of the ADC under test.

[0008] By adopting the above technical scheme, the high-precision successive approximation ADC test circuit provided by the present invention can accurately control the output voltage of the test circuit when generating the value of the initial digital signal, so that it falls within the input voltage range of the ADC under test, thereby avoiding test failure or error caused by the test signal exceeding the range. At the same time, the value of the initial digital signal, the test circuit can output a test signal that matches the ADC under test, ensuring the smooth progress of the test process and the accuracy of the test results. At the same time, by optimizing the selection of test points, the key code values ​​that are easy to introduce errors are tested, thereby improving the test efficiency and accuracy.

[0009] Optionally, the control comparison module includes a control signal generating unit, a data comparison unit and a logic judgment unit; the control signal generating unit is electrically connected to the data comparison unit and the logic judgment unit in sequence; The control signal generating unit is used to determine the input digital quantity DB according to the digital signal; The control signal generating unit is further used to generate an output digital quantity DA according to the data output by the ADC under test; The data comparison unit is used to compare the preset digital quantity B with the input digital quantity DB to obtain an initial comparison result; The data comparison unit is further used to compare the preset digital quantity B with the output digital quantity DA to obtain an adjustment comparison result; The logic judgment unit is used to generate the corresponding control signal to the power module according to the initial comparison result or the adjustment comparison result.

[0010] By adopting the above technical scheme, the high-precision successive approximation ADC test circuit provided by the present invention adopts a combination of a control signal generating unit, a data comparison unit and a logic judgment unit in the design of the control comparison module, and realizes accurate control and automatic adjustment of the test process through reasonable electrical connection and functional division. The control signal generating unit generates an output digital quantity DA according to the digital signal, which provides a basis for subsequent data comparison and logic judgment. The data comparison unit compares the preset digital quantity B with the input digital quantity DB and the output digital quantity DA respectively, obtains an initial comparison result and an adjustment comparison result, and provides a basis for the decision of the logic judgment unit. The logic judgment unit generates a corresponding control signal to the power supply module according to the initial comparison result or the adjustment comparison result, and realizes automatic adjustment and feedback control of the test circuit. Through the coordinated work of the control comparison module, the test circuit can dynamically adjust the test signal according to the output data of the ADC under test, so that it is stable at a level corresponding to the preset digital signal, ensuring the adaptability and robustness of the test process. Compared with the traditional open-loop test method, the present invention introduces a closed-loop feedback control mechanism, which monitors the output data of the ADC under test in real time, dynamically adjusts the test signal, effectively compensates for environmental interference and device drift during the test process, and improves the test accuracy and reliability. At the same time, by reasonably dividing the functional units of the control comparison module, the modularization and structuring of the test process are realized, and the maintainability and scalability of the test circuit are improved. The design of the control signal generating unit, the data comparison unit and the logic judgment unit clearly reflects the logical flow of the test process, is easy to understand and optimize, and provides convenience for further improvement of the test circuit. Therefore, in the design of the control comparison module, the present invention realizes the adaptability and robustness of the test process by introducing a closed-loop feedback control mechanism, and improves the test accuracy and reliability. At the same time, through modular and structured design, the maintainability and scalability of the test circuit are enhanced, and a powerful technical support is provided for the test of high-precision ADC.

[0011] Optionally, the integrator module includes: an operational amplifier and an integrating capacitor; The integrating capacitor is connected in parallel with the operational amplifier; and the operational amplifier is electrically connected with the control comparison module.

[0012] By adopting the above technical scheme, the high-precision successive approximation ADC test circuit provided by the present invention adopts a structure of parallel connection of an operational amplifier and an integral capacitor in the design of an integrator module, and realizes accurate integration and voltage output of the input current through reasonable electrical connection and device selection. As the core device of the integrator, the operational amplifier has the characteristics of high gain, high input impedance and low output impedance, and can amplify and convert a tiny input current to obtain an output voltage proportional to the integral value. The integral capacitor is connected in parallel with the operational amplifier, and plays a key role in the feedback loop of the operational amplifier. By continuously integrating the input current, the current signal is converted into a voltage signal, and the signal conversion and processing are realized. At the same time, the capacitance of the integral capacitor directly affects the sensitivity and time constant of the integrator. By reasonably selecting the capacitance of the integral capacitor, the performance of the integrator can be optimized, and the test accuracy and speed can be improved. Compared with the traditional resistor feedback integrator, the present invention adopts the capacitor feedback method to avoid the noise and drift of the resistor device, and improve the stability and reliability of the integrator. Through the parallel design of the operational amplifier and the integrating capacitor, the integrator module can convert the control signal output by the control comparison module into a voltage signal proportional to the integral value, providing a basis for subsequent signal conditioning and ADC conversion. The output voltage of the integrator module is precisely controlled and adjusted, and stabilized at a level corresponding to the preset digital signal, ensuring the accuracy and consistency of the test signal. Therefore, in the design of the integrator module, the present invention realizes the precise integration and voltage output of the input current through the parallel structure of the operational amplifier and the integrating capacitor, and improves the stability and reliability of the integrator. At the same time, by reasonably selecting the capacitance of the integrating capacitor, the performance of the integrator is optimized, and the test accuracy and speed are improved. The precise output of the integrator module provides a reliable basis for subsequent signal conditioning and ADC conversion, ensures the accuracy and consistency of the entire test circuit, and provides a strong technical guarantee for the test of high-precision ADC.

[0013] Optionally, the input signal conditioning module includes: an adder and a differential amplifier; The adder is electrically connected to the differential amplifier; and the differential amplifier is electrically connected to the ADC under test.

[0014] By adopting the above technical scheme, the high-precision successive approximation ADC test circuit provided by the present invention adopts a combination of an adder and a differential amplifier in the design of the input signal conditioning module, and realizes the accurate conditioning and processing of the integrator output signal through reasonable electrical connection and functional division. The adder receives the integrated voltage output by the integrator module, superimposes it with other signals, and obtains a composite signal. The differential amplifier receives the composite signal output by the adder, converts it into a differential signal, and amplifies it to obtain an analog input signal ADIN proportional to the integrated voltage. Through the cascade design of the adder and the differential amplifier, the input signal conditioning module can accurately condition the integrated voltage, suppress common-mode interference, and improve the quality and integrity of the signal. Compared with the single-ended signal, the differential signal has stronger anti-interference ability and noise suppression ability, can effectively reduce electromagnetic interference and noise in the test environment, and improve the test accuracy and reliability. At the same time, through the amplification of the differential amplifier, the amplitude of the analog input signal ADIN is improved, the driving ability of the signal is enhanced, and the normal operation of the ADC under test is ensured. In addition, the high common mode rejection ratio and low offset voltage characteristics of the differential amplifier further improve the accuracy and stability of the test signal. The precise output of the input signal conditioning module directly affects the conversion performance of the ADC under test. Through the reasonable design of the adder and the differential amplifier, it is ensured that the analog input signal ADIN corresponds to the preset digital signal, providing a reliable input for the precise conversion of the ADC. At the same time, the input signal conditioning module also generates a target voltage signal according to the integrated voltage, providing a reference for the evaluation and calibration of the test results. Through the precise conditioning and processing of the input signal conditioning module, the test circuit can provide a high-quality, low-noise analog input signal to the ADC under test, meeting the requirements of high-precision testing. Therefore, in the design of the input signal conditioning module, the present invention realizes the precise conditioning and processing of the integrator output signal through the combination of the adder and the differential amplifier, thereby improving the quality and integrity of the test signal. The differential signal transmission mode is adopted to enhance the anti-interference ability and noise suppression ability, and improve the test accuracy and reliability. At the same time, through the amplification effect and excellent characteristics of the differential amplifier, the amplitude and stability of the analog input signal ADIN are ensured, providing a reliable input for the precise conversion of the ADC under test. The precise output of the input signal conditioning module provides a reference for the evaluation and calibration of the test results, further improving the performance and reliability of the test circuit and providing a strong technical guarantee for the testing of high-precision ADCs.

[0015] Optionally, the parameters of the ADC under test include a reference voltage Vref, a supply voltage VS, and an input voltage range Vrange of the ADC under test; the preset digital quantity B is determined according to the parameters of the ADC under test, where B≈(VS / Vrange)*2^N, where N is the resolution of the ADC under test.

[0016] By adopting the above technical solution, the preset digital quantity B is determined according to the parameters of the ADC under test, that is, B≈(VS / Vrange)*2^N, where VS is the power supply voltage, Vrange is the input voltage range of the ADC under test, and N is the resolution of the ADC under test. This setting method has the following advantages and technical effects: the determination of the preset digital quantity B comprehensively considers key parameters such as the power supply voltage VS, input voltage range Vrange and resolution N of the ADC under test. Since B≈(VS / Vrange)*2^N, it can be seen that the preset digital quantity B is proportional to the power supply voltage VS, inversely proportional to the input voltage range Vrange, and increases exponentially with the increase of resolution N. This relationship accurately reflects the conversion characteristics of the ADC and provides a reasonable reference benchmark for subsequent DNL error testing.

[0017] On the other hand, the present application also provides a high-precision successive approximation ADC testing method, the method comprising: Selecting a set of representative test code values ​​according to the resolution and test requirements of the ADC under test; Generate a corresponding initial digital signal according to the test code value, and input the initial digital signal into the high-precision successive approximation ADC test circuit in sequence to obtain an initial measurement voltage; The DNL error is determined according to the initial measurement voltage, and the ADC under test is evaluated according to the DNL error to obtain an evaluation result.

[0018] By adopting the above technical solution, the present application selects a set of representative test code values, generates corresponding initial digital signals according to the test code values, inputs the initial digital signals into the high-precision successive approximation ADC test circuit in sequence, obtains the initial measurement voltage, determines the DNL error according to the initial measurement voltage, and evaluates the ADC under test based on the DNL error, thereby obtaining the evaluation result. This method makes full use of the high-precision characteristics of the high-precision successive approximation ADC test circuit. By accurately measuring the actual output voltage of the ADC under test at different code values, the nonlinear error characteristics of the ADC can be accurately obtained. By selecting representative test code values, the performance of the ADC in the entire input range can be comprehensively evaluated, thereby improving the pertinence and effectiveness of the test. At the same time, by analyzing the DNL error, the nonlinearity of the ADC can be quantitatively evaluated, providing an important basis for subsequent calibration and optimization.

[0019] In summary, one or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages: 1. This application selects a set of representative test code values, generates corresponding initial digital signals according to the test code values, inputs the initial digital signals into a high-precision successive approximation ADC test circuit in sequence, obtains an initial measurement voltage, determines the DNL error according to the initial measurement voltage, and evaluates the ADC under test based on the DNL error, thereby obtaining an evaluation result. This method makes full use of the high-precision characteristics of the high-precision successive approximation ADC test circuit. By accurately measuring the actual output voltage of the ADC under test at different code values, the nonlinear error characteristics of the ADC can be accurately obtained. By selecting representative test code values, the performance of the ADC in the entire input range can be comprehensively evaluated, thereby improving the pertinence and effectiveness of the test. At the same time, by analyzing the DNL error, the nonlinearity of the ADC can be quantitatively evaluated, providing an important basis for subsequent calibration and optimization.

[0020] 2. Subtract the initial measured voltage from the ideal output voltage of the corresponding code value to obtain the actual voltage error at each test code value. This step accurately quantifies the actual error characteristics of the ADC at different input code values ​​by directly comparing the difference between the measured voltage and the ideal voltage. By eliminating the system bias and common-mode error in the measured voltage, the inherent nonlinear error component of the ADC is extracted. After obtaining the voltage error of each test code value, the voltage errors corresponding to the two adjacent test code values ​​are further subtracted to obtain the DNL error. This differential calculation method cleverly utilizes the correlation between adjacent code values, and directly obtains the quantification result of the DNL error by comparing the voltage error difference of adjacent code values. Since the input signal corresponding to adjacent code values ​​changes the least, the voltage error difference between them can best reflect the nonlinearity of the ADC at the code value conversion point. The DNL error calculated in this way can accurately characterize the small nonlinear error characteristics of the ADC when adjacent code values ​​are converted.

[0021] 3. In the process of evaluating the ADC under test based on the DNL error, an intuitive and effective analysis method is adopted. By drawing the DNL error distribution histogram of the ADC under test, the frequency distribution of the DNL error in different size intervals can be clearly displayed. The DNL error distribution histogram uses the size of the DNL error as the horizontal axis and the corresponding frequency as the vertical axis. Through intuitive graphical representation, it reveals the probability and distribution law of the ADC under different nonlinear error levels. By observing the DNL error distribution histogram, the nonlinear error characteristics of the ADC can be directly judged. Ideally, the DNL error should be concentrated near the zero value and present a shape similar to a normal distribution. If the DNL error distribution histogram shows obvious offset, broadening, or multiple peaks, it means that the ADC has significant nonlinear errors and its performance may be affected. By analyzing the frequency distribution of the DNL error in different size intervals, the nonlinearity of the ADC can be quantitatively evaluated to determine whether it meets the design indicators and application requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of the structure of a high-precision successive approximation ADC test circuit provided in an embodiment of the present application; Figure 2 A flowchart of a high-precision successive approximation ADC testing method provided in an embodiment of the present application; Figure 3 A schematic diagram of a high-precision successive approximation ADC test circuit provided in this application; Figure 4 A diagram illustrating a DNL provided in this application; Figure 5 A ramp input waveform diagram of a full code test provided in this application Figure 6 A measurement time reference diagram for a full code test of an ADC provided in this application Figure 7 A test result diagram of a 16-bit successive approximation ADC provided for this application Figure 8 This is a test efficiency diagram of a certain 16-bit successive approximation ADC provided in this application. DETAILED DESCRIPTION

[0023] In order to enable technicians in this field to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below in conjunction with the drawings in the embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments.

[0024] In the description of the embodiments of the present application, words such as "for example" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "for example" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "for example" or "for example" is intended to present related concepts in a specific way.

[0025] In the description of the embodiments of the present application, the meaning of the term "multiple" refers to two or more. For example, multiple systems refer to two or more systems, and multiple screen terminals refer to two or more screen terminals. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. The terms "include", "comprise", "have" and their variations all mean "including but not limited to", unless otherwise specifically emphasized.

[0026] The testing of mixed-signal integrated circuits has always been the focus of the industry. Among them, the successive approximation analog-to-digital converter (SAR ADC) has been widely used in various electronic devices due to its advantages of low power consumption, high speed and high resolution. However, with the continuous advancement of technology and the increasing expansion of application fields, the accuracy requirements for ADCs are also increasing. In actual work, ADCs often face the challenge of differential nonlinearity (DNL) errors, that is, the jump step lengths between adjacent code values ​​are inconsistent, resulting in the conversion accuracy being affected, which has become one of the key bottlenecks restricting the improvement of ADC performance.

[0027] In order to comprehensively evaluate the differential nonlinearity of ADC, the industry at home and abroad generally adopts a test solution based on high-precision arbitrary waveform generator (AWG) and digital channel resources. By using AWG to generate an analog signal that matches the input range of the ADC under test, and using digital channel resources to control the ADC to collect the analog signal, the collected data is processed and fitted to obtain a result that is comparable to the input signal, thereby analyzing the differential linearity (DNL) of the ADC. DNL is the core parameter of ADC electrical parameter testing. Its description is shown in Figure 4 )) parameters. DNL is the core indicator of ADC electrical parameter testing. Its definition and test method are clearly defined in the domestic industry standard SJ20961 "Basic Principles of Integrated Circuit A / D and D / A Converter Test Methods".

[0028] According to the SJ20961 standard, the basic steps for testing DNL are as follows: First, by gradually adjusting the input level, find out the input level Va corresponding to the output code jumping from i-1 to i; then, continue to adjust the input level until the output code jumps from i to i+1, and record the input level Vb at this time. It can be obtained that when the output code is i, its actual code width is Vb-Va. Finally, according to the formula DNLi= (Vb-Va) / LSB, calculate the DNL value at the output code i, where LSB represents the ideal code width voltage (LeastSignificant Bit). Repeat the above steps to obtain the DNL distribution corresponding to all output codes of the ADC. This test method is called the "full code test method" in the industry. For details, please refer to Figure 5 and Figure 6 . However, the above-mentioned traditional test method based on high-precision DAC has some limitations that cannot be ignored. First, the cost of high-precision DAC is high, and the linearity and stability of its output signal are difficult to guarantee, which easily introduces additional test errors and affects the accuracy of the test results. Secondly, this method requires traversal testing of the entire input range of the ADC, which is time-consuming and has low test efficiency. In addition, due to the differences in the conversion characteristics of the ADC at different code values, it is difficult to accurately capture the DNL error at the key code value by simply scanning the input signal at equal intervals, which further affects the reliability of the test results.

[0029] After the background introduction of the above content, those skilled in the art can understand the problems existing in the prior art. The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments.

[0030] Based on the above background technology, please refer to Figure 1 , Figure 1 A schematic diagram of a high-precision successive approximation ADC test circuit provided in an embodiment of the present application, specifically, the high-precision successive approximation ADC test circuit includes: a control bus terminal, a control comparison module, an integrator module, a power supply module and an input signal conditioning module; The control comparison module is electrically connected to the ADC under test; the control comparison module is electrically connected to the integrator module; the integrator module is electrically connected to the input signal conditioning module; the input signal conditioning module is electrically connected to the ADC under test; the power supply module is electrically connected to the control comparison module, the integrator module and the input signal conditioning module; the control bus terminal is electrically connected to the control comparison module; The control bus terminal is used to generate an initial digital signal according to a key weight carry point that is easy to introduce a DNL error, and output the initial digital signal to the control comparison module to start the test; The control comparison module is used to generate an initial control signal according to the digital signal; The control comparison module is further used to generate an adjustment control signal according to the data output by the ADC under test; The power supply module is used to charge or discharge the integrator module according to the initial control signal or the adjustment control signal; The integrator module is used to integrate the input current according to the initial control signal or the adjustment control signal output by the control comparison module to obtain an integral value, and output an integral voltage proportional to the integral value to the input signal conditioning module; The input signal conditioning module is used to generate an analog input signal ADIN according to the integrated voltage to perform analog-to-digital conversion on the ADC under test and output a digital code value; The input signal conditioning module is further used to generate a target voltage signal according to the integrated voltage.

[0031] For details, please refer to Figure 3 A high-precision successive approximation ADC test circuit includes a control bus terminal, a control comparison module, an integrator module, a power module and an input signal conditioning module. Through the coordinated work of these modules, the test circuit can effectively test and evaluate the differential nonlinear error of the ADC and improve the test accuracy and efficiency.

[0032] During the test, the control bus terminal generates an initial digital signal based on the key weight carry point that is prone to DNL errors, and outputs it to the control comparison module to start the test. This step fully considers the conversion characteristics of the ADC, and by focusing on selecting key code values ​​that are prone to DNL errors as test points, it avoids blind scanning of the entire input range, shortens the test time, and improves test efficiency.

[0033] The control comparison module receives the initial digital signal, generates an adjustment control signal according to the difference between the actual code value and the expected code value, and dynamically adjusts the charging and discharging process of the power module to ensure the accuracy and stability of the test signal.

[0034] The power module charges or discharges the integrator module according to the initial control signal or adjustment control signal output by the control comparison module, providing stable and reliable power support. The integrator module integrates the input current according to the control signal, obtains the integral voltage proportional to the integral value, and outputs it to the input signal conditioning module.

[0035] The input signal conditioning module receives the integrated voltage output by the integrator module, generates the corresponding analog input signal ADIN, and inputs it to the ADC under test for analog-to-digital conversion to obtain the actual digital code value. At the same time, the input signal conditioning module also generates a target voltage signal based on the integrated voltage as a reference for evaluating the ADC performance.

[0036] Through the above steps, the test circuit can accurately and efficiently test the differential nonlinear error of the ADC. The initial digital signal generated by the control bus end focuses on covering the key code values ​​that are easy to introduce DNL errors, avoiding unnecessary test overhead. The control comparison module achieves precise control and dynamic adjustment of the test process by generating initial control signals and adjusting control signals, ensuring the quality of the test signal. The cooperation of the power module and the integrator module provides a stable and reliable hardware foundation for the generation of test signals. The input signal conditioning module provides reliable data support for the evaluation of ADC performance by generating high-quality analog input signals and target voltage signals.

[0037] It should be further explained that the analog input signal ADIN is the integrated voltage after conditioning and amplification. It is directly input into the ADC under test for analog-to-digital conversion to obtain the actual digital code value. This process is a key step in the test system to actually evaluate the ADC performance. By comparing the difference between the actual output code value and the expected code value, the differential nonlinearity error (DNL) of the ADC can be obtained.

[0038] The target voltage signal is used as a reference for evaluating the ADC performance. By comparing the difference between the target voltage and the ADIN signal, the conversion accuracy and linearity of the ADC can be judged more accurately.

[0039] The differential amplifier introduced in the input signal conditioning module plays a key role. It performs 100 times differential amplification on the ADIN signal, allowing the test system to detect tiny voltage changes at the 10uV level. This amplification process greatly improves the sensitivity and resolution of the test, and compared with the traditional full-code test solution, the test accuracy is improved by nearly 100 times.

[0040] Figure 7 The test results shown demonstrate the superiority of this test solution. For a 16-bit ADC, its LSB (least significant bit) is about 76uV. Such a small voltage change is difficult to measure accurately with traditional test methods. By introducing 100 times differential amplification, the test system can clearly distinguish 10uV level voltage changes, making the differential nonlinear error test of the ADC more accurate and reliable.

[0041] In addition to the significant improvement in test accuracy, the present invention also makes full use of the characteristics of the successive approximation ADC to further optimize the test efficiency. Based on the architecture of the successive approximation ADC, the DNL error is mainly concentrated at the weight carry point. Therefore, by focusing on testing the weight carry point, the DNL performance of the ADC can be quickly evaluated without traversing the entire input range. This targeted testing strategy can shorten the test time by nearly 50%. Figure 8 shown.

[0042] Based on the above embodiment, as an optional embodiment, the value of the initial digital signal is related to the reference voltage of the ADC under test, the supply voltage of the DAC, and the input voltage range of the ADC under test.

[0043] Specifically, in a high-precision successive approximation ADC test circuit, the value of the initial digital signal generated by the control bus is closely related to the reference voltage of the ADC under test, the supply voltage of the DAC, and the input voltage range of the ADC under test. Consideration and design of this correlation are crucial to ensuring the accuracy and applicability of the test signal.

[0044] First, the reference voltage of the ADC under test determines its quantization step and input range. The value of the initial digital signal needs to match the reference voltage to ensure that the generated test signal can cover the entire input range of the ADC and coordinate with its quantization step. By reasonably setting the value of the initial digital signal, the test circuit can generate a test signal corresponding to the ADC input range to ensure the integrity and effectiveness of the test. Secondly, the supply voltage of the DAC determines the amplitude range of its output signal. The value of the initial digital signal needs to take into account the supply voltage of the DAC to ensure that the generated test signal is within the output range of the DAC to avoid signal distortion or clipping. By matching the value of the initial digital signal with the supply voltage of the DAC, the test circuit can generate a test signal with appropriate amplitude and good quality, providing a reliable input for the evaluation of ADC performance.

[0045] In addition, the input voltage range of the ADC under test is also an important basis for determining the initial digital signal value. The voltage range of the test signal needs to match the input range of the ADC, covering the entire input range while avoiding overloading the ADC input due to exceeding the range. By comprehensively considering the input voltage range of the ADC and setting the value of the initial digital signal accordingly, the test circuit can generate a test signal with an appropriate voltage range that matches the ADC input, ensuring the accuracy and reliability of the test.

[0046] In the actual test process, the control bus terminal calculates and generates the optimal value of the initial digital signal according to the parameters and characteristics of the ADC under test. These values ​​must not only meet the accuracy and applicability requirements of the test signal, but also take into account the test efficiency and resource utilization.

[0047] Based on the above embodiment, as an optional embodiment, the control comparison module includes a control signal generating unit, a data comparison unit and a logic judgment unit; the control signal generating unit is electrically connected to the data comparison unit and the logic judgment unit in sequence; The control signal generating unit is used to determine the input digital quantity DB according to the digital signal; The control signal generating unit is further used to generate an output digital quantity DA according to the data output by the ADC under test; The data comparison unit is used to compare the preset digital quantity B with the input digital quantity DB to obtain an initial comparison result; The data comparison unit is further used to compare the preset digital quantity B with the output digital quantity DA to obtain an adjustment comparison result; The logic judgment unit is used to generate the corresponding control signal to the power module according to the initial comparison result or the adjustment comparison result.

[0048] Specifically, in the high-precision successive approximation ADC test circuit, the control comparison module plays a vital role. It includes a control signal generation unit, a data comparison unit, and a logic judgment unit. Through the coordinated work of these units, precise control and dynamic adjustment of the test process are achieved.

[0049] First, the control signal generating unit determines the input digital quantity DB according to the digital signal. This step converts the initial digital signal generated by the control bus end into the working digital quantity inside the control comparison module, providing a basis for subsequent comparison and judgment. By processing and converting the input digital signal, the control signal generating unit realizes the signal connection and matching between the modules of the test circuit, ensuring the accuracy and consistency of signal transmission. Secondly, the control signal generating unit also generates the output digital quantity DA according to the data output by the ADC under test. This process converts the actual output code value of the ADC into a digital quantity form that can be processed by the control comparison module, providing a basis for subsequent comparison and judgment. By acquiring and converting the output data of the ADC in real time, the control signal generating unit realizes the dynamic tracking and feedback of the actual conversion results of the ADC, providing data support for the real-time adjustment and optimization of the test process.

[0050] The data comparison unit compares the preset digital quantity B with the input digital quantity DB and the output digital quantity DA respectively to obtain the initial comparison result and the adjustment comparison result. The preset digital quantity B represents the ideal code value that the test circuit expects the ADC to output. By comparing it with the actual input and output digital quantities, the data comparison unit can evaluate the conversion performance of the ADC in real time and determine whether it meets expectations. The initial comparison result reflects whether the setting of the test signal is reasonable, while the adjustment comparison result reflects the difference between the actual output of the ADC and the ideal output, providing a basis for subsequent control and adjustment.

[0051] Finally, the logic judgment unit generates a corresponding control signal to the power module according to the initial comparison result or the adjustment comparison result. When the initial comparison result shows that the test signal setting is reasonable, the logic judgment unit generates a corresponding control signal to instruct the power module to charge and discharge the integrator module according to the preset scheme to maintain the stable output of the test signal. When the adjustment comparison result shows that the ADC output is different from the expected value, the logic judgment unit generates an adjustment control signal to instruct the power module to adjust the charging and discharging strategy accordingly and dynamically optimize the test signal to reduce the conversion error and improve the test accuracy.

[0052] Through the coordinated work of the control signal generation unit, the data comparison unit and the logic judgment unit, the control comparison module realizes precise control and real-time adjustment of the test process. The digital quantity conversion and processing of the control signal generation unit ensures the accuracy and consistency of signal transmission. The comparison and evaluation of the data comparison unit provides a basis for the judgment and optimization of the test process. The control signal generation of the logic judgment unit realizes the effective control of the power module and the integrator module, ensuring the quality and stability of the test signal.

[0053] Based on the above embodiment, as an optional embodiment, the integrator module includes: an operational amplifier and an integrating capacitor; The integrating capacitor is connected in parallel with the operational amplifier; and the operational amplifier is electrically connected with the control comparison module.

[0054] Specifically, in the high-precision successive approximation ADC test circuit, the integrator module plays a key role. It is mainly composed of an operational amplifier and an integral capacitor. Through the cooperation of these two core components, the precise integration of the input current and the stable output of the integrated voltage are achieved.

[0055] The integration capacitor and the operational amplifier are connected in parallel to form the basic circuit structure of the integrator module. This parallel connection method gives full play to the amplification function of the operational amplifier and the charge storage function of the integration capacitor, ensuring the accuracy and stability of the integration process.

[0056] During the test, the control comparison module outputs the initial control signal or the adjustment control signal, and transmits these control signals to the operational amplifier in the integrator module through electrical connection. The operational amplifier performs precise integration operation on the input current according to the received control signal. Specifically, when the control signal indicates charging, the operational amplifier converts the input current into charge and stores it in the integration capacitor. As the charging process proceeds, the voltage across the integration capacitor continues to rise, forming an integration voltage proportional to the integral value.

[0057] At the same time, the high gain characteristics of the operational amplifier and the filtering effect of the integral capacitor effectively suppress the noise and interference in the integration process, ensuring the stability and accuracy of the integral voltage. The capacitance selection of the integral capacitor has also been carefully designed and optimized to meet the requirements of integral accuracy while taking into account the stability and response speed of the circuit.

[0058] When the control signal indicates discharge, the operational amplifier releases the charge stored in the integral capacitor, causing the integral voltage to gradually decrease until it reaches the preset lower limit. By controlling the charge and discharge process, the integrator module achieves precise regulation and dynamic control of the integral voltage, providing a stable and reliable input signal for subsequent signal conditioning and ADC conversion.

[0059] The output integrated voltage of the integrator module is carefully conditioned and then passed to the input signal conditioning module. The conditioned analog input signal ADIN has good linearity, noise characteristics and dynamic range, which can meet the input requirements of the ADC under test and ensure the accuracy and reliability of the conversion results.

[0060] Based on the above embodiment, as an optional embodiment, the parameters of the ADC under test include a reference voltage Vref, a power supply voltage VS, and an input voltage range Vrange of the ADC under test; the preset digital quantity B is determined according to the parameters of the ADC under test, wherein B≈(VS / Vrange)*2^N, where N is the resolution of the ADC under test.

[0061] Specifically, the reference voltage Vref of the ADC under test is 2.5V, the supply voltage VS is 3.3V, the input voltage range Vrange is 2V, and the resolution N is 12 bits. According to the calculation formula of the preset digital quantity B, it can be obtained: B ≈ (VS / Vrange) * 2^N= (3.3V / 2V) * 2^12= 1.65 * 4096= 6758.4 For ease of implementation, the preset digital quantity B may be rounded to 6758.

[0062] During the test, the control bus terminal first selects key code values ​​that are easy to introduce DNL errors as test code values ​​according to the resolution of the ADC being tested and the test requirements. For example, for a 12-bit ADC, 0, 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, and 4095 can be selected as test code values.

[0063] Then, the control bus terminal generates a corresponding initial digital signal according to the test code value and inputs it to the control comparison module. The control signal generating unit in the control comparison module receives the initial digital signal and converts it into an input digital quantity DB.

[0064] Next, the data comparison unit compares the preset digital quantity B (6758) with the input digital quantity DB. If DB is less than 6758, it indicates that the current input voltage has not reached the ideal conversion threshold, and the output voltage of the integrator needs to be further increased. The control comparison module outputs an initial control signal, triggering the power module to charge the integrator module, so that its output voltage continues to rise.

[0065] When the output voltage of the integrator module passes through the input signal conditioning module, the generated analog input signal ADIN is input to the ADC under test and converted into a digital code value. The control comparison module reads the digital code value output by the ADC and converts it into an output digital quantity DA.

[0066] The data comparison unit compares the preset digital quantity B (6758) with the output digital quantity DA. If DA is greater than or equal to 6758, it indicates that the current output code value has reached or exceeded the expected value, and the output voltage of the integrator needs to be maintained or reduced. The control comparison module outputs an adjustment control signal to trigger the power supply module to discharge or maintain the integrator module so that its output voltage is stabilized at an appropriate level.

[0067] In this way, the test circuit can accurately control the input voltage of the ADC under test at the key code value and obtain its actual output code value. The voltage corresponding to the actual output code value is compared with the ideal output voltage to obtain the voltage error, and the DNL error can be obtained by calculating the difference in voltage errors at adjacent code values.

[0068] For example, assuming that when the test code value is 1024, the actual output code value of the ADC under test is 1023, the corresponding actual conversion voltage is 1.998V, and the ideal output voltage is 2.000V. The voltage error is 1.998V - 2.000V = -0.002V. Assuming that when the test code value is 1023, the actual output code value is 1022, the corresponding actual conversion voltage is 1.996V, the ideal output voltage is 1.998V, and the voltage error is 1.996V - 1.998V = -0.002V. The DNL error is (-0.002V) - (-0.002V) = 0, indicating that there is no DNL error at the code value 1024.

[0069] By selecting more test code values ​​and repeating the above test process, the DNL error distribution of the ADC under test at different code values ​​can be obtained. The DNL error is divided into different intervals according to size, and the frequency of occurrence in each interval is counted. Then, a DNL error distribution histogram can be drawn to intuitively evaluate the nonlinear error characteristics of the ADC.

[0070] On the other hand, the present application also provides a test method for a high-precision successive approximation ADC test circuit. For details, please refer to Figure 2 , Figure 2 A flow chart of a test method for a high-precision successive approximation ADC test circuit provided in an embodiment of the present application, the method comprising the following steps: S101, selecting a set of representative test code values ​​according to the resolution and test requirements of the ADC under test; Specifically, the resolution of the ADC under test determines the number of bits and quantization levels of its digital output code. For example, the output code range of an 8-bit ADC is 0255, with a total of 256 quantization levels. The output code range of a 10-bit ADC is 01023, with a total of 1024 quantization levels. The higher the resolution, the more bits of the ADC's output code and the larger the quantization level. Correspondingly, the more complex the test and evaluation of its nonlinear error will be. Therefore, based on the resolution of the ADC under test, the selection range and quantity level of the test code value can be preliminarily determined.

[0071] In addition to considering resolution, the test code value also needs to be selected according to specific test requirements. Different applications and performance indicators have different focuses and evaluation criteria for the nonlinear error characteristics of the ADC. For example, in the field of high-precision measurement, there are strict requirements for the differential nonlinearity (DNL) and integral nonlinearity (INL) errors of the ADC, and it is necessary to focus on testing and evaluating the distribution of the nonlinear error of the ADC within the full-scale range. In the field of high-speed data conversion, more attention is paid to the dynamic performance indicators of the ADC, such as the signal-to-noise ratio (SNR) and total harmonic distortion (THD), and it is necessary to select test code values ​​that can reflect these indicators.

[0072] When actually selecting the test code value, a stratified sampling method is usually used to uniformly select a certain number of representative code values ​​from the entire input code range of the ADC. These code values ​​should cover the key conversion points and sensitive intervals of the ADC, such as the zero point, full-scale point, midpoint, etc., as well as critical code values ​​that are prone to introduce nonlinear errors. At the same time, in order to fully evaluate the nonlinear characteristics of the ADC, it is also necessary to select enough sample points in different code value intervals to ensure the statistical significance and reliability of the test results.

[0073] S102, generating a corresponding initial digital signal according to the test code value, and sequentially inputting the initial digital signal into the high-precision successive approximation ADC test circuit to obtain an initial measurement voltage; In the specific implementation, it is first necessary to generate the corresponding initial digital signal according to the selected test code value. These initial digital signals are usually in the form of binary coding, which matches the input code format of the ADC under test. For example, for an 8-bit ADC, the initial digital signal with a test code value of 0xFF (binary 11111111) is 8 high-level pulses. The required initial digital signal sequence can be easily generated by a digital signal generator or a programmable logic device.

[0074] After the initial digital signal is generated, it needs to be input into the high-precision successive approximation ADC test circuit for measurement. The high-precision successive approximation ADC test circuit is a high-precision digital-to-analog conversion device specially used for ADC performance testing and evaluation. Its core is a high-resolution successive approximation register (SAR) ADC. Through the successive approximation algorithm, the high-precision successive approximation ADC test circuit can convert the initial digital signal into a corresponding high-precision analog voltage, that is, the initial measurement voltage. The accuracy of this measurement voltage is usually much higher than the resolution of the ADC under test, which can meet the requirements of DNL error and INL error testing.

[0075] During the measurement process, the high-precision successive approximation ADC test circuit will sample and convert each initial digital signal multiple times, and average and filter the conversion results to improve the measurement accuracy and stability. At the same time, in order to eliminate the error and nonlinear influence of the test circuit itself, the high-precision successive approximation ADC test circuit also needs to be self-calibrated and error compensated. Through a series of calibration and optimization measures, the accuracy and reliability of the initial measurement voltage can be guaranteed, providing a high-quality data basis for subsequent error calculations.

[0076] By using a high-precision successive approximation ADC test circuit to measure the initial digital signal, a high-precision analog voltage value corresponding to the input code value of the ADC under test can be obtained, namely the initial measurement voltage. These initial measurement voltage data are complete and accurate, and can truly reflect the actual output characteristics of the ADC under test at different input code values. Based on the initial measurement voltage, key performance indicators such as the DNL error and INL error of the ADC can be easily calculated, and the nonlinear characteristics of the ADC can be intuitively displayed in the form of error distribution histograms. The accuracy and reliability of the initial measurement voltage directly determine the accuracy and credibility of the ADC performance evaluation, and are the data basis of the entire test plan.

[0077] The following is an explanation of some of the technical terms in the above content: 1. Successive approximation register (SAR) ADC: SAR ADC is a common ADC architecture that achieves analog-to-digital conversion by successive comparison and approximation. It uses a binary search algorithm to continuously approach the digital equivalent value of the analog input signal through multiple comparisons and adjustments, thereby achieving high-precision digital-to-analog conversion.

[0078] 2. Self-calibration: Self-calibration refers to the process of real-time detection and compensation of the ADC's own errors and nonlinearities during operation. Through the built-in self-calibration circuit and algorithm, the ADC can dynamically adjust its quantization level and comparison threshold to minimize conversion errors and improve measurement accuracy.

[0079] 3. Error compensation: Error compensation refers to the process of correcting and calibrating the conversion results in the digital output of the ADC based on the known error model and calibration data. The error compensation algorithm implemented by software or hardware can effectively eliminate the system error and nonlinear distortion of the ADC and improve its measurement accuracy and dynamic performance.

[0080] 4. Quantization level: The quantization level refers to the minimum analog signal change that the ADC can distinguish within its input range. It is determined by the resolution and reference voltage of the ADC. The size of the quantization level reflects the sensitivity and resolution of the ADC. The smaller the quantization level, the higher the resolution of the ADC and the more detailed the description of the analog signal.

[0081] 5. Comparison threshold: The comparison threshold refers to the voltage limit used by the ADC when comparing analog signals with digital code values. When the voltage of the analog input signal is greater than the comparison threshold, the ADC outputs a corresponding high level; when the voltage of the analog input signal is less than the comparison threshold, the ADC outputs a corresponding low level. The accuracy and stability of the comparison threshold directly affect the conversion accuracy and linearity of the ADC.

[0082] S103, determining a DNL error according to the initial measurement voltage, and evaluating the ADC under test according to the DNL error to obtain an evaluation result.

[0083] Specifically, after obtaining the initial measurement voltage data, the high-precision successive approximation ADC test method of the present invention enters the critical error calculation and performance evaluation stage. According to the initial measurement voltage, through a series of calculation and analysis steps, the differential nonlinearity (DNL) error of the ADC under test can be accurately determined, and the ADC is comprehensively evaluated based on the DNL error to obtain the final evaluation result. The purpose of this process is to deeply analyze the nonlinear characteristics of the ADC, quantitatively evaluate its dynamic performance, and provide an objective and reliable basis for the design optimization and application selection of the ADC.

[0084] First, the DNL error needs to be determined based on the initial measurement voltage. The DNL error reflects the nonlinearity of the ADC when converting adjacent code values ​​and is an important indicator for evaluating the dynamic performance of the ADC. In order to calculate the DNL error, the initial measurement voltage needs to be compared with the ideal conversion characteristic. The ideal conversion characteristic refers to the linear correspondence between the output code value of the ADC and the input analog signal under ideal conditions. By subtracting the ideal output voltage of the corresponding code value from the initial measurement voltage, the voltage error under each test code value can be obtained. Then, the voltage errors of two adjacent test code values ​​are subtracted to obtain the corresponding DNL error value. This differential operation method can effectively eliminate the system error and bias of the measurement circuit itself and improve the accuracy of the DNL error calculation.

[0085] After calculating the DNL errors of all test code values, it is necessary to perform statistical analysis on these error data to comprehensively evaluate the nonlinear characteristics of the ADC. A common analysis method is to draw a DNL error distribution histogram. By dividing the DNL error into several intervals according to the numerical value and counting the number of errors in each interval, the performance of the ADC under different nonlinear levels can be intuitively displayed. Ideally, the DNL error should be concentrated near the zero value and present a shape similar to a normal distribution. If the DNL error distribution shows obvious offset, broadening or multi-peak phenomenon, it means that the ADC has significant nonlinear distortion and its dynamic performance may be affected.

[0086] Based on the DNL error distribution histogram, the nonlinear characteristics of the ADC can be further quantitatively evaluated. By calculating the mean, variance, maximum, minimum and other statistical parameters of the DNL error, the nonlinearity and dynamic range of the ADC can be comprehensively measured. At the same time, the qualified threshold or rating standard of the DNL error can be set according to the specific application requirements and performance indicators, and the ADC can be graded and evaluated and screened. For example, for high-precision measurement applications, the absolute value of the DNL error may be required not to exceed 0.5 LSB (least significant bit), while for high-speed data conversion applications, the DNL error may be allowed to float within the range of ±1 LSB. By quantitatively analyzing and evaluating the DNL error, it is possible to objectively and accurately determine whether the dynamic performance of the ADC meets the requirements of a specific application.

[0087] Through the above series of error calculation, statistical analysis and performance evaluation steps, a comprehensive evaluation result of the nonlinear characteristics of the ADC under test can be obtained. These evaluation results can not only reflect the dynamic performance level of the ADC, but also reveal the source and influencing factors of its nonlinear distortion. For ADC designers, the evaluation results can guide them to optimize circuit design, improve device processes, and improve conversion accuracy and speed. For ADC users, the evaluation results can help them select appropriate device models, determine the best working conditions, and evaluate the performance margin and reliability of the system.

[0088] The above are only exemplary embodiments of the present disclosure and cannot be used to limit the scope of the present disclosure. That is, any equivalent changes and modifications made according to the teachings of the present disclosure are still within the scope of the present disclosure. After considering the disclosure of the specification and the truth of practice, those skilled in the art will easily think of other embodiments of the present disclosure.

[0089] This application is intended to cover any variation, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary technical means in the art not described in the present disclosure. The description and examples are to be regarded as exemplary only, and the scope and spirit of the present disclosure are defined by the claims.

Claims

1. A high-precision successive approximation ADC test circuit, characterized in that: The circuit comprises: a control bus terminal, a control comparison module, an integrator module, a power supply module and an input signal conditioning module; The control comparison module is electrically connected to the ADC under test; the control comparison module is electrically connected to the integrator module; the integrator module is electrically connected to the input signal conditioning module; the input signal conditioning module is electrically connected to the ADC under test; the power supply module is electrically connected to the control comparison module, the integrator module and the input signal conditioning module; the control bus terminal is electrically connected to the control comparison module; The control bus terminal is used to generate an initial digital signal according to a key weight carry point that is easy to introduce a DNL error, and output the initial digital signal to the control comparison module to start the test; The control comparison module is used to generate an initial control signal according to the digital signal; The control comparison module is further used to generate an adjustment control signal according to the data output by the ADC under test; The power supply module is used to charge or discharge the integrator module according to the initial control signal or the adjustment control signal; The integrator module is used to integrate the input current according to the initial control signal or the adjustment control signal output by the control comparison module to obtain an integral value, and output an integral voltage proportional to the integral value; The input signal conditioning module is used to generate an analog input signal ADIN according to the integrated voltage to perform analog-to-digital conversion on the ADC under test and output a digital code value; The input signal conditioning module is further used to generate a target voltage signal according to the integrated voltage.

2. The test circuit according to claim 1, characterized in that: The value of the initial digital signal is related to the reference voltage of the ADC under test, the supply voltage of the DAC, and the input voltage range of the ADC under test.

3. The test circuit according to claim 1, characterized in that: The control comparison module includes a control signal generating unit, a data comparison unit and a logic judgment unit; the control signal generating unit is electrically connected to the data comparison unit and the logic judgment unit in sequence; The control signal generating unit is used to determine the input digital quantity DB according to the digital signal; The control signal generating unit is further used to generate an output digital quantity DA according to the data output by the ADC under test; The data comparison unit is used to compare the preset digital quantity B with the input digital quantity DB to obtain an initial comparison result; The data comparison unit is further used to compare the preset digital quantity B with the output digital quantity DA to obtain an adjustment comparison result; The logic judgment unit is used to generate the corresponding control signal to the power module according to the initial comparison result or the adjustment comparison result.

4. The test circuit according to claim 1, characterized in that: The integrator module comprises: an operational amplifier and an integrating capacitor; The integrating capacitor is connected in parallel with the operational amplifier; and the operational amplifier is electrically connected with the control comparison module.

5. The test circuit according to claim 1, characterized in that: The input signal conditioning module comprises: an adder and a differential amplifier; The adder is electrically connected to the differential amplifier; and the differential amplifier is electrically connected to the ADC under test.

6. The test circuit according to claim 1, characterized in that: The parameters of the ADC under test include a reference voltage Vref, a supply voltage VS, and an input voltage range Vrange of the ADC under test; the preset digital quantity B is determined according to the parameters of the ADC under test, where B≈(VS / Vrange)*2^N, where N is the resolution of the ADC under test.

7. A high-precision successive approximation ADC test method, applied to the high-precision successive approximation ADC test circuit according to any one of claims 1 to 6, characterized in that: include: Selecting a set of representative test code values ​​according to the resolution and test requirements of the ADC under test; Generate a corresponding initial digital signal according to the test code value, and input the initial digital signal into the high-precision successive approximation ADC test circuit in sequence to obtain an initial measurement voltage; The DNL error is determined according to the initial measurement voltage, and the ADC under test is evaluated according to the DNL error to obtain an evaluation result.

8. The testing method according to claim 7, characterized in that: The test code value is a key transition point that easily introduces DNL errors.

9. The testing method according to claim 7, characterized in that: The determining the DNL error according to the initial measured voltage comprises: The initial measured voltage is subtracted from the ideal output voltage of the corresponding code value to obtain the corresponding voltage error, and the voltage errors corresponding to two adjacent test code values ​​are subtracted to obtain the DNL error.

10. The testing method according to claim 7, characterized in that: The step of evaluating the ADC under test according to the DNL error to obtain an evaluation result includes: Draw a DNL error distribution histogram of the ADC under test according to the DNL error, and determine the frequency distribution of the DNL error in different size intervals according to the DNL error distribution histogram; The evaluation result is obtained according to the frequency distribution of the DNL error in different size intervals.

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