A quantum adder, operation method and related device

Abstract

The application discloses a quantum adder, an operation method and related devices. The quantum adder comprises a plurality of chips connected through an EPR module. One chip is used for processing one data segment. The data segment comprises an addend segment and a summand segment. The chip comprises: an addition module, which is used for obtaining an addition result and carry information of the data segment based on a quantum Fourier transform; a loading module, which is used for loading the carry information transmitted through the EPR module on the addition result and the carry information obtained by the chip based on the addition module, so as to update the addition result and the carry information of the chip; and an inverse quantum Fourier transform module, which is used for converting the latest addition result into a binary string. According to the embodiments of the application, the efficiency of the addition operation in quantum computing can be improved.

Description

Technical Field

[0001] This application belongs to the field of quantum computing technology, specifically a quantum adder, a computation method, and related devices. Background Technology

[0002] With the rapid development of quantum computing, the number of qubits required is also increasing. Due to the difficulty of integrating qubits, multiple small-qubit chips need to be connected to form large-qubit chips to achieve large-scale quantum computing, thereby promoting the development of quantum computing.

[0003] For large-scale chips composed of small-bit chips, entanglement operations between these chips are necessary, making a quantum / classical hybrid channel indispensable. A currently popular approach is teleportation to achieve entanglement. Executing quantum algorithms on a teleportation-integrated chip requires distributing the algorithm across the individual small-bit chips to achieve distributed processing. Specifically, this can be achieved as follows: Figure 1 As shown, each small-bit chip implements teleportation via EPR (an acronym for Einstein, Podolsky, and Rosen). The teleportation operation is highly complex; the time required to perform one teleportation operation is comparable to the time required to perform thousands of quantum logic gate operations.

[0004] Currently, distributed adders are achieved by splitting quantum circuits, with each sub-circuit operating on a small bit chip. The splitting of quantum circuits also decomposes the multi-bit quantum logic gates that operate on the two sub-circuits. After decomposition, the multi-bit quantum logic gates are located on different small bit chips. In order to realize the addition function, many teleportation operations are required, and a large number of teleportation operations will seriously affect the efficiency of addition in quantum computing. Summary of the Invention

[0005] The purpose of this application is to provide a quantum adder, a computation method, and related devices, which aim to improve the computational efficiency of addition in quantum computing.

[0006] One embodiment of this application provides a quantum adder, which includes multiple chips connected via an EPR module. One chip processes a data segment, the data segment including an addend segment and an augend segment. The chip includes:

[0007] The addition module is used to obtain the addition result and carry information of data segments based on quantum Fourier transform.

[0008] A loading module is used to load the carry information transmitted through the EPR module onto the addition result and carry information obtained by the chip based on the addition module, so as to update the addition result and carry information of the chip;

[0009] The inverse quantum Fourier transform module is used to convert the latest addition result into a binary string.

[0010] Optionally, the addition module operates on the first, second, and third qubits in the chip, wherein the first qubit is a qubit in the chip allocated for the addend segment, the second qubit is a qubit in the chip allocated for the addend segment, and the third qubit is a qubit in the chip allocated for storing carry information.

[0011] Optionally, the EPR module operates on the third and fourth qubits of one chip, and the fourth and fifth qubits of another chip, wherein the fourth qubit is a qubit allocated in the chip for generating EPR pairs, and the fifth qubit is a qubit allocated in the chip for receiving carry information updated by other chips.

[0012] Optionally, the loading module is used to load the received carry information as the least significant bit data of the addition result onto the phase of the quantum state corresponding to the second and third qubits of the chip, wherein the second qubit stores the addition result.

[0013] Optionally, the quantum adder further includes an inverse EPR module for setting the fifth qubit in the chip to the |0> state.

[0014] Optionally, the quantum adder further includes a zero-return module for setting the third and / or fifth qubits in a specific chip to the |0> state without changing the addition result of the data segment of that specific chip.

[0015] Another embodiment of this application provides a calculation method, the method comprising:

[0016] Process the data to be added to obtain data segments;

[0017] Using any of the quantum adders described above, obtain a binary string representing the addition result of each data segment;

[0018] Based on all binary strings, generate the result of the operation on the data to be added.

[0019] Optionally, the method further includes:

[0020] When all binary strings are obtained, the zero-return module in the specific chip is executed sequentially according to the data segment sequence number from high to low.

[0021] Another embodiment of this application provides a computing device, the device comprising:

[0022] The processing module is used to process the data to be added and obtain data segments;

[0023] The module is used to obtain a binary string representing the addition result of each data segment using the quantum adder described in any of the above.

[0024] The generation module is used to generate the operation result of the data to be added based on all binary strings.

[0025] One embodiment of this application provides a storage medium storing a computer program, wherein the computer program is configured to implement the quantum adder and / or the arithmetic method described in any of the preceding claims when running.

[0026] One embodiment of this application provides a computer device including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to implement the quantum adder and / or the arithmetic method described in any of the preceding claims.

[0027] Compared with existing technologies, this application provides a quantum adder comprising multiple chips connected via an EPR module. Each chip processes a data segment, which includes an addend segment and an augend segment. Each chip includes an addition module for obtaining the addition result and carry information of the data segment based on a quantum Fourier transform; a loading module for loading the carry information transmitted through the EPR module onto the addition result and carry information obtained by the chip based on the addition module, thereby updating the chip's addition result and carry information; and an inverse quantum Fourier transform module for converting the latest addition result into a binary string. In this application, one chip processes one data segment, and no carry is required within a single chip. Carry information is transmitted via the EPR module, eliminating the need to further decompose the quantum circuit. This significantly reduces the decomposition of quantum logic gates, thereby greatly reducing the number of teleportation operations and thus reducing the time required for addition operations, improving the efficiency of addition operations in quantum computing. Attached Figure Description

[0028] Figure 1 A schematic diagram of a distributed structure for running a quantum algorithm provided in this application;

[0029] Figure 2A network block diagram of a quantum computing system for implementing a quantum adder, provided in an embodiment of this application;

[0030] Figure 3 A schematic diagram of a quantum adder provided in an embodiment of this application;

[0031] Figure 4 A schematic diagram of a quantum circuit for QFTA provided in an embodiment of this application;

[0032] Figure 5 A schematic diagram of another quantum circuit for QFTA provided in an embodiment of this application;

[0033] Figure 6 A schematic diagram of a quantum circuit for a quantum adder provided in an embodiment of this application;

[0034] Figure 7 A schematic diagram of the quantum circuit of another quantum adder provided in an embodiment of this application;

[0035] Figure 8 A flowchart illustrating a calculation method provided in an embodiment of this application;

[0036] Figure 9 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application;

[0037] Figure 10 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0038] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, in order to help those skilled in the art better understand the implementation of this application, and should not be construed as limiting this application.

[0039] In the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not limit the implementation process of the embodiments of this application in any way. It should be noted that unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps described in these embodiments do not limit the scope of this application. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this application or its application or use.

[0040] Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0041] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0042] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0043] Figure 2 This is a network block diagram of a quantum computing system for implementing a quantum adder, provided in an embodiment of this application. The quantum computing system may include a network 110, a server 130, a wireless device 130, a client 140, a storage unit 150, a classical processing system 160, a quantum processing system 170, and may also include additional memory, a classical processor, a quantum processor, and other devices not shown.

[0044] Network 110 is a medium used to provide communication links between various devices and computers connected together within a quantum computing system, including but not limited to the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof. The connection method can be wired, wireless communication links, or fiber optic cables.

[0045] Server 130 and client 140 are conventional data processing systems that may contain data and application programs or software tools that perform conventional computational processes. Client 140 may be a personal computer or a network computer, so the data may also be provided by server 130. Wireless device 130 may be a smartphone, tablet, laptop, smart wearable device, etc. Storage unit 150 may include database 151, which can be configured to store data such as qubit parameters, quantum logic gate parameters, quantum circuits, and quantum programs.

[0046] The classical processing system 160 (quantum processing system 170) may include a classical processor 161 (quantum processor 171) for processing classical data (quantum data) and a memory 163 (memory 172) for storing classical data (quantum data). The classical data (quantum data) may be a boot file, an operating system image, and an application program 162 (application program 173). The application program 162 (application program 173) may be used to implement the quantum adder provided according to the embodiments of this application.

[0047] Any data or information stored or generated in the classical processing system 160 (quantum processing system 170) can also be configured to be stored or generated in another classical (quantum) processing system in a similar manner, and any application executed therein can also be configured to be executed in another classical (quantum) processing system in a similar manner.

[0048] It should be noted that a true quantum computer has a hybrid structure, which includes at least... Figure 1 The system consists of two main parts: the classical processing system 160, which is responsible for performing classical calculations and control; and the quantum processing system 170, which is responsible for running quantum programs and thus realizing quantum computing.

[0049] The aforementioned classical processing system 160 and quantum processing system 170 can be integrated into a single device or distributed across two different devices. For example, the first device, including the classical processing system 160, runs a classical computer operating system that provides quantum application development tools and services, as well as the storage and network services required for quantum applications. Users develop quantum applications using the quantum application development tools and services on the second device and send the quantum program to the second device, including the quantum processing system 170, via the network services. The second device runs a quantum computer operating system, which parses the code of the quantum program and compiles it into instructions that can be recognized and executed by the quantum computer control system. The quantum processor 170 then implements the quantum algorithm corresponding to the quantum program based on these instructions.

[0050] In the classic silicon-based processing system 160, the units of the classic processor 161 are CMOS transistors. These computing units are not limited by time or coherence; that is, they are available at any time without time constraints. Furthermore, the number of these computing units in a silicon chip is sufficient; currently, a classic processor contains tens of thousands of computing units. The sufficient number of computing units and the fixed selectable computing logic of the CMOS transistors, such as AND logic, allow for computational efficiency through a combination of numerous CMOS transistors and limited logic functions.

[0051] Unlike the logic units in the classical processing system 160, the basic computational unit of the quantum processor 171 in the quantum processing system 170 is the qubit. The input of a qubit is limited by coherence and coherence time; that is, a qubit is limited by its available usage time and is not always readily available. Making full use of qubits within their available usage time is a key challenge in quantum computing. Furthermore, the number of qubits in a quantum computer is one of the representative indicators of its performance. Each qubit performs computational functions through on-demand configured logic functions. Given the limited number of qubits and the diverse logic functions available in quantum computing, such as Hadamard gates (H gates), Pauli-X gates (X gates), Pauli-Y gates (Y gates), Pauli-Z gates (Z gates), X gates, RY gates, RZ gates, CNOT gates, CR gates, iSWAP gates, Tofoli gates, etc., quantum computing requires combining a limited number of qubits with diverse logic function combinations to achieve computational effects.

[0052] Based on these differences, the design of logical functions applied to qubits (including the design of whether qubits are used and the design of the efficiency of each qubit's use) is crucial for improving the computational performance of quantum computers and requires specialized design. The aforementioned design considerations for qubits are technical problems that ordinary computing devices do not need to address. Therefore, this application proposes a quantum adder, a computation method, and related devices to improve the efficiency of addition operations in quantum computing.

[0053] See Figure 3 , Figure 3 This is a schematic diagram of a quantum adder provided in an embodiment of this application. The quantum adder 300 includes multiple chips 301 connected through an EPR module 302. Each chip 301 is used to process a data segment, which includes an addend segment and an augend segment. The chip 301 includes:

[0054] The addition module 3011 is used to obtain the addition result and carry information of data segments based on quantum Fourier transform;

[0055] The loading module 3012 is used to load the carry information transmitted through the EPR module 302 onto the chip 301 based on the addition result and carry information obtained by the addition module 3011, so as to update the addition result and carry information of the chip 301;

[0056] The inverse quantum Fourier transform module 3013 is used to convert the latest addition result into a binary string.

[0057] A quantum adder is used to calculate the sum of data to be added. Data segments are obtained by processing the data to be added, which includes the addend and the augend. This data can be in binary form. Dividing the binary data string into segments yields the corresponding sub-segments. Based on the number of qubits in the chip, the augend b can be divided into b sub-segments. t b t-1 …b 0 Divide the addend a into a t a t -1 …a 0 A data segment includes an addend segment b. t A segment a with an addend t The length of a data segment is determined by the number of qubits in the chip. Different data segments can have different lengths depending on the number of qubits. Both the addend and the augend segments can be numbered in ascending order of bit depth. For example, if the addend b = 011110, and is processed into 3 data segments, then b... 3 =01, b 2 =11, b 1 =10, b 1 Divide the least significant addend into segments, b 2 Compared to b 1 The high-order addend is segmented, b 3 The most significant bit of the augend is segmented, and the sequence number of a data segment is determined by the numbers of the addend and augend segments. One chip processes one data segment, i.e., it is used to calculate the addition of one data segment. The data segments are stored in qubits on the chip, so that addition between them will not introduce teleportation operations. Additionally, the storage of a... t and storage b t The number of bits can be equal, or in certain cases, unequal.

[0058] Adder module 3011 can be used in a quantum Fourier transform (QFT) adder to implement a t +b t The module. A quantum circuit of QFTA (QFT adder) can be like... Figure 4 As shown, anc is the qubit storing carry information, b0-b m It is a qubit that stores segments of the addend, a0-a m These are qubits storing the addend segments. Specifically, the phase of the addend segments, which are stored as binary strings, is transformed into the phase of the quantum state using a QFT module, and then passed through multiple controlled R gates (R1...R...). mThe R-gate module, composed of [variable name], implements the addition operation between the addend segment and the augend segment in phase. QFT + The inverse quantum Fourier transform (IFT) is used to transform the result of data segmentation operations back into a binary string. The adder module 3011 can consist of a QFT module and an R-gate module. In fact, the QFT module in the QFT adder can be swapped out; in this case, only the target bit of the controlled R-gate needs to be swapped, and the quantum circuit can then... Figure 5 As shown, QFTs represent QFT modules without swap. Figure 5 The adder shown is still a QFTA.

[0059] The EPR module 302 transmits carry information from one chip to another; specifically, it transmits carry information from one chip to the chip that processes adjacent high-order data segments. Upon receiving the carry information, the loading module 3012 of the chip processing the high-order data segments loads the carry information onto its own addition result obtained through the addition module 3011 and the carry information to achieve upward carry. It should be noted that the chip processing the least significant data segment does not receive carry information, and therefore its loading module 3012 is not executed in practice. In the quantum circuit of the quantum adder 300, this means that the quantum circuit corresponding to that chip does not have a loading module 3012.

[0060] QFT + Module 3013 is used to convert the latest addition result. For chips that process the least significant bit data segmentation, the addition result obtained by the addition module 3011 is the latest addition result. The addition result obtained by other chips using the addition module 3011 is not the latest addition result because it needs to be updated with the received carry information. The addition result updated by the loading module 3012 is the latest addition result.

[0061] The quantum adder provided in this application is a distributed quantum adder. One chip performs addition operations on a data segment, and an EPR module is used between different chips to transmit carry information, enabling distributed processing of data segments. The data to be processed is segmented according to the processing capabilities of the chips, eliminating the need to further decompose the quantum circuits. This significantly reduces the decomposition of quantum logic gates, thereby greatly reducing the number of teleportation operations and ultimately decreasing the time required for addition operations, thus improving the efficiency of addition operations in quantum computing.

[0062] In this application, the addition module 3011 can be executed in parallel. When the addition modules 3011 of all chips have finished executing, the chip processing the least significant bit data segment transmits the carry information to the chip processing the next higher bit data segment through the EPR module 302. This chip then executes the loading module 3012 and QFT. + Module 3013 then executes EPR module 302, and so on, until the chip processing the highest bit data segment completes the QFT. + Module 3013.

[0063] Furthermore, the quantum adder provided in this application does not require carry operations on the chip, which improves the utilization rate of qubits and allows a single chip to process more data. Therefore, fewer chips are needed to process the same order of magnitude of data. The reduced number of chips also reduces teleportation operations, thus saving computational resources and shortening the addition operation time, thereby improving the efficiency of addition operations in quantum computing.

[0064] In some embodiments of this application, the addition module 3011 can operate on a first qubit, a second qubit, and a third qubit in the chip, wherein the first qubit is a qubit in the chip allocated for the addend segment, the second qubit is a qubit in the chip allocated for the addend segment, and the third qubit is a qubit in the chip allocated for storing carry information.

[0065] In this embodiment, for each chip, the first qubit is used to store the addend segment, specifically the quantum state of the addend segment. The second qubit is used to store the augend segment. After the addend result is obtained using the addend module 3021, the second qubit is used to store the addend result. The addend result referred to here is the result of adding the augend segment and the addend segment without carrying. The first qubit and the second qubit may include more than one qubit, and the specific number is determined by the length of the augend segment or the addend segment.

[0066] In some possible embodiments of this application, the EPR module 302 can operate on the third and fourth qubits of one chip, and the fourth and fifth qubits of another chip, wherein the fourth qubit is a qubit allocated in the chip for generating EPR pairs, and the fifth qubit is a qubit allocated in the chip for receiving carry information updated by other chips. In some embodiments, the EPR module 302 can utilize CNOT gates to transmit carry information.

[0067] To achieve quantum teleportation, at least one qubit needs to be allocated in each chip to generate EPR pairs. A fourth qubit between two chips can also generate EPR pairs. EPR module 302 implements entanglement between the third qubit on one chip and the fifth qubit on another chip, transferring the carry information from the third qubit in one chip to the fifth qubit in the other chip via teleportation. It should be noted that the chip processing the least significant bit data segment does not allocate a fifth qubit.

[0068] In some possible embodiments of this application, the loading module 3012 is used to load the received carry information as the least significant bit data of the addition result onto the phase of the quantum state corresponding to the second and third qubits of the chip, wherein the second qubit stores the addition result.

[0069] For example, if the carry information received by chip 3 is 1, the addition result obtained by chip 3 using the addition module 3011 is 1010. After processing the carry information using the loading module 3012, the addition result stored in the second qubit of chip 3 becomes 1011, while the quantum state of the third qubit remains unchanged. If the carry information received by chip 3 is 1, the addition result obtained by chip 3 using the addition module 3011 is 1111. After processing the carry information using the loading module 3012, the addition result stored in the second qubit of chip 3 becomes 0000, and the carry information of the third qubit changes from 0 to 1. In some embodiments, the loading module 3012 can be implemented using a controlled R-gate.

[0070] In some possible embodiments of this application, the quantum adder further includes an inverse EPR module for setting the fifth qubit in the chip to the |0> state.

[0071] The inverse EPR module operates on the same qubit as the EPR module 302. The inverse EPR module is the inverse operation of the EPR module 302, which sets the fifth qubit in the chip to the |0> state.

[0072] When a quantum adder includes an inverse EPR module, the quantum circuitry of a quantum adder can be as follows: Figure 6 As shown, the chip that processes the least significant bit of the data segment does not need to receive carry information, thus eliminating the need for further processing by the loading module 3012. Therefore, this chip can directly use QFTA to process data segments. (QFTA is shown in the figure.) 1 It is stated that QFTA 2- and QFTA t- This indicates that QFT is not included. + The module's QFTA, R indicates loading module 3012, anc i Anc represents the third quantum bit in the i-th chip.i0 This represents the fifth qubit in the i-th chip. When there are relatively few chips, teleportation time can be reduced by returning only the fifth qubit to zero.

[0073] In some possible embodiments of this application, the quantum adder further includes a zero-return module for setting the third and / or fifth qubits in a specific chip to the |0> state without changing the addition result of the data segment of that specific chip.

[0074] The specific chip refers to any chip used in a quantum adder, excluding the chip that processes the highest-order bit data segment. From, for example... Figure 7 The quantum circuit of another quantum adder shown can be used to deduce that the zero-return module can contain multiple functions, and the specific structure will vary depending on the chip on which the zero-return module is used. Figure 7 The functions implemented by the modules within the two dashed boxes are reversible. Chips 2 to t-1 contain the same zero-return module. The zero-return module in chip 1 will... The module will return the third quantum bit in chip 1 to zero. The module is a QFTA that operates on the first, second, and third qubits in chip 1. 1 The inverse operation of the module, then through QFTA applied to the first and second qubits. 1 The module implements the addition of data segments, ensuring that measuring the second qubit yields the binary string of the addition result. In the zero-return modules between chips 2 and t-1, unit 1 is used to achieve zero-return for the third qubit, unit 2 is used to implement the addition of data segments to obtain the corresponding binary string, and the inverse EPR module operating between the two chips is used for zero-return for the fifth qubit.

[0075] This application provides a quantum adder, which includes multiple chips connected via an EPR module. Each chip processes a data segment, which includes an addend segment and an augend segment. Each chip includes an addition module for obtaining the addition result and carry information of the data segment based on a quantum Fourier transform; a loading module for loading the carry information transmitted through the EPR module onto the addition result and carry information obtained by the chip based on the addition module, thereby updating the chip's addition result and carry information; and an inverse quantum Fourier transform module for converting the latest addition result into a binary string. In this application, one chip processes one data segment, and the length of the data segment is determined by the number of qubits in the chip. No carry is required within a single chip; carry information is transmitted via the EPR module, eliminating the need to further decompose the quantum circuit. This significantly reduces the decomposition of quantum logic gates, thereby greatly reducing the number of teleportation operations and ultimately reducing the time required for addition operations, thus improving the efficiency of addition operations in quantum computing.

[0076] See Figure 8 , Figure 8 A calculation method provided in this application embodiment includes:

[0077] S801: Process the data to be added to obtain data segments;

[0078] S802: Using the quantum adder described in any of the above embodiments, obtain a binary string representing the addition result of each data segment;

[0079] S803: Based on all binary strings, generate the result of the operation of the data to be added.

[0080] In this application embodiment, one chip is allocated for each data segment. When processing data segments using the quantum adder provided in any of the above embodiments of this application, for each data segment, the addition module in the corresponding chip is used to perform the operation to obtain the addition result and carry information. Chips 1-t respectively correspond to processing data segments 1-t. When chip 1 performs QFT... + After the module, the carry information is transmitted to chip 2 through the EPR module between chip 1 and chip 2. Chip 2 processes the received carry information using the loading module, and then executes the QFT in chip 2. + Module, get b 2 b 1 +a 2 a 1 The result is that the updated carry information from chip 2 is then transmitted to chip 3, and this process continues until chip t performs a QFT. +The module measures the updated carry information in chip t and the second qubits of all chips to obtain the carry information and a binary string. The binary string is sorted according to the sequence number of the data segments. The highest bit of the sorted binary string is the measured carry information, thus obtaining the operation result. For example, the quantum adder contains three chips. Chip 3 measures a carry of 0, chip 1 measures a binary string of 001, chip 2 measures a binary string of 101, and chip 3 measures a binary string of 010, resulting in a binary string of 010101001. This binary string can be directly used as the result of the addend and augend, or it can be converted to decimal and used as the result. Other methods are also possible, but will not be elaborated upon here.

[0081] In some possible implementations of this application, when all binary strings are obtained, the zero-return module in a specific chip is executed sequentially according to the data segment sequence number from high to low.

[0082] For specific implementation methods, please refer to the above embodiments, which will not be described in detail here.

[0083] See Figure 9 , Figure 9 This is a schematic diagram of a computing device provided in an embodiment of this application. The device includes:

[0084] Processing module 901 is used to process the data to be added and obtain data segments;

[0085] The module 902 is used to obtain a binary string representing the addition result of each data segment using the quantum adder described in any of the above embodiments;

[0086] The generation module 903 is used to generate the operation result of the data to be added based on all binary strings.

[0087] Please see Figure 10 This application also provides a computer device, including a memory and a processor. The memory stores a computer program, and the processor is configured to run the computer program to implement the quantum adder and / or the arithmetic method described in any of the above embodiments. Please refer to... Figure 10 The computer device can be a classical computer or a quantum computer.

[0088] This application also provides a storage medium storing a computer program, wherein the computer program is configured to implement the quantum adder and / or the operation method described in any of the above embodiments when running.

[0089] This application also provides a computer program product containing instructions that, when executed by a computer, cause the computer to implement the quantum adder and / or the arithmetic method described in any of the above embodiments.

[0090] It is understood that the various implementation methods described in this application can be implemented individually or in combination, and the implementation methods in this application are not limited in this respect.

[0091] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0092] It is understood that the processor in the embodiments of this application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method embodiments can be completed by the integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0093] It is understood that the memory in the embodiments of this application may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Specifically, non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM). It should be noted that the memory in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0094] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0095] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the aforementioned method implementations, and will not be repeated here.

[0096] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0097] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

Claims

1. A quantum adder, characterized in that, The quantum adder includes multiple chips connected via an EPR module. Each chip processes a data segment, which includes an addend segment and an augend segment. The EPR module transmits a carry information from one chip to a chip that processes adjacent high-order data segments. Each chip includes: The addition module is used to obtain the addition result and carry information of data segments based on quantum Fourier transform. The loading module is used to load the carry information transmitted through the EPR module onto the addition result and carry information obtained by itself based on the addition module, so as to update the addition result and carry information of the chip. The chip that processes the least significant bit data segment does not receive carry information. The inverse quantum Fourier transform module is used to convert the latest addition result into a binary string.

2. The quantum adder according to claim 1, characterized in that, The addition module operates on the first, second, and third qubits in the chip. The first qubit is a qubit allocated in the chip for the addend segment, the second qubit is a qubit allocated in the chip for the addend segment, and the third qubit is a qubit allocated in the chip for storing carry information. The specific number of the first and second qubits is determined by the length of the addend segment or the addend segment.

3. The quantum adder according to claim 2, characterized in that, The EPR module operates on the third and fourth qubits of one chip, and the fourth and fifth qubits of another chip. The fourth qubit is a qubit allocated in the chip for generating EPR pairs, and the fifth qubit is a qubit allocated in the chip for receiving carry information updated by other chips.

4. The quantum adder according to claim 3, characterized in that, The loading module is used to load the received carry information onto the phase of the quantum state corresponding to the second and third qubits of the chip, wherein the second qubit stores the addition result.

5. The quantum adder according to claim 4, characterized in that, The quantum adder also includes an inverse Module used to set the fifth quantum bit in the chip to state.

6. The quantum adder according to claim 4, characterized in that, The quantum adder also includes a zero-return module for setting the third and / or fifth qubits in a specific chip to zero. The state is maintained without changing the addition result of the data segment of the specific chip, wherein the specific chip is any chip of the quantum adder except the chip that processes the highest bit data segment.

7. A calculation method, characterized in that, The method includes: Process the data to be added to obtain data segments; Using the quantum adder according to any one of claims 1-6, a binary string representing the addition result of each data segment is obtained; Based on all binary strings, generate the result of the operation on the data to be added.

8. The method according to claim 7, characterized in that, The method further includes: When all binary strings are obtained, the zero-return modules in a specific chip are executed sequentially according to the data segment number from high to low. The specific chip is any chip in the quantum adder except the chip that processes the highest bit data segment.

9. A computing device, characterized in that, The device includes: The processing module is used to process the data to be added and obtain data segments; The module is configured to obtain a binary string representing the addition result of each data segment using the quantum adder according to any one of claims 1-6; The generation module is used to generate the operation result of the data to be added based on all binary strings.

10. A storage medium, characterized in that, The storage medium stores a computer program, wherein the computer program is configured to implement the quantum adder according to any one of claims 1-6 and / or the method according to claim 7 or 8 when it is run.

11. A computer device, comprising a memory and a processor, characterized in that, The memory stores a computer program, and the processor is configured to run the computer program to implement the quantum adder of any one of claims 1-6 and / or the method of claim 7 or 8.

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