Voltage-sharing control method and controller for three-level circuit converter

Abstract

The invention is suitable for the technical field of electric energy conversion, and provides a voltage-sharing control method of a three-level circuit converter and a controller. The method comprises the following steps: acquiring average values of half-bus bias voltage and inductive current of a current switching period and a previous switching period of the three-level circuit converter; determining a duty ratio compensation amount based on the half-bus bias voltage of the current switching period; judging a corresponding compensation direction, a target compensation tube and an integral parameter for eliminating a static error based on the average values of the half-bus bias voltage and the inductive current of the current switching period and the previous switching period; and performing voltage-sharing control on the target compensation tube based on the duty ratio compensation amount, the compensation direction, the target compensation tube and the integral parameter for eliminating the static error so as to perform voltage correction. According to the method provided by the invention, the repeated debugging work of debugging personnel on the grading ring parameters due to the change of the equipment application scene can be avoided, the rectification speed and precision are improved, and the output voltage and current control precision is improved.

Description

Technical Field

[0001] The present application belongs to the technical field of electric energy conversion, and in particular, relates to a voltage equalization control method and a controller for a three-level circuit converter. Background Art

[0002] Converters, such as DC-DC converters and DC-AC converters, are mainly used to convert one form of electrical energy into another form of electrical energy, which may involve changes in electrical parameters such as voltage, current, frequency, number of phases or power factor. The control circuit of the converter includes but is not limited to open-loop control and closed-loop control. Open-loop control circuits are usually used in situations where output accuracy is not required. Their control strategies are relatively simple and do not rely on output feedback. Closed-loop control circuits, on the other hand, achieve precise control and adjustment of output parameters by introducing output feedback signals, and are widely used in power electronic equipment that require high accuracy, high stability and dynamic response.

[0003] In three-level circuit converters and other related equipment, the voltage balancing problem of the voltage-dividing capacitor is a key problem that must be solved. Ideally, the voltage-dividing capacitor should maintain voltage balance and be half of the output voltage value. However, in actual circuits, since the driving circuit of the switch tube and the switching characteristics of the switch tube cannot be exactly the same, the duty cycle of the two switch tubes will inevitably be different, which will cause the energy provided by the two voltage-dividing capacitors in one cycle to be impossible to be completely equal, resulting in the problem of uneven voltage of the voltage-dividing capacitors. Therefore, it is necessary to use voltage balancing control technology to solve this problem.

[0004] In the existing three-level circuit converter voltage balancing control technology, the voltage balancing loop usually uses a PI controller with fixed control parameters. In order to avoid overshoot oscillation, the proportional parameters are usually selected to be small when the parameters are fixed. The control speed is relatively slow during power conversion. When the power is switched quickly, the transition process in the string device may cause uneven current faults, making the equipment unable to operate normally. Some designs do not have integral parameters, resulting in static errors in the half-bus voltage, causing certain ripples in the output voltage and current, and reducing the output power performance. In designs that include integral parameters, the debugging of integral parameters is often related to the hardware specifications and application conditions of the equipment. If the integral link is too strong, it will cause response lag, and even trigger equipment failure and control instability. If the integral link is too weak, it will reduce the dynamic response speed, which requires the experience of the debugging personnel. Improper debugging can easily cause bias voltage, making the equipment unable to operate normally. Summary of the invention

[0005] In order to overcome the problems existing in the related technology, the embodiment of the present application provides a voltage equalization control method and controller for a three-level circuit converter, which can avoid the debugging personnel from repeatedly debugging the voltage equalization ring parameters due to changes in the equipment application scenario, improve the correction speed and accuracy, and improve the output voltage and current control accuracy.

[0006] This application is implemented through the following technical solutions: In a first aspect, an embodiment of the present application provides a voltage balancing control method for a three-level circuit converter, comprising: Obtaining a half bus bias voltage of a current switching cycle of a three-level circuit converter, an average value of an inductor current of the current switching cycle, a half bus bias voltage of a previous switching cycle, and an average value of an inductor current of a previous switching cycle; Determine a duty cycle compensation amount based on a half bus bias voltage of a current switching cycle; Based on the half bus bias of the current switching cycle, the average value of the inductor current of the current switching cycle, the half bus bias of the previous switching cycle and the average value of the inductor current of the previous switching cycle, the corresponding compensation direction, the target compensation tube and the integral parameter for eliminating static error are determined; Based on the duty cycle compensation amount, compensation direction, target compensation tube and integral parameters for eliminating static error, the target compensation tube is subjected to voltage equalization control to perform voltage correction.

[0007] In a possible implementation manner of the first aspect, determining a duty cycle compensation amount based on a half bus bias of a current switching cycle includes: Determine the conversion relationship between the duty cycle compensation amount and time based on the carrier cycle value and the switching frequency of the time reference module of the three-level circuit converter; The duty cycle compensation amount is determined based on the conversion relationship between the half bus bias voltage and the duty cycle compensation amount and time in the current switching cycle.

[0008] In a possible implementation of the first aspect, the duty cycle compensation amount It is expressed as:

[0009] in, is the absolute value of the half bus bias voltage of the current switching cycle; is the half bus capacitance value; is the switching frequency; is the carrier period value of the time reference module of the three-level circuit converter; is the average value of the inductor current in the current switching cycle.

[0010] In a possible implementation manner of the first aspect, after determining the duty cycle compensation amount based on the half bus bias of the current switching cycle, the voltage sharing control method of the three-level circuit converter further includes: A preset value of a maximum adjustment bias voltage in a single switching cycle is set, and a limit value of a duty cycle compensation amount is determined based on the preset value of the maximum adjustment bias voltage in a single switching cycle; the limit value of the duty cycle compensation amount is used to limit the duty cycle compensation amount; wherein, when the average value of the inductor current in the current switching cycle is less than 2A, the limit value of the duty cycle compensation amount is 0; The duty cycle compensation amount is updated based on the limit value of the duty cycle compensation amount to obtain an updated duty cycle compensation amount.

[0011] In a possible implementation manner of the first aspect, the corresponding compensation direction, the target compensation tube, and the integral parameter for eliminating static error are determined based on the half-bus bias of the current switching cycle, the average value of the inductor current of the current switching cycle, the half-bus bias of the previous switching cycle, and the average value of the inductor current of the previous switching cycle, including: Determine a change trend of the half bus bias based on the half bus bias of the current switching cycle and the half bus bias of the previous switching cycle; Determine a change trend of the inductor current based on an average value of the inductor current in a current switching cycle and an average value of the inductor current in a previous switching cycle; Determine the compensation direction based on the change trend of the half-bus bias voltage and the change trend of the inductor current; Determine the target compensation tube in the compensation direction; For the target compensation tube, determine the corresponding integral parameter for eliminating static error.

[0012] In a possible implementation manner of the first aspect, determining a corresponding integral parameter for eliminating static error includes: Determining a rate of change of the inductor current based on an average value of the inductor current in a current switching cycle and an average value of the inductor current in a previous switching cycle; Based on the rate of change of the inductor current and the half bus bias voltage of the current switching cycle, an integral parameter for eliminating static error is determined.

[0013] In a possible implementation of the first aspect, the rate of change of the inductor current is It is expressed as:

[0014] in, is the average value of the inductor current in the current switching cycle; is the average value of the inductor current in the previous switching cycle; is the switching frequency; Integral parameters to eliminate static errors It is expressed as:

[0015] in, is the initial integration parameter, ; k is the current switching cycle; is the half bus bias voltage of the current switching cycle; t For time.

[0016] In a possible implementation manner of the first aspect, the voltage sharing control method of the three-level circuit converter further includes: In the commutation process of voltage-equalizing control of the target compensation tube, the commutation digital logic is set; the commutation digital logic includes clearing the integral parameter for eliminating static error when the positive or negative polarity of a single quantity in the average value of the half-bus bias or the inductor current changes between the current moment and the previous moment.

[0017] In a possible implementation manner of the first aspect, obtaining an average value of a half bus bias voltage of a current switching cycle of a three-level circuit converter and an average value of an inductor current of a current switching cycle includes: Obtaining a capacitance value of a half busbar of a three-level circuit converter in a current switching cycle and an inductor current in a current switching cycle; Based on the inductor current of the current switching cycle, determining an average value of the inductor current of the current switching cycle; A half bus bias voltage of the current switching cycle is determined based on the capacitance value of the current switching cycle and the inductor current of the current switching cycle.

[0018] In a second aspect, the present application provides a controller, which is used to execute the voltage balancing control method of the three-level circuit converter as described in the first aspect.

[0019] It can be understood that the beneficial effects of the second aspect mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here.

[0020] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: In the embodiment of the present application, the integral parameter for eliminating static error is determined based on the average value of the half-bus bias and the inductor current of the current and previous switching cycles. This dynamic adjustment based on real-time data can avoid response lag and control instability caused by an overly strong integral link, and also reduce the problem of reduced dynamic response speed caused by a too weak integral, thereby avoiding the lack of reliance on personnel experience during the debugging process and reducing the risk of bias and equipment failure caused by improper debugging. In addition, based on the data of the current and previous switching cycles to determine the compensation direction, target compensation tube, and duty cycle compensation amount, and to perform voltage equalization control on the compensation tube, it is possible to ensure the accuracy and timeliness of compensation, thereby effectively performing voltage correction, effectively solving the problem caused by an integral link that is too strong or too weak, reducing the workload of equipment later maintenance and technical support, reducing output voltage and current ripple, improving output control accuracy, and also improving the overall performance and stability of the system, providing a strong guarantee for the normal operation of the equipment.

[0021] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0023] Figure 1 1 is a flow chart of a voltage balancing control method for a three-level circuit converter provided in an embodiment of the present application; Figure 2 It is a topological diagram of a single-channel bidirectional DC converter provided in one embodiment of the present application; Figure 3 is a block diagram of a voltage balancing ring provided in an embodiment of the present application; Figure 4 It is a schematic diagram of the relationship between the duty cycle compensation amount of the voltage balancing control and the output PWM waveform in the three-level phase-shifted wave generation mode provided in one embodiment of the present application; Figure 5 is a duty cycle compensation calculation block diagram provided by an embodiment of the present application; Figure 6 is a block diagram of a direction identification module provided in an embodiment of the present application; Figure 7 It is a schematic diagram of the structure of a controller provided in one embodiment of the present application. DETAILED DESCRIPTION

[0024] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0025] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0026] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0027] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0028] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0029] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0030] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0031] Figure 1 is a flow chart of a voltage balancing control method for a three-level circuit converter provided in an embodiment of the present application, with reference to Figure 1 The voltage balancing control method of the three-level circuit converter is described in detail as follows: The present application provides a method for controlling voltage sharing of a three-level circuit converter, the method comprising: Step 101, obtaining a half bus bias voltage of a current switching cycle of a three-level circuit converter, an average value of an inductor current of the current switching cycle, a half bus bias voltage of a previous switching cycle, and an average value of an inductor current of the previous switching cycle.

[0032] Exemplarily, half bus bias Refers to the difference between the half bus voltage at the input and output ends. Taking a single-channel bidirectional DC converter as an example, Figure 2 As shown, the half bus bias is the voltage of capacitor C2 minus the voltage of capacitor C1, and the average value of the inductor current in the current switching cycle is Refers to the average value of the current through the inductor L1 in the current switching cycle. Or half bus bias The voltage of capacitor C3 minus the voltage of capacitor C1, the average value of the inductor current in the current switching cycle Refers to the average value of the current passing through the inductor L2 in the current switching cycle.

[0033] Step 102, determining a duty cycle compensation amount based on a half bus bias voltage of a current switching cycle.

[0034] For example, Figure 3 The block diagram of the voltage balancing loop is shown in Figure 1. The voltage balancing loop includes a compensation calculation module and a direction detection module. The compensation calculation module obtains the half bus bias voltage of the current switching cycle. Determine the amount of duty cycle compensation , the compensation calculation module calculates the duty cycle compensation Passed to the identification module.

[0035] Step 103, based on the half bus bias of the current switching cycle, the average value of the inductor current of the current switching cycle, the half bus bias of the previous switching cycle and the average value of the inductor current of the previous switching cycle, determine the corresponding compensation direction, the target compensation tube and the integral parameter for eliminating static error.

[0036] For example, k represents the current switching cycle, then k -1 indicates the last switching cycle, such as Figure 3 As shown, the direction detection module determines the half bus bias voltage of the current switching cycle. , the average value of the inductor current in the current switching cycle , half bus bias voltage of the previous switching cycle and the average value of the inductor current in the previous switching cycle Determine the changing trends of the bus voltage and the inductor current. According to the changing trends of the bus voltage and the inductor current, the current compensation direction and the switch tube that needs to be compensated can be determined. The corresponding compensation direction, the target compensation tube and the integral parameter for eliminating the static error can be determined, so that the corresponding duty cycle compensation value can be output to the target compensation tube to adjust the bias.

[0037] Step 104, based on the duty cycle compensation amount, the compensation direction, the target compensation tube and the integral parameter for eliminating static error, the target compensation tube is subjected to voltage equalization control to perform voltage correction.

[0038] For example, when the no-load / light-load voltage deviation is large, the inductor current increases and reaches the control threshold and control begins. According to the determined compensation direction (positive or negative) and the determined target compensation tube (G1, G2, G3 or G4), on the basis of the original duty cycle of the target compensation tube, voltage equalization control is performed according to the duty cycle compensation amount and the integral parameter for eliminating static error to perform voltage correction.

[0039] This embodiment determines the integral parameter for eliminating static error by taking the average value of the half-bus bias and the inductor current of the current and previous switching cycles. This dynamic adjustment based on real-time data can avoid response lag and control instability caused by an overly strong integral link, and also reduces the problem of reduced dynamic response speed caused by a too weak integral link, thereby avoiding the lack of reliance on personnel experience during the debugging process and reducing the risk of bias and equipment failure caused by improper debugging. In addition, based on the data of the current and previous switching cycles to determine the compensation direction, target compensation tube, and duty cycle compensation amount, and to perform voltage equalization control on the compensation tube, the accuracy and timeliness of compensation can be ensured, thereby effectively performing voltage correction and effectively solving the problem caused by an integral link that is too strong or too weak.

[0040] In one embodiment, a specific process of obtaining the half bus bias voltage of the current switching cycle of the three-level circuit converter and the average value of the inductor current of the current switching cycle is specifically introduced. Then, step 101 includes: First, obtain the capacitance value C of the half bus of the three-level circuit converter in the current switching cycle and the inductor current of the current switching cycle .

[0041] Then, based on the inductor current of the current switching cycle, , determine the average value of the inductor current in the current switching cycle .

[0042] For example, since the capacitor current cannot be sampled directly, the current loop , use the inductor current instead of the capacitor current in the calculation. Figure 4 The figure shows the relationship between the duty cycle compensation of the voltage-sharing control and the output PWM waveform under the three-level phase-shifting wave mode. In a single switching cycle, the sawtooth wave Figure 4 As shown in the figure, the shaded part of the compensation tube G2 PWM is the effective time of the voltage-balanced control. According to the effective time of the bias control, the rising edge and falling edge of CMP+DutyComp correspond to the peak value of the inductor current. t / 2 time. The inductor current acts near the valley value ∆ t / 2 time. It is approximately considered that the peak value acts on ∆ t / 2 time, the valley value acts on ∆ t / 2 time, that is Action time ∆t, that is .

[0043] Finally, based on the capacitance value C of the current switching cycle and the inductor current of the current switching cycle , determine the half bus bias voltage of the current switching cycle .

[0044] For example, since the half bus voltage control time is in microseconds, the inductor can be approximated as a constant current source, and the voltage deviation of a single switching cycle can be obtained according to the constant current source charging formula for the capacitor. , we can get the half bus bias voltage The expression is:

[0045] in, is the voltage-equalizing control time, C is the half-bus capacitor value, is the half bus capacitance current, t For time.

[0046] In one embodiment, see Figure 5 , introduces the specific process of determining the duty cycle compensation amount. Step 102 includes: Firstly, based on the carrier cycle value and the switching frequency of the time reference module of the three-level circuit converter, the conversion relationship between the duty cycle compensation amount and the time is determined.

[0047] Exemplarily, the conversion relationship between the duty cycle compensation amount and time is expressed as:

[0048] The duty cycle compensation amount is determined based on the conversion relationship between the half bus bias voltage and the duty cycle compensation amount and time in the current switching cycle.

[0049] Exemplarily, adjusting the half bus bias voltage Duty cycle compensation required It is expressed as:

[0050] in, is the absolute value of the half bus bias voltage of the current switching cycle; is half bus capacitance value; is the switching frequency; is the carrier period value of the time reference module of the three-level circuit converter; is the average value of the inductor current in the current switching cycle. The carrier period value of the TB (time base) module of the DSP TMS320F28335 chip can be selected.

[0051] In addition, to prevent calculation errors and overshoot, the duty cycle compensation amount Therefore, after determining the duty cycle compensation amount based on the half bus bias of the current switching cycle, the voltage balancing control method of the three-level circuit converter further includes: A preset value of a maximum adjustment bias voltage in a single switching cycle is set, and a limit value of a duty cycle compensation amount is determined based on the preset value of the maximum adjustment bias voltage in a single switching cycle; the limit value of the duty cycle compensation amount is used to limit the duty cycle compensation amount; the duty cycle compensation amount is updated based on the limit value of the duty cycle compensation amount to obtain an updated duty cycle compensation amount.

[0052] For example, the preset value of the maximum bias voltage adjustment in a single switching cycle is set to 10V. When , substitute into formula (3) to get the limit value of duty cycle compensation, and update after limit .

[0053] Among them, when the average value of the inductor current in the current switching cycle is less than 2A, the limit value of the duty cycle compensation is 0. When the inductor current is close to 0A under no-load / light load, the bias compensation error may be caused by the previous stage noise or sampling deviation. hour, ,otherwise DutyComp = DutyComp .

[0054] In one embodiment, see Figure 6 , specifically introduces the process of the direction identification module judging the corresponding compensation direction, the target compensation tube and the integral parameter for eliminating static error, step 103 includes: Determine the changing trend of the half-bus bias based on the half-bus bias of the current switching cycle and the half-bus bias of the previous switching cycle; determine the changing trend of the inductor current based on the average value of the inductor current of the current switching cycle and the average value of the inductor current of the previous switching cycle; determine the compensation direction based on the changing trend of the half-bus bias and the changing trend of the inductor current; determine the target compensation tube in the compensation direction; and determine the corresponding integral parameter for eliminating static error for the target compensation tube.

[0055] For example, the direction identification module mainly calculates the current cycle voltage equalization compensation direction, compensation tube, and control static error elimination based on the physical quantity of the current switching cycle combined with the physical quantity state of the previous switching cycle. , , last moment , The combined logic relationship determines the compensation direction and compensation switch tube.

[0056] For example, if the bus voltage drops and the inductor current increases, reactive power needs to be injected into the circuit, that is, the compensation direction is positive. If the bus voltage rises and the inductor current decreases, reactive power needs to be absorbed from the circuit, that is, the compensation direction is negative. According to the compensation direction, determine the switch tube that needs to be turned on or off. If the compensation direction is positive, reactive power needs to be injected into the circuit, and the upper group of switch tubes needs to be turned on to increase the inductor current. If the compensation direction is negative, reactive power needs to be absorbed from the circuit, and the lower group of switch tubes needs to be turned on to reduce the inductor current.

[0057] Among them, the corresponding integral parameters for eliminating static errors are determined, including: The change rate of the inductor current is determined based on an average value of the inductor current in the current switching cycle and an average value of the inductor current in the previous switching cycle.

[0058] For example, when eliminating static error, the half bus bias Introduce integration and judge the current steady state and transient state according to the rate of change of inductor current. Calculate the rate of change of inductor current. It is expressed as:

[0059] in, is the average value of the inductor current in the current switching cycle; is the average value of the inductor current in the previous switching cycle; is the switching frequency.

[0060] Next, an integral parameter for eliminating static error is determined based on the rate of change of the inductor current and the half bus bias of the current switching cycle.

[0061] like Figure 6 1 / S in the equation represents the half bus bias voltage of the current switching cycle. The integral parameter to eliminate static error It is expressed as:

[0062] in, is the initial integration parameter, ; k is the current switching cycle; is the half bus bias voltage of the current switching cycle; t is time. Integral compensation direction and duty cycle compensation amount Consistent, after entering steady state, half bus bias When it is small, it automatically recognizes and increases the integral ratio to reduce the static error in the steady state.

[0063] It should be noted that when determining the integral parameter to eliminate static error In the process of calculating the duty cycle, the duty cycle compensation amount still needs to be limited.

[0064] In addition, a special design is made for the commutation. When the no-load / light-load voltage deviation is large, the inductor current increases and reaches the control threshold to start control. The voltage lags behind the current, and there is a period of integral accumulation of the initial half-bus voltage bias. When the power is reversed, the response will lag due to the large hysteresis, which may cause compensation error direction; when the power is reversed, when the dominant position of the dominant tube remains unchanged, The positive and negative will change when the average value of the inductor current When the reverse threshold is reached, the initial value of the average value of the inductor current is the forward commutation error value, and the integral output needs to be cleared to increase the direction identification speed. Then, the voltage equalization control method of the three-level circuit converter also includes: During the commutation process of the target compensation tube for voltage equalization control, the commutation digital logic is set.

[0065] The commutation digital logic includes clearing the integral parameter for eliminating static error when the positive or negative polarity of a single quantity of the half-bus bias voltage or the average value of the inductor current changes between the current moment and the previous moment.

[0066] Exemplarily, based on determining the duty cycle compensation amount, compensation direction, target compensation tube and integral parameter for eliminating static error, the specific process of performing voltage equalization control on the target compensation tube is as follows: like The result of is 0, or , then: when When the target compensation tubes G2 and G3 are compensated: G2 duty cycle + DutyComp , G3 duty cycle - DutyCom - ; when When the target compensation tubes G2 and G3 are compensated: G2 duty cycle - DutyComp , G3 duty cycle + DutyCom + ; when When the target compensation tubes G2 and G3 are compensated: G2 duty cycle - DutyComp , G3 duty cycle + DutyCom + ; when When the target compensation tubes G2 and G3 are compensated: G2 duty cycle + DutyComp , G3 duty cycle - DutyCom - .

[0067] like The result of is 1, then there is : when When the target compensation tubes G2 and G3 are compensated: G2 duty cycle + DutyComp , G3 duty cycle - DutyCom ; when When the target compensation tubes G2 and G3 are compensated: G2 duty cycle - DutyComp , G3 duty cycle + DutyCom ; when When the target compensation tubes G2 and G3 are compensated: G2 duty cycle - DutyComp , G3 duty cycle + DutyCom ; when When the target compensation tubes G2 and G3 are compensated: G2 duty cycle + DutyComp , G3 duty cycle - DutyCom .

[0068] Among them, G1, G4 tubes and G2, G3 tubes complement each other in output, controlling the output duty cycle compensation value to correct the voltage of the corresponding switch tubes.

[0069] In order to make the technical solution of the present invention more clear, in a three-level circuit converter, a 3-sink 1-way bidirectional DC converter with a rated power of 50kW is taken as an example to specifically illustrate the specific implementation process of the technical solution of the present invention.

[0070] Figure 2 For the single-channel topology diagram, the relevant parameters are as follows: the inductance of inductor L1 is 424μH, the capacitance of half-bus capacitors C2 and C3 are both 1μf, the maximum current on the low-voltage side is 100A, the control cycle is 18kHz, and TBPRD=2083.

[0071] First, calculate the amplitude of the voltage-sharing control loop limiter module according to the circuit parameters. When the running direction is forward, the voltage-sharing loop selects the output limiter value. If the current on the low-voltage side is , select 10V / control cycle as the maximum voltage regulation capability, and reverse the output limit value of the voltage equalizing ring :

[0072] Therefore, the output limit value of the voltage equalizing ring is selected as ±187 V. The integral selects the output limit value, so the maximum voltage regulation capability of the integral link in a single cycle is selected as 2 V, and the maximum limit value of the integral link is reversed to 187×2 / 10 = 37. Therefore, the maximum limit value of the integral link is ±37 V.

[0073] During operation, the equipment is self-adapted according to the current load and power change rate parameters to perform voltage control. For example, when the limit is switched, when the positive and negative 50kW are switched, the low voltage side voltage is 500V, the high voltage side voltage is 800V, and the power response time is 80ms. The current change rate at this time is calculated to be 200A / 80ms×55μs=0.137A. At this time, the power changes faster, so take k is 0.00001, after adaptive calculation of integral parameter K i =0.00001 / 0.137=0.00007299.

[0074] The current single-cycle bias voltage is measured to be 16V (this value cannot be predicted and is related to environmental factors such as IGBT switch temperature, switch gate resistance, collector current, drive power supply voltage, etc., and needs to be based on the actual measured value). Assuming that the current inductor current reaches 2A during the power change process, the duty cycle compensation amount is calculated as:

[0075] Since the duty cycle compensation value 299V exceeds the duty cycle compensation limit value 187V, the output after limiting is 187V. Finally, according to the above process, the current time is used , , last moment , Calculate the corresponding compensation tube and whether the integral is cleared, and finally control the output duty cycle compensation value to the corresponding switch tube for voltage correction.

[0076] It can be seen that the voltage-equalizing control method of the three-level circuit converter proposed in the present invention determines the integral parameter for eliminating static error based on the average value of the half-bus bias voltage and the inductor current of the current and previous switching cycles. This dynamic adjustment based on real-time data can avoid the response lag and control instability caused by the excessively strong integral link, and also reduces the problem of reduced dynamic response speed caused by the integration being too weak, thereby avoiding the lack of reliance on personnel experience during the debugging process and reducing the risk of bias and equipment failure caused by improper debugging. In addition, based on the data of the current and previous switching cycles to determine the compensation direction, the target compensation tube, and the duty cycle compensation amount, the voltage-equalizing control of the compensation tube can ensure the accuracy and timeliness of the compensation, thereby effectively performing voltage correction, effectively solving the problem caused by the integral link being too strong or too weak, reducing the workload of the equipment's later maintenance and technical support, reducing the output voltage and current ripple, improving the output control accuracy, and also improving the overall performance and stability of the system, providing a strong guarantee for the normal operation of the equipment.

[0077] See also Figure 7 , an embodiment provides a controller, which is used to execute the voltage balancing control method of the three-level circuit converter in the above embodiment.

[0078] The present application also provides a controller, see Figure 7 The controller 200 may include: at least one processor 210 and a memory 220, wherein the memory 220 stores a computer program that can be run on at least one processor 210, and when the processor 210 executes the computer program, the steps in any of the above method embodiments are implemented.

[0079] Exemplarily, the computer program may be divided into one or more modules / units, one or more modules / units are stored in the memory 220, and executed by the processor 210 to complete the present application. One or more modules / units may be a series of computer program segments capable of completing specific functions, and the program segments are used to describe the execution process of the computer program in the controller 200.

[0080] Those skilled in the art will understand that Figure 7 These are merely examples of controllers and do not constitute a limitation of the controller, which may include more or fewer components than those shown in the figure, or a combination of certain components, or different components, such as input and output devices, network access devices, buses, etc.

[0081] The processor 210 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0082] The memory 220 may be an internal storage unit of the controller or an external storage device of the controller, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. The memory 220 is used to store computer programs and other programs and data required by the controller. The memory 220 may also be used to temporarily store data that has been output or is to be output.

[0083] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, the bus in the drawings of this application is not limited to only one bus or one type of bus.

[0084] The voltage balancing control method of the three-level circuit converter provided in the embodiment of the present application can be applied to controllers such as computers, tablet computers, laptop computers, netbooks, personal digital assistants (PDAs), etc. The embodiment of the present application does not impose any restrictions on the specific type of the controller.

[0085] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0086] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A voltage balancing control method for a three-level circuit converter, characterized in that: include: Obtaining a half bus bias voltage of a current switching cycle of a three-level circuit converter, an average value of an inductor current of the current switching cycle, a half bus bias voltage of a previous switching cycle, and an average value of an inductor current of a previous switching cycle; Determining a duty cycle compensation amount based on a half bus bias voltage of the current switching cycle; Determine the corresponding compensation direction, target compensation tube and integral parameter for eliminating static error based on the half bus bias of the current switching cycle, the average value of the inductor current of the current switching cycle, the half bus bias of the previous switching cycle and the average value of the inductor current of the previous switching cycle; Based on the duty cycle compensation amount, the compensation direction, the target compensation tube and the integral parameter for eliminating static error, the target compensation tube is subjected to voltage equalization control to perform voltage correction.

2. The voltage balancing control method of a three-level circuit converter according to claim 1, characterized in that: The determining of the duty cycle compensation amount based on the half bus bias of the current switching cycle includes: Determine the conversion relationship between the duty cycle compensation amount and time based on the carrier cycle value and the switching frequency of the time reference module of the three-level circuit converter; The duty cycle compensation amount is determined based on the half bus bias of the current switching cycle and the conversion relationship between the duty cycle compensation amount and time.

3. The voltage balancing control method of a three-level circuit converter according to claim 1, characterized in that: The duty cycle compensation amount It is expressed as: in, is the absolute value of the half bus bias voltage of the current switching cycle; is half bus capacitance value; is the switching frequency; is the carrier period value of the time reference module of the three-level circuit converter; is the average value of the inductor current in the current switching cycle.

4. The voltage balancing control method of a three-level circuit converter according to claim 1, characterized in that: After determining the duty cycle compensation amount based on the half bus bias of the current switching cycle, the voltage sharing control method of the three-level circuit converter further includes: A preset value of a maximum adjustment bias voltage of a single switching cycle is set, and a limit value of a duty cycle compensation amount is determined based on the preset value of the maximum adjustment bias voltage of a single switching cycle; the limit value of the duty cycle compensation amount is used to limit the duty cycle compensation amount; wherein, when the average value of the inductor current of the current switching cycle is less than 2A, the limit value of the duty cycle compensation amount is 0; The duty cycle compensation amount is updated based on the limit value of the duty cycle compensation amount to obtain an updated duty cycle compensation amount.

5. The voltage balancing control method of a three-level circuit converter according to claim 1, characterized in that: The method of judging the corresponding compensation direction, the target compensation tube and the integral parameter for eliminating static error based on the half bus bias of the current switching cycle, the average value of the inductor current of the current switching cycle, the half bus bias of the previous switching cycle and the average value of the inductor current of the previous switching cycle includes: Determining a change trend of the half bus bias based on the half bus bias of the current switching cycle and the half bus bias of the previous switching cycle; Determining a change trend of the inductor current based on an average value of the inductor current in the current switching cycle and an average value of the inductor current in the previous switching cycle; Determining a compensation direction based on a change trend of the half-bus bias voltage and a change trend of the inductor current; determining the target compensation tube in the compensation direction; For the target compensating tube, a corresponding integral parameter for eliminating static error is determined.

6. The voltage balancing control method of a three-level circuit converter according to claim 5, characterized in that: The step of determining the corresponding integral parameter for eliminating static error comprises: Determining a rate of change of the inductor current based on an average value of the inductor current of the current switching cycle and an average value of the inductor current of the previous switching cycle; An integral parameter for eliminating static error is determined based on the rate of change of the inductor current and the half bus bias of the current switching cycle.

7. The voltage balancing control method of a three-level circuit converter according to claim 6, characterized in that: The rate of change of the inductor current It is expressed as: in, is the average value of the inductor current in the current switching cycle; is the average value of the inductor current in the previous switching cycle; is the switching frequency; The integral parameter for eliminating static error It is expressed as: in, is the initial integration parameter, ; k is the current switching cycle; is the half bus bias voltage of the current switching cycle; t For time.

8. The voltage balancing control method of a three-level circuit converter according to claim 1, characterized in that: The voltage balancing control method of the three-level circuit converter further includes: In the commutation process of voltage-equalizing control of the target compensation tube, a commutation digital logic is set; the commutation digital logic includes clearing the integral parameter for eliminating static error when the positive or negative polarity of a single quantity of the half-bus bias or the average value of the inductor current changes between the current moment and the previous moment.

9. The voltage balancing control method of a three-level circuit converter according to any one of claims 1 to 8, characterized in that: Obtaining the half bus bias voltage of the current switching cycle of the three-level circuit converter and the average value of the inductor current of the current switching cycle, including: Obtaining a capacitance value of a half busbar of a three-level circuit converter in a current switching cycle and an inductor current in a current switching cycle; Determining an average value of the inductor current in the current switching cycle based on the inductor current in the current switching cycle; A half bus bias voltage of the current switching cycle is determined based on the capacitance value of the current switching cycle and the inductor current of the current switching cycle.

10. A controller, characterized in that: The controller is used to execute the voltage balancing control method of a three-level circuit converter according to any one of claims 1 to 9.

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