Offset calibration method, and OLDI interface test method and device

Abstract

The invention provides an offset calibration method and an OLDI interface test method and device. Relates to the technical field of data transmission. According to the specific implementation scheme, a first data stream is input into a first register and a second register of a control chip in sequence, and a target processing signal output by the first register or the second register is obtained; calibrating the first data stream based on a target instruction in the target processing signal and then inputting the first data stream to a corresponding data channel in the OLDI interface; wherein the target instruction is determined according to a display result which comprises calibration information and is output by the display after the Lth round of data transmission is finished. According to the embodiment of the invention, the offset among the plurality of data channels in the interface is calibrated, so that the condition of data transmission errors caused by the offset can be effectively eliminated, and the accuracy of data transmission can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of data transmission, and in particular to an offset calibration method, and a test method and device for an OLDI interface. Background Art

[0002] In data transmission, the Open LVDS Display Interface (OLDI) is an interface that connects a controller to a liquid crystal display (LCD). As the demand for high-resolution display screens grows, the transmission speed of the OLDI interface is also increasing. However, various anomalies may occur during testing, such as the skew between several data channels in the interface. Therefore, it is urgent to calibrate the skew between multiple data channels in the interface. Summary of the invention

[0003] The present disclosure provides an offset calibration method, and a test method and device for an OLDI interface.

[0004] According to a first aspect of the present disclosure, there is provided an offset calibration method for calibrating the offset between multiple data channels in an OLDI interface, the OLDI interface being used to connect a control chip and a display, the method comprising: Inputting the first data stream into the first register and the second register of the control chip successively to obtain a target processing signal output by the first register or the second register; The first data stream is calibrated based on the target instruction in the target processing signal and then input into the corresponding data channel in the OLDI interface; wherein the target instruction is determined according to the display result including the calibration information output by the display after the Lth round of data transmission is completed.

[0005] According to a second aspect of the present disclosure, a method for testing an OLDI interface is provided, the method comprising: Obtaining data to be transmitted corresponding to the first data stream of the L+1th round; the first data stream is obtained according to the method described in the first aspect; The data to be transmitted is transmitted from the control chip to the display through the OLDI interface to test the functions of other OLDI interfaces except the OLDI interface offset.

[0006] According to a third aspect of the present disclosure, there is provided an offset calibration device for calibrating the offset between multiple data channels in an OLDI interface, the OLDI interface being used to connect a control chip and a display, the device comprising: A first acquisition module, used to input the first data stream into the first register and the second register of the control chip in sequence, and obtain a target processing signal output by the first register or the second register; A calibration module is used to calibrate the first data stream based on the target instruction in the target processing signal and input it into the corresponding data channel in the OLDI interface; wherein the target instruction is determined according to the display result including the calibration information output by the display after the Lth round of data transmission is completed.

[0007] According to a fourth aspect of the present disclosure, there is provided an offset calibration device, the device comprising: A third acquisition module acquires the data to be transmitted corresponding to the first data stream of the L+1th round; the first data stream is obtained according to the method described in the first aspect; The test module transmits the data to be transmitted from the control chip to the display through the OLDI interface to test the functions of other OLDI interfaces except the OLDI interface offset.

[0008] According to a fifth aspect of the present disclosure, there is provided an electronic device, including: at least one processor; a memory communicatively coupled to the at least one processor; The memory stores instructions that can be executed by at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the offset calibration method and / or the OLDI interface testing method provided in the first aspect.

[0009] According to a sixth aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to enable a computer to execute the offset calibration method and / or the OLDI interface testing method provided in the first aspect.

[0010] According to a seventh aspect of the present disclosure, a computer program product is provided, including a computer program stored on a storage medium, and when the computer program is executed by a processor, the offset calibration method and / or the OLDI interface testing method provided in the first aspect is implemented.

[0011] According to the technical solution of the present disclosure, by calibrating the offset between multiple data channels in the interface, data transmission errors caused by the offset can be effectively eliminated, thereby helping to improve the accuracy of data transmission.

[0012] The above summary is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present application will be readily apparent by reference to the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A schematic diagram of a flow chart of an offset calibration method provided by an embodiment of the present invention; Figure 2 A schematic diagram of an application of an OLDI interface provided by an embodiment of the present invention; Figure 3 A schematic diagram of a serial clock channel and a data channel in an OLDI interface provided in an embodiment of the present invention; Figure 4 A schematic diagram of a first register and a second register provided in an embodiment of the present invention; Figure 5 A schematic diagram of a data channel provided by an embodiment of the present invention having an early one-bit offset; Figure 6 A schematic diagram of a data channel with a one-bit delay offset provided by an embodiment of the present invention; Figure 7 A schematic diagram of offset calibration provided by an embodiment of the present invention; Figure 8 A schematic diagram of a flow chart of a method for testing an OLDI interface provided by an embodiment of the present invention; Fig. 9 A schematic diagram of the structure of an offset calibration device provided by an embodiment of the present invention; Fig.10 A schematic diagram of the structure of an OLDI interface testing device provided by an embodiment of the present invention; Fig.11 It is a schematic diagram of the structure of an electronic device used to implement the offset calibration method of the embodiment of the present disclosure. DETAILED DESCRIPTION

[0014] The present disclosure will be further described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0015] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the main purpose of the present disclosure.

[0016] The term "and / or" herein means that there may be three relationships. For example, A and / or B may mean: A exists alone, A and B exist at the same time, and B exists alone. The term "at least one" herein means any combination of at least two of any one or more of a plurality of. For example, at least one of A, B, and C may mean any one or more elements selected from the set consisting of A, B, and C. The terms "first" and "second" herein refer to and distinguish a plurality of similar technical terms. They do not mean to limit the order or to limit the meaning to only two. For example, the first feature and the second feature refer to two types / two features. The first feature may be one or more, and the second feature may also be one or more.

[0017] In the related art, OLDI is an interface connecting a controller and an LCD display panel, which is widely used in various display devices, such as laptops, car displays, etc. As the application demand for high-resolution display screens increases, the transmission speed of the OLDI interface is also getting higher and higher. However, various anomalies may also be encountered during the test process, such as skew between several data channels in the interface.

[0018] In the prior art, usually, the offset balance between multiple data channels in OLDI depends on the layout and configuration of the routing, including the routing inside the chip and the routing outside the chip. However, if the offset between the data channels is large during the test, it may affect the accuracy of data transmission. In the above situation, there is no better way to eliminate the offset between the multiple data channels, which may affect other test items.

[0019] In order to at least partially solve one or more of the above problems and other potential problems, the present disclosure proposes a calibration scheme applied to OLDI, which includes: inputting a first data stream into a first register and a second register of a control chip in sequence to obtain a target processing signal output by the first register or the second register; calibrating the first data stream based on the target instruction in the target processing signal and then inputting it into the corresponding data channel in the OLDI interface. In this way, in a test scenario, by calibrating the offset between multiple data channels in the interface, data transmission errors caused by the offset can be effectively eliminated, thereby helping to improve the accuracy of data transmission and thereby reducing the impact on other test items.

[0020] Figure 1 is a schematic diagram of a flow chart of offset calibration according to an embodiment of the present disclosure, such as Figure 1 As shown, the method comprises at least the following steps: S101: inputting a first data stream into a first register and a second register of a control chip in sequence to obtain a target processing signal output by the first register or the second register; S102: Calibrate the first data stream based on the target instruction in the target processing signal and input it into the corresponding data channel in the OLDI interface; wherein the target instruction is determined according to the display result including the calibration information output by the display after the Lth round of data transmission is completed.

[0021] In some embodiments, the interface refers to an OLDI interface, which is used to connect the interface between the control chip and the LCD display. The OLDI interface is built based on low-voltage differential signaling (LVDS) technology. The OLDI interface utilizes the differential signal transmission characteristics of LVDS, which can realize the transmission of high-speed digital signals with very low voltage and current while maintaining the integrity of the signal. Figure 2 The application diagram of OLDI interface is shown in FIG. Figure 2 As shown in FIG. 1 , one end of the OLDI interface is connected to the controller chip, and the other end is connected to the LCD display. In actual application scenarios, the controller chip is the transmitter and the LCD display is the receiver; the controller chip transmits the data to be transmitted from the controller chip to the LCD display through the OLDI interface.

[0022] In some embodiments, the OLDI interface supports multiple data channels to meet the needs of high-speed data transmission. The OLDI interface usually includes multiple data channels for transmitting video, audio, and other control signals. For example, in some applications, the OLDI interface may support 8 LVDS data channels plus a clock channel to support high-resolution video transmission. The data channels in the OLDI interface can work in parallel to transmit video signals at a high rate, thereby supporting high-resolution and high-refresh rate display screens. Figure 3 FIG. 4 shows a schematic diagram of a serial clock channel and a data channel in an OLDI interface. Figure 3 As shown, the OLDI interface includes four data channels and one clock channel; wherein the first data channel is denoted as A0, the second data channel is denoted as A1, the third data channel is denoted as A2, and the fourth data channel is denoted as A3.

[0023] In some embodiments, the offset between multiple data channels in the interface may refer to a phase offset (PhaseOffset). In the test of the OLDI interface function, if the display result of the LCD display is abnormal when the control chip sends the Nth data to be transmitted to the LCD display, the control chip re-acquires the Nth data to be transmitted as the data to be transmitted for the L+1th data transmission, and before the control chip sends the L+1th data to be transmitted to the LCD display, the target instruction in the target processing signal is generated according to the display result of the Lth data transmission. In this way, the offset between multiple data channels in the test can be calibrated to reduce the impact on the test items, such as the test of the OLDI interface function. At the same time, the accurate positioning of the offset position between multiple data channels can be achieved.

[0024] In some embodiments, the controller chip is also called a microcontroller, which is an integrated circuit chip. The controller chip integrates a processor core, memory, input / output interface, and various peripherals. It controls and operates a device or system by receiving input signals, processing and calculating, and generating corresponding output signals. The controller chip is usually composed of one or more processor cores, which can be general-purpose processors or processors designed specifically for specific application areas. There is a high bandwidth between the core and the memory, which can quickly transmit and process a large amount of data. The controller chip can control and manage the operation of various devices, including but not limited to smartphones, tablet computers, household appliances, automobiles, industrial robots, etc. Specifically, the controller chip includes at least a first register and a second register; the controller chip is connected to the display via an OLDI interface. Here, the display can be an LCD display.

[0025] In some embodiments, the first data stream is obtained by serializing the data to be processed. The data to be processed is obtained from the memory of the control chip. In the test environment of the OLDI interface function, if the control chip sends the Nth data to be transmitted to the LCD display, the display result of the LCD display is abnormal; then the L+1th round of data to be transmitted is obtained from the memory of the control chip; wherein the content of the L+1th round of data to be transmitted is the same as that of the Nth round of data to be transmitted.

[0026] In some embodiments, the first register and the second register are used to output a target processing signal carrying a target instruction. Specifically, the first register is used to output a target processing signal carrying a standard timing instruction and a delay instruction; the second register is used to output a target processing signal carrying an advance instruction. The first register and the second register are important components of the control chip, which are used to store and process data and are important storage units inside the central processing unit (CPU). Registers are used to temporarily store processing objects such as instructions, data, and addresses. In the control chip, the main function of the register is to store instructions and data so that the CPU can quickly access and process these data.

[0027] In some embodiments, the target processing signal is a signal output by the first register or the second register of the control chip. The target processing signal carries a target instruction. The target instruction includes but is not limited to: a delay instruction and an advance instruction.

[0028] Figure 4 A schematic diagram of the first register and the second register is shown, as shown in Figure 4 As shown in the figure, the data[6:0] signal is a 7-bit bus after the parallelization of a data channel, and the Clock signal is a parallel clock; the clock signal passes through the first register and the second register; the clock signal is used to control the working status and timing of each module inside the chip. The data[6:0] signal passes through the first register to become the data_s1[6:0] signal, and then passes through the second register to become the data_s2[6:0] signal. The parallel data data[6:0] is mapped to the serial data channel in the order of sending the low bit 0 first. Here, each data channel has Figure 4 The first register and second register paths are shown so that each data channel can adjust the offset independently.

[0029] According to the solution of the embodiment of the present disclosure, the first data stream is input into the first register and the second register of the control chip successively to obtain the target processing signal output by the first register or the second register; the first data stream is calibrated based on the target instruction in the target processing signal and then input into the corresponding data channel in the OLDI interface; wherein the target instruction is determined according to the display result including the calibration information output by the display after the Lth round of data transmission is completed. In this way, in the test scenario, by calibrating the offset between multiple data channels in the interface, the data transmission error caused by the offset can be effectively eliminated, thereby helping to improve the accuracy of data transmission and thus reduce the impact on other test items.

[0030] In the embodiment of the present disclosure, the offset calibration method also includes: obtaining the L+1th round of data to be transmitted from the memory of the control chip for processing to obtain a first data stream; wherein the content of the L+1th round of data to be transmitted is the same as the content of the Lth round of data to be transmitted.

[0031] In some embodiments, the memory refers to a storage element embedded in or closely associated with the control chip, which is used to store instructions, data, configuration parameters and other information to support the normal operation and function realization of the chip. Specifically, the instructions, data, configuration parameters and other information stored in the memory can be obtained in advance from other devices (such as sensors), or can be dynamically generated by the chip during operation.

[0032] In some embodiments, obtaining the L+1th round of data to be transmitted from the memory of the control chip for processing to obtain a first data stream may include: encoding and compressing the L+1th round of data to be transmitted to obtain the first data stream.

[0033] In this way, by serializing the data to be transmitted, complex data structures can be simplified into a single data stream, which helps reduce errors and interference in data transmission and improves the accuracy and stability of data transmission.

[0034] In the disclosed embodiment, the calibration information indicates that the first data stream enters the data channel N bits in advance, and the target processing signal is a signal output by the first register; wherein the target instruction in the target processing signal is a delay instruction, and N is an integer not less than 1.

[0035] In some embodiments, the display result corresponding to the calibration information is an abnormal display image or video. For example, if the control chip sends a color line picture "composed of black, white and red" to the vehicle-mounted LCD display through the OLDI interface, the display result of the vehicle-mounted LCD display is a line picture "composed of black and white". Figure 5 FIG. 4 shows a schematic diagram of a data channel shifting one bit ahead of the other. Figure 5 As shown in Figure 1, the OLDI interface consists of 1 serial clock channel (CLK1) and 4 serial data channels (A0-A3). Figure 5 For example, if data channel A2 has an abnormality of one-bit advance offset and a data transmission error, the vehicle-mounted LCD display outputs a display result including calibration information indicating that the first data stream enters the data channel 1 bit in advance.

[0036] In some embodiments, the display result corresponding to the calibration information is an abnormal display image or video, such as garbled characters, a black screen, or an error prompt. For example, if the control chip sends a picture of "green radish" to the LCD display of a laptop computer through the OLDI interface, the display result of the laptop computer is garbled characters. Figure 5 For example, the OLDI interface contains 1 serial clock channel (CLK1) and 4 serial data channels (A0-A3). Figure 5 For example, if data channel A2 has an abnormality of one-bit advance offset and a data transmission error, the display output includes a display result of calibration information indicating that the first data stream enters the data channel N bits in advance.

[0037] In some embodiments, the target instruction is used to adjust the offset in the data channel. Specifically, the delay instruction refers to an abnormality in which the first data stream is offset by N bits in advance in the data channel. When the control chip responds to detecting the delay instruction, the first data stream is delayed by N bits and input to the corresponding data channel in the OLDI interface, where N is an integer not less than 1.

[0038] In this way, when the calibration information indicates that the first data stream enters the data channel N bits in advance and the first data stream passes through the first register, the target processing signal carrying the delay instruction is obtained from the output of the first register. The offset between multiple data channels is calibrated through the delay instruction to ensure the accuracy of data transmission.

[0039] In an embodiment of the present disclosure, the first data stream is calibrated based on the target instruction in the target processing signal and then input into the corresponding data channel in the OLDI interface, including: based on the delay instruction, the first data stream is delayed by N bits and input into the corresponding data channel in the OLDI interface, where N is an integer not less than 1.

[0040] by Figure 5 For example, when the data channel A2 is shifted one bit ahead during the Lth round of data transmission, during the L+1th round of data transmission, the data to be transmitted in the Lth round is obtained as the data to be transmitted in the L+1th round, and the data to be transmitted in the L+1th round is serialized to obtain a first data stream; the first data stream passes through the first register and the second register to obtain a target processing signal carrying a delay instruction output by the first register; based on the delay instruction, the first data stream is delayed by N bits and input into the corresponding data channel in the OLDI interface, and the calibrated first data stream is transmitted to the display through the data channel.

[0041] In this way, by calibrating the offset between multiple data channels in the interface through delay instructions, data transmission errors caused by the offset can be effectively eliminated, thereby helping to improve the accuracy of data transmission.

[0042] In the disclosed embodiment, the calibration information indicates that the first data stream is delayed by M bits to enter the data channel, and the target processing signal is a signal output by the second register; wherein the target instruction in the target processing signal is an advance instruction, and M is an integer not less than 1.

[0043] In some embodiments, the third display result corresponding to the calibration information is an abnormal display image or video, such as garbled characters, a black screen, or an error prompt, etc. For example, if the control chip sends a 5s video of "ephemeral blooming" to the LCD display of the mobile phone through the OLDI interface, an error prompt appears on the mobile phone. Figure 6 FIG. 4 is a schematic diagram showing a data channel having a one-bit delay offset. Figure 6 As shown in Figure 2, the OLDI interface contains one serial clock channel (CLK1) and four serial data channels (A0-A3). Figure 6 As shown, if the data channel A2 has an abnormal delay of one bit offset and a data transmission error, the display output includes a display result of calibration information indicating that the first data stream enters the data channel with a delay of M bits.

[0044] In some embodiments, the target instruction is used to adjust the offset in the data channel. Specifically, the advance instruction refers to an abnormality in which the first data stream has a delayed M-bit offset in the data channel. When the control chip responds to detecting the advance instruction, the first data stream is input to the corresponding data channel in the OLDI interface in advance by M bits, where M is an integer not less than 1.

[0045] In this way, when the calibration information indicates that the first data stream is delayed by M bits to enter the data channel and the first data stream passes through the second register, the target processing signal carrying the advance instruction is output by the second register. By calibrating the offset between multiple data channels through the advance instruction, the accuracy of data transmission can be guaranteed.

[0046] In an embodiment of the present disclosure, the first data stream is calibrated based on the target instruction in the target processing signal and then input into the corresponding data channel in the OLDI interface, including: based on the advance instruction, so that the first data stream is input into the corresponding data channel in the OLDI interface M bits in advance, where M is an integer not less than 1.

[0047] by Figure 6 For example, when a one-bit delay offset occurs in the data channel A2 during the Lth round of data transmission, during the L+1th round of data transmission, the data to be transmitted in the Lth round is obtained as the data to be transmitted in the L+1th round, and the data to be transmitted in the L+1th round is serialized to obtain a first data stream; the first data stream passes through the first register and the second register to obtain a target processing signal carrying an advance instruction output by the second register; based on the advance instruction, the first data stream is advanced by M bits and input into the corresponding data channel in the OLDI interface, and the calibrated first data stream is transmitted to the display through the data channel.

[0048] Figure 7 A schematic diagram of the offset calibration is shown, as Figure 7As shown, the clk_s signal is the serial clock, and the clock signal is the parallel clock. The size is 1 / 7 of the serial clock, and the cycle (cycle) 0 / 1 / 2 corresponds to the parallel clock clock cycle. The data[6:0] signal is data0[6:0], data1[6:0] and data2[6:0] during cycle0 / 1 / 2. The data_s1[6:0] signal passing through the first register is delayed by one clock cycle on data[6:0]. Similarly, the data_s2[6:0] signal is delayed by one clock cycle on data_s1[6:0]. Data channel A2 is a transmission without exception. postA2 is a transmission that is designed to be delayed by one serial clock cycle, and preA2 is a transmission that is designed to be advanced by one serial clock cycle. When no exception occurs, the parallel signal data_s1[6:0] is used to serially output from data channel A2. The M[N] format transmitted by A2 represents dataM[N], for example, 0[0] represents data0[0]. In cycle0, the data_s1[6:0] signal is invalid data, and A2 outputs invalid data. In cycle1, the data_s1[6:0] signal is data0[6:0], and A2 serially outputs data0[6:0], outputting the low bit first. Cycle2 is similar. Figure 5 When the advance deviation exception is shown, the data_post[6:0] signal is used, and the corresponding target processing signal is {data_s1[5:0], data_s2[6]}. Cycle1 is calibrated to {data0[5:0], x}. The serial output effect is like postA2, and cycle2 is similar. The overall delay is one serial clock cycle. Combined with the advance exception, the normal data transmission A2 can be obtained. When the following occurs Figure 6 When the exception is shown, the data_pre[6:0] signal is used, and the corresponding target processing signal is {data[0], data_s1[6:1]}. In cycle0, it is calibrated to {data0[0], 6{x}}. The effect of serial output is like preA2. Cycle1 and 2 are similar. The whole is advanced by one serial clock cycle. Combined with the delay exception, A2 of normal data transmission can be obtained.

[0049] In this way, by calibrating the offsets between multiple data channels in the interface through advance instructions, data transmission errors caused by the offsets can be effectively eliminated, thereby helping to improve the accuracy of data transmission.

[0050] In the embodiment of the present disclosure, the offset calibration method further includes: sending the first data stream to the display through the OLDI interface, and obtaining a display result of the L+1th round of data transmission output by the display.

[0051] In this way, the accuracy of data transmission can be determined through the display results output by the display, which helps to improve the efficiency of related tests on the OLDI interface.

[0052] Figure 8 is a schematic diagram of a flow chart of offset calibration according to an embodiment of the present disclosure, such as Figure 8 As shown, the method comprises at least the following steps: S801: Obtain the data to be transmitted corresponding to the first data stream of the L+1th round; S802: Send the data to be transmitted from the control chip to the display through the OLDI interface to test the functions of other OLDI interfaces except the OLDI interface offset.

[0053] The first data stream is obtained by the above-mentioned offset calibration method.

[0054] In some embodiments, the functions of other OLDI interfaces include but are not limited to: boundary value testing, permission control testing, load testing, etc. Specifically, boundary value testing refers to testing the boundary values ​​of input data, such as maximum value, minimum value, null value, etc., to ensure that the interface can be processed correctly. Permission control testing refers to verifying the security and permission control of the interface by testing the access rights of different user roles to the interface to ensure that the interface will not be illegally accessed or abused. Load testing refers to formulating test scenarios, including parameters such as concurrency and request frequency, to simulate the pressure in real scenarios; for example, running performance tests to collect indicators such as interface response time and throughput.

[0055] The present disclosure provides an offset calibration device, such as Fig. 9 As shown, the offset calibration device includes: a first acquisition module 901, which is used to input the first data stream into the first register and the second register of the control chip in sequence to obtain a target processing signal output by the first register or the second register; a calibration module 902, which is used to calibrate the first data stream based on the target instruction in the target processing signal and then input it into the corresponding data channel in the OLDI interface; wherein the target instruction is determined according to the display result including the calibration information output by the display after the Lth round of data transmission is completed.

[0056] In some embodiments, the offset calibration device further includes: a second acquisition module ( Fig. 9 ), obtains the data to be transmitted in the N+1th round from the memory of the control chip; wherein the data to be transmitted in the N+1th round has the same content as the data to be transmitted in the Nth round; the processing module ( Fig. 9 ), which is used to serialize the data to be transmitted in the N+1th round to obtain a first data stream.

[0057] In some embodiments, the calibration information indicates that the first data stream enters the data channel N bits in advance, and the target processing signal is a signal output by the first register; wherein the target instruction in the target processing signal is a delay instruction, and N is an integer not less than 1.

[0058] In some embodiments, the calibration module 902: based on the delay instruction, delays the first data stream by N bits and inputs it into the corresponding data channel in the OLDI interface, where N is an integer not less than 1.

[0059] In some embodiments, the calibration information indicates that the first data stream is delayed by M bits to enter the data channel, and the target processing signal is a signal output by the second register; wherein the target instruction in the target processing signal is an advance instruction, and M is an integer not less than 1.

[0060] In some embodiments, the calibration module 902 includes: based on the advance instruction, so that the first data stream is input into the corresponding data channel in the OLDI interface M bits in advance, where M is an integer not less than 1.

[0061] In some embodiments, the offset calibration device further includes: a sending module ( Fig. 9 (not shown) sends the first data stream to the display through the OLDI interface to obtain the display result of the L+1th round of data transmission output by the display.

[0062] The offset calibration device of the disclosed embodiment can effectively eliminate data transmission errors caused by offsets by calibrating the offsets between multiple data channels in an interface, thereby helping to improve the accuracy of data transmission.

[0063] The present disclosure provides an offset calibration device, such as Fig.10 As shown, the offset calibration device includes: a third acquisition module, which acquires the data to be transmitted corresponding to the first data stream of the L+1th round; a test module, which transmits the data to be transmitted from the control chip to the display through the OLDI interface to test the functions of other OLDI interfaces except the OLDI interface offset; wherein the first data stream is obtained by the above-mentioned offset calibration method.

[0064] In the technical solution disclosed herein, the acquisition, storage and application of user personal information involved are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0065] Fig.11 FIG. 1 is a structural block diagram of an electronic device according to an embodiment of the present disclosure. Fig.11As shown, the electronic device includes: a memory 1110 and a processor 1120, and the memory 1110 stores a computer program that can be run on the processor 1120. The number of memories 1110 and processors 1120 can be one or more. The memory 1110 can store one or more computer programs. When the one or more computer programs are executed by the electronic device, the electronic device executes the method provided by the above method embodiment. The electronic device may also include: a communication interface 1130, which is used to communicate with external devices and perform data exchange transmission.

[0066] If the memory 1110, the processor 1120 and the communication interface 1130 are implemented independently, the memory 1110, the processor 1120 and the communication interface 1130 can be connected to each other through a bus and communicate with each other. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig.11 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0067] Optionally, in a specific implementation, if the memory 1110, the processor 1120 and the communication interface 1130 are integrated on a chip, the memory 1110, the processor 1120 and the communication interface 1130 can communicate with each other through an internal interface.

[0068] It should be understood that the processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc. It is worth noting that the processor may be a processor that supports the Advanced RISC Machines (ARM) architecture.

[0069] Further, the above-mentioned memory may include a read-only memory and a random access memory, and may also include a non-volatile random access memory. The memory may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may include a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may include a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available. For example, static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM) and direct memory bus random access memory (DR RAM).

[0070] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on the computer, the process or function according to the embodiment of the present disclosure is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center by wired (for example: coaxial cable, optical fiber, data subscriber line (Digital Subscriber Line, DSL)) or wireless (for example: infrared, Bluetooth, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that can be accessed by a computer, or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a digital versatile disc (DVD)), or a semiconductor medium (e.g., a solid state disk (SSD)), etc. It is worth noting that the computer-readable storage medium mentioned in the present disclosure may be a non-volatile storage medium, in other words, a non-transient storage medium.

[0071] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware, or by a program to instruct the relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0072] In the description of the embodiments of the present disclosure, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.

[0073] The above are merely exemplary embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. An offset calibration method, characterized in that: Used to calibrate the offset between multiple data channels in an OLDI interface, wherein the OLDI interface is used to connect a control chip and a display, and the method includes: Inputting the first data stream into the first register and the second register of the control chip successively to obtain a target processing signal output by the first register or the second register; The first data stream is calibrated based on the target instruction in the target processing signal and then input into the corresponding data channel in the OLDI interface; wherein the target instruction is determined according to the display result including the calibration information output by the display after the Lth round of data transmission is completed.

2. The method according to claim 1, characterized in that: Also includes: The data to be transmitted in the L+1th round is obtained from the memory of the control chip for processing to obtain a first data stream; wherein the data to be transmitted in the L+1th round has the same content as the data to be transmitted in the Lth round.

3. The method according to claim 2, characterized in that The calibration information indicates that the first data stream enters the data channel N bits in advance, and the target processing signal is a signal output by the first register; wherein the target instruction in the target processing signal is a delay instruction, and N is an integer not less than 1.

4. The method according to claim 3, characterized in that The step of calibrating the first data stream based on the target instruction in the target processing signal and inputting the first data stream into the corresponding data channel in the OLDI interface comprises: Based on the delay instruction, the first data stream is delayed by N bits and input into a corresponding data channel in the OLDI interface, where N is an integer not less than 1.

5. The method according to claim 2, characterized in that: The calibration information indicates that the first data stream is delayed by M bits to enter the data channel, and the target processing signal is a signal output by the second register; wherein the target instruction in the target processing signal is an advance instruction, and M is an integer not less than 1.

6. The method according to claim 5, characterized in that The step of calibrating the first data stream based on the target instruction in the target processing signal and inputting the first data stream into the corresponding data channel in the OLDI interface comprises: Based on the advance instruction, the first data stream is input into the corresponding data channel in the OLDI interface M bits in advance, where M is an integer not less than 1.

7. The method according to claim 1, characterized in that The method further comprises: The first data stream is sent to the display through the OLDI interface, and a display result of the L+1th round of data transmission output by the display is obtained.

8. A method for testing an OLDI interface, characterized in that: The method comprises: Obtaining data to be transmitted corresponding to the first data stream of the L+1th round; the first data stream is obtained by the method according to any one of claims 1 to 7; The data to be transmitted is sent from the control chip to the display through the OLDI interface to test the functions of the other OLDI interfaces except the OLDI interface offset.

9. An offset calibration device for calibrating the offset between multiple data channels in an OLDI interface, wherein the OLDI interface is used to connect a control chip and a display, the device comprising: A first acquisition module, used to input the first data stream into the first register and the second register of the control chip in sequence, and obtain a target processing signal output by the first register or the second register; A calibration module is used to calibrate the first data stream based on the target instruction in the target processing signal and input it into the corresponding data channel in the OLDI interface; wherein the target instruction is determined according to the display result including the calibration information output by the display after the Lth round of data transmission is completed.

10. A test device for an OLDI interface, characterized in that: The device comprises: A third acquisition module is used to acquire the data to be transmitted corresponding to the first data stream of the L+1th round; the first data stream is obtained according to any one of the methods of claims 1-7; The test module is used to send the data to be transmitted from the control chip to the display through the OLDI interface to test the functions of the other OLDI interfaces except the OLDI interface offset.

11. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively coupled to the at least one processor; The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 8.

12. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to cause the computer to execute the method according to any one of claims 1-8.

13. A computer program product, comprising a computer program stored on a storage medium, characterized in that The computer program implements the method according to any one of claims 1 to 8 when executed by a processor.

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