Self-adaptive micro-energy driven passive sensing node security encryption architecture

Abstract

The invention discloses a self-adaptive micro-energy driven passive sensing node security encryption architecture, and belongs to the field of communication. The method comprises the following steps: a micro-power consumption energy detection module monitors the energy state of a sensing node in real time to perform energy grading, and then adaptively triggers an encryption mechanism matched with the current energy level to perform security enhancement on node sensing data; for a lightweight encryption algorithm, power consumption is reduced through adaptive energy interval matching and an optimization strategy; and for a stream cipher encryption algorithm, through adding a random salt value, the collision resistance of a hash value of a hash function is improved, micro-power-consumption-driven adaptive data dynamic encryption is realized, and the data security protection problem caused by energy consumption constraint of massive distributed deployment passive sensing nodes is solved. According to the invention, the service life of the passive sensor equipment can be prolonged while the safety of the distributed passive sensor is guaranteed, so that the maintenance cost of the passive sensor equipment is reduced.

Description

Technical Field

[0001] The invention belongs to the field of communications, and in particular relates to an adaptive micro-energy driven passive sensor node security encryption architecture. Background Art

[0002] With the development of various key technologies of the Internet of Things, the wide application scenarios of the Internet of Things require the deployment of terminal sensor devices in every corner. Through the large-scale distributed deployment of sensor nodes, it can widely monitor various production and operating environments and obtain a large amount of data from them. However, due to the complexity and diversity of the deployment environment, such as high mountains, high temperature environments, uninhabited areas, and areas far away from power sources, high requirements are placed on the life and power supply of sensors. In order to overcome the limitations brought by these extreme environments, it is necessary to use the energy obtained from the environment (solar energy, wind energy, vibration energy, temperature difference energy) for autonomous power supply, so that the equipment can operate stably for a long time without human intervention.

[0003] The energy source of passive sensor nodes is limited and unstable. The traditional method requires the use of a microprocessor to control ADC (analog-digital converter) sampling, which consumes high power and is obviously not applicable to passive sensor nodes with unstable energy sources. For the data security encryption process, since these devices cannot have a stable and sufficient energy supply like traditional devices, they need to use most of their energy for sensing tasks, simplifying or even canceling safety protection measures to save energy. Fixed encryption methods will also burden the passive energy that is already insufficient for passive sensor nodes, that is, traditional encryption methods are difficult to adapt to the dynamic nature of energy acquisition of passive sensor nodes. In the process of implementing the technical solution of the present invention, the inventors found that: by adaptively selecting different optimized lightweight encryption algorithms according to the energy state of the passive sensor nodes, the data of the passive sensor nodes can be securely transmitted under the condition of unstable energy supply of the sensor nodes, thereby achieving the best security and energy utilization of the passive sensor nodes. Summary of the invention

[0004] The present invention provides an adaptive micro-energy driven passive sensing security encryption architecture, which accurately divides different energy thresholds and transmits terminal data to algorithms with different encryption strengths to achieve low power consumption and dynamic data encryption of nodes, thereby reducing the maintenance cost of sensor nodes.

[0005] The technical solution adopted by the present invention is:

[0006] A micro-energy driven adaptive security encryption architecture for the Internet of Things, the process comprising:

[0007] For the energy detection process, in order to realize micro-power driven energy detection, this patent designs a micro-power driven multi-level threshold division detection circuit based on the principle of linear integration circuit, and configures N micro-power voltage comparators.

[0008] Furthermore, an energy determination circuit driven by near-zero power consumption is designed based on the RC circuit, which is characterized by comprising a multi-threshold terminal node energy window division circuit and a near-zero power consumption micro-energy adaptive triggering circuit. According to the change of the battery energy of the sensor node, the determination circuit enables different energy states to be represented as voltages with different values, thereby allowing the micro-power consumption driven multi-threshold comparator group to grade the energy of the passive sensor node according to the voltage.

[0009] For the data security encryption process, lightweight algorithm encryption, micro-energy driven multi-level hash stream cipher encryption or near-zero power consumption digital conversion encryption is adaptively selected according to the energy state of the passive sensor node. The encryption method includes N-level modules: near-zero power consumption digital conversion cyclic shift encryption (first-level encryption method), adaptive micro-energy driven multi-level hash stream cipher encryption (2nd to N-2nd level encryption), and lightweight security enhancement algorithm encryption (N-1st to Nth level encryption).

[0010] Furthermore, the energy state of the passive sensor node is divided into four different energy levels: low, medium, high, and extremely high. The N encryption modules are: near-zero power digital conversion level 1 encryption (cyclic right shift by two bits after each round of encryption XOR), adaptive micro-energy driven N-3 level hash stream cipher encryption, innovative and optimized N-1 level PRESENT encryption, and innovative and optimized N level HIGHT encryption. The N encryption modules perform data encryption according to different energy levels.

[0011] Furthermore, the near-zero power digital conversion level 1 encryption algorithm is based on the message XOR algorithm, which converts the data to be encrypted into XOR and then cyclically right-shifts it by two bits to achieve zero power data security encryption; the adaptive micro-energy driven N-3 level hash encryption enhances data security by adding periodic trigger keys, real-time environment-driven micro-energy signals, and energy thresholds; the innovative and optimized N-1 level PRESENT encryption introduces the Feistel structure, which reduces the complexity of the original PRESENT encryption algorithm through the iterative mode of "split-transform-combination" and improves the security of the encryption algorithm; the innovative and optimized N-level HIGHT encryption reduces the energy consumption of the algorithm and enhances the security of the algorithm by redividing the plaintext and ciphertext blocks and splitting the original key into 8 16-bit blocks.

[0012] Furthermore, the periodic trigger key is the periodic trusted key used for adaptive micro-energy driven N-3 level hash encryption to generate hash values, which is generated based on the clock signal; the real-time environment driven micro-energy signal is the time trusted quantity obtained according to the clock signal, which is used as a salt variable for the hash function to generate hash values; the energy threshold is the lowest value of the energy range of each passive sensor node, which is also used as a salt variable for the hash function to generate hash values.

[0013] Furthermore, the implementation of the adaptive micro-energy driven N-3 level hash encryption includes the following steps: ①Receive periodic trusted key ②Receive timestamp signal ③Receive energy threshold signal ④ Select a micro-energy driven hash encryption algorithm with different energy consumption levels according to the energy threshold signal.

[0014] Furthermore, the hash stream cipher calculation formula is: Among them, H() represents the hash algorithm selected according to the energy threshold of the sensor node, r represents the periodic trusted key, T represents the real-time environment-driven micro-energy signal, N represents the energy threshold signal, and M represents the data transmitted by the sensor node.

[0015] The technical solution provided by the present invention brings at least the following beneficial effects:

[0016] In the process of passive sensor node energy detection, the energy of different passive sensor nodes can be divided into different energy levels. After the multi-threshold processing circuit, the data of different energy levels can be encrypted with different strengths, so as to maximize the use of sensor node energy for security enhancement. In the process of data security enhancement, by optimizing the PRESENT and HIGHT encryption algorithms, the power consumption of the algorithm can be reduced while improving the security of the algorithm, which greatly improves the security enhancement of passive sensor nodes. The stream cipher encryption mode based on the hash algorithm not only adds a periodic trusted key variable, but also adds two salt variables, namely the timestamp and the passive sensor node energy threshold. The salted hash algorithm can effectively resist rainbow table attacks and prevent dictionary attacks. In this way, a balance is achieved between the data security protection and low power consumption requirements of passive sensor nodes, and the maximum utilization of terminal energy and data security enhancement are achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 A basic schematic diagram of an adaptive micro-energy driven passive sensor node security encryption architecture provided by an embodiment of the present invention;

[0019] Figure 2 A schematic diagram of a circuit flow of an adaptive micro-energy driven passive sensor node security encryption architecture provided by an embodiment of the present invention

[0020] Figure 3 Schematic diagram of the operation logic of the GPRESENT encryption algorithm in an embodiment of the present invention

[0021] Figure 4 Schematic diagram of S-box data transformation of GPRESENT encryption algorithm in an embodiment of the present invention

[0022] Figure 5 Schematic diagram of the algorithm structure of the GHIGHT encryption algorithm in an embodiment of the present invention DETAILED DESCRIPTION

[0023] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0024] In the current context of the development of the Internet of Things, the Internet of Things perceives the world and acquires data through massive deployment of distributed sensor nodes, providing the necessary data sources for various digital applications. According to the IOT ANalytics report, it is estimated that by 2025, the number of global IoT devices will reach 20 billion. As the scale of IoT devices continues to expand, in order to better realize the interconnection of all things, sensors need to be able to adapt to complex and diverse deployment environments, such as remote areas, areas far away from power sources, high temperature and humid environments, etc., all of which put high demands on the life and power supply of sensors to withstand extreme working environments. Therefore, researchers have proposed installing self-energy devices such as solar panels and radio frequency energy receivers on sensor nodes. In this way, sensor nodes can continuously obtain energy from the environment, and the network formed by this is called a passive wireless sensor network. Passive wireless networks can achieve self-sufficiency in energy, greatly reducing the cost of later maintenance, and effectively expanding the application scenarios of passive sensor networks.

[0025] However, environmental factors such as light intensity, temperature changes, and the availability of RF sources will directly affect the efficiency and stability of energy harvesting. For example, when the device is in an area with weak signals, the collection of RF energy may be greatly reduced, thus affecting the normal operation of the device. This energy instability makes it difficult for sensor nodes to allocate their precious energy for data security protection. Traditional encryption methods, such as AES, DES, RSA and other encryption algorithms, usually require high computing resources and energy consumption. For passive sensor nodes with unstable energy sources, in order to reduce power consumption, they often choose to adopt simpler security measures, and may even omit some necessary security encryption links. The current hardware method has an obvious limitation, that is, it cannot be adaptively adjusted according to energy changes. This means that the hardware encryption module cannot flexibly adjust its operation to adapt to different energy constraints or power consumption requirements, and thus cannot fully meet the flexibility requirements of intermittent computing systems. As a result, it is difficult to achieve a relative balance between data security protection and low power consumption requirements of passive sensor nodes. The instability of its energy and low security have seriously restricted the widespread application of passive sensor nodes in the Internet of Things.

[0026] In view of the above problems, the embodiment of the present invention provides an adaptive security encryption architecture for passive sensor node energy drive, which includes two modules: terminal energy detection and data security encryption. The specific architecture implementation flow chart is as follows: Figure 1 shown.

[0027] For the different energy levels of passive sensor nodes, namely the first energy level, the second energy level (including n-3 sub-energy levels), and the third energy level (including two sub-energy levels), the embodiment of the present invention designs a micro-power-driven multi-level threshold division detection circuit based on the RC circuit, and configures N linear window comparators, so that different sensor nodes can maximize the use of their energy for data security enhancement. Specifically, the architecture has a total of N different encryption mechanisms, each encryption mechanism corresponds to a different optimized encryption algorithm. At the same time, the passive sensor node can select the encryption algorithm corresponding to the energy level state for encryption according to its own energy level state, thereby achieving the effect of adaptive security encryption of the passive sensor node.

[0028] like Figure 2 As shown, the embodiment of the present invention provides a micro-power driven multi-level threshold division detection circuit based on an RC circuit, and N linear window comparators together form an adaptive security encryption architecture. The multi-level adaptive security encryption method includes two parts: a multi-level threshold division detection circuit and N linear window comparators. The specific implementation process of each part is as follows:

[0029] Multi-level threshold division detection circuit: The battery power status of the passive sensor node is used as the circuit input signal. When the circuit power supply is connected, the current flows through the resistor to charge the capacitor. During the charging process, the voltage across the capacitor gradually increases. According to the formula (Wherein, V c is the voltage across the capacitor, V is the power supply voltage, t is the time, and RC is the integration time constant). After the set resistance value, the battery power state of the passive sensor node is divided into different voltage levels and then enters N linear window comparators.

[0030] Linear window comparator: The linear window comparator has a total of N linear voltage comparators. The terminal energy processed by the RC circuit has a maximum threshold and a minimum threshold. When the terminal energy signal is transmitted to the linear window voltage comparator, the threshold interval may include multiple voltage thresholds. The voltage threshold is used to determine whether the energy falls in the first energy level interval, the second energy level interval or the third energy level interval.

[0031] The encryption model of the present invention mainly includes four encryption modules, namely, near-zero power consumption digital conversion cyclic shift encryption, adaptive micro-energy driven multi-level hash stream cipher encryption, lightweight security enhanced PRESENT algorithm encryption and lightweight security enhanced HIGHT algorithm encryption.

[0032] Embodiment 1:

[0033] refer to Figure 1 The embodiment of the present invention provides a near-zero power consumption digital conversion cyclic shift encryption, corresponding to encryption energy level 1, taking data length n as an example, including:

[0034] The plaintext data to be processed is stored in the shift register, and the feedback shift register (LFSR) generates a pseudo-random sequence of length n; depending on the length of the plaintext data, the D flip-flops of the shift register and the feedback shift register will also change accordingly.

[0035] Furthermore, for a plaintext data string of length n, M = a0a1a2…a n and a pseudo-random sequence S = b0b1b2…b of length n n This patent sets a total of n XOR logic gates based on the XOR gate, and connects the data bits of M and S to the two ends of the XOR gate accordingly; specifically, a0 and b0 are connected to the two input ends of the first XOR gate, a1 and b1 are connected to the two input ends of the second XOR gate, and so on. The output end of the XOR gate constitutes the result data string C after XOR = c0c1c2…c n .

[0036] Where M is the plaintext data string; a iis a single data character in the plaintext data string; S is a pseudo-random sequence data string; b i A single numeric character in a pseudo-random sequence data string; C is the result data string after XOR; c i Is a single data character in the result data string.

[0037] Embodiment 2:

[0038] refer to Figure 1 The embodiment of the present invention provides an adaptive micro-energy driven multi-level hash stream cipher encryption, taking encryption energy level 2 as an example, including:

[0039] Based on xxHash, an adaptive micro-energy driven multi-level hash stream cipher encryption was designed and applied to data encryption at energy level 2. The plaintext data to be processed was stored in the shift register, and a pseudo-random sequence was generated by the feedback shift register (LFSR) as the periodic trusted key. The clock signal and the highest threshold were used as salt variables to generate the hash value.

[0040] Furthermore, three registers are used to store the periodic trusted key, the clock signal and the highest threshold respectively; a data input and hash stream synchronization circuit is used to receive the hash value and the plaintext data; an XOR gate circuit is used to perform bit-by-bit XOR on the plaintext data and the hash value; and a ciphertext output circuit is used to output the encrypted ciphertext data.

[0041] Embodiment three:

[0042] like Figure 3 As shown, the embodiment of the present invention provides an optimized PRESENT encryption algorithm, namely the GPRESENT encryption algorithm, whose algorithm strength is level N-1. The optimization scheme introduces the Feistel structure and modifies part of the P permutation algorithm structure. The various theoretical and hardware implementation steps of this algorithm are as follows:

[0043] A new S-box input and output: Figure 4 As shown in the figure, the input of one S-box of the algorithm comes from four different S-boxes, and the output of one S-box enters four different S-boxes. 32-bit data enters eight S-boxes, and then enters the P-box for permutation and data reordering. For the output data of the S-box, different lines represent that the data enters different S-boxes in the next round. Similarly, the input of one S-box comes from four different S-boxes. The input and output expressions of the S-box are as follows: X=X3∥X2∥X1∥X0→Y=Y3∥Y2∥Y1∥Y0 Y i =S(X i ),0≤i≤3

[0044] Among them, the S box is a nonlinear permutation operation commonly used in cryptography; the P box is a permutation operation in cryptography used to reorder data; Represents the input-output relationship of the S-box; X=X3|X2|X1|X0→Y=Y3|Y2|Y1|Y0 means that each data bit X3, X2, X1, X0 of X is calculated through the S-box to obtain the output of each data bit (Y3, Y2, Y1, Y0) of Y; || represents the connection operation.

[0045] A new P permutation: This P permutation maps the 32 bits of the state plaintext, replacing each bit position to the corresponding position. The function corresponding to the P layer is shown as follows: For 0≤i≤7 b i ←b 4*i , b i+8 ←b 4*i+1 b i+16 ←b 4*i+2 ,b i+24 ←b 4*i+3

[0046] Among them, b i represents the i-th bit in the state plaintext, P(i) is the P function that performs the permutation operation, and mod is a modulus operation that returns the remainder after dividing two numbers.

[0047] Table 1 GPESENT P-box replacement table i 0 1 2 3 4 5 6 7 <![CDATA[P i ]]> 0 8 16 24 1 9 17 25 i 8 9 10 11 12 13 14 15 <![CDATA[P i ]]> 2 10 18 26 3 11 19 27 i 16 17 18 19 20 21 22 23 <![CDATA[P i ]]> 4 12 20 28 5 13 21 29 i 24 25 26 27 28 29 30 31 <![CDATA[P i ]]> 6 14 22 30 7 15 23 31

[0048] Furthermore, for the GPRESENT lightweight encryption algorithm, a register consisting of 64 D flip-flops is used to store plaintext data, and 64 multiplexers (MUX) are used to divide the stored data into two 32-bit branches on the left and right.

[0049] Furthermore, in each round of encryption, the key generation unit generates a corresponding round key according to the current round number and the initial key, and the 2-bit XOR gate array converts the 32-bit R i-1 (or other intermediate data) and the round key K i-1 The bitwise XOR operation is synchronously performed under the control of the clock signal, followed by the S-box replacement operation.

[0050] Furthermore, for the S-box replacement operation, 4 bits of input data are sent to the read-only memory (ROM), and the ROM outputs the corresponding mapping value according to the input address; for the P-box replacement, it realizes the data replacement through a group of multiplexers (MUX), and the selection signal of the MUX is set according to the replacement rule of the P-box, and the bits of the input data are rearranged and output, completing a round of function operations.

[0051] Furthermore, the XOR circuit module in the left and right branch update circuit of the Feistel structure is used to update the output of the round function and L i-1 A 32-bit XOR operation is performed between them, and the inputs of the 32-bit XOR gate array are connected to the storage L i-1 The register and round function output signal line are triggered by the clock signal to calculate R i The register composed of D flip-flops will calculate the value of L at the rising edge of the clock signal. i and R i The values ​​are stored, and the inputs of these registers are connected to the XOR circuit module and the R of the previous round. i-1 (For updating L i ), the output is connected to the input port required for the next round of encryption operation, preparing for the next round of encryption operation.

[0052] Furthermore, the counter in the 32-round iterative control circuit starts counting from 1, and each rising edge of the count triggers a round of encryption operation. The clock signal of the counter is synchronized with the main clock signal of the entire circuit, and its counting range is set to 0 to 32. When the counter value is 0, the circuit performs initial data processing and initial key loading operations. When the counter value is between 1 and 32, each clock cycle coordinates the various sub-circuits (round key generation, round function, left and right branch updates, etc.) to complete a round of encryption operations. During each round of encryption, control signals are transmitted between the sub-circuits to ensure that they work in the correct order and timing. For example, the control signal can enable or disable the operation of certain circuit modules, or adjust the working mode inside the module to ensure the orderly progress of the entire encryption process. When the counter reaches 32, the encryption process is completed, and the storage L 32 and R 32 The data in the register is used as the final ciphertext, ultimately achieving data security enhancement.

[0053] The optimized PRESENT encryption algorithm has good improvement effects in terms of security and power consumption. After modifying the algorithm, the embodiment of the present invention makes a detailed analysis of the security of GPRESENT, which is mainly divided into linear cryptanalysis and differential cryptanalysis. The specific analysis process is as follows:

[0054] Linear cryptanalysis: The 5-round iterative structure of the PRESENT algorithm has at least 10 differentially active S-boxes, and the maximum linear approximation probability of the 4-round iterative structure of the PRESENT algorithm is about 2 -7 The maximum linear approximation probability of the S-box of the PRESENT cipher is 2 -2 , the algorithm contains at least 4 active S-boxes in each round. By applying the PiliNg-Up Lemma stacking lemma, the linear deviation of the active S-boxes for the 10-round GPRESENT cipher can be calculated as shown in the formula: ε=2 10*4-1 ×(2 -2 ) 10*4 =2 -41

[0055] Among them, ε represents the linear deviation. The higher the linear deviation, the higher the success rate of linear attack. L Represents the square of the reciprocal of the linear deviation, which is used to measure the data complexity required for a linear attack.

[0056] The improved PRESENT lightweight encryption algorithm, for 32 rounds of the algorithm, according to the formula, the data complexity of the linear attack is estimated to be 2 82 , more than 2 64 The security threshold of SFP cipher is 100%, so SFP cipher is completely resistant to linear cryptanalysis.

[0057] Differential cryptanalysis: For differential and linear cryptanalysis, the minimum number of active S-boxes determines the security of the cipher. For this GPRESENT algorithm, the S-boxes in the entire round function satisfy: 1. The input of an S-box comes from four different S-boxes, and the output of an S-box goes to four different S-boxes. 2. An input with a one-bit difference will always result in an output difference of two bits or more. 3. The 1-1-1 and 1-2-1 activity S box modes will not appear. The 4.1-2-2-1 pattern will have the least number of active S-boxes, because any other pattern with a lower number of active S-boxes will violate 1, 2, and 3. 5. If in any other case any round function body contains three or four differentially active S-boxes, there will be at least six or more active S-boxes in total. Therefore, the entire algorithm contains at least 6 active S-boxes in each round, so there will be at least 6×10=60 active S-boxes in the first 10 rounds of the algorithm. For the GPRESENT algorithm, the maximum difference probability of its S-box is 2 -2 , the difference probability in the first ten rounds is 2 -60A successful attack requires at least 2 120 The data complexity is more than 2 64 , so the algorithm can resist differential analysis.

[0058] The GPRESENT algorithm and the PRESENT algorithm are more secure than the original PRESENT encryption algorithm. Specifically, for the GPRESENT cipher, the maximum difference probability of 12 rounds is 2 -144 , the complexity of 12 rounds of differential analysis is 2 144 ,GPRESENT cipher only needs 12 rounds to achieve the same resistance to differential analysis as PRESENT cipher. For GPRESENT cipher, the maximum linear deviation of 11 rounds is 2 -45 , that is, the GPRESENT cipher only needs 11 rounds to reach 2 90 That is, for the GPRESENT cipher, only 11 rounds are needed to achieve the same ability to resist linear analysis as the PRESENT cipher with 28 rounds.

[0059] like Figure 5 As shown, the embodiment of the present invention provides an optimized HIGHT encryption algorithm, and the algorithm strength is level N. Consider dividing the plaintext P and the ciphertext C into four 16-bit blocks P3, ..., P0 and C3, ..., C0, and the original key K into eight 16-bit blocks K7, ..., K0. The initial transformation uses two whitened key bytes RK0 and RK1 to transform a plaintext P into the input of the first round function, X0 = X 0,3 ||……||X 0,0 In the final transformation, the data is shifted to the right and X is converted to 32 =X 32,3 ||……||X 32,0 Transformed into ciphertext C. Both transformations perform XOR and modular addition. The four 16-bit whitening keys WK3, ..., WK0 for the initial and final transformations. For l ≥ 0, WK l ←K 6+l ,WK l+2 ←K l The rouNd function remains unchanged, and the key RK of round i i By SK 2*i and SK 2*i+1 Composition, the values ​​are: SK 2*i =SK 4*i+1 |SK 4*i+2 SK 2*i+1 =SK 4*i|SK 4*i+3 Among them, SK 4*i ,SK 4*i+1 ,SK 4*i+2 ,SK 4*i+3 The generation is consistent with the HIGHT encryption algorithm.

[0060] The initial transformation module uses two whitened key bytes RK0 and RK1 to transform the plaintext P into the input X0 of the first round function. To implement XOR and modular addition operations, a dedicated 16-bit XOR gate array and a modular adder are designed for each 16-bit block. The modular adder is designed based on an adder and a comparator. 16 Taking addition as an example, the adder first adds the input data and connects the output result to the comparator. The comparator compares the addition result with 2 16 Compare, if greater then subtract 2 through the subtractor 16 , and get the final modular addition result.

[0061] Furthermore, the whitened keys RK0 and RK1 are stored in specific registers, which are composed of D flip-flops and stably store the key values ​​under the control of the clock signal. The outputs of the registers storing RK0 and RK1 are connected to the corresponding input ports of the XOR gate array and the modular adder with the corresponding plaintext block inputs. Specifically, for P0, it and RK0 are operated in turn through the XOR gate array and the modular adder to obtain X 0,0 , perform the same operation on P1, P2, and P3 respectively, and finally obtain X0=X 0,3 ||……||X 0,0 The round function module remains unchanged, and the round key plus transformation part is designed as a 16-bit XOR gate array. The input data and the round key are connected to two sets of input pins of the XOR gate array respectively. Under the control of the clock signal, the bitwise XOR operation of the input data and the round key is realized.

[0062] Furthermore, the S-box circuit is implemented using a lookup table (LUT). For a specific S-box, such as a 4-bit input and output S-box, a ROM (read-only memory) with 16 storage cells is used. The address line of the ROM is connected to the corresponding bit of the input data, and the corresponding mapping value is output according to the input address. For the processing of 16-bit data, multiple S-boxes may need to be cascaded. The input and output of each S-box must be synchronized with the clock signal to perform data transmission to ensure the correctness of data processing.

[0063] Furthermore, the P-box circuit realizes data permutation through a multiplexer (MUX). According to the permutation rule of the P-box, the input and output pins of the MUX are connected accordingly. The input data is connected to the input port of the MUX, and under the triggering of the clock signal, the data bits are rearranged according to the selection signal to achieve the permutation effect.

[0064] Furthermore, the round key generation module is used to generate the i-th round key RK i , which was created by SK 2*i and SK 2*i+1 Among them, SK 4*i SK 4*i+1 SK 4*i+2 SK 4*i+3 The generation of is consistent with the HIGHT encryption algorithm. According to the SK generation logic of the HIGHT algorithm, this module design includes circuit components such as shift registers and logic operation units. Driven by the clock signal, the shift register moves data according to specific displacement rules. The logic operation unit (such as AND gate, OR gate, NOT gate, etc.) performs logic operations on the shifted data according to the algorithm requirements to generate the SK value; according to the formula SK 2*i =SK 4*i+1 |SK 4*i+2 and SK 2*i+1 =SK 4*i |SK 4*i+3 , use logic gates (such as OR gates) to combine the generated SK into RK i In the hardware circuit, the generated SK 4*i SK 4*i+1 SK 4*i+2 SK 4*i+3 The value is connected to the corresponding OR gate input pin, and the output of the OR gate is RK i The value of .

[0065] The final transformation module transforms the data X 32 Shift right and use four whitening keys WK2 and WK3 to transform it into ciphertext C. The data shift circuit realizes the data right shift operation by designing a shift register. 32 =X 32,3 ||……||X 32,0 , each 16-bit block is right-shifted through a 16-bit shift register, and the shift amount is precisely set according to the algorithm requirements. The shift register moves data according to the specified shift rhythm under the control of the clock signal. Similar to the whitening key processing in the initial transformation module, this module uses XOR and modular addition circuits. WK2 and WK3 are stored in special registers, and the outputs of these registers and the shifted data are connected to the corresponding inputs of the XOR gate array and modular adder. After XOR and modular addition operations, the blocks C3, C2, C1, and C0 of the ciphertext C are obtained.

[0066] The optimized HIGHT encryption algorithm has good improvement effects in terms of its security and power consumption. After modifying the algorithm, the embodiment of the present invention makes a detailed analysis of the security of GPRESENT, which is mainly divided into avalanche effect cryptanalysis and differential resistance cryptanalysis. The specific analysis process is as follows:

[0067] Avalanche effect cryptanalysis: The avalanche effect test steps for the GHIGHT algorithm are as follows: 1. Randomly fix a set of keys K and randomly select a set of plaintext P. 2. After encryption, the initial ciphertext C is obtained. 3. Flip the first bit of the plaintext, keep the rest unchanged, and then encrypt it together with the key. 4. After encryption, the ciphertext C0 is obtained. 5. Obtain As the avalanche level of the plaintext on the first bit. 6. Repeat the above steps to find the avalanche degree on all bits of plaintext P. 7. Repeat the previous steps 1000 times, each time the plaintext P is random, and the key is the initial fixed key. After the above experiments, a total of 1000 sets of avalanche data are obtained. Under the condition of reducing energy consumption, this avalanche data shows good performance.

[0068] Anti-differential cryptanalysis: GHIGHT uses modular addition as a nonlinear component in the round function. In the differential process, the cyclic shift and XOR operation propagate the difference with a probability of 1. Therefore, the differential cryptanalysis of GHIGHT only needs to analyze the XOR difference of the modular addition operation. When the input modular addition difference Δα, Δβ, Δr and the output modular addition difference Δσ are given, where Δα and Δβ are the input differences of the XOR operation, the modular addition difference probability in the GHIGHT encryption algorithm can be calculated by the following formula: Where C = (10000000) T , L=(11111111), A w[i] Represents the state transfer matrix. w[i]=Δα[i]∥Δβ[i]∥Δσ[i+r], its value has 8 states, w[i]=001, 010, 100 corresponding to the same state transfer matrix, 011, 110, 101 corresponding to the same state matrix, as shown below: From the above formula, it can be obtained that when the input difference of the round function used by GHIGHT is not all 0, the maximum difference probability obtained by the input word length of 16 bits is 2 -3 , the maximum differential probability of GHIGHT after 27 rounds of encryption is 2-81 , a successful attack requires at least data complexity 2 81 , much larger than the safety threshold 2 64 , so GHIGHT can resist differential analysis.

[0069] Compared with the original HIGHT encryption algorithm, the GHIGHT encryption algorithm is more suitable for micro-power driven passive sensor node energy systems in terms of security and encryption performance.

[0070] In summary, the embodiment of the present invention provides an adaptive micro-energy driven passive sensor node security encryption architecture, which can adaptively and fully utilize the energy of the sensor nodes when the energy of the passive sensor nodes is extremely unstable, provide sufficient security enhancement for data transmission, and ultimately achieve a relative balance between the data security protection and low power consumption requirements of the passive sensor nodes.

[0071] Although embodiments of the present invention have been shown and described, it will be apparent to those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and creative concepts of the present invention, all of which fall within the scope of protection of the present invention.

Claims

1. An adaptive micro-energy driven passive sensor node security encryption architecture, characterized in that: The following steps are involved: (1) Detect node energy status with near-zero power consumption and perform energy classification (energy level division) (2) Triggering an encryption mechanism that matches the current energy level to enhance data security Among them, for the energy detection process, the traditional method needs to use a microprocessor to control ADC (analog-digital converter) sampling, which consumes a lot of power. Therefore, this patent designs a micro-power-driven multi-level threshold division detection method and implementation circuit based on an RC circuit, and configures N linear window comparators at the same time to achieve near-zero power consumption energy detection and energy level division; For the data security encryption process, traditional methods are difficult to adapt to the dynamic nature of energy acquisition in passive sensor nodes. Therefore, this patent designs a multi-energy-level adaptive security encryption method, which is automatically triggered according to the current energy level of the node and selects the encryption strength that matches the current energy level, from low to high: near-zero power digital conversion cyclic shift encryption (first-level encryption method), adaptive micro-energy driven multi-level hash stream cipher encryption (2nd to N-2nd level encryption), and lightweight security enhancement algorithm encryption (N-1st to Nth level encryption).

2. The method according to claim 1, based on the RC circuit, designs a micro-power drive multi-level threshold division detection method and implementation circuit, characterized in that: It includes a multi-threshold passive sensor node energy window division circuit and a near-zero power consumption micro-energy adaptive trigger circuit, which obtains energy changes according to the passive sensor node environment, so that different energy states are represented by voltages with different values, so that the micro-power driven multi-threshold comparator group can grade the passive sensor node energy according to the voltage.

3. The method according to claim 1, characterized in that The N encryption modules are: near-zero power digital conversion level 1 encryption (cyclically shift right by two bits after each round of encryption XOR), micro-energy adaptive drive N-3 level hash stream cipher encryption, innovative and optimized N-1 level PRESENT encryption, innovative and optimized N level HIGHT encryption. The N encryption modules perform data encryption according to different energy levels.

4. The method according to claim 3, characterized in that The near-zero power digital conversion level 1 encryption algorithm is based on the message XOR algorithm. After the data to be encrypted is XOR-converted, it is cyclically right-shifted by two bits to achieve zero power data security encryption.

5. The method according to claim 3, characterized in that Adaptive micro-energy driven N-3 level hash encryption, that is, enhancing data security by adding periodic trigger keys, real-time environment driven micro-energy signals, and energy thresholds. The periodic trigger key is a periodic trusted key used for adaptive micro-energy driven N-3 level hash encryption to generate hash values, which is generated based on clock signals. The real-time environment driven micro-energy signal is the time trust value obtained according to the clock signal, which is used as the salt variable for the hash function to generate the hash value; The energy threshold is the maximum value of the energy range of each passive sensor node, and is also used as a salt variable for the hash function to generate a hash value.

6. The method according to claim 3, characterized in that The innovative and optimized N-1 level PRESENT encryption introduces the Feistel structure, which reduces the complexity of the original PRESENT encryption algorithm through the iterative mode of "split-transform-combination" and improves the security of the encryption algorithm.

7. The method according to claim 3, characterized in that The innovative and optimized N-level HIGHT encryption reduces the algorithm energy consumption and enhances the algorithm security by redividing the plaintext and ciphertext blocks and splitting the original key into 8 16-bit blocks.

8. The method according to claim 5, characterized in that The implementation of adaptive micro-energy driven N-3 level hash stream cipher encryption includes the following steps: ① Receive periodic trusted key; ②Receive timestamp signal; ③ Receive energy threshold signal; ④ Select a micro-energy driven hash encryption algorithm with different energy consumption levels according to the energy threshold signal.

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